TWI908386B - Semiconductor circuit structure with direct die heat removal structure - Google Patents

Abstract

A semiconductor circuit structure. The semiconductor circuit structure includes a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO₂.

Description

Semiconductor circuit structure with direct grain heat dissipation

This disclosure relates to a semiconductor structure, and more particularly to a semiconductor circuit structure having a direct grain heat dissipation structure.

Silicon wafer integration capabilities have evolved from gigascale integration (GSI: billions of transistors on a single chip) to terascale integration (TSI: trillions of transistors on a single chip). Operating such a large number of transistors leads to a dramatic increase in power consumption. Limited by current technology's heat dissipation capabilities, the increased power consumption adversely raises the transistor junction temperature, thereby increasing the overall chip temperature. Furthermore, silicon dioxide has a very low thermal conductivity, and silicon itself is not particularly thermally conductive. This material and component structural issue results in a negative cyclic effect, meaning that the increase in chip temperature slows down the transistor operation. Then, inevitably, designs are enhanced to increase circuit power and accelerate transistor performance, but this mechanism causes a sharp rise in chip temperature, exacerbating heat dissipation problems. This problem of insufficient heat dissipation leading to elevated chip operating temperatures is one of the most critical issues that the entire chip industry urgently needs to address, and a major obstacle to avoid when integrating more components onto the chip. However, progress in reducing the temperature of massive scalability integrated circuit (GSI) chips has not been as good as it should be.

In reality, as process technology nodes continue to shrink, transistor sizes inevitably become smaller (for example, the minimum feature size shrinks from 7nm to 5nm, then to 3nm, and so on). The percentage of the total transistor size covered by oxides also increases, leading to a further concentration of heat dissipation capabilities through the device junctions. Although the industry has created many heat dissipation methods, such as covering the entire chip with a taller thermal pad or using liquid cooling circulation outside the packaged chip, these methods are very expensive, but their return on investment in effectively reducing transistor junction temperatures is very low.

This invention focuses on creating a heat remover (HR) structure within the semiconductor die during monolithic processes of transistor manufacturing. This HR structure acts as a single-piece component attached to the die, maximizing the heat dissipation area. Furthermore, this HR structure can be connected to the entire edge of the die, allowing for easier connection to external heatsinks and creating a larger heat dissipation path to the external environment and ultimately to the packaged chip. This novel HR structure is considered the closest approach to achieving highly efficient heat dissipation when integrated with a single transistor. Moreover, all these heat dissipation structures can be connected together and span the entire grain as part of an optimized heat dissipation network built into the grain.

Embodiments of the present invention provide a semiconductor circuit structure. This semiconductor circuit structure includes a semiconductor substrate having an original semiconductor surface (OSS), a set of active regions located within the semiconductor substrate, and a first shallow groove isolation region (STI) adjacent to the set of active regions and extending along a first direction. The first shallow groove isolation region includes a heat dissipation layer, and the material of the heat dissipation layer is different from silicon dioxide ( _SiO2 ).

According to one aspect of this manual, the thermal conductivity of the heat dissipation layer is higher than that of silicon dioxide.

According to one aspect of this specification, the heat dissipation layer is an electrical insulator during the operation of the semiconductor circuit structure.

According to one aspect of this manual, the heat dissipation layer extends into one of the active zones of this assembly.

According to one aspect of this specification, the heat dissipation layer comprises a metal layer and an insulating thin layer, which is located between the metal layer and this set of active regions.

According to one aspect of this specification, the heat dissipation layer comprises a composite material.

According to one aspect of this specification, the first shallow groove isolation zone further includes a silicon dioxide layer located below the heat dissipation layer.

According to one aspect of this specification, the heat dissipation layer is located within the front end of line (FEOL) region of the semiconductor circuit structure.

According to one aspect of this instruction manual, the first shallow groove isolation zone surrounds this group of active zones.

According to one aspect of this specification, the heat dissipation layer is located in the first shallow groove isolation region and below the original semiconductor surface, and the heat dissipation layer surrounds this set of active regions.

According to one aspect of this instruction manual, a spare shallow groove isolation region is also included, which is connected to the first shallow groove isolation region, and the heat dissipation layer extends into the spare shallow groove isolation region along the first direction.

According to one aspect of this specification, the alternative shallow groove isolation region is located near the center of the semiconductor substrate or near the edge of the semiconductor substrate.

According to one aspect of this instruction manual, a heat dissipation pad is located within the spare shallow groove isolation area, and the heat dissipation layer is connected to the heat dissipation pad.

According to one aspect of this specification, a thermal via is located above the spare shallow groove isolation area and connected to a heat dissipation solder pad within the spare shallow groove isolation area.

According to one aspect of this manual, a heat dissipation plate is also included, located above the heat port plug and connected to the heat port plug.

According to one aspect of this instruction manual, multiple insulators are located above this active area, with heat-perforated plugs penetrating the multiple insulators and connecting to heat-dissipating solder pads located in the backup shallow groove isolation area.

According to one aspect of this specification, multiple insulators and thermal via plugs are located within the back end of line (BEOL) region of the semiconductor circuit structure.

According to one aspect of this specification, a through semiconductor via (TSV) extends from the back surface of the semiconductor substrate to the bottom surface of the heat dissipation pad located in the standby shallow groove isolation area, wherein the back surface and the original semiconductor surface are located on opposite sides.

According to one aspect of this specification, the heatsink is located below the back surface of the semiconductor substrate and connected to the semiconductor via plug.

According to one aspect of this instruction manual, the first shallow groove isolation zone surrounds the four side walls of one of the active zones in this group.

Another embodiment of the present invention provides a semiconductor circuit structure, including a semiconductor substrate having a raw semiconductor surface, a group of transistors formed within the semiconductor substrate, and a composite material shallow groove isolation region adjacent to the group of transistors and extending along a first direction to the edge portion of the semiconductor substrate. The composite material shallow groove isolation region is located within the front end of line (FEOL) region of the semiconductor circuit structure.

According to one aspect of this specification, the composite shallow groove isolation region includes a row of thermal layers adjacent to the group of transistors and extending along a first direction to the edge portion of the semiconductor substrate.

According to one aspect of this specification, a heat dissipation hole plug is provided above or below the heat dissipation layer, wherein the heat dissipation hole plug is connected to the heat dissipation layer.

According to one aspect of this specification, the heatsink is located above or below the semiconductor substrate, wherein the semiconductor substrate is connected to the thermal via plug.

According to one aspect of this specification, the thermal via plug is located in the back-end process area of the semiconductor circuit structure.

Another embodiment of the present invention provides a semiconductor circuit structure, including a semiconductor substrate having a raw semiconductor surface, a first set of active regions located in the semiconductor substrate and extending along a first direction, a second set of active regions located in the semiconductor substrate and extending along the first direction, and a first shallow groove isolation region located between the first set of active regions and the second set of active regions, the first shallow groove isolation region extending along the first direction; wherein the first shallow groove isolation region includes a heat dissipation layer extending along the first direction, and the thermal conductivity of the heat dissipation layer is higher than that of silicon dioxide.

According to one aspect of this specification, this semiconductor circuit structure also includes a backup shallow groove isolation region located away from the first set of active regions and the second set of active regions. This backup shallow groove isolation region is connected to the first shallow groove isolation region and includes a heat dissipation pad located in the backup shallow groove isolation region, wherein the heat dissipation layer is connected to the heat dissipation pad.

According to one aspect of this manual, the width of the heat dissipation pad is greater than the width of the heat dissipation layer.

The above and other embodiments of this specification will be better understood through a detailed description of the following non-limiting embodiments and with reference to the accompanying diagrams.

The various embodiments will be described more fully below with reference to the accompanying drawings, which are for illustrative and explanatory purposes only and are not intended to limit the invention. For clarity, the components in the drawings may not be drawn to scale. Additionally, some components and/or component designations may be omitted in some drawings. It is expected that the components and features of one embodiment can be incorporated into another embodiment without further description. In the methods for manufacturing semiconductor components described below, one or more additional steps may exist between the described steps, and the order of these steps can be varied. The same/similar component designations may be used in the various drawings to indicate the same/similar components.

Ordinal numbers used to describe elements in the specification and claims, such as "first," "second," etc., do not imply or represent a specific location in the structure, or the order of arrangement, or the order of manufacture. Ordinal numbers are used only to clearly distinguish multiple components with the same name. Spatial relation terms used in the specification and claims, such as "above," "above," "on top," "upper part," "top," "below," "below," "under," "lower part," "bottom," etc., are used only to describe the relative spatial or positional relationships between one or more elements in the drawing, and these spatial or positional relationships, unless otherwise stated, can be direct or indirect. Spatial relation terms are intended to cover different directions of the structure, in addition to the directions depicted in the drawing. The structure can be inverted or rotated at various angles, and can correspondingly explain the descriptions of various spatial relationships used in this manual.

Additionally, terms such as "electrical connection" and "electrical coupling" used in the specification and request can refer to ohmic contact between components, the passage of current through the components, or the operational relationship between components. For example, the operational relationship could mean that one component drives another component, but current may not flow directly between the two components.

In traditional semiconductor circuit structures, numerous transistors or circuit components reside within active areas (AA) of the semiconductor substrate, surrounded by shallow groove isolation regions, as illustrated in Figure 1a. Figure 1b is a top view showing a portion of the structure in Figure 1a; Figure 1c is a cross-sectional view of the structure in Figure 1a. Prior to transistor fabrication, silicon islands in the active areas are covered by oxide and nitride layers, which are deposited above the original semiconductor surface of the semiconductor substrate. Shallow groove isolation regions typically extend downwards from the original semiconductor surface to a depth of 250 to 300 nanometers, and the material used is usually silicon dioxide, which has a relatively low thermal conductivity of 1.3 to 1.5 W/m×K. Therefore, shallow groove isolation regions can increase grain temperature and reduce transistor speed. Worse still, shallow groove isolation regions in semiconductor substrates can occupy 40% or more of the total semiconductor substrate area, and these shallow groove isolation regions have no special function other than isolation.

The following describes how a heat dissipation structure is fabricated in a substrate or grain according to embodiments of the present invention. Please refer to Figure 1. Please refer to Figures 2a and 2b. First, a thin pad-oxide layer 101 is thermally grown on top of the original semiconductor surface, and then a first pad-nitride layer 102 is deposited on top of the thin pad-oxide layer 101. An active region 103 is defined using a photolithography technique, wherein the transistor body 1031 or fin structure is located beneath the composite layer consisting of the first pad-nitride layer 102 and the thin pad-oxide layer 101. A concave groove region 104 (with a depth t1, calculated from the original semiconductor surface to be 250 nm to 300 nm) is formed on the outer side of the active region 103, connecting to the inside of the grain. Then, a thick silicon oxide layer is deposited, and a shallow groove isolation region 201 is fabricated using chemical-mechanical-polishing (CMP) technology, so that its top surface is flush with the top surface of the first pad silicon nitride layer 102 (wherein the top view and structural cross-sectional schematic diagram are shown in Figures 2a and 2b, respectively).

Referring to Figures 3a and 3b, a second pad-nitrogen nitride layer 301 is deposited, and a portion of the second pad-nitrogen nitride layer 301 is left in the center of the active region 103 using photolithography. Figures 3a and 3b respectively show the top view and cross-sectional view of the fabrication structure. Next, referring to Figures 4a and 4b (Figures 4a and 4b respectively show a top view and a cross-sectional view of the fabrication structure), a portion of the exposed silicon oxide in the shallow groove isolation region 201 is etched away to a depth t2 (e.g., a depth t2 of 70 nm, or 100 nm to 150 nm); the silicon oxide in the second pad silicon nitride layer 301 and the shallow groove isolation region 201 located below the second pad silicon nitride layer 301 remains unaffected. This exposes the silicon sidewalls located below the original semiconductor surface. Then, using a thermal oxidation process, a thin silicon oxide layer 401 (e.g., approximately 1.5 nm to 3 nm thick) is grown on these sidewalls. Then, a third pad-nitride layer 403 is deposited. The third pad-nitride layer 403 is etched using anisotropic etching to serve as a gap wall on the vertical sidewalls. With proper intentional design, the second pad-nitride layer 301 remains on a flat surface, but is made thinner due to the anisotropic etching used to create the gap wall of the third pad-nitride layer 403.

Please refer to Figures 5a and 5b, which are top and cross-sectional views of the fabrication structure, respectively. Anisotropic etching is used to remove a portion of the exposed silicon oxide layer in the shallow groove isolation region 201. The etching thickness t3 is approximately 8 nanometers, thereby forming a flat silicon oxide surface. The distance from the top of the exposed silicon oxide surface to the original semiconductor surface is approximately 78 nanometers (t2+t3). Anisotropic etching is then used to remove the exposed silicon oxide thin layer 401, thereby exposing the silicon on the sidewalls.

Please refer to Figures 6a, 6b, and 6c, where Figure 6a is a top view of the fabrication structure; Figure 6b is a cross-sectional view of the structure drawn along tangent 6b-6b' in Figure 6a; and Figure 6c is a cross-sectional view of the structure drawn along tangent 6c-6c' in Figure 6a. A portion of the exposed silicon surface is removed using isotropic etching, preferably by adjusting the etching rate along the lattice alignment direction (1,1,0) to be much faster than the etching rate along the lattice alignment direction (1,0,0). Therefore, the exposed silicon layer can be removed, thereby forming the etched tunnel region 601. The silicon removal process is well controlled and can be stopped at the appropriate time to ensure that a vertical distance of silicon is protected by the gap walls of the third silicon nitride layer 403.

It is worth noting that different processes can be used to achieve structures similar to those shown in Figures 6a, 6b, and 6c. For example, after forming the structures shown in Figures 5a and 5b, instead of using the aforementioned anisotropic etching technique to remove a portion of the exposed silicon surface, a thermal oxidation process can be used to grow silicon oxide to replace the exposed silicon region. Because the exposed silicon regions may have narrow horizontal spacing, the silicon oxide layer (e.g., thermally oxidized silicon) grown beneath the top surface of the silicon islands can quickly fill the horizontal gaps, exhibiting a smooth, closed-up shape. The bulk silicon material covered by the third pad silicon nitride layer 403 is well protected as a strong pillar to connect the semiconductor body region of the transistor to the wafer substrate region without being over-oxidized. This thermally oxidized silicon is then removed using anisotropic etching techniques to produce a structure similar to that shown in Figures 6a, 6b, and 6c.

Referring to Figures 7a and 7b, the interstitial walls of the third pad silicon nitride layer 403 are removed using isotropic etching. A very thin (e.g., 1 nm to 3 nm) silicon oxide layer 701 is grown using a thermal oxidation process to effectively protect the newly formed and exposed silicon surface. A suitable material with a very high thermal conductivity is then selected (e.g., boron nitride (BN), which is an electrical insulator but has a very high thermal conductivity, such as 600 W/m × K, compared to silicon's 149 W/m × K; aluminum nitride (AlN), a material with a thermal conductivity up to 321 W/m × K; or any other material with a suitable thermal conductivity, any of which can be referred to as material Z 702). Next, a chemical vapor deposition (CVD) process, for example, boron nitride (BN), is used to fill the hollow tunnel region 601 formed in the previous process. Of course, the voids inside the shallow groove isolation region are also filled with boron nitride (BN) material (Figures 7a and 7b are top views and cross-sectional schematic diagrams of the process structure, respectively).

In another embodiment, the thermal conductivity of material Z 702 is higher than that of silicon, or higher than that of silicon nitride, or higher than 10 W/mK or 30 W/mK. Of course, other materials that could be used as material Z 702 could be graphene or metals (e.g., copper, tungsten, or composite metals). Preferably, a titanium nitride (TiN) barrier layer or other suitable material layer is coated on the tungsten layer. When the material of material Z 702 is metal, an insulating thin layer, such as a thermally oxidized silicon layer, can exist between the active region and material Z 702. Furthermore, the material of material Z 702 can be a composite material layer comprising two or more of the aforementioned materials. Clearly, material Z 702 is different from the original material (silicon dioxide) of the shallow groove isolation region. In another embodiment, material Z 702 is also different from silicon nitride. Material Z 702 may include materials with higher thermal conductivity than the original material (e.g., silicon oxide) of the shallow groove isolation region, such as aluminum nitride, boron nitride, silicon carbide (SiC), silicon (Si), deposited diamond, or silicon-germanium (SiGe).

Subsequently, chemical mechanical polishing (CMP) can be used to remove the boron nitride material or Z material 702 located above the first silicon nitride layer 102 to form a flat surface. Anisotropic etching is then used to remove a portion of the boron nitride material or Z material 702, aligning the top of the Z material 702 with or below the original semiconductor surface. Next, a layer of silicon oxide 801 is deposited on top of the remaining Z material 702 until it is flush with the top surface of the first silicon nitride layer 102. After the second silicon nitride layer 301 is removed, the silicon surface is covered by silicon oxide above the first silicon nitride layer 102 and the shallow groove isolation region, and familiar processes can be performed in the remaining active semiconductor region to complete the fabrication of a transistor (e.g., a planar transistor, a fin field-effect transistor, or a gate-all-around (GAA) transistor, etc.) (see Figure 8, where Figures 8a and 8b are top and cross-sectional views of the fabrication structure, respectively).

Since boron nitride or Z material 702 is filled in the hollowed-out tunnel region beneath the active region (or finned field-effect transistor/tri-gate device), it can be referred to as a horizontal heatsink. Some Z material 702 filling the vertical voids in the shallow groove isolation region, as illustrated in Figure 8, can be referred to as vertical heatsink pillars. After the transistor is formed in the active region, the source/drain regions of the transistor can be positioned close to the horizontal heatsink and vertical heatsink pillars, which have a higher thermal conductivity than the silicon dioxide (or silicon) material conventionally used to surround the transistor. In fact, the hottest areas of a transistor during full operation are concentrated in the p/n junction region between the drain region and the source region, which are connected to the transistor channel region. These horizontal heat dissipation plates and vertical heat dissipation pillars can very effectively disperse the heat generated in these p/n junction regions.

Another possibility is to use a similar method to create a horizontal heatsink structure deeper than the original silicon surface, increasing the heat dissipation area by adding more horizontal heatsinks. For example, after the deposition of boron nitride material or Z material 702 by chemical vapor deposition, anisotropic etching can be used to remove the boron nitride material or Z material 702 vertically located inside the shallow groove isolation region 201. Then, anisotropic etching can also be used to remove or etch away the silicon oxide material at the bottom of the shallow groove isolation region 201 (e.g., leaving only 20 to 50 nanometers thick silicon oxide inside the shallow groove isolation region 201 without damaging the boron nitride material that has been horizontally inserted into the hollow tunnel region 601). Then, boron nitride material or Z material 702 is deposited a second time into the voids in the shallow groove isolation region 21. The two-step process of forming boron nitride material or Z material 702 involves forming a horizontal heat dissipation plate in the first step and optimizing the volume of all boron nitride or Z material 702 within the shallow groove isolation region 21 (see Figure 9, where Figures 9a and 9b are top and cross-sectional views of the process structure, respectively). Of course, before the second deposition of Z material 702, an additional step can be applied to form a thin vertical isolation layer (e.g., a silicon oxide layer 401) such that the vertical isolation layer is located below the horizontal heat dissipation plate and between the sidewall of the silicon substrate and the Z material 702.

It is also worth noting that, as shown in Figure 1a, the shallow groove isolation region covers the entire wafer substrate. Since the horizontal heat dissipation plate material is entirely located below the body region (or active region) of the metal-oxide-semiconductor field-effect transistor (MOSFET)/transistor and connected to all the vertical heat dissipation pillar materials within the shallow groove isolation region, the constructed high-heat-dissipation material network can serve as a heat-dissipation sink connecting the working P/N junction of the transistor. By designing Z-materials in a monolithic die and utilizing familiar monolithic die process parameters (formulas), all Z-materials can be connected to the edge ring of the die or chip. Furthermore, the Z material 702 located within the shallow groove isolation region can form contact by opening its top surface, allowing the entire Z material 702 of the die to be thermally connected to the outer edge of the wafer/die for more direct and efficient heat dissipation. See Figure 10, where Figures 10a and 10b respectively illustrate the top view and cross-sectional schematic of the fabrication structure. Therefore, the horizontal heat sink in the shallow groove isolation region (and/or the horizontal heat sink in the active region) can be termed a Direct Die Heat Remover (DDHR). This invention provides a Direct Die Cooling Technology (DDCT) based on the aforementioned vertical heat sink (and/or horizontal heat sink).

The semiconductor substrate contains multiple active regions, which in this invention can be surrounded by a Z material 702. The Z material 702 extends from one active region to another and further to the edge of the wafer/die. Each active region can accommodate a circuit element, such as a transistor. In another embodiment, the wafer/die with vertical heat dissipation pillars (and/or horizontal heat dissipation plates) can be thinned first, and then exposed through openings, so that another substrate with thermal vias or heat sinks can be connected from the bottom of the wafer/die to the vertical heat dissipation pillars (and/or horizontal heat dissipation plates).

After the structure of the vertical heat pillar (and/or horizontal heat plate) is completed through a portion of the front-end fabrication process, the transistor can be formed in the active region using the remaining front-end foundry processes, as illustrated in Figure 11. The diffusion region (or source/drain region) of the transistor can be in contact with or nearly in contact with the vertical heat pillar (and/or horizontal heat plate). Therefore, it can be said that the vertical heat pillar (and/or horizontal heat plate) is formed during the semiconductor front-end foundry process, or within the front-end fabrication region of the semiconductor die.

In Figure 11, this transistor includes a gate structure comprising a gate metal region 1101 and a high-k dielectric layer 1102. The transistor also includes a source region 1103 comprising lightly doped regions extending laterally from the sidewalls of the substrate and heavily doped regions extending laterally from the sidewalls of the lightly doped regions. These lightly doped and heavily doped regions are formed using selective growth methods (e.g., epitaxial growth methods). The source region 1104 is located above the top of the source region 1104. A metal contact 1105 exists between the gate structure of the transistor and the shallow groove isolation region (the upper silicon oxide 801). Notably, the top surface of the shallow groove isolation region (the upper silicon oxide 801) is higher than the original semiconductor surface (e.g., flush with the top of the gate structure), thus automatically forming a contact via, eliminating the need for a photolithography process. Therefore, the metal contact 1105 is self-aligned with the source region 1103. Furthermore, in another embodiment, the metal contact 1105 can be connected not only to the top of the source region 1103 but also to the outermost lateral sidewall of the source region 1103. This transistor also includes a drain region 1104, whose structure is the same as or substantially the same as that of the source region 1103, and will not be described further here. The final transistor structure illustrated in Figure 11 has a microstructure with vertical heat dissipation pillars (and/or horizontal heat dissipation plates) for fabricating a new "transistor cooling (CQT)" structure, which is the best term to describe embodiments of the invention. This transistor cooling (CQT) structure enables performance scaling (more transistors) and size miniaturization (smaller transistor size) strategies from the current era of massive scalar integrated circuits (GSI) to the near future era of mega scalar integrated circuits (TSI). The new heat dissipation path created for a chip or die is a direct heat dissipation path formed from the transistor level to the entire die level. Some designs can connect the die-level heat dissipation path to the chip-level thermal path. Under current cooling methods used in chips and heterogeneous integration modules, it can certainly serve as an effective heat dissipation device for chips and heterogeneous integration modules (e.g., through through-silicon vias (TSVs) or through-insulator vias (TIVs), etc.).

In another embodiment, the process of forming a horizontal heat sink can be omitted, and only a vertical heat sink pillar can be constructed. For example, referring to Figure 12, the shallow groove isolation region 201 can be etched downwards to expose the sidewalls of the silicon substrate, such that the depth of the remaining material in the shallow groove isolation region is approximately 150 nm to 200 nm. Then, a silicon oxide (thermal silicon oxide) thin layer 401 is formed along the exposed sidewalls of the silicon substrate. Then, Z material 702 is deposited and etched back to a depth of 100 nm to 150 nm to form a vertical heat sink pillar, and additional silicon oxide 801 or other isolation materials are deposited on the vertical heat sink pillar, as illustrated in Figure 12a.

Figure 12b is a schematic cross-sectional view of the structure of a vertical heat dissipation pillar located in a shallow groove isolation region, according to another embodiment of the present invention. The difference between Figures 12a and 12b is that most of the silicon dioxide material in the shallow groove isolation region is replaced by the vertical heat dissipation pillar. The depth of a conventional shallow groove isolation region, measured from the original semiconductor surface (OSS) of the wafer, is 250 nm to 300 nm. In Figure 12b, only silicon dioxide material with a depth of 20 nm to 50 nm remains in the lower part of the shallow groove isolation region; while in the shallow groove isolation region shown in Figure 12a, silicon dioxide material with a depth of 150 nm to 200 nm remains in the lower part. The more silicon dioxide replaced by vertical heat dissipation pillars, the higher the thermal conductivity of the grain structure. Of course, the top of the vertical heat dissipation pillars can be lower or higher than the original semiconductor surface. Similarly, the vertical heat dissipation pillar structure illustrated in Figure 12a or 12b can also extend along all the shallow groove isolation regions inside the semiconductor grain, as illustrated in Figure 12c. The lower sub-figure of Figure 12c is a schematic cross-sectional view of the structure drawn along the tangent 12c of the upper sub-figure of Figure 12c.

Figure 13 is a schematic diagram illustrating another transistor cooling structure. The difference between Figure 13 and Figure 11 is that the transistor cooling structure in Figure 13 is based on the vertical heat dissipation column located in the shallow groove isolation region shown in Figure 12b. Since the other descriptions of the transistor cooling structure shown in Figure 13 are the same as those in Figure 11, detailed descriptions will be skipped for the sake of brevity.

As previously mentioned, the vertical heat dissipation pillar or Z-material can be made of a single high-heat-dissipation material or a composite structure. For example, the vertical heat dissipation pillar includes a first high-heat-dissipation material (e.g., boron nitride, aluminum nitride, etc., not shown in Figures 12a or 12b) and another metal or metal-like pillar covered by the first high-heat-dissipation material. Since the vertical heat dissipation pillar is located in a shallow groove isolation region and the metal-like material is surrounded by the first high-heat-dissipation material, which does not conduct electricity during the operation of the transistors in the wafer/die (in this case, the silicon oxide layer 401 can be omitted), the metal-like material in the vertical heat dissipation pillar will not affect the operation of the transistors in the wafer/die. Of course, the first high heat dissipation material and the metal or metal-like pillars can further extend to the edge of the wafer/grain and form a heat dissipation network as described above. Therefore, the semiconductor structure of the present invention contains a shallow groove isolation region of composite material (including the original shallow groove isolation region silicon dioxide material and vertical heat dissipation pillars; only the vertical heat dissipation pillars are included, which can be a composite material with two different layers) or a heterogeneous shallow groove isolation region (HSTI).

Furthermore, in one embodiment, all or most of the shallow groove isolation regions in Figure 1a can be replaced by shallow groove isolation regions of a composite material. These composite material shallow groove isolation regions can extend from one active region to another, and further to the edge of the wafer/die. In another embodiment, the peripheral border of the first set of active regions is surrounded by these composite material shallow groove isolation regions, extending to the second set of active regions, and further to the edge of the wafer/die.

Figure 14a is a top view of a semiconductor circuit structure 200 illustrated according to some embodiments of this specification. The semiconductor circuit structure 200 may be formed in a semiconductor wafer or substrate. Figure 14a illustrates additional active regions or active regions 220A, shallow groove isolation regions 220B, and pad open layers 220C that can accommodate the contact pads of the semiconductor circuit structure 200. Some large shallow groove isolation regions 224-1 to 224-4 in the shallow groove isolation regions 220B may be located in corner areas adjacent to the outer/edge areas of the semiconductor wafer, or in the center spare area of the wafer. Large vertical heat dissipation pillar structures (e.g., vertical heat dissipation pillar pads) 209 are located within large shallow groove isolation regions 224-1 to 224-4 and below the original semiconductor surface of the semiconductor substrate. Additionally, other thin or long vertical heat dissipation pillar structures (e.g., vertical heat dissipation pillar lines) 205 are located below the original semiconductor surface of the semiconductor substrate and are formed within those thin or long shallow groove isolation regions 224-1 to 224-4 in the shallow groove isolation region 220B. The vertical heat dissipation pillar structures 205 and the shallow groove isolation regions 214-1 to 214-4 may extend along the X-axis direction (or along the long axis of the active region). In addition, the vertical heat dissipation column structure 205 may extend over two or more active zones 220A. For example, the vertical heat dissipation column structure 205 located in the upper right of Figure 14a extends from a predetermined point near the active zone 220A-1 to a large shallow groove isolation zone 224-1.

In Figure 14a, on one side of the shallow groove isolation region 214-1, there is a first set of active regions extending along the X-axis; on the other side of the shallow groove isolation region 214-1, there is a second set of active regions extending along the X-axis. Therefore, the shallow groove isolation region 214-1 is located between the first and second sets of active regions and extends along the X-axis. Furthermore, the vertical heat dissipation column structure 205 inside the shallow groove isolation region 214-1 is also located between the first and second sets of active regions and extends along the X-axis. In one embodiment, the minimum width and/or maximum width (e.g., along the Y-axis) of the vertical heat dissipation column structure 205 located between the first set of active regions and the second set of active regions is less than the width of the vertical heat dissipation column structure 209 (e.g., along the y-direction) connected to the vertical heat dissipation column structure 205.

Furthermore, each of the shallow groove isolation regions 214-1 to 214-4 may be adjacent to one group of transistors in the plurality of active regions 220A, and the large shallow groove isolation region 214-1 is distanced from this group of transistors. The vertical heat dissipation pillar structure 205 is coupled to or directly connected to the vertical heat dissipation pillar structure 209.

The width of the vertical heat dissipation pillar 209 along the Y-axis is greater than the width of the vertical heat dissipation pillar 205 along the Y-axis. The width of the vertical heat dissipation pillar 209 along the Y-axis can be between approximately 2 micrometers (μm) and 8 micrometers. The width of the vertical heat dissipation pillar 205 along the Y-axis can be between approximately 10 nanometers (nm) and 100 nanometers (nm). The area of the vertical heat dissipation pillar 209 can be between approximately 4 square micrometers ( ^μm² ) and approximately 50 square micrometers (nm²). The materials of the vertical heat dissipation pillars 205 and 209 can be the same or different.

The spare or large shallow groove isolation area 224 may form additional alignment marks for back-through-silicon via (TSV) or hot-through-hole plugs extending from the bottom of the large shallow groove isolation area 224 to the bottom side of the substrate, as illustrated in Figure 14b. These back-through-silicon via (TSV) or hot-through-hole plugs are located directly below and connected to the large vertical heat dissipation pillar pads inside the large shallow groove isolation area 224. The spare or large shallow groove isolation area 224 is large enough to accommodate one or more TSVs or hot-through-hole plugs. Of course, the spare or large shallow groove isolation areas 224 can also form additional alignment marks for the through-silicon via (TSV) or hot-through-hole plugs extending from the top of the large shallow groove isolation area 22 to the top side of the substrate. These hot-through-hole plugs are located directly above and connected to the large vertical heat dissipation pillar pads within the spare shallow groove isolation areas. The through-silicon via (TSV) or hot-through-hole plugs of the present invention can be manufactured by back-end processing and connected to the large vertical heat dissipation pillar pads. Therefore, it can be said that through-silicon via (TSV) plugs or thermal via plugs are formed during back-end foundry manufacturing or within the back-end processing area of the semiconductor die.

In other embodiments, the vertical heat dissipation pillar structure may extend along a direction other than the X-axis, as illustrated in Figure 15a. Figure 15a is a top view of a semiconductor circuit structure 300 illustrated according to some embodiments of this specification. Compared to the semiconductor circuit structure 200 illustrated in Figure 14a, the semiconductor circuit structure 300 illustrated in Figure 15a further includes shallow groove isolation regions 314-1, 314-2, and 314-3 extending along the Y-axis, as well as vertical heat dissipation pillar structures 305-1, 305-2, and 305-3. Vertical heat dissipation pillar structures 305-1, 305-2, and 305-3 are located below the original semiconductor surface of the semiconductor substrate and are formed inside shallow groove isolation regions 314-1, 314-2, and 314-3, respectively. The vertical heat dissipation pillar structures 305-1, 305-2, and 305-3 can be vertical heat dissipation pillars. The vertical heat dissipation pillar structures 305-1, 305-2, and 305-3, as well as the shallow groove isolation regions 314-1, 314-2, and 314-3, can extend along the Y-axis direction (or along the width direction of the active region). Furthermore, the vertical heat dissipation pillar structures 305-1, 305-2, and 305-3 can extend above two or more active regions 220A. For example, the vertical heat dissipation pillar structure 305-1 located in the upper left portion of Figure 15 extends from a predetermined point adjacent to the active region 220A-2 to the horizontal shallow groove isolation region 214. Each of the shallow groove isolation regions 314-1, 314-2, and 314-3 can be adjacent to a set of transistors located in the active region 220A.

In Figure 15a, vertical heat dissipation pillar structures extending along a non-X-axis direction can be connected to (or electrically coupled to) vertical heat dissipation pillar structures extending along the X-axis direction and/or vertical heat dissipation pillar pads located within a large shallow groove isolation zone. For example, vertical heat dissipation pillar structure 305-1 is connected to (or electrically coupled to) vertical heat dissipation pillar structure 205; vertical heat dissipation pillar structure 305-2 is connected to (or electrically coupled to) two vertical heat dissipation pillar structures 205 and is located between these two vertical heat dissipation pillar structures 205; vertical heat dissipation pillar structure 305-3 is connected to (or electrically coupled to) vertical heat dissipation pillar pads 209 located within a large shallow groove isolation zone 224. The dimensions and materials of the vertical heat dissipation column structures 305-1, 305-2 and 305-3 can be similar to those of the vertical heat dissipation column structure 205.

A vertical heat dissipation column structure/line extending along the X-axis, a vertical heat dissipation column structure/line extending along the Y-axis (or in a direction other than the X-axis), and a vertical heat dissipation column pad located within a large shallow groove isolation area can provide a vertical heat dissipation column mesh (VHDC mesh) (or "Direct Die Cooling Technology") inside the grain or semiconductor substrate and below the original semiconductor surface of the semiconductor substrate. Vertical heat dissipation column structures extending along the X-axis (i.e., horizontal vertical heat dissipation column lines) can be used to connect vertical heat dissipation column structures (i.e., vertical heat dissipation column pads) located within large shallow trench isolation areas; and vertical heat dissipation column structures extending along the Y-axis (i.e., vertical vertical heat dissipation column lines) can be used to connect vertical heat dissipation column pads or horizontal vertical heat dissipation column lines.

In some embodiments, vertical heat dissipation pillar structures extending along a non-X-axis direction, such as the vertical heat dissipation pillar structures 305-1, 305-2, and 305-3 illustrated in Figure 15a, can be manufactured through the following steps. Figures 15b to 15c are top views illustrating the fabrication structure at different stages of manufacturing the semiconductor circuit structure 300 of Figure 15a. A silicon oxide layer (not shown) and a silicon nitride layer 3206 are sequentially deposited on the semiconductor substrate. Next, a temporary active region is defined using a photolithography process, and temporary shallow groove isolation regions and large shallow groove isolation regions are defined outside the temporary active region (as shown by the dashed lines in Figure 15b). Z material is then formed within the temporary shallow groove isolation regions and the large shallow groove isolation regions. The actual active region 150A can then be defined using another photolithography process, and the removed temporary active region is used as the remaining shallow groove isolation region, as shown in Figure 15c.

The location, size, and number of vertical heat dissipation columns are not limited to those shown in Figures 14 and 15a. As mentioned above, for heat dissipation applications, the vertical heat dissipation column structure may include (or may be made of) high thermal conductivity materials, such as tungsten (with a thermal conductivity of about 170 W/mK), boron nitride (with a thermal conductivity of about 600 W/mK), and aluminum nitride (with a thermal conductivity of about 321 W/mK). Other materials with higher thermal conductivity than the original material (silicon dioxide) of the shallow groove isolation zone may also be used, such as silicon carbide, silicon germanium, undoped silicon, or deposited diamond. In some embodiments, the vertical heat dissipation column structure may include (or may be made of) a composite material comprising two or more high thermal conductivity materials. This invention can use a vertical heat dissipation column structure to replace part of the silicon dioxide in the original shallow groove isolation zone. Since the thermal conductivity of the material of the vertical heat dissipation column structure is higher than that of silicon dioxide and/or silicon, the heat dissipation capacity can be improved.

As illustrated in Figure 15a, the vertical heat dissipation pillar structure for heat dissipation can extend from some shallow groove isolation regions adjacent to the active region where the transistor is located to a large shallow groove isolation region where the vertical heat dissipation pillar pads are located (e.g., the area of the vertical heat dissipation pillar pads can be between about 4 square micrometers and 50 square micrometers). In another embodiment, all the vertical heat dissipation pillar structures can be thermally coupled together. For example, the vertical heat dissipation pillar structure located in the large shallow groove isolation region (i.e., the vertical heat dissipation pillar pad) can be thermally coupled to the vertical heat dissipation pillar structure located in the shallow groove isolation region (i.e., the vertical heat dissipation pillar line). Furthermore, a large shallow groove isolation region can be used to align with one or more thermal via plugs, as illustrated in Figure 14b. Furthermore, all or most (e.g., more than 60%, or even 70% to 90%) of the shallow groove isolation areas in the semiconductor chip can be filled by the vertical heat dissipation pillar structure provided by the present invention to achieve heat dissipation.

Figure 16a is a schematic cross-sectional view of a semiconductor circuit structure 700 illustrated according to some embodiments of this specification. The semiconductor circuit structure 700 includes an upper interconnect structure 440 located above a semiconductor substrate 400. The upper interconnect structure 440 includes contact structures 441, metal layers M1 to M3, connecting vias V1 and V2, and a dielectric layer (or a set of insulating layers) 442. Contact structures 441, metal layers M1 to M3, and connecting vias V1 and V2 are located within a dielectric layer 442, which may contain multiple sub-dielectric layers. Contact structure 441 is located between a transistor TS and metal layer M1. Metal layers M1 to M3 are sequentially located above the original semiconductor surface of the semiconductor substrate 400 along the Z-axis. Metal layers M1 to M3 are perpendicularly separated from each other. Connecting plugs V1 and V2 are located above the original semiconductor surface of the semiconductor substrate 400. Connecting plug V1 is located between metal layers M1 and M2. Connecting plug V2 is located between metal layers M2 and M3. Metal layers M1 to M3 are electrically connected to connecting plugs V1 and V2.

The semiconductor circuit structure 700 also includes a back-side through-silicon via (TSV) plug 733 located directly below and connected to the second vertical heat dissipation pillar structure 209 (i.e., the vertical heat dissipation pillar pad including the composite layer as shown in Figure 16a) within the large shallow groove isolation region 424; including a heat dissipation film 734 on the sidewall of the through-silicon via plug (TSV) 733, a barrier or isolation film 735 on the sidewall of the heat dissipation film 734, a heat dissipation plate 737 located on or near the back surface 400B of the semiconductor substrate 400 (or the back side of the wafer), and a top heat dissipation plate 739 located above the upper interconnect structure 440. The through-silicon via (TSV) 733 is used for heat dissipation and can be understood as a (backside) heat via plug. The heatsink 737 can be a heatsink made of the same material as the heatsink film 734 or the through-silicon via (TSV) 733. The through-silicon via (TSV) 733 extends from the bottom surface of the second vertical heatsink structure 209 to the back surface 400B of the semiconductor substrate 400. The through-silicon via (TSV) 733 connects the second vertical heatsink structure 209 and the heatsink 737 to form a heat dissipation path including the second vertical heatsink structure 209, the through-silicon via (TSV) 733, and the heatsink 737.

For heat dissipation, the vertical heat dissipation column structure in this embodiment may include a material with a thermal conductivity higher than that of silicon dioxide (or may be made of a material with a thermal conductivity higher than that of silicon dioxide). For example, the vertical heat dissipation column structure may include tungsten, copper, boron nitride, aluminum nitride, silicon carbide, silicon germanium, or deposited diamond, undoped silicon, or any combination of the above materials. In some embodiments, the vertical heat dissipation column structure includes a insulating material with a thermal conductivity higher than that of silicon. The through-silicon via plug (TSV) 733 may include copper, and the heat dissipation film 734 may be boron nitride or aluminum nitride.

Furthermore, the through-silicon via (TSV) 733 is directly connected to the second vertical heat dissipation pillar structure 209, which in turn is connected to the first vertical heat dissipation pillar structure 205 (i.e., the vertical heat dissipation pillar containing the composite layer as shown in Figure 16a) located in the shallow groove isolation region 414. The first vertical heat dissipation pillar structure 205 can also be connected to the transistor (e.g., the source/drain region of the transistor) via a corresponding connecting plug 431. In this way, the heat generated by the transistor can be dissipated to the through-silicon via (TSV) 733 through the connecting plug 431, the first vertical heat dissipation pillar structure 205, and the second vertical heat dissipation pillar structure 209, thereby providing a vertical heat dissipation pillar heat dissipation network with high heat dissipation efficiency. In another embodiment, the vertical heat dissipation pillar structure can be isolated from the transistor, but can achieve heat dissipation through the vertical heat dissipation pillar lines, vertical heat dissipation pillar pads, and through-silicon via plugs (TSV) 733.

The vertical heat dissipation pillar structure 205, located within and extending along the shallow groove isolation region 414, can be connected to the source or drain terminal of the transistor via a connection plug 431 located within the transistor's active region using a self-aligned or self-constructed method. The connection plug 431 is connected to the sidewall of the vertical heat dissipation pillar structure.

Traditional semiconductor circuit structures only include upper thermal via plugs in the upper interconnect structure 440, and do not include vertical heat dissipation pillar structures, especially vertical heat dissipation pillar pads. Therefore, the alignment of the upper thermal via plugs is a critical issue. Furthermore, in traditional semiconductor circuit structures, the upper thermal via plugs are located only inside the dielectric layer 442 of the upper interconnect structure 440 and are isolated by the dielectric layer 442 of the upper interconnect structure 440, and these upper thermal via plugs are far from the transistor. Therefore, the heat generated by the transistor is difficult to dissipate effectively. The semiconductor circuit structure provided in this specification provides a larger alignment window for the thermal via plugs with the help of vertical heat dissipation pillar pads. Furthermore, the vertical heat dissipation pillar structure shortens the thermal coupling path between the heat through-hole plug and the source/drain terminals of the transistor. Therefore, the configuration in this manual effectively dissipates the heat generated by the transistor.

Figure 16b is a schematic cross-sectional view of a semiconductor circuit structure 800 illustrated according to some embodiments of this specification. The semiconductor circuit structure 800 includes an upper or top thermal via plug 833 located inside the dielectric layer 442 of the upper interconnect structure 440. The upper thermal via plug 833 extends upward from the upper surface of the second vertical heat dissipation pillar structure 209 to the top heat dissipation plate 739 and penetrates the dielectric layer 442 of the upper interconnect structure 440.

Therefore, the upper heat through-hole plug 833 is connected to the second vertical heat dissipation pillar structure 209 (i.e., the vertical heat dissipation pillar washer located in the shallow groove isolation region 424), and then the second vertical heat dissipation pillar structure 209 is connected to the first vertical heat dissipation pillar structure 205 (i.e., the vertical heat dissipation pillar located in the shallow groove isolation region 414). The first vertical heat dissipation pillar structure 205 is connected to the transistor (e.g., the source/drain region of the transistor) via a corresponding connecting plug 431. Thus, the top heat dissipation plate 739, the upper heat through-hole plug 833, the first vertical heat dissipation pillar structure 205, and the second vertical heat dissipation pillar structure 209 can form a heat dissipation path to dissipate the heat generated by the transistor. In this way, the heat generated by the transistor can be dissipated to the upper heat-through-hole plug 833 through the connecting plug 431, the first vertical heat-dissipating pillar structure 205, and the second vertical heat-dissipating pillar structure 209. A high-efficiency vertical heat-dissipating pillar heat dissipation network is provided according to the direct heat cooling technology provided in this specification. In another embodiment, heat dissipation can still be achieved even when the vertical heat-dissipating pillar structure 205 (i.e., the vertical heat-dissipating pillars located in the shallow groove isolation region 414) is isolated from the transistor. In other embodiments, the upper heat-through-hole plug 833 can extend from the upper surface of the upper interconnect structure 440 to the first vertical heat-dissipating pillar structure 205. Furthermore, the material constituting the upper heat-through-hole plug 833 can be a Z material with a thermal conductivity higher than silicon or silicon dioxide, such as copper. The material constituting the upper heat vent plug 833 may be the same as or different from the material constituting the top heat sink 739.

Figure 16c is a schematic cross-sectional view of a semiconductor circuit structure 900 illustrated according to some embodiments of this specification. The difference between the semiconductor circuit structure 900 shown in Figure 16c and the semiconductor circuit structure 800 shown in Figure 16b is that the semiconductor circuit structure 900 includes an upper heat dissipation film 934 located on the sidewall of the upper heat port plug 833. The upper heat dissipation film 934 may comprise a material with a thermal conductivity higher than silicon or silicon dioxide, such as boron nitride or aluminum nitride (or may be made of such material). Providing the upper heat dissipation film 934 on the upper heat port plug 833 can improve heat dissipation efficiency.

In some embodiments, the through-silicon via (TSV) plug 733 illustrated in Figure 16a and the upper heat via plug 833 illustrated in Figure 16b (or the upper heat dissipation film 934 and upper heat via plug 833 illustrated in Figure 16c) may be combined together, as illustrated in Figure 16d. Some of the upper heat via plugs 833 extend from the upper surface of the upper interconnect structure 440 to the second vertical heat dissipation pillar structure 209 and are connected to the top heat dissipation plate 739. The through-silicon via plug (TSV) 733 (an additional heat via plug) extends from the back surface 400B of the semiconductor substrate 400 to the second vertical heat dissipation pillar structure 209 (or other vertical heat dissipation pillar structure) and is connected to the heat dissipation plate 737 located above or near the back surface 400B of the semiconductor substrate 400. This sandwich structure (a central vertical heat dissipation pillar structure within the chip, a top heat dissipation plate connected to the central vertical heat dissipation pillar structure, and a heat dissipation plate located on the back surface of the semiconductor substrate and connected to the central vertical heat dissipation pillar structure) can greatly improve the heat dissipation capability of IC chips.

Advanced 2.5D or 3D package structures, and even high-bandwidth memory (HBM) structures, involve stacking two or more IC/memory chips together. Therefore, any structure illustrated in Figures 16a through 16d can be applied to these vertically stacked IC chips. For example, as shown in Figure 16e, the vertical heat pillar structure illustrated in Figure 16e can be applied to vertically stacked chips C1 and C2. In another embodiment, chip C1 (having the vertical heat pillar structure illustrated in Figure 16b) can be flipped and then stacked on top of chip C2 (having the vertical heat pillar structure illustrated in Figure 16d), as shown in Figure 16f. Of course, another interposer (such as a silicon interposer or other interposer) can be placed between these two IC chips, and any structure shown in Figures 16a to 16d can be applied to the interposer.

Figure 17a illustrates a semiconductor circuit structure with a finned field-effect transistor and shallow groove isolation regions adjacent to (or surrounding) the finned field-effect transistor, where a portion of the shallow groove isolation regions (marked by diagonal lines) is replaced by vertical heat dissipation pillars made of tungsten. Figure 17a further illustrates the temperature distribution of the finned field-effect transistor, generated by the TCAD simulation software Sentaurus. When a portion of the shallow groove isolation regions is replaced by tungsten, the temperature difference (∆T) between the transistor peak temperature (hot spot region) and the ambient temperature (40°C) is calculated, as further illustrated in Figure 17b. The term "completely" used in Figure 17b indicates that all shallow groove isolation regions are not replaced by tungsten. The terms "1nm" to "15nm" refer to the remaining thickness of the shallow groove isolation region before it is replaced by tungsten. It is clear that the smaller the remaining thickness of the shallow groove isolation region, the smaller the temperature difference between the transistor's peak temperature and the ambient temperature (the better the heat dissipation performance). Therefore, this invention can effectively reduce the peak temperature of the transistor.

This specification provides a direct grain cooling technique (or heat dissipation structure, such as vertical heat dissipation pillars and vertical heat dissipation pillar pads located below the original semiconductor surface and within the shallow groove isolation region) based on a composite material shallow groove isolation region. Depending on requirements, some vertical heat dissipation pillar structures can be connected to the transistor, and the heat dissipation structure can be formed into a vertical heat dissipation pillar grid or heat dissipation network within the wafer or semiconductor substrate. Because the large shallow groove isolation region provides sufficient space to accommodate the vertical heat dissipation pillar pads, it offers greater misalignment tolerance and shortens the path for connecting back-side through-silicon via (TSV) plugs to the vertical heat dissipation pillar grid, thereby improving IR drop in signal transmission and enhancing heat dissipation performance.

It is worth noting that the above structures and methods are provided only to illustrate the technical features of the present invention. The technical content of this specification is not limited to the above structures and methods. Other embodiments with different configurations of known components can be applied. The illustrated structures can be adjusted and modified according to the needs of actual applications. Of course, it should be noted that the configurations shown in the accompanying figures are for illustration only and are not intended to limit the present invention. Therefore, those skilled in the art will understand that the relevant components and layers in a semiconductor structure, the shape or positional relationship of the components, and the process details can be adjusted or modified according to actual needs and/or actual applications.

Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the art may make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended patent claims.

101: Silicon oxide thin layer 102: First silicon nitride thin layer 103: Active region 201: Shallow groove isolation region 301: Second silicon nitride thin layer 401: Silicon oxide thin layer 403: Third silicon nitride thin layer 601: Hollow tunnel region 701: Silicon oxide layer 702: Z material 801: Silicon oxide 1101: Gate metal region 1102: High dielectric constant dielectric layer 1103: Source region 1104: Drain region 200: Semiconductor circuit structure 205: Vertical heat dissipation pillar structure 209: Vertical heat dissipation pillar structure 214: Horizontal shallow groove isolation area; 214-1 to 214-4: Shallow groove isolation area; 220A-1: Active area; 220A: Active area; 220B: Shallow groove isolation area; 220C: Solder pad opening layer; 224: Large shallow groove isolation area; 224-1 to 224-4: Large shallow groove isolation area; 300: Semiconductor circuit structure; 314-1, 314-2, 314-3: Shallow groove isolation area; 305-1, 305-2, 305-3: Vertical heat dissipation pillar structure; 400: Semiconductor substrate; 400B: Back side surface; 414: Shallow groove isolation area. 424: Large shallow groove isolation area; 431: Connector plug; 440: Upper internal interconnect structure; 441: Contact structure; 442: Dielectric layer; 700: Semiconductor circuit structure; 733: Through-silicon via plug; 734: Heat dissipation film; 735: Barrier or isolation film; 737: Heat dissipation plate; 739: Top heat dissipation plate; 800: Semiconductor circuit structure; 833: Upper heat via plug; 900: Semiconductor circuit structure; 934: Upper heat dissipation film; 12c: Tangent; 6b-6b’: Tangent; 6c-6c’: Tangent; OSS: Raw semiconductor surface; t1: Depth; t2: Depth; t3: Thickness; M1-M3: Metal layer; V1, V2: Connector plug; C1, C2: Wafer.

Figure 1a is a top view of a conventional semiconductor circuit structure with shallow groove isolation regions and active regions; Figure 1b is a top view of a portion of the structure in Figure 1a; Figure 1c is a cross-sectional view of the structure in Figure 1a; Figure 2 (including Figures 2a and 2b) are top and cross-sectional views of the fabrication structure after the formation of the active regions and shallow groove isolation regions, respectively; Figure 3 (including Figures 3a and 3b) are top and cross-sectional views of the fabrication structure after the formation of a nitride protection region above the center of the active region, respectively; Figure 4 (including Figures 4a and 4b) are top and cross-sectional views of the fabrication structure after the formation of vertical gap walls to cover the exposed silicon sidewalls, respectively; Figure 5 Figures 5a and 5b (including Figures 5a and 5b) show the top view and cross-sectional view of the process structure after the deeper silicon sidewalls are exposed, respectively; Figure 6 (including Figures 6a, 6b, and 6c) shows the top view and cross-sectional view of the process structure after the vacant tunnel regions are formed, respectively; Figure 7 (including Figures 7a and 7b) shows the top view and cross-sectional view of the process structure after the high thermal dissipation material is deposited, respectively; Figure 8 (including Figures 8a and 8b) shows the formation of the Horizontal Heat-Dissipation Plate (HHDP) and the Vertical Heat-Dissipation Column (VHDC), respectively. The following are top and cross-sectional views of the manufacturing process structure; Figure 9 (including Figures 9a and 9b) is a top and cross-sectional view of the manufacturing process structure after the formation of the horizontal heat dissipation plate and the vertical heat dissipation pillar, respectively, according to another embodiment; Figure 10 is a structural diagram after the horizontal heat dissipation plate and the vertical heat dissipation pillar are connected and extended to the edge of the wafer/die; Figure 11 is a structural diagram of a cool transistor (CQT) according to the present invention; Figures 12a and 12b are cross-sectional views of the vertical heat dissipation pillar structure according to different embodiments of the present invention; Figure 12c is a structural diagram after the vertical heat dissipation pillar shown in Figure 12b is extended to the edge of the wafer/die, according to another embodiment. Figure 13 is a schematic diagram of another transistor cooling structure illustrated in Figure 12b; Figure 14a is a top view of a semiconductor circuit structure illustrated in some embodiments of this specification; Figure 14b is a top view of a semiconductor circuit structure illustrated in some embodiments of this specification; Figure 15a is a top view of a semiconductor circuit structure illustrated in some embodiments of this specification; Figures 15b to 15c are top views of the fabrication structure at different stages of fabricating the semiconductor circuit structure of Figure 15a; Figures 16a to 16f are schematic cross-sectional views of different semiconductor circuit structures illustrated in some embodiments of this specification; Figure 17a shows the temperature distribution of a finned field-effect transistor (FinFET) created by the TCAD simulation software Sentaurus; and Figure 17b shows the relationship between temperature difference and the thickness of the shallow groove isolation region.

101: Silicon oxide thin layer; 102: First silicon nitride layer; 201: Shallow groove isolation region; 401: Silicon oxide thin layer; 801: Silicon oxide; 701: Silicon oxide layer; 702: Z material; t2: Depth; t3: Thickness

Claims (23)

A semiconductor circuit structure includes: a semiconductor substrate having an original semiconductor surface (OSS); a set of active regions located in the semiconductor substrate; and a first shallow groove isolation region (STI) adjacent to the set of active regions and extending along a first direction to a spare shallow groove isolation region; the spare shallow groove isolation region being remote from the set of active regions; wherein the first shallow groove isolation region includes a heat removing layer, and the material of the heat removing layer is different from silicon dioxide ( _SiO2 ). The semiconductor circuit structure as described in claim 1, wherein the thermal conductivity of the heat dissipation layer is higher than that of silicon dioxide. The semiconductor circuit structure as described in claim 2, wherein the heat dissipation layer is an electrical insulator during an operation of the semiconductor circuit structure. The semiconductor circuit structure as described in claim 2, wherein the heat dissipation layer extends into one of the active regions of the group. The semiconductor circuit structure as described in claim 2, wherein the heat dissipation layer includes a metal layer and an insulating thin layer located between the metal layer and the set of active regions. The semiconductor circuit structure as described in claim 2, wherein the heat dissipation layer comprises a composite material. The semiconductor circuit structure as described in claim 2, wherein the first shallow groove isolation region further includes a silicon dioxide layer located below the heat dissipation layer. The semiconductor circuit structure as described in claim 1, wherein the heat dissipation layer is located within a front end of line (FEOL) region of the semiconductor circuit structure. The semiconductor circuit structure as described in claim 1, wherein the first shallow groove isolation region surrounds the set of active regions. The semiconductor circuit structure as described in claim 9, wherein the heat dissipation layer is located in the first shallow groove isolation region and below the original semiconductor surface, and the heat dissipation layer surrounds a peripheral border of the set of active regions. The semiconductor circuit structure as described in claim 1, wherein the backup shallow groove isolation region is connected to the first shallow groove isolation region, and the heat dissipation layer extends to the backup shallow groove isolation region along the first direction. The semiconductor circuit structure as described in claim 11, wherein the backup shallow groove isolation region is located near a center of the semiconductor substrate or near a peripheral portion of the semiconductor substrate. The semiconductor circuit structure as described in claim 11 further includes a row of heat removing pads located within the backup shallow groove isolation area, and the heat removal layer is connected to the row of heat removing pads. The semiconductor circuit structure as described in claim 13 further includes a thermal via located above the standby shallow groove isolation area and connected to the heat sink located within the standby shallow groove isolation area. The semiconductor circuit structure as described in claim 14 further includes a heat dissipation plate located above and connected to the heat via plug. The semiconductor circuit structure as described in claim 14 further includes a plurality of insulators located above the set of active regions, wherein the thermal via plug penetrates the plurality of insulators and is connected to the row of thermally soldered pads located in the backup shallow groove isolation region. The semiconductor circuit structure as described in claim 16, wherein the plurality of insulators and the thermal via plug are located within a back end of line (BEOL) region of the semiconductor circuit structure. The semiconductor circuit structure as described in claim 13 further includes a through semiconductor via (TSV) extending from a back surface of the semiconductor substrate to a bottom surface of the heat sink located within the spare shallow groove isolation area, wherein the back surface and the original semiconductor surface are located on opposite sides. The semiconductor circuit structure as described in claim 18 further includes a heat dissipation plate located below the back surface of the semiconductor substrate and connected to the semiconductor via plug. As described in claim 18, the first shallow groove isolation region surrounds the four sidewalls of one of the active regions. A semiconductor circuit structure includes: a semiconductor substrate having a raw semiconductor surface; a first set of active regions located in the semiconductor substrate and extending along a first direction; a second set of active regions located in the semiconductor substrate and extending along the first direction; and a first shallow groove isolation region located between the first set of active regions and the second set of active regions, extending along the first direction to a backup shallow groove isolation region away from the first set of active regions and the second set of active regions; wherein the first shallow groove isolation region includes a row of heat-dissipating layers extending along the first direction, and the thermal conductivity of the heat-dissipating layers is higher than that of silicon dioxide. The semiconductor circuit structure as described in claim 21, wherein the backup shallow groove isolation region is connected to the first shallow groove isolation region, and includes a row of hot solder pads located in the backup shallow groove isolation region, wherein the row of hot solder pads is connected to the row of hot solder pads. The semiconductor circuit structure as described in claim 22, wherein the width of the heat sink is greater than the width of the heat sink layer.