TWI907830B - Input circuit for artificial neural network array and operating methods thereof - Google Patents

Abstract

Numerous examples are disclosed of input circuitry and associated methods in an artificial neural network. In one example, a system comprises a plurality of address decoders to receive an address and output a plurality of row enabling signals in response to the address; a first plurality of registers to store, sequentially, activation data in response to the plurality of row enabling signals; and a second plurality of registers to store, in parallel, activation data received from the first plurality of registers.

Description

Input circuit and its operation method for artificial neural network arrays

This application claims priority to U.S. Patent Application No. 18/077,686, filed December 8, 2022, entitled "Input Circuit for Artificial Neural Network Array," and U.S. Provisional Application No. 63/409,140, filed September 22, 2022, entitled "Input and Output Circuits for Parallel and Pipeline Operation in Artificial Neural Network Array."

Numerous examples of input circuit systems and related methods are disclosed to implement parallel and pipelined operation in artificial neural networks.

Artificial neural networks are analogous to biological neural networks (the central nervous system of animals, especially the brain) and are used to estimate or approximate functions that depend on large amounts of input and are often unknown. Artificial neural networks typically consist of layers of interconnected "neurons" that exchange information with each other.

Figure 1 illustrates an artificial neural network, where circles represent neuron inputs or layers. Connections (called synapses) are represented by arrows and have numerical weights that can be tuned based on experience. This allows the neural network to adapt to inputs and learn. Typically, a neural network consists of one layer with multiple inputs. There are typically one or more intermediate neuron layers and output neuron layers that provide the network's outputs. Each neuron makes decisions individually or collectively based on data received from synapses.

One of the major challenges in developing artificial neural networks for high-performance information processing is the lack of sufficient hardware technology. Practical neural networks rely on a vast number of synapses to achieve high connectivity between neurons, i.e., extremely high computational parallelism. In principle, this complexity can be achieved using digital supercomputers or dedicated clusters of graphics processing units. However, in addition to high cost, these methods are also plagued by mundane energy efficiency compared to biological networks, mainly because biological networks perform low-precision analog computations and therefore consume far less energy. CMOS analog circuits have been used in artificial neural networks, but given the large number of neurons and synapses, most CMOS implementations have excessively large synapses.

The applicant previously disclosed an artificial (analog) neural network utilizing one or more nonvolatile memory arrays as synapses in U.S. Patent Application Publication 2017/0337466A1, which is incorporated herein by reference. The nonvolatile memory arrays operate as analog neural memory and include nonvolatile memory cells arranged in columns and rows. The neural network includes: a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs from the first plurality of inputs; and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses include a plurality of memory cells, each of which includes: a source region and a drain region formed in a semiconductor substrate and spaced apart, and a channel region extending between the source and drain regions; a floating gate disposed above and insulated from a first portion of the channel region; and a non-floating gate disposed above and insulated from a second portion of the channel region. Each of the plurality of memory cells stores a weighted value corresponding to the number of electrons on the floating gate. The plurality of memory cells multiply the first plurality of inputs by the stored weighted values to generate the first plurality of outputs.

Non-volatile memory cells:

Non-volatile memory is well known. For example, U.S. Patent 5,029,130 (“130 Patent”), incorporated herein by reference, discloses a separate gate non-volatile memory cell array, which is a type of flash memory cell. This memory cell 210 is shown in Figure 2. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, wherein a channel region 18 is located between the source region and the drain region. A floating gate 20 is formed above and insulated from (and controls the conductivity of) a first portion of the channel region 18, and is also formed above a portion of the source region 14. A character line terminal 22 (generally coupled to a character line) has: a first portion disposed above and insulated from (and controlling the conductivity of) a second portion of the channel region 18; and a second portion extending upward above the floating gate 20. The floating gate 20 and the character line terminal 22 are insulated from the substrate 12 by a gate oxide. A bit line 24 is coupled to the drain region 16.

Memory cell 210 is erased by applying a high positive voltage to word line terminal 22 (whereby electrons are removed from the floating gate). This causes electrons on the floating gate 20 to tunnel through the Fowler-Nordheim (FN) tunnel from the floating gate 20 through the intermediate insulation to the word line terminal 22.

Memory cell 210 is programmed via source-side injection (SSI) with hot electrons (where electrons are placed on the floating gate) by applying a positive voltage to word line terminals 22 and a positive voltage to source region 14. Electron current flows from drain region 16 towards source region 14. When electrons reach the gap between word line terminals 22 and floating gate 20, they are accelerated and heated. Due to the attractive electrostatic force from floating gate 20, some of the heated electrons are injected into floating gate 20 via gate oxide.

Memory cell 210 reads data by applying a positive read voltage to drain region 16 and word line terminal 22 (this opens a portion of channel region 18 below the word line terminal). If float gate 20 is positively charged (i.e., electrons are erased), the portion of channel region 18 below float gate 20 is also open, and current flows through channel region 18; this is sensed as erased or a "1" state. If float gate 20 is negatively charged (i.e., electronically programmed), the portion of channel region below float gate 20 is almost or completely closed, and current does not flow through channel region 18 (or flows very little); this is sensed as programmed or a "0" state.

Table 1 depicts the typical voltage and current ranges that can be applied to the terminals of memory cell 210 for performing read, erase, and programmed operations:

Other isolated gate memory cell configurations are known, which are other types of flash memory cells. For example, Figure 3 depicts a quad-gate memory cell 310, including a source region 14, a drain region 16, a floating gate 20 above a first portion of a channel region 18, a selection gate 22 above a second portion of the channel region 18 (typically coupled to a word line WL), a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is depicted in U.S. Patent 6,747,310, which is incorporated herein by reference for all purposes. Here, except for the floating gate 20, all gates are non-floating gates, meaning that these gates are electrically connected or can be electrically connected to a voltage source. Programming is performed by injecting heated electrons from channel region 18 into the floating gate 20. Erasure is performed by tunneling electrons from the floating gate 20 to the erasure gate 30.

Table 2 depicts the typical voltage and current ranges that can be applied to the terminals of memory cell 310 for performing read, erase, and programmed operations:

Figure 4 depicts a three-gate memory cell 410, another type of flash memory cell. Memory cell 410 is identical to memory cell 310 in Figure 3, except that it does not have a separate control gate. Erasure operations (and thus erasure via the erase gate) and read operations are similar to those in Figure 3, except that no control gate bias is applied. Programming operations are also performed without a control gate bias, and therefore, a higher voltage is applied to the source line during programming operations to compensate for the lack of a control gate bias.

Table 3 depicts the typical voltage and current ranges that can be applied to the terminals of memory cell 410 for performing read, erase, and programmed operations:

Figure 5 depicts a stacked gate memory cell 510, which is another type of flash memory cell. Memory cell 510 is similar to memory cell 210 in Figure 2, except that the floating gate 20 extends over the entire channel area 18, and the control gate 22 (which will be coupled to the character line here) extends over the floating gate 20, separated by an insulating layer (not shown). The erasure is accomplished by electron tunneling from the source region (FG) to the substrate via the source region (FN). This is programmed by hot channel electron (CHE) injection in the region between the channel region 18 and the drain region 16, and by electron flow from the source region 14 to the drain region 16. The read operation is similar to that for reading memory cells 210 with higher control gate voltages.

Table 4 depicts the typical voltage ranges that can be applied to the terminals of memory cell 510 and substrate 12 for performing read, erase, and programmed operations:

The methods and techniques described herein can be applied to other non-volatile memory technologies, such as FinFET gate flash or stacked gate flash memory, NAND flash, SONOS (silicon oxide-nitride-oxide-silicon, charge trapping in nitrides), MONOS (metal oxide-nitride-oxide-silicon, metal charge trapping in nitrides), ReRAM (resistive RAM), PCM (phase change memory), MRAM (magnetic RAM), FeRAM (ferroelectric RAM), CT (charge trapping) memory, CN (carbon nanotube) memory, OTP (two- or multi-level one-time programmable) and CeRAM (correlated electronic RAM), but are not limited thereto.

To utilize a memory array containing one of the nonvolatile memory cell types described above in artificial neural networks, two modifications are made. First, the lines are configured such that each memory cell can be individually programmed, erased, and read without adversely affecting the memory state of other memory cells in the array, as explained further below. Second, continuous (analogous) programming of memory cells is provided.

Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can independently and continuously change from a completely erased state to a fully programmed state, and vice versa, with minimal interference to other memory cells. This means that the cell memory can effectively analog to or at least store one of many discrete values (e.g., 16 or 64 different values), allowing for extremely precise and individual tuning of all memory cells in the memory array, and making the memory array ideal for storing and finely tuning the synaptic weights of neural networks.

Neural networks employing non-volatile memory cell arrays:

Figure 6 conceptually illustrates a non-limiting example of a neural network utilizing a non-volatile memory array, as described in this invention. This example uses a non-volatile memory array neural network for a face recognition application, but any other suitable application can be implemented using a neural network based on a non-volatile memory array.

S0 is the input layer. In this example, the input layer is a 32×32 pixel RGB image with 5-bit accuracy (i.e., three 32×32 pixel arrays, one array for each color R, G, and B, with each pixel having 5-bit accuracy). In some cases, different weight sets are applied to the synapses CB1 from the input layer S0 into the input layer C1, while in others, the weights are shared and the input image is scanned with a 3×3 pixel overlay filter (core), shifting the filter by 1 pixel (or more than 1 pixel, as specified by the model). Specifically, the values of nine pixels in the 3×3 portion of the image (i.e., the filter or core) are provided to synapse CB1, where these nine input values are multiplied by appropriate weights, and after summing the multiplied outputs, a single output value is determined and provided by the first synapse of CB1 for the generation of one of the feature maps of layer C1. The 3×3 filter is then shifted one pixel to the right within the input layer S0 (i.e., a row of three pixels is added on the right and a row of three pixels is discarded on the left), thereby providing the nine pixel values in this newly positioned filter to synapse CB1, where these pixel values are multiplied by the same weights, and a second single output value is determined by the relevant synapse. This procedure continues for all three colors and for all bits (accuracy values) until the 3×3 filter scans the entire 32×32 pixel image of the input layer S0. The procedure is then repeated using different weight sets to generate different feature maps for layer C1 until all feature maps for layer C1 have been calculated.

In this example, there are 16 feature maps in layer C1, each with 30×30 pixels. Each pixel is extracted from the new feature pixel obtained by multiplying the input by the kernel, and therefore each feature map is a two-dimensional array. Thus, in this example, layer C1 constitutes 16 layers of two-dimensional arrays (it should be noted that the terms "layer" and "array" as used herein are logical relationships, not necessarily entity relationships—that is, the array is not necessarily oriented within a real two-dimensional array). Each of the 16 feature maps in layer C1 is generated from one of sixteen different sets of synaptic weights applied to the filter scan. The C1 feature maps can all target different variations of the same image feature, such as boundary recognition. For example, a first image (generated using a first set of weights, which are shared by all scans that generated this first image) can identify circular edges, while a second image (generated using a second set of weights different from the first set) can identify rectangular edges, or the aspect ratio of certain features, etc.

The excitation function P1 (pooling) is applied before entering layer S1 from layer C1. Its pooling values are derived from the values of consecutive, non-overlapping 2×2 regions in each feature map. For example, the purpose of the pooling function P1 is to take the average of nearby locations (or a max function could also be used) to reduce the dependency at edge locations and reduce the data size before moving to the next stage. At layer S1, there are 16 15×15 feature maps (i.e., sixteen different arrays, each with 15×15 pixels). The synapse CB2, which allows entry from layer S1 into layer C2, scans the map in layer S1 using a 4×4 filter, with the filter shifted by one pixel. At layer C2, there are 22 12×12 feature maps. The activation function P2 (pooling) is applied before entering layer S2 from layer C2, and its pooling value comes from the values of consecutive, non-overlapping 2×2 regions in each feature map. At layer S2, there are 22 6×6 feature maps. The activation function (pooling) is applied at the synapse CB3 between layer S2 and layer C3, where each neuron in layer C3 is connected to each feature map in layer S2 via individual synapses in CB3. At layer C3, there are 64 neurons. The synapse CB4 between layer C3 and the output layer S3 completely connects C3 to S3; that is, each neuron in layer C3 is connected to every neuron in layer S3. The output at layer S3 comprises 10 neurons, with the highest output neuron determining the category. This output can, for example, indicate the identification or classification of the content of the original image.

Each layer of a synapse is implemented using arrays or portions of arrays of nonvolatile memory cells.

Figure 7 is a block diagram of an array that can be used for this purpose. The Vector Multiplication Matrix Multiplication (VMM) array 32 includes non-volatile memory cells and serves as synapses between layers (such as CB1, CB2, CB3, and CB4 in Figure 6). Specifically, the VMM array 32 includes a non-volatile memory cell array 33, an erase gate and character line gate decoder 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, which decode the respective inputs of the non-volatile memory cell array 33. The inputs to the VMM array 32 can come from the erase gate and character line gate decoder 34 or from the control gate decoder 35. In this example, the source line decoder 37 also decodes the output of the non-volatile memory cell array 33. Alternatively, the bit line decoder 36 can decode the output of the non-volatile memory cell array 33.

The non-volatile memory cell array 33 serves two purposes. First, it stores the weights to be used by the VMM array 32. Second, the non-volatile memory cell array 33 efficiently multiplies the inputs by the weights stored in it and adds them along the output lines (source lines or bit lines) to produce an output that will serve as the input to the next layer or the final layer. By performing multiplication and addition functions, the non-volatile memory cell array 33 eliminates the need for separate multiplication and addition logic circuits and is also power efficient due to its in-situ memory computation.

The output of the nonvolatile memory cell array 33 is supplied to a differential summator (such as a summing operational amplifier or a summing current mirror) 38, which sums the output of the nonvolatile memory cell array 33 to produce a single value for the convolution. The differential summator 38 is configured to perform summation of positive and negative weights.

The summed output of the differential summer 38 is then supplied to the excitation function block 39, which corrects the output. The excitation function block 39 can provide a sigmoid, hyperbolic tangent, or ReLU function. The corrected output of the excitation function block 39 becomes an element of the feature map of the next layer (e.g., C1 in Figure 6), and is then applied to the next synapse to produce the next feature map layer or the final layer. Therefore, in this example, the nonvolatile memory cell array 33 constitutes a plurality of synapses (which receive input from the preceding neuronal layer or from an input layer, such as an image database), and the operational amplifier 38 and the excitation function block 39 together constitute a plurality of neurons.

The inputs to the VMM array 32 in Figure 7 (WLx, EGx, CGx, and optionally BLx and SLx) can be analog, binary, or digital (in which case the DAC is configured to convert digital bits to the appropriate input analog level), and the outputs can be analog, binary, or digital (in which case the output ADC is configured to convert the output analog level to digital bits).

Figure 8 is a block diagram depicting the use of the multiple layers of VMM array 32, denoted here as VMM arrays 32a, 32b, 32c, 32d, and 32e. As shown in Figure 8, the input represented as Inputx is converted from digital to analog by a digital-to-analog converter 31 and provided to the input VMM array 32a. The converted analog input can be voltage or current. The input D/A conversion of the first layer can be performed by using a function or lookup table (LUT) that maps the input Inputx to the appropriate analog level for the matrix multiplier of the input VMM array 32a. Input conversion can also be accomplished using an analog-to-analog (A/A) converter to convert external analog inputs to mapped analog inputs to the input VMM array 32a.

The output generated by the input VMM array 32a is set to the input of the next VMM array (hidden bit level 1) 32b, which in turn generates an output, which is set to the input of the next VMM array (hidden bit level 2) 32c, and so on. The various layers of the VMM array 32 serve as different synaptic layers and neuron layers of a convolutional neural network (CNN). Each VMM array 32a, 32b, 32c, 32d, and 32e can be a single physical nonvolatile memory array, or multiple VMM arrays can utilize different portions of the same physical nonvolatile memory array, or multiple VMM arrays can utilize overlapping portions of the same physical nonvolatile memory array. The example shown in Figure 8 contains five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c), and two fully interconnected layers (32d, 32e). Those with ordinary knowledge in the relevant technical field should understand that this is merely an example, and the system may alternatively contain more than two hidden layers and more than two fully connected layers.

Vector Matrix Multiplication (VMM) array:

Figure 9 depicts a neuronal VMM array 900, which is particularly suitable for memory cells 310 as shown in Figure 3, and serves as a portion of the synapses and neurons between the input layer and the next layer. The VMM array 900 includes a memory array 901 of nonvolatile memory cells and a reference array 902 of nonvolatile reference memory cells (at the top of the array). Alternatively, another reference array may be placed at the bottom.

In the VMM array 900, control gate lines, such as control gate line 903, extend vertically (therefore, the reference array 902 in the column direction is orthogonal to control gate line 903), and erased gate lines, such as erased gate line 904, extend horizontally. Here, the inputs to the VMM array 900 are set on the control gate lines (CG0, CG1, CG2, CG3), and the outputs of the VMM array 900 appear on the source lines (SL0, SL1). In one example, only even-numbered columns are used, and in another example, only odd-numbered columns are used. The current placed on each source line (SL0, SL1, etc.) is summed against all currents from memory cells connected to that particular source line.

As described in this paper regarding neural networks, the non-volatile memory cells of the VMM array 900, namely memory cells 310 of the VMM array 900, can be configured to operate in subcritical regions.

The nonvolatile reference memory cells and nonvolatile memory cells described in this article are biased in weak reversal (subcritical region): in

Where Ids is the drain-to-source current; Vg is the gate voltage on the memory cell; Vth is the critical voltage of the memory cell; Vt is the thermoelectric pressure = k*T/q, where k is the Boltzmann constant, T is the temperature in Kelvin, and q is the electron charge; n is the slope factor = 1 + (Cdep/Cox), where Cdep = the capacitance of the depletion layer, and Cox is the capacitance of the gate oxide layer; Io is the memory cell current at the gate voltage equal to the critical voltage, and Io is the sum of (Wt/L)*u*Cox*(n-1)*Vt The ratio is ² , where u is the carrier migration rate of the memory cell, and Wt and L are the width and length of the memory cell, respectively.

For an I-to-V logarithmic converter that uses memory cells (such as reference memory cells or peripheral memory cells) or transistors to convert input current into input voltage: Vg = n * Vt * log[Ids/wp * Io]

Where wp represents the w in the reference or peripheral memory cell.

For a memory array used as a vector matrix multiplier (VMM) array with current input, the output current is: , that is, Iout=(wa/wp)* Iin=W * Iin

Here, wa = w of each memory cell in the memory array.

Vthp is the effective critical voltage of the peripheral memory cell, and Vtha is the effective critical voltage of the main (data) memory cell. It should be noted that the critical voltage of the transistor is a function of the substrate bias voltage, and the substrate bias voltage, expressed as Vsb, can be modulated to compensate for various conditions at this temperature. The critical voltage Vth can be expressed as: Vth = Vth0 + γ(SQRT｜Vsb - 2*φF) - SQRT｜2*φF｜)

Where Vth0 is the critical voltage with zero substrate bias, φF is the surface potential, and γ is the host effect parameter.

Character lines or control gates can be used to input memory cells that operate on the input voltage.

Alternatively, the flash memory cells of the VMM array described herein can be configured to operate in a linear region: Ids = β*(Vgs - Vth)*Vds; β = u*Cox* _Wt /LW = α(Vgs - Vth)

This means that the weight W in the linear region is proportional to (Vgs - Vth).

Character lines, control gates, bit lines, or source lines can be used as inputs to memory cells operating in the linear region. Bit lines or source lines can be used as outputs to memory cells.

For I-to-V linear converters, memory cells (e.g., reference memory cells or peripheral memory cells) or transistors operating in the linear region can be used to linearly convert input/output currents into input/output voltages.

Alternatively, the memory cells of the VMM array described herein can be configured to operate in saturation regions: β=u*Cox*Wt/L

Wα(Vgs-Vth) ² means that the weight W is proportional to (Vgs-Vth) ² .

Character lines, control gates, or erase gates can be used as inputs to memory cells operating in the saturation region. Bit lines or source lines can be used as outputs to output neurons.

Alternatively, the memory cells of the VMM array described herein can be used in all regions or combinations thereof (subcritical regions, linear regions, or saturation regions) of each or more layers of a neural network.

Further examples of the VMM array 32 in Figure 7 are described in U.S. Patent No. 10,748,630, which is incorporated herein by reference. As described in that application, source lines or bit lines can be used as neural outputs (current summation outputs).

Figure 10 depicts a neuronal VMM array 1000, which is particularly suitable for memory cells 210 as shown in Figure 2 and serves as a synapse between an input layer and the next layer. The VMM array 1000 includes a memory array 1003 of nonvolatile memory cells, a reference array 1001 of first nonvolatile reference memory cells, and a reference array 1002 of second nonvolatile reference memory cells. The reference arrays 1001 and 1002, arranged in the row direction of the array, are used to convert current inputs flowing to terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second nonvolatile reference memory cells are diode-connected through-type multiplexers 1014 (partially depicted), in which current input flows into these multiplexers. The reference cells are tuned (e.g., programmed) to a target reference level. The target reference level is provided by a reference miniature array matrix (not shown).

The memory array 1003 serves two purposes. First, it stores the weights used by the VMM array 1000 in each of its individual memory cells. Second, the memory array 1003 effectively multiplies the inputs (i.e., the current inputs provided in terminals BLR0, BLR1, BLR2, and BLR3, which are converted into input voltages by reference arrays 1001 and 1002 to supply word lines WL0, WL1, WL2, and WL3) by the weights stored in the memory array 1003, and then adds all the results (memory cell currents) to produce an output on the respective bit lines (BL0-BLN), which will be the input to the next layer or the input to the final layer. By performing multiplication and addition functions, the memory array 1003 eliminates the need for separate multiplication and addition logic circuits and is also power-efficient. Here, voltage inputs are provided on word lines WL0, WL1, WL2, and WL3, and outputs are presented on their respective bit lines BL0-BLN during read (inference) operations. The current on each of the bit lines BL0-BLN performs an aggregator function on the current from all non-volatile memory cells connected to that particular bit line.

Table 5 depicts the operating voltages and currents used in the VMM array 1000. The row indicators in the table are located at the following voltages: word lines for selected cells, word lines for unselected cells, bit lines for selected cells, bit lines for unselected cells, source lines for selected cells, and source lines for unselected cells. The column indicators are for read, erase, and programming operations.

Table 5: Operation of VMM array 1000 in Figure 10:

Figure 11 depicts a neuronal VMM array 1100, which is particularly suitable for memory cells 210 as shown in Figure 2, and serves as a portion of synapses and neurons between the input layer and the next layer. The VMM array 1100 includes a memory array 1103 of nonvolatile memory cells, a reference array 1101 of first nonvolatile reference memory cells, and a reference array 1102 of second nonvolatile reference memory cells. Reference arrays 1101 and 1102 extend in the column direction of the VMM array 1100. The VMM array is similar to VMM 1000, except that in the VMM array 1100, the character lines extend in the vertical direction. Here, inputs are provided on character lines (WLA0, WLB0, WLA1, WLB1, WLA2, WLB2, WLA3, WLB3), and outputs are presented on source lines (SL0, SL1) during read operations. The current on each source line is summed against all currents from the memory cells connected to that particular source line.

Table 6 depicts the operating voltages and currents used in the VMM array 1100. The row indicators in the table are located at the following voltages: word lines for selected cells, word lines for unselected cells, bit lines for selected cells, bit lines for unselected cells, source lines for selected cells, and source lines for unselected cells. The column indicators are for read, erase, and programming operations.

Figure 12 depicts a neuronal VMM array 1200, which is particularly suitable for memory cells 310 as shown in Figure 3, and serves as a portion of synapses and neurons between the input layer and the next layer. The VMM array 1200 includes a memory array 1203 of nonvolatile memory cells, a reference array 1201 of first nonvolatile reference memory cells, and a reference array 1202 of second nonvolatile reference memory cells. Reference arrays 1201 and 1202 are used to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In practice, the first and second non-volatile reference memory cells are diode-connected through-multiplexers 1212 (partially shown), with current input flowing into these multiplexers via BLR0, BLR1, BLR2, and BLR3. Each multiplexer 1212 includes its own multiplexer 1205 and an overlay transistor 1204 to ensure a constant voltage on the bit lines (e.g., BLR0) of each of the first and second non-volatile reference memory cells during read operations. The reference cell is tuned to a target reference level.

The memory array 1203 serves two purposes. First, it stores the weights to be used by the VMM array 1200. Second, the memory array 1203 effectively multiplies the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, wherein reference arrays 1201 and 1202 convert these current inputs into input voltages to supply to the control gates (CG0, CG1, CG2, and CG3)) by the weights stored in the memory array, and then adds all the results (cell currents) to produce an output, which is displayed on BL0-BLN and will be the input to the next layer or to the final layer. By performing multiplication and addition functions, the memory array eliminates the need for separate multiplication and addition logic circuits and is also power-efficient. Here, inputs are provided on control gate lines (CG0, CG1, CG2, and CG3), and outputs are presented on bit lines (BL0-BLN) during read operations. The current on each bit line is summed against all currents from the memory cells connected to that particular bit line.

The VMM array 1200 performs unidirectional modulation on the non-volatile memory cells in the memory array 1203. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge is reached on the floating gate. If excessive charge is placed on the floating gate (causing an error value to be stored in the cell), the cell is erased and the sequence of partially programmed operations restarts. As shown, two columns sharing the same erase gate (such as EG0 or EG1) are erased together (this is called page erasure), and thereafter, each cell is partially programmed until the desired charge is reached on the floating gate.

Table 7 depicts the operating voltages and currents used in the VMM array 1200. The row indicators in this table are placed on the following voltages: word lines for selected cells, word lines for unselected cells, bit lines for selected cells, bit lines for unselected cells, control gate for selected cells, control gate for unselected cells in the same segment as the selected cell, control gate for unselected cells in a different segment from the selected cell, erase gate for selected cells, erase gate for unselected cells, source lines for selected cells, and source lines for unselected cells. The column indicators show the read, erase, and programmed operations.

Figure 13 depicts a neuronal VMM array 1300, which is particularly suitable for memory cells 310 as shown in Figure 3, and serves as a portion of synapses and neurons between the input layer and the next layer. The VMM array 1300 includes a memory array 1303 of nonvolatile memory cells, a reference array 1301 of first nonvolatile reference memory cells, and a reference array 1302 of second nonvolatile reference memory cells. EG lines EGR0, EG0, EG1, and EGR1 extend vertically, while CG lines CG0, CG1, CG2, and CG3 and WL lines WL0, WL1, WL2, and WL3 extend horizontally. VMM array 1300 is similar to VMM array 1200, except that VMM array 1300 implements bidirectional tuning. Because it uses a separate EG line, each individual cell can be completely erased, partially programmed, or partially erased as needed to achieve the required charge on the floating gate. As shown, reference arrays 1301 and 1302 convert the input current in terminals BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 to be applied to the memory cells in the column direction (through the operation of multiplexer 1314 via diode-connected reference cells). The current output (neuron) is located in bit lines BL0-BLN, where each bit line sums all currents from non-volatile memory cells connected to that specific bit line.

Table 8 depicts the operating voltages and currents used in the VMM array 1300. The row indicators in this table are located at the voltages for each of the following: word lines for selected cells, word lines for unselected cells, bit lines for selected cells, bit lines for unselected cells, control gate for selected cells, control gate for unselected cells in the same segment as the selected cell, control gate for unselected cells in a different segment from the selected cell, erase gate for selected cells, erase gate for unselected cells, source lines for selected cells, and source lines for unselected cells. The column indicators show the read, erase, and programmable operations.

Figure 22 depicts a neuronal VMM array 2200, which is particularly suitable for memory cell 210 as shown in Figure 2, and serves as a portion of synapses and neurons between the input layer and the next layer. In the VMM array 2200, inputs INPUT ₀ , ..., INPUT _N are received on bit lines BL ₀ , ..., BL _N , respectively, and outputs OUTPUT ₁ , OUTPUT 2, OUTPUT ₃ , and OUTPUT ₄ are generated on source lines SL ₀ , SL ₁ , SL ₂ , and SL ₃ , _respectively .

Figure 23 depicts a neuronal VMM array 2300, which is particularly suitable for memory cell 210 as shown in Figure 2, and serves as a portion of synapses and neurons between input layers and the next layer. In this example, inputs INPUT ₀ , INPUT ₁ , INPUT ₂ , and INPUT ₃ are received on source lines SL ₀ , SL ₁ , SL ₂ , and SL ₃ , respectively, and outputs OUTPUT ₀ , ..., OUTPUT _N are generated on bit lines BL ₀ , ..., BL _N.

Figure 24 depicts a neuronal VMM array 2400, which is particularly suitable for memory cell 210 as shown in Figure 2, and serves as a portion of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT ₀ , ..., INPUT _M are received on word lines WL ₀ , ..., WL _M , respectively, and outputs OUTPUT ₀ , ..., OUTPUT _N are generated on bit lines BL ₀ , ..., BL _N.

Figure 25 depicts a neuronal VMM array 2500, which is particularly suitable for memory cell 310 as shown in Figure 3, and serves as a portion of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT ₀ , ..., INPUT _M are received on word lines WL ₀ , ..., WL _M , respectively, and outputs OUTPUT ₀ , ..., OUTPUT _N are generated on bit lines BL ₀ , ..., BL _N.

Figure 26 depicts a neuronal VMM array 2600, which is particularly suitable for memory cell 410 as shown in Figure 4, and serves as a portion of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT ₀ , ..., INPUT _N are received on vertical control gate lines CG ₀ , ..., CG _N , respectively, and outputs OUTPUT ₁ and OUTPUT ₂ are generated on source lines SL ₀ and SL ₁ .

Figure 27 depicts a neuronal VMM array 2700, which is particularly suitable for memory cell 410 as shown in Figure 4, and serves as a portion of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT ₀ , ..., INPUT _N are received at the gates of bit line control gates 2701-1, 2701-2, ..., 2701-(N-1), and 2701-N, respectively, which are coupled to bit lines BL ₀ , ..., BL _N. Example outputs OUTPUT ₁ and OUTPUT ₂ are generated on source lines SL ₀ and SL ₁ .

Figure 28 depicts a neuronal VMM array 2800, which is particularly suitable for memory cells 310 as shown in Figure 3, memory cells 510 as shown in Figure 5, and memory cells 710 as shown in Figure 7, and serves as a portion of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT ₀ , ..., INPUT _M are received on word lines WL ₀ , ..., WL _M , and outputs OUTPUT ₀ , ..., OUTPUT _N are generated on bit lines BL ₀ , ..., BL _N , respectively.

Figure 29 depicts a neuronal VMM array 2900, which is particularly suitable for memory cells 310 as shown in Figure 3, memory cells 510 as shown in Figure 5, and memory cells 710 as shown in Figure 7, and serves as a portion of synapses and neurons between input layers and the next layer. In this example, inputs INPUT ₀ , ..., INPUT _M are received on control gate lines CG ₀ , ..., CG _M. Outputs OUTPUT ₀ , ..., OUTPUT _N are generated on vertical source lines SL ₀ , ..., SL _N , respectively, where each source line SL _i is coupled to the source line of all memory cells in row i.

Figure 30 depicts a neuronal VMM array 3000, which is particularly suitable for memory cells 310 as shown in Figure 3, memory cells 510 as shown in Figure 5, and memory cells 710 as shown in Figure 7, and serves as a portion of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT ₀ , ..., INPUT _M are received on control gate lines CG ₀ , ..., CG _M. Outputs OUTPUT ₀ , ..., OUTPUT _N are generated on vertical bit lines BL ₀ , ..., BL _N , respectively, where each bit line BL _i is coupled to the bit lines of all memory cells in row i.

Long Short-Term Memory (LSTM):

Previous technologies included a concept known as Long Short-Term Memory (LSTM). LSTM cells are commonly used in neural networks. LSTM allows neural networks to remember information at predetermined time intervals and use that information in subsequent operations. A known LSTM cell consists of a cell, an input gate, an output gate, and a forget gate. These three gates regulate the flow of information into and out of the cell and the time interval at which information is remembered in the LSTM. Virtual Memory Models (VMMs) are particularly well-suited for LSTM cells.

Figure 14 illustrates an example LSTM 1400. This example LSTM 1400 includes cells 1401, 1402, 1403, and 1404. Cell 1401 receives the input vector _x0 and produces the output vector _h0 and cell state vector _c0 . Cell 1402 receives the input vector _x1 , the output vector (hidden state) _h0 from cell 1401, and the cell state _c0 from cell 1401, and produces the output vector _h1 and cell state vector _c1 . Cell 1403 receives the input vector _x2 , the output vector (hidden state) _h1 from cell 1402, and the cell state _c1 from cell 1402, and produces the output vector _h2 and cell state vector _c2 . Cell 1404 receives input vector _x3 , output vector (hidden state) _h2 from cell 1403, and cell state _c2 from cell 1403, and produces output vector _h3 . Additional cells can be used, and an LSTM with four cells is only an example.

Figure 15 illustrates an example implementation of LSTM cell 1500, which can be used in cells 1401, 1402, 1403, and 1404 in Figure 14. LSTM cell 1500 receives an input vector x(t), a cell state vector c(t-1) from the previous cell, and an output vector h(t-1) from the previous cell, and generates the cell state vector c(t) and the output vector h(t).

LSTM cell 1500 includes sigmoid function devices 1501, 1502, and 1503, each applying a number between 0 and 1 to control how much of each component of the input vector is allowed to pass through the output vector. LSTM cell 1500 also includes: hyperbolic tangent function devices 1504 and 1505 for applying the hyperbolic tangent function to the input vector; multiplier devices 1506, 1507, and 1508 for multiplying two vectors together; and adder device 1509 for adding two vectors together. The output vector h(t) can be provided to the next LSTM cell in the system or accessed for other purposes.

Figure 16 depicts LSTM cell 1600, which is an example of an implementation of LSTM cell 1500. For ease of reading, the same designations from LSTM cell 1500 are used in LSTM cell 1600. S-shaped function devices 1501, 1502, and 1503, and hyperbolic tangent function device 1504 each contain multiple VMM arrays 1601 and excitation function blocks 1602. Therefore, it can be seen that VMM arrays are particularly suitable for LSTM cells used in certain neural network systems. Multiplier devices 1506, 1507, and 1508, and adder device 1509 are implemented digitally or analogously. Excitation function block 1602 can be implemented digitally or analogously.

Figure 17 shows an alternative to LSTM cell 1600 (and another example of an implementation of LSTM cell 1500). In Figure 17, sigmoid function devices 1501, 1502, and 1503 and hyperbolic tangent function device 1504 share the same physical hardware (VMM array 1701 and excitation function block 1702) in a time-multiplexed manner. The LSTM cell 1700 also includes: a multiplier 1703 for multiplying two vectors together; an adder 1708 for adding two vectors together; a hyperbolic tangent function 1505 (which includes the excitation function block 1702); a register 1707 for storing the value i(t) when i(t) is output from the sigmoid function block 1702; and a register 1704 for storing the value f(t). *c(t-1) is stored when it is output from multiplier device 1703 via multiplexer 1710; register 1705 is used to store the value i(t)*u(t) when it is output from multiplier device 1703 via multiplexer 1710; and register 1706 is used to store the value o(t)*c~(t) when it is output from multiplier device 1703 via multiplexer 1710 and multiplexer 1709.

LSTM cell 1600 contains multiple sets of VMM arrays 1601 and their respective excitation function blocks 1602, while LSTM cell 1700 contains only one set of VMM arrays 1701 and excitation function blocks 1702, which is used to represent multiple layers in the example of LSTM cell 1700. LSTM cell 1700 will require less space than LSTM 1600 because LSTM cell 1700 requires 1/4 of the space for VMMs and excitation function blocks compared to LSTM cell 1600.

As can be further understood, an LSTM cell will typically contain multiple VMM arrays, each requiring functionality provided by certain circuit blocks outside the VMM arrays, such as summer and excitation function blocks, and high-voltage generation blocks. Providing a separate circuit block for each VMM array would require a significant amount of space within the semiconductor device and would be somewhat inefficient. Therefore, the examples described below reduce the circuitry required outside the VMM arrays themselves.

Gate return unit:

A VMM implementation can be used in GRU (Gate Recursive Unit) systems. A GRU is the gate control mechanism in a recursive neural network. A GRU is similar to an LSTM, except that a GRU cell typically contains fewer components than an LSTM cell.

Figure 18 illustrates an example GRU 1800. This example GRU 1800 includes cells 1801, 1802, 1803, and 1804. Cell 1801 receives the input vector _x0 and produces the output vector _h0 . Cell 1802 receives the input vector _x1 , the output vector _h0 from cell 1801, and produces the output vector _h1 . Cell 1803 receives the input vector _x2 and the output vector (hidden state) _h1 from cell 1802, and produces the output vector _h2 . Cell 1804 receives the input vector _x3 and the output vector (hidden state) _h2 from cell 1803, and produces the output vector _h3 . Additional cells can be used, and this four-cell GRU is only an example.

Figure 19 illustrates an example embodiment of GRU cell 1900, which can be used in cells 1801, 1802, 1803, and 1804 of Figure 18. GRU cell 1900 receives an input vector x(t) and an output vector h(t-1) from the previous GRU cell, and generates an output vector h(t). GRU cell 1900 includes sigmoid function devices 1901 and 1902, each of which applies a number between 0 and 1 to the components of the output vector h(t-1) and the input vector x(t). The GRU cell 1900 also includes a hyperbolic tangent function device 1903 for applying a hyperbolic tangent function to the input vector, multiple multiplier devices 1904, 1905, and 1906 for multiplying two vectors together, an adder device 1907 for adding two vectors together, and a complementary device 1908 for subtracting the input from 1 to produce the output.

Figure 20 depicts GRU cell 2000, which is an example of an implementation of GRU cell 1900. For the reader's convenience, the same designations from GRU cell 1900 are used in GRU cell 2000. As can be seen in Figure 20, the sigmoid function devices 1901 and 1902 and the hyperbolic tangent function device 1903 each contain multiple VMM arrays 2001 and excitation function blocks 2002. Therefore, it can be seen that VMM arrays are particularly useful in GRU cells used in certain neural network systems. Multiplier devices 1904, 1905, 1906, adder device 1907, and complement device 1908 are implemented digitally or analogously. Excitation function block 2002 can be implemented digitally or analogously.

An alternative to GRU cell 2000 (and another example of an implementation of GRU cell 1900) is shown in Figure 21. In Figure 21, GRU cell 2100 utilizes VMM array 2101 and excitation function block 2102, which, when configured as a sigmoid function, uses numbers between 0 and 1 to control how much of each component in the input vector is allowed through the output vector. In Figure 21, sigmoid function devices 1901 and 1902 and hyperbolic tangent function device 1903 share the same physical hardware (VMM array 2101 and excitation function block 2102) in a time-multiplexed manner. The GRU cell 2100 also includes: a multiplier 2103 for multiplying two vectors together; an adder 2105 for adding two vectors together; a complement 2109 for subtracting the input from 1 to produce the output; a multiplexer 2104; a register 2106 for storing the value h(t-1)*r(t) when it is output from the multiplier 2103 via the multiplexer 2104; a register 2107 for storing the value h(t-1)*z(t) when it is output from the multiplier 2103 via the multiplexer 2104; and a register 2108 for storing the value h^(t)*(1-z(t)) when it is output from the multiplier 2103 via the multiplexer 2104.

GRU cell 2000 contains multiple sets of VMM arrays 2001 and excitation function blocks 2002, while GRU cell 2100 contains only one set of VMM arrays 2101 and excitation function blocks 2102, used to represent multiple layers in the example of GRU cell 2100. GRU cell 2100 will require less space than GRU cell 2000, as GRU cell 2100 requires 1/3 of the space for VMM and excitation function blocks.

As can be further understood, a GRU system will typically contain multiple VMM arrays, each requiring functionality provided by certain circuit blocks outside the VMM arrays, such as summer and excitation function blocks, and high-voltage generation blocks. Providing a separate circuit block for each VMM array would require a significant amount of space within the semiconductor device and would be somewhat inefficient. Therefore, the examples described below reduce the circuitry required outside the VMM arrays themselves.

The inputs to the VMM array can be analog levels, binary levels, pulses, time-modulated pulses, or digital bits (in which case, a DAC is needed to convert the digital bits to the appropriate input analog level), and the outputs can be analog levels, binary levels, timing pulses, pulses, or digital bits (in which case, an output ADC is needed to convert the output analog level to digital bits).

Typically, for each memory cell in a VMM array, each weight W can be implemented by a single memory cell, a differential cell, or two mixed memory cells (the average of the two cells). In the case of differential cells, two memory cells are needed to implement the weight W as a differential weight (W = W+ - W-). In the case of two mixed memory cells, two memory cells are needed to implement the weight W as the average of the two cells.

Figure 31 illustrates a VMM system 3100. In some examples, the weights W stored in the VMM array are stored as differential pairs W+ (positive weights) and W- (negative weights), where W = (W+) - (W-). In the VMM system 3100, half of the bit lines are designated as W+ lines, i.e., bit lines connected to memory cells that will store positive weights W+, and the other half of the bit lines are designated as W- lines, i.e., bit lines connected to memory cells that implement negative weights W-. The W- lines are interspersed among the W+ lines. Subtraction The operation is performed by a summing circuit that receives current from the W+ and W- lines, such as summing circuits 3101 and 3102. The outputs of the W+ and W- lines are combined to effectively derive W = W+ - W- for each (W+, W-) cell of all pairs of (W+, W-) lines. Although the alternating arrangement of the W- lines among the W+ lines has been described above, in other examples, the W+ and W- lines can be positioned arbitrarily anywhere in the array.

Figure 32 illustrates another example. In the VMM system 3210, positive weights W+ are implemented in a first array 3211 and negative weights W- are implemented in a second array 3212, which is separate from the first array, and the resulting weights are appropriately combined by a summing circuit 3213.

Figure 33 depicts a VMM system 3300. The weights W stored in the VMM array are stored as difference pairs W+ (positive weights) and W- (negative weights), where W = (W+) - (W-). The VMM system 3300 includes arrays 3301 and 3302. Half of the bit lines in each of arrays 3301 and 3302 are designated as W+ lines, i.e., bit lines connected to memory cells where positive weights W+ will be stored, and the other half of the bit lines in each of arrays 3301 and 3302 are designated as W- lines, i.e., bit lines connected to memory cells where negative weights W- are implemented. W- lines are interspersed among the W+ lines in an alternating manner. The subtraction operation is performed by summing circuits that receive current from the W+ and W- lines, such as summing circuits 3303, 3304, 3305, and 3306. The outputs of the W+ and W- lines from each array 3301 and 3302 are combined to effectively derive W = W+ - W- for each (W+, W-) cell of all pairs of (W+, W-) lines. Furthermore, the W values from each array 3301 and 3302 can be further combined via summing circuits 3307 and 3308, such that each W value is the result of subtracting the W value from array 3302 from the W value from array 3301. This means that the final result from summing circuits 3307 and 3308 is the difference between two differential values.

This analogy is used to describe how each non-volatile memory cell in a neural memory system is to be erased and programmed to maintain a very specific and precise amount of charge, i.e., the number of electrons, in a floating gate. For example, each floating gate should retain one of N different values, where N is the number of different weights that can be indicated by each cell. Examples of N include 16, 32, 64, 128, and 256.

Existing VMM systems require a large area and involve significant latency at both the input and output stages. At the input stage, multiple clock cycles are needed to load the excitation data into the column registers before programmed operations can begin. For example, for 8-bit I/O, each column requires 8 bits of excitation data, typically 1024 columns or more, requiring one clock cycle per row, or 1024 clock cycles if there are 1024 columns, resulting in a latency between 10 ns and 10 μs. At the output stage, moving neuron output data also involves latency. For example, for a 128-bit ADC, an 8-bit output requires 128 clock cycles.

The goal is to reduce latency at the input and output stages to improve the overall operating speed of artificial neural networks.

Numerous examples of input and output circuit systems and related methods are disclosed to implement parallel and pipelined operation in artificial neural networks.

12: Semiconductor substrate

14: Source Area

16: Jiji Area

18: Passage Area

20: Floating gate pole

22: Character Line Terminal

24: Bitline

28: Control Gate

30: Erasure of the gate pole

31: Digital-to-Analog Converter

32, 32a, 32b, 32c, 32d, 32e: Vector-matrix multiplication arrays

33: Non-volatile memory cell arrays

34: Gate and character line eraser decoder

35: Control Gate Decoder

36-bit line decoder

37: Source Line Decoder

38: Differential Additive

Blocks 39, 1602, 1702, 2002, 2102: Excitation function blocks

210, 310, 410, 510, 710: Memory cells

900, 1000, 1100, 1200, 1300, 1601, 1701, 2001, 2101, 2200, 2300, 2400, 2500, 2600, 2700, 2800, 2900, 3000, 3401: VMM Array

901, 1003, 1103, 1203, 1303: Memory arrays

902, 1001, 1002, 1101, 1102, 1201, 1202, 1301, 1302: Reference Array

903: Control Gate Electrode

904: Remove gate polarity wire

1014: Diode-connected through-type multiplexer

1204: Overlay transistor

1205, 1212: Multiplexer

1314: Diode-connected reference cell through-type multiplexer

1400:LSTM

1401, 1402, 1403, 1404, 1801, 1802, 1803, 1804: Cells

1500, 1600, 1700: LSTM cells

1501, 1502, 1503, 1901, 1902: S-shaped function device

1504, 1505, 1903: Hyperbolic Tangent Function Apparatus

1506, 1507, 1508, 1703, 1904, 1905, 1906, 2103: Multiplier device

1509, 1708, 1907, 2105: Adding device

1704, 1705, 1706, 1707, 2106, 2107, 2108: Registers

1709, 1710, 2104: Multiplexer

1800:GRU

1900, 2000, 2100: GRU cells

1908, 2109: Complementary Device

2701-1, 2701-2, ... , 2701-(N-1), 2701-N: Bit line control gate

3100, 3210, 3300, 3400: VMM systems

3101, 3102, 3213, 3303, 3304, 3305, 3306, 3307, 3308: Summarization circuit

3211: First Line

3212: Second Formation

3301, 3302: Formation

3402: Column decoder

3403: High Voltage Decoder

3404: Line decoder

3405: Bitline Driver

3406: Input Circuit

3407: Output Circuit

3408: Control Logic

3409: Bias Generator

3410: High Voltage Generation Block

3411: Electric Charge Pump

3412: Electric Charge Pump Regulator

3413: High Voltage Position Generator

3414: Algorithm Controller

3415: Analog Circuit System

3416: Control Engine

3417: Test Control Logic

3418: Static Random Access to Memory Blocks

3500, 3550, 3600, 3800, 3900, 3920, 3940, 3960: Input blocks

3501, 3551, 3601, 3601-0, 3601-1: Global Digital-to-Analog Converters

3502, 3502-0, 3502-1, ..., 3502-(n-1), 3502-n: Column registers

3503, 3503-0, 3503-1, ..., 3503-(n-1), 3503-n: Comparator blocks

3504, 3504-0, 3504-1, ..., 3504-(n-1), 3504-n: Column sampling and holding buffers

3505, 3505-0, 3505-1, ..., 3505-(n-1), 3505-n: Output signals

3552, 3552-0, 3552-1, ..., 3552-(n-1), 3552-n: Column registers

3553,3553-0,3553-1,． ． ． ,3553-(n-1),3553-n: Digital multiplexer blocks

3554, 3554-0, 3554-1, ..., 3554-(n-1), 3554-n: Column sampling and holding buffers

3555, 3555-0, 3555-1, ..., 3555-(n-1), 3555-n: Output signal

3602, 3602-0, 3602-1, ..., 3602-(n-1), 3602-n: Column registers

3603, 3603-0, 3603-1, ..., 3603-(n-1), 3603-n: Digit comparator blocks

3604, 3604-0, 3604-1, ..., 3604-(n-1), 3604-n: Column sampling and holding buffers

3605, 3605-0, 3605-1, ..., 3605-(n-1), 3605-n: Output signals

3700, 3720: Waveform

3701, 3721: Signal GDACsup

3702, 3703, 3722, 3723: Signals

3704, 3724: Signal DAC_sampling_en

3705, 3706, 3707, 3708, 3725, 3726, 3727, 3728: Edge

3801, 3801-0, 3801-1, ... , 3801-n: Registers

3802, 3802-0, 3802-1, ..., 3802-n: Registers

3803, 3803-0, 3803-1, ..., 3803-n: Column sampling and holding buffers

3804, 3804-0, 3804-1, ..., 3804-n: Address decoder

3810, 3910: Sub-blocks

3850: Input Method

3902, 3902-0, 3902-1, ..., 3902-n: Column registers

3903, 3903-0, 3903-1, ..., 3903-n: Column sampling and holding buffers

3904, 3904-0, 3904-1, ..., 3904-n: Address decoder

3905, 3905-0, 3905-1, ..., 3905-n: Label bits

3906, 3906-0, 3906-1, ..., 3906-n: Column registers

3907, 3907-0, 3907-1, ..., 3907-n: Label bits

3908, 3908-0, 3908-1, ..., 3908-n: Column registers

3909, 3909-0, 3909-1, ... , 3909-n: Label bits

3911, 3911-0, 3911-1, ... , 3911-n: Column sampling and holding buffers

4000, 4020: Output blocks

4001: Current to Voltage Converter

4002: Analog to Digital Converter

4003, 4004: Output Registers

4005: Row label bit

4021: Accumulator

4042: Shifter

4043: Adder

4044: Accumulator Register

4100, 4200, 4300, 4400: Waveforms

4101: First Stage

4102: Second Stage

4201: Random access read operation

4301: Sudden Read Operation

4401: Neural Reading Operations

4500, 4600, 4700, 4900: Neural readout operations

4800: Read operation

C1: Layer

C2: Layer

C3: Layer

CB1: Synapse

CB2: Synapse

CB3: Synapse

CB4: Synapse

P1: Incentive Function

P2: Incentive Function

S1: Layer

S2: Layer

S3: Layer

Figure 1 is a diagram illustrating an artificial neural network.

Figure 2 depicts the separation of gated ultra-fast flash memory cells using prior art techniques.

Figure 3 depicts another prior art technique for isolating gate-type ultra-fast flash memory cells.

Figure 4 depicts another prior art technique for isolating gate-type ultra-fast flash memory cells.

Figure 5 depicts another prior art technique for isolating gate-type ultra-fast flash memory cells.

Figure 6 is a diagram illustrating different levels of an exemplary artificial neural network utilizing one or more non-volatile memory arrays.

Figure 7 is a block diagram illustrating the VMM system.

Figure 8 is a block diagram illustrating an exemplary artificial neural network utilizing one or more VMM systems.

Figure 9 illustrates another example of a VMM system.

Figure 10 depicts another example of a VMM system.

Figure 11 illustrates another example of a VMM system.

Figure 12 illustrates another example of a VMM system.

Figure 13 illustrates another example of a VMM system.

Figure 14 illustrates a prior art Long Short-Term Memory (LSTM) system.

Figure 15 depicts an exemplary cell for use in a Long Short-Term Memory (LSTM) system.

Figure 16 illustrates an exemplary implementation of the cell in Figure 15.

Figure 17 illustrates another exemplary implementation of the cell of Figure 15.

Figure 18 illustrates a prior art gate return unit system.

Figure 19 depicts an exemplary cell used in a gate control return unit system.

Figure 20 illustrates an exemplary implementation of the cell in Figure 19.

Figure 21 depicts another exemplary implementation of the cell of Figure 19.

Figure 22 illustrates another example of a VMM system.

Figure 23 illustrates another example of a VMM system.

Figure 24 illustrates another example of a VMM system.

Figure 25 illustrates another example of a VMM system.

Figure 26 illustrates another example of a VMM system.

Figure 27 illustrates another example of a VMM system.

Figure 28 illustrates another example of a VMM system.

Figure 29 illustrates another example of a VMM system.

Figure 30 depicts another example of a VMM system.

Figure 31 depicts another example of a VMM system.

Figure 32 illustrates another example of a VMM system.

Figure 33 illustrates another example of a VMM system.

Figure 34 illustrates another example of a VMM system.

Figures 35A and 35B depict the input blocks of the VMM system.

Figure 36 depicts the input block of the VMM system.

Figures 37A and 37B depict the signals associated with the input operations of the VMM array.

Figure 38A depicts the input block of a VMM system.

Figure 38B depicts the input method.

Figures 39A, 39B, 39C, and 39D depict the input blocks of the VMM system.

Figure 40A depicts the output block of the VMM system.

Figure 40B depicts the output block of the VMM system.

Figure 40C depicts the output block of the VMM system.

Figure 41 depicts the waveforms of the VMM system.

Figure 42 depicts the waveforms of the VMM system.

Figure 43 depicts the waveforms of the VMM system.

Figure 44 depicts the waveforms of the VMM system.

Figure 45 illustrates the procedure for nerve reading.

Figure 46 illustrates the neurotransmission procedure.

Figure 47 illustrates the procedure for nerve reading.

Figure 48 illustrates the neurotransmission procedure.

Figure 49 illustrates the neurotransmission procedure.

VMM system architecture:

Figure 34 depicts a block diagram of a VMM system 3400. The VMM system 3400 includes a VMM array 3401, a column decoder 3402, a high-voltage decoder 3403, a row decoder 3404, a bit line driver 3405 (e.g., for a programmable bit line control circuit system), an input circuit 3406, an output circuit 3407, a control logic 3408, and a bias generator 3409. The VMM system 3400 further includes a high-voltage generation block 3410, which includes a charge pump 3411, a charge pump regulator 3412, and a high-voltage level generator 3413. The VMM system 3400 further includes a (programmed/erase, or weighted tuning) algorithm controller 3414, an analog circuit system 3415, a control engine 3416 (which may include, but is not limited to, special functions such as arithmetic functions, excitation functions, embedded microcontroller logic), a test control logic 3417, and static random access memory (SRAM) blocks 3418 for storing intermediate data, such as intermediate data for input circuits (e.g., excitation data) or intermediate data for output circuits (neural output data, partially summed output neuron data) or for programmable data input (e.g., for single or multiple columns of data input).

Input circuitry 3406 may include circuitry such as a DAC (digital-to-analog converter), DPC (digital-to-pulse converter, digital-to-time-modulated pulse converter), AAC (analog-to-analog converter, e.g., current-to-voltage converter, logarithmic converter), PAC (pulse-to-analog level converter), or any other type of converter. Input circuitry 3406 may implement one or more normalization, linear, or nonlinear up/down scaling functions or arithmetic functions. Input circuitry 3406 may implement temperature compensation for the input level. Input circuitry 3406 may implement excitation functions such as ReLU or sigmoid. Input circuit 3406 can store digital excitation data that will be used as or combined with input signals during programming or read operations. The digital excitation data can be stored in a register. Input circuit 3406 may include circuitry for driving array terminals (e.g., CG, WL, EG, and SL lines), and may include sampling and holding circuitry and a buffer. A DAC can be used to convert the digital excitation data into an analog input voltage for application to the array.

Output circuit 3407 may include circuitry such as an ITV (current-to-voltage) circuit, an ADC (analog-to-digital converter for converting analog neuron outputs to digital bits), an AAC (analog-to-analog converter, e.g., a current-to-voltage converter, a logarithmic converter), an APC (analog-to-pulse converter, analog-to-time-modulated pulse converter), or any other type of converter. Output circuit 3407 may convert array outputs into excitation data. Output circuit 3407 may implement an excitation function, such as a rectified linear excitation function (ReLU) or a sigmoid excitation function. Output circuit 3407 may apply one or more of the following statistical functions to the neural output: statistical normalization, regularization, up/down scaling/gain functions, statistical trimming, and arithmetic functions (e.g., addition, subtraction, division, multiplication, shifting, logarithmic). Output circuit 3407 may apply a temperature compensation function to the neural output or array output (e.g., bitline output) to maintain approximately constant power consumption of the array or improve the accuracy of the array (neuron) output, for example, by keeping the IV slope approximately the same with temperature. Output circuit 3407 may include a register storing output data.

Figure 35A depicts the input block 3500 used to provide input to the VMM array 3401. The input block 3500 includes a global digital-to-analog converter (DAC) 3501; column registers 3502-0 to 3502-n, each corresponding to one of the columns numbered 0 to n in the array; digital comparator blocks 3503-0 to 3503-n, each corresponding to one of the columns numbered 0 to n in the array; column sample and hold buffers 3504-0 to 3504-n, each corresponding to one of the columns numbered 0 to n in the array; and output signals 3505-0 to 3505-n, each corresponding to one of the columns numbered 0 to n in the array, and are respectively denoted as CGIN0, CGIN1..., CGINn-1, and CGINn. The signal GDACsup is a global DAC signal provided by the global DAC 3501. Signals CGIN0 through CGINn are coupled to their respective column inputs of array 3401. CLKDAC is the input clock of the GDAC used to provide the analog output values. In one example, these analog output values correspond to the count of the CLKDAC clock.

The comparator block 3503 compares the value stored in the associated column register 3502 with the signal CLKCOUNTx. CLKCOUNTx is the result of a counter that counts the clock signal at predetermined intervals; if a match is found, the corresponding column S/H 3504 is enabled by its respective comparator block 3503 to sample the value from the global DAC 3501 into its respective column S/H buffer. This technique is referred to as global column DAC sampling. As described above, each column in the VMM array 3401 has a corresponding column register 3502, comparator block 3503, and column S/H 3504.

During operation, column registers 3502-0 to 3502-n are loaded with the digital input bits DINx (where x is the number of bits, such as 8 or 16 bits) for that particular column and receive the clock signal CLK. The CLK signal is used to load the data from the digital input bits DINx into their respective column registers 3502-x. The global DAC 3501 is shared by all columns and performs digital-to-analog conversion on the digital bits DINx stored in the particular column registers 3502 in a time-multiplexed manner. This conversion is accomplished by each of the digital comparator blocks 3503 by comparing the digital input bits of the particular column with a signal CLKCOUNTx, which serves as the digital counter value. When the digital count value of signal CLKCOUNTx matches the contents of the respective column register 3502, the corresponding column sample-and-hold buffer 3504 samples and holds the value of the analog output from the global DAC 3501, and then uses that value as the output signal 3505 for that particular column. Output signal 3505 can be applied during programmed operation in that particular column, for example, to control gate lines or word lines, or to erase gates, in a manner described with respect to the other diagrams above.

Alternatively, the column sampling and holding buffer 3504 can be shared among two or more columns by time multiplexing the column sampling and holding buffer.

Figure 35B depicts the input block 3550 used to provide input to the VMM array 3401. The input block 3550 includes a global digital-to-analog converter (DAC) 3551; column registers 3552-0 to 3552-n, each corresponding to one of the columns numbered 0 to n in the VMM array 3401; digital multiplexer (mux) blocks 3553-0 to 3553-n, each corresponding to one of the columns numbered 0 to n; column sample-and-hold (S/H) buffers 3554-0 to 3554-n, each corresponding to one of the columns numbered 0 to n; and output signals 3555-0 to 3555-n, denoted as CGIN0, CGIN1, ... CGINn-1 and CGINn correspond to columns numbered 0 to n, respectively. The digital multiplexer block 3553 multiplexes data from its respective column registers 3552 into the bus GDAC_DINx, which is then used as input to the global DAC 3551. The corresponding column S/H buffer 3554 samples the values from the global DAC into its local S/H buffer 3554. Each column has its own column register 3552, S/H buffer 3554, and output signal 3555.

During operation, column registers 3552-0 to 3552-n load the digital input bits DINx (where x is the number of bits, such as 8 or 16 bits) for that specific column and receive the clock signal CLK. The CLK signal is used to load the data from the digital input bits DINx into their respective column registers 3552. The global digital-to-analog converter 3551 is shared by all columns and performs digital-to-analog conversion on the digital bits DINx stored in the specific column registers 3552 in a time-multiplexed manner. This conversion is accomplished by time-multiplexing the data from the column registers into the data inputs (bus GDAC_DINx) of the global DAC 3551. The column register data becomes multiplexed on the data input bus GDAC_DINx by a separate enable signal EN-x 3557-x for each column. The corresponding column sample-and-hold buffer 3554 samples and holds the analog output from the global DAC 3551, then uses that value as the output signal 3555 for that specific column. For example, during programmed operation in that specific column, the output signal 3555 can be applied to control gate lines or word lines in the manner described above with respect to other diagrams.

Alternatively, the column sampling and holding buffer 3554 can be shared across multiple columns by time multiplexing the column sampling and holding buffer.

Figure 36 depicts the input block 3600, which is intended to provide input to the VMM array 3401. The input block 3600 includes two global DACs 3601-0 and 3601-1; column registers 3602-0 to 3602-n, each corresponding to one of the columns numbered 0 to n in the VMM array 3401; digital comparator blocks 3603 to 3603-n, each corresponding to one of the columns numbered 0 to n in the VMM array 3401; column sample and hold buffers 3604-0 to 3604-n, each corresponding to one of the columns numbered 0 to n in the VMM array 3401; and output signals 3605-0 to 3605-n, represented as CGIN0, CGIN1..., CGINn-1, and CGINn, each corresponding to one of the columns numbered 0 to n. The comparator block 3603 compares the value stored in its respective column register 3602 with the signal CLKCOUNTx, which is the result of a counter that counts the clock signal at predetermined intervals. When the digital count value of the signal CLKCOUNTx matches the contents of its respective column register 3602, the respective column S/H buffer 3604 is enabled to sample the value from the global DAC 3601 into its respective S/H buffer 3604. Each column has its own column register 3602, comparator block 3603, and column S/H buffer 3604.

During operation, column registers 3602-0 to 3602-n load the digital input bits DINx (where x is the number of bits, such as 8 or 16 bits) for the associated column and receive the clock signal CLK. The CLK signal is used to load data from the digital input bits DINx into column register 3602-x. The global DAC 3601 (which consists of multiple global DACs, such as 3601-0 and 3601-1) is shared by all columns. In one example, global DAC 3601-0 operates on even-numbered columns and global DAC 3601-1 operates on odd-numbered columns. The global DAC 3601 receives the clock signal CLKDAC and outputs an analog value corresponding to the count of the CLKDAC clock. The global DAC 3601 performs a digital-to-analog conversion on the digital bits DINx stored in the relevant column register 3602 (via the GDAC_DINx bus). The corresponding column sample-and-hold buffer 3604 samples and holds the analog output from the global digital-to-analog converter 3601, which is then used as the output signal 3605 for that specific column. For example, during programmed operation in that specific column or multiple columns, the output signal 3605 can be applied to control gate lines or word lines in the manner described above with respect to other diagrams.

Figure 37A depicts waveform 3700, illustrating example voltage levels CGIN0 and CGIN1 output after sampling and holding operations by the column sample and hold buffer 3504 in Figure 35A, the column sample and hold buffer 3554 in Figure 35B, or the column sample and hold buffer 3604 in Figure 36 in response to GDACsup 3701. The signal GDACsup 3701 is the supply voltage from the global DAC (e.g., global DAC 3501 in Figure 35A, global DAC 3551 in Figure 35B, and global DACs 3601-0 and 3601-1 in Figure 36). GDACsup 3701 is a linear DAC voltage curve, representing a linear shift of the digital input value to the analog value at the global DAC output. This linear translation is suitable for memory cells operating in linear regions. As an example, signal 3702 displays the sampled voltage value (level) on column 0 (CGIN0), and signal 3703 displays the sampled voltage value (level) on column 1 (CGIN1). Signal DAC_sampling_en 3704 is the control signal enabling the sampling and holding operation. Four sampling examples are shown at the edges 3705, 3706, 3707, and 3708 corresponding to the different voltages being sampled.

Figure 37B depicts waveform 3720, showing that, in response to GDACsup 3721, after the corresponding sampling and holding action of column sample and hold buffer 3504 in Figure 35A, after the corresponding sampling and holding action of column sample and hold buffer 3554 in Figure 35B, or after column sample and hold buffer 3604 in Figure 36, the example logarithmic voltage levels of CGIN0 and CGIN1 are output. The use of logarithmic conversion from digital input values to analog values is suitable for memory units operating in the subthreshold region. Alternatively, it can be used for memory units operating in the saturation region. Signal GDACsup 3721 is the voltage supplied from a global DAC (e.g., global DAC 3501 in Figure 35A, global DAC 3551 in Figure 35B, and global DACs 3601-0 and 3601-1 in Figure 36). GDACsup 3721 is a logarithmic DAC curve. As an example, signal 3722 shows the sampled voltage value (level) at column 0 (CGIN0), and signal 3723 shows the sampled voltage value (level) at column 1 (CGIN1). Signal DAC_sampling_en 3724 is the control signal enabling sampling and holding operations. Four examples of sampling are shown at the edges 3725, 3726, 3727, and 3728 corresponding to the different voltages being sampled.

The intelligent DAC sampling method is as follows. As shown in Figures 37A and 37B, sampling enable is performed only on the column register used for a specific input operation. This means that sampling is enabled at the first minimum value of the column register and terminates at the maximum value. This is to reduce the required sampling time by only considering the range of the input values (i.e., the excitation input values) on the column register.

Furthermore, for a single sampling, if the maximum number of columns is enabled, for example, a maximum of 128 columns, then for the same input value, if 180 columns are enabled, sampling will occur twice: a first sample for 128 columns and a second sample for 62 columns. Alternatively, a first sample for 90 columns and a second sample for 90 columns. This is to reduce the load on the sampling circuitry to prevent undesirable settling times caused by high loads.

Figure 38 depicts the input block 3800 used in conjunction with the VMM array 3401. Input block 3800 includes sub-block 3810, SRAM 3418, registers 3801-0, 3801-1, ..., 3801-n, and address decoders 3804-0, 3804-1, ..., 3804-n. Sub-block 3810 may optionally include one of the input blocks 3500, 3550, and 3600 from Figures 35A, 35B, and 36, respectively. Sub-block 3810 includes registers 3802-0, 3802-1, ... The circuitry includes 3802-n and column sample and hold buffers 3803-0, 3803-1, ..., 3803-n, as well as the circuitry between them according to Figures 35A, 35B, and 36, depending on the specific circumstances. In the case where sub-block 3810 includes input block 3500, register 3802 includes column register 3502 and column sample and hold buffer 3803 includes column sample and hold buffer 3504. If subblock 3810 includes input block 3550, then register 3802 includes column register 3552 and column sample and hold buffer 3803 includes column sample and hold buffer 3554. If subblock 3810 includes input block 3600, then register 3802 includes column register 3602 and column sample and hold buffer 3803 includes column sample and hold buffer 3604.

Address decoder 3804 receives an address for a data input loading operation to load data into register 3802 or register 3801. The data may be, for example, activation data or input data, such as objects or images to be classified or identified in a neural network application. It outputs a signal enabling register 3801 or register 3802, indicating which registers are asserted during the data input loading operation. Data input (not shown) typically varies between 8 and 256 bits.

Address decoder 3804 also receives addresses for read verification or programming operations and outputs a signal to register 3801 or register 3802 indicating which column(s) are confirmed for read verification or programming operations. Read verification is a read operation used for weight adjustment, where cells are programmed as target currents representing target weights in the neural network, and then the cell currents are verified to ensure they approach the target current during the weight adjustment algorithm.

Register 3802 uses the excitation data stored in each of these registers to enable column sampling and holding buffer 3803. In the example implementation, register 3802 may have 1024 columns and 1024 instances, with 8-bit excitation data stored in each register 3802.

To load data into register 3802, the required number of clock cycles R is R = number of columns x 8 (for 8-bit stimulus data) divided by the data input width, for example, 16-bit data input (e.g., R = 1024 * 8 / 16 = 512).

Register 3801 includes registers coupled to and associated with each register 3802. Each register 3801 loads the stimulus data of its associated register 3802, which can be performed sequentially over R clock cycles. Thereafter, during the first clock cycle, data from each register 3801 is loaded in parallel into its associated register 3802. Therefore, registers 3802 are loaded from their respective registers 3801 in parallel within a single clock cycle, rather than serially over R clock cycles. This significantly accelerates the timing of data input loading operations.

Optionally, SRAM 3418 can be used to sequentially load all registers 3802 during the R clock cycle for background operation.

Optionally, SRAM 3418 is used to sequentially load its data into register 3801. Figure 38B depicts an input method 3850 that can be performed using the input block 3800 of Figure 38A. The first operation is to respond to an address by a plurality of address decoders, outputting a plurality of column enable signals (3851). The next operation is to respond to the plurality of column enable signals by sequentially storing the activation data via a first plurality of registers (3852). This sequential storage may optionally include receiving the activation data from static random access memory via the first plurality of registers. The next operation is to store the stimulus data received from the first plurality of registers in parallel using a second plurality of registers (3853). The next operation is to respond to the stimulus data received from the second plurality of registers during read neuronal operations by driving multiple columns of the non-volatile memory cell array (3854) using a multi-column sampling and holding buffer.

Figure 39A depicts input block 3900. Input block 3900 includes sub-block 3910, VMM array 3401, and address decoders 3904-0, 3904-1, ..., 3904-n. Sub-block 3910 may optionally include one of input blocks 3500, 3550, and 3600 from Figures 35A, 35B, and 36, respectively. Sub-block 3910 includes column registers 3902-0, 3902-1, ..., 3902-n, and column sample and hold buffers 3903-0, 3903-1, ... 3903-n and the circuit system between Figures 35A, 35B and 36, as appropriate. In the case where sub-block 3910 includes input block 3500, then column register 3902 includes column register 3502 and column sample and hold buffer 3803 includes column sample and hold buffer 3504. In the case where sub-block 3910 includes input block 3550, then column register 3902 includes column register 3552 and column sample and hold buffer 3901 includes column sample and hold buffer 3554. If subblock 3910 includes input block 3600, then column register 3902 includes column register 3602, and column sample and hold buffer 3903 includes column sample and hold buffer 3604.

Address decoder 3904 receives the address used for the data input loading operation to load data (not shown) into column register 3902. The data may be, for example, stimulus data or input data, such as objects or images to be classified or identified in neural network applications. It outputs a signal enabling column register 3902, indicating which registers are established during the data input loading operation. The data input (not shown) typically varies between 8 and 256 bits.

Address decoder 3904 can also receive addresses used for read authentication or programmed operations and output signals to column register 3902 indicating which column(s) are confirmed for read authentication or programmed operations. In this example, each column register stores stimulus data (e.g., 8-bit stimulus data) and one or more tag bits, such as one for column enable and another for column DAC sampling. For example, column register 3902-0 includes tag bit 3905-0, column register 3902-1 includes tag bit 3905-1, column register 3902-n includes tag bit 3905-n, and so on. The label bit (column enable label bit) 3905 is used to enable the column to disable the activation input data stored in the column register, regardless of whether the column is selected by the address decoder 3904. For example, if label bit 3905-0 of column 0 has a specific value (e.g., a "1" value), the activation data in column register 3902-0 is output. If label bit 3905-0 has a different value (e.g., a "0" value), the activation data in column register 3902-0 will not be output, and column S/H buffer 3903-0 will receive the Z state from column register 3902-0. Another tag bit (column S/H tag bit) is used for column DAC sampling to enable or disable sampling the global DAC value into the local column S/H buffer 3903.

Figure 39B depicts input block 3920. Input block 3920 is similar to input block 3900, except that it contains a second set of column registers (shadow registers) 3906-0, 3906-1, ..., 3906-n, each column register containing a separate tag bit 3907-0, 3907-1, ..., 3907-n. Each column can be switched between column registers 3902 and 3906. For example, during one operation, address decoder 3904 provides output to column register 3902, and during another operation, address decoder 3904 provides output to column register 3906. For example, during one operation, if tag bit 3905 is enabled, column register 3902-0 outputs data, and during another operation, if tag bit 3907 is enabled, column register 3906 outputs data. This switching can be implemented using a multiplexer (not shown) or other control logic. In this way, one set of column registers 3902 or 3906 can be loaded with excitation data, while another set is used to actively output its excitation data based on signals from address decoder 3904.

Figure 39C depicts input block 3940. Input block 3940 is similar to input block 3900, except that it contains a second set of column registers 3908-0, 3908-1, ..., 3908-n, each column register containing its own tag bits 3909-0, 3909-1, ..., 3909-n. Each column can be switched between column registers 3902 and 3908. For example, during one operation, address decoder 3904 provides a signal to column register 3902, and during another operation, address decoder 3904 provides an output to column register 3908. For example, during one operation, if tag bit 3905 is enabled, column register 3902 outputs data, and during another operation, if tag bit 3909 is enabled, column register 3908 outputs data. This switching can be implemented using a multiplexer (not shown) or other control logic. In this way, one set of column registers 3902 or 3908 can be loaded with excitation data, while another set of column registers is used to actively output its excitation data based on signals from address decoder 3904.

Figure 39D depicts input block 3960. Input block 3960 is similar to input block 3940, except that it includes a second set of column sample and hold buffers 3911-0, 3911-1, ..., 3911-n for the same array inputs (e.g., CGINx). Each column can be switched between column registers 3902 and 3908. For example, during one operation, address decoder 3904 provides a signal to column register 3902, and during another operation, address decoder 3904 provides an output to column register 3908. Similarly, during one operation, column register 3902 outputs data according to tag bit 3905, and during another operation, column register 3908 outputs data according to tag bit 3909. Each column can be switched between column S/H buffer 3903 and column S/H buffer 3911 (using control signals, not shown). This switching can be implemented via a multiplexer (not shown) or other control logic. In this way, one set of column registers 3902 or 3908 can be loaded with excitation data, while another set is used to actively output its excitation data according to signals from address decoder 3904.

In one example, the first stimulus data and the first tag bit are loaded into column register 3902, and the second stimulus data and the second tag bit are loaded into column register 3908. The first stimulus data and the second stimulus data may be the same or different, and the first tag bit and the second tag bit may be the same or different.

Figure 40A depicts output block 4000. Output block 4000 typically receives output current from VMM array 3401 (not shown) via bit lines or source lines. Output block 4000 includes a current-to-voltage converter 4001, an analog-to-digital converter 4002, an output register 4003, and an output register 4004. The current-to-voltage converter 4001 converts the current received from VMM array 3401 into a voltage that reflects the value of the current received from VMM array 3401. Analogous to digital converter 4002, each voltage is converted into bits representing the value of the voltage received from the respective current-to-voltage converter 4001, thus reflecting the current value received from the VMM array 3401. These bits are then stored in output register 4003 or output register 4004. Output operations can be switched between output register 4003 and output register 4004. For example, during the first operation period within a first time cycle (e.g., one or more clock cycles), output data is loaded into output register 4003. During a second operation period following the first time period (e.g., one or more clock cycles), data is read from output register 4003 by another device in the system, while new output data is loaded into output register 4004. During a third operation period following the second time period (e.g., one or more clock cycles), new output data is read from output register 4004 by another device in the system, and optionally, output data can be loaded into output register 4003 and the sequence can be repeated. This reduces latency associated with output operations because data can be read from the first output register by an external device while other data is loaded into other output registers. Optionally, output block 4000 may include row label bits 4005 to enable current to voltage converter 4001 and analog-to-digital converter 4002. Row label bits 4005 may include row label bits for each row in the VMM array 3401. Loading of row label bits 4005 is similar to the loading of column label bits discussed above with respect to Figures 39A to 39D. The function of the row label bits is similar to the function of the column label bits discussed above with respect to Figures 39A to 39D. For example, the current-to-voltage converter 4001 and the analog-to-digital converter 4002 can be configured to output data for a row when the row label bit 4005 has a first value, and not output data when the row label bit has a second value.

Figure 40B depicts output block 4020. Output block 4020 is the same as output block 4000, except that an accumulator 4021 is added. Accumulator 4021 can sum the values received from current-to-voltage converter 4001, analog-to-digital converter 4002, output register 4003, and output register 4004 over a certain time period. For example, this could be useful if a neural read operation is performed on the VMM array 3401 in a time-multiplexed manner, such as by reading half a row during a first time cycle and the other half during a second time cycle. The output from the first time period can be received by output register 4003, and the output from the second time period can be received by output register 4004. The accumulator can sum the values received from output registers 4003 and 4004.

Output block 4000 may optionally include row label bits 4005 to enable current-to-voltage converter 4001 and analog-to-digital converter 4002. Row label bits 4005 may include row label bits for each row in the VMM array 3401. Loading of row label bits 4005 is similar to the loading of column label bits described above with respect to Figures 39A-39D. The function of the row label bits is similar to the function of the column label bits described above with respect to Figures 39A-39D. For example, current-to-voltage converter 4001 and analog-to-digital converter 4002 may be configured to output data for that row when the row label bit 4005 of that row has a first value, and not output data when the row label bit of that row has a second value.

Figure 40C provides an example circuit for an output accumulator 4021. The output accumulator receives data from a current-to-voltage converter 4001, an analog-to-digital converter 4002, an output register 4003, and an output register 4004. The data is received by a shifter 4042, which responds to EN_SHIFT to perform a shift function. The output D1 of shifter 4042 is provided to adder 4043, which adds D1 to D2, and receives and is enabled by EN_ADD. The output of adder 4043 is provided to accumulator register 4044, which stores the output of adder 4043 and provides it back to adder 4043 as D2 for the next addition operation. In this way, the outputs of the voltage converter 4001, the analog-to-digital converter 4002, the output register 4003, and the output register 4004 can be summed within a time cycle.

For example, shifter 4042 is used during serial input (DAC) mode, where one bit of the excitation input is read at a time, and the shift amount of the output bit depends on the binary position of the input bit. For example, the LSB (least significant bit) of the input bit results in no output shift, (LSB+1) of the input bit results in a 1-bit left shift, (LSB+2) of the input bit results in a 2-bit left shift, and so on. For an 8-bit excitation input, the read operation is performed 8 times. The final output from accumulator register 4044 is the result of the entire 8-bit excitation input.

Figure 41 depicts waveforms 4100 of the first stage 4101 and the second stage 4102, where the first stage 4101 loads stimulus data into a register, and the second stage 4102 uses the stimulus data to perform neural readout operations.

Figure 42 depicts the waveform 4200 of the random access read operation 4201.

Figure 43 depicts the waveform 4300 of the burst read operation 4301.

Figure 44 depicts the waveform 4400 of the neural readout operation 4401.

Figure 45 depicts neural read operation 4500. Neural read operation 4500 begins (4501). Excitation data is loaded into the column register (4502). Then, a group of N columns is enabled (4503). Next, the row address is input (4504). A read operation (4505) is performed, which involves DAC sampling as shown in Figures 37A and 37B (which utilizes the circuits shown in Figures 35A-B, 36, 38, and 39A-39D) and the (bit line) output circuit 3407 as shown in Figure 34 (which uses ITV to convert current to voltage and uses ADC to convert voltage to digital output), where the output data is from the digital output of the ADC. The data is loaded into the output register (4506). The system determines whether another row address needs to be read. If yes, it returns to operation 4504. If no, the system determines whether another set of N columns needs to be read (4508). If yes, it returns to operation 4503. If no, the neural read operation is completed (4509), at which point the data output can be optionally shifted out (4510) or the neural read operation ends. For each neural read operation, for a set of columns with row switching, the neural read time is 1 column DAC delay + N ITV+DAC delay with N row multiplexing. For example, if the DAC delay is 2μs and the ITV+ADC delay is 1μs, then the time to read the entire column is 1x(DAC delay) + 16x(ITV+ADC delay) = 18μs. Basically, the DAC delay doesn't contribute any extra time for the next line of neural readout.

Figure 46 illustrates neural read operation 4600. Neural read operation 4600 begins (4601). Activation data is loaded into the first set of column registers (4603). Then, activation data is loaded into the second set of column registers (4602). Simultaneously, the row address or column group changes (4604). The read operation is performed (4605). Output data is loaded into the output register (4606). If the read operation is not completed (4607), the process returns to operation 4604. If the read operation is completed, the system (using a logic controller, not shown) determines whether data needs to be loaded from the second set of column registers into the first set of column registers (4608). If not, the neural read operation is completed (4611). If yes, the data is loaded from the second set of column registers into the first set of column registers (4609). Then the system determines whether the neural read operation is complete (4610). If yes, the neural read operation is completed (4611). If not, it returns to operation 4604.

Figure 47 depicts neural read operation 4700. First, the activation data is loaded into the first set of column registers (4701). Then, the activation data is loaded into the second set of column registers (4702). Simultaneously, the row address or column group changes (4703). The read operation is performed (4704). The data is loaded into the output register (4705). If the read operation is complete (4706), the system proceeds to operation 4707. If not, the system returns to operation 4703. In operation 4707, the system determines whether the second set of column registers and its corresponding column S/H buffers are enabled. If yes, the operation is complete (4708). If not, the second set of column registers and their corresponding column S/H buffers are enabled, and the system returns to operation 4703 to continue the neural read operation.

Figure 48 illustrates read operation 4800. Previously, digital output data has been loaded into output register 1 or output register 2. Then, the output data is removed from output register 1 or output register 2 (4801).

Figure 49 depicts neural read operation 4900. First, activation data is loaded into the column register (4901). Then, the data is removed from output register 1 or output register 2 (4902). Simultaneously, the row address or column group changes (4903). The neural read operation is performed (4904). Data is loaded into output register 1 or output register 2 (4905). If the neural read operation completes (4906), the operation is complete (4907). If not, the system returns to operation 4903 to continue the neural read operation.

It should be noted that, as used herein, the terms "above" and "on" include, in a comprehensive manner, "directly on" (without any intermediate material, component, or space) and "indirectly on" (with any intermediate material, component, or space). Similarly, the term "proximate" includes "directly proximate" (without intermediate materials, components, or spaces) and "indirectly proximate" (with intermediate materials, components, or spaces), "mounted to" includes "directly mounted to" (without intermediate materials, components, or spaces) and "indirectly mounted to" (with intermediate materials, components, or spaces), and "electrically coupled" includes "directly electrically coupled to" (without intermediate materials or components electrically connecting the components together) and "indirectly electrically coupled to" (with intermediate materials or components electrically connecting the components together). For example, forming a component "above the substrate" can include forming a component directly on the substrate without intermediate materials/components, and forming a component indirectly on the substrate with one or more intermediate materials/components.

C1: Layer C2: Layer C3: Layer CB1: Synapse CB2: Synapse CB3: Synapse CB4: Synapse P1: Excitation Function P2: Excitation Function S1: Layer S2: Layer

Claims (18)

An input circuit for an artificial neural network array includes: a plurality of address decoders for receiving an address and outputting a plurality of column enable signals in response to an address; a first plurality of registers electrically connected to the plurality of address decoders for sequentially storing excitation data in response to the plurality of column enable signals; and a second plurality of registers electrically connected to the first plurality of registers for storing excitation data received from the first plurality of registers in parallel. The input circuit of claim 1 includes: a plurality of column sampling and holding buffers for responding to excitation data received from the second plurality of registers, and driving each column of a non-volatile memory cell array during a neural read operation. The input circuit of claim 1 includes: a static random access memory for providing the stimulus data to be stored in the first plurality of registers. An operation method of an input circuit includes: outputting a plurality of column enable signals in response to an address using a plurality of address decoders; sequentially storing excitation data in response to the plurality of column enable signals using a first plurality of registers; and storing excitation data received from the first plurality of registers in parallel using a second plurality of registers. The method of operation, as described in claim 4, includes: responding to stimulus data received from the second plurality of registers by means of a plurality of column sampling and holding buffers, and driving columns of a non-volatile memory cell array during a read neuron operation. As in the method of operation of claim 4, the sequential storage includes receiving the stimulus data from a static random access memory via the first plurality of registers. An input circuit for an artificial neural network array includes: a plurality of address decoders for receiving an address and outputting a plurality of column enable signals in response to an address; and a first plurality of registers electrically connected to the plurality of address decoders for storing first excitation data and at least one first tag bit in response to the plurality of column enable signals; wherein, when the at least one first tag bit has a first value, the first plurality of registers respectively output the first excitation data, and when the at least one first tag bit has a second value, the first plurality of registers do not output the first excitation data. The input circuit of claim 7 includes: a plurality of column sampling and holding buffers for responding to the first stimulus data output by the first plurality of buffers to drive the columns of a non-volatile memory cell array. The input circuit of claim 7 includes: a second plurality of registers electrically connected to the plurality of address decoders for responding to the plurality of column enable signals to store second excitation data and at least one second tag bit; wherein, when the at least one second tag bit has a first value, the second plurality of registers respectively output the second excitation data, and when the at least one second tag bit has a second value, the second plurality of registers do not output the second excitation data. The input circuit of claim 9 includes: a plurality of column sampling and holding buffers for responding to a first stimulus data from the first plurality of registers or a second stimulus data from the second plurality of registers to drive columns of a non-volatile memory cell array. An operation method of an input circuit includes: outputting a plurality of column enable signals in response to an address using a plurality of address decoders; storing activation data and a first set of tag bits in response to the plurality of column enable signals using a first plurality of registers; outputting the activation data using the first plurality of registers when the first set of tag bits respectively contain a first value; and not outputting the activation data using the first plurality of registers when the first set of tag bits respectively contain a second value. The method of operation of claim 11 includes: driving columns of a nonvolatile memory cell array in response to the stimulus data output from the first plurality of registers by means of a plurality of column sampling and holding buffers. The method of operation of claim 11 includes: storing second stimulus data and a second set of tag bits in response to the multiple column enable signals using a first plurality of registers; outputting the second stimulus data when the second set of tag bits contains a first value using a second plurality of registers; and not outputting the second stimulus data when the second set of tag bits contains a second value using the second plurality of registers. The method of operation, as described in claim 13, includes: driving columns of a non-volatile memory cell array in response to stimulus data output from the second plurality of registers by means of a plurality of column sampling and holding buffers. An input circuit for an artificial neural network array includes: a plurality of address decoders for receiving an address and outputting a plurality of column enable signals in response to an address; and a first plurality of registers electrically connected to the plurality of address decoders for storing first activation data and a first tag bit in response to the plurality of column enable signals, wherein when a stored first tag bit has a first value, the first plurality of registers respectively output the first activation data, and when the stored first tag bit has a first value, the first plurality of registers respectively output the first activation data. When a second value is present, the first plurality of registers do not output the first excitation data, and the second plurality of registers are electrically connected to the plurality of address decoders to store the second excitation data and the second tag bit in response to the plurality of column enable signals. When a stored second tag bit has a first value, the second plurality of registers respectively output the second excitation data, and when the stored second tag bit has a second value, the second plurality of registers do not output the second excitation data. The input circuit of claim 15 includes: a first plurality of column sampling and holding buffers for driving columns of a non-volatile memory cell array in response to a first stimulus data output from the first plurality of buffers; and a second plurality of column sampling and holding buffers for driving columns of the non-volatile memory cell array in response to a second stimulus data output from the second plurality of buffers. An operation method of an input circuit includes: receiving an address and outputting a plurality of column enable signals in response to an address using a plurality of address decoders; storing first excitation data and a first set of tag bits in response to the plurality of column enable signals using a first plurality of registers; storing second excitation data and a second set of tag bits in response to the plurality of column enable signals using the first plurality of registers; outputting the first excitation data in response to the first set of tag bits using the first plurality of registers; and outputting the second excitation data in response to the second set of tag bits using the second plurality of registers. The method of operation of claim 17 includes: driving a column of a non-volatile memory cell array in response to the first stimulus data from the first plurality of registers using a first plurality of column sampling and holding buffer; and driving a column of a non-volatile memory cell array in response to the second stimulus data from the second plurality of registers using a second plurality of column sampling and holding buffer.