TWI906547B - A circuit, an integrated circuit and a method of operating a circuit - Google Patents

Abstract

In accordance with an embodiment, a circuit includes a plurality of comparators disposed on an integrated circuit, the plurality of comparators having inputs coupled to a monitored power supply line; and a voting circuit having inputs coupled to outputs of the plurality of comparators. An output of the voting circuit is configured to provide a signal indicative of a brown out condition of a power source coupled to the monitored power supply line.

Description

Methods of circuits, integrated circuits, and operating circuits

This invention generally relates to undervoltage detector devices with or without C-element compensation and their operation methods.

Cross-referencing of related applications

This application claims the benefit of U.S. Provisional Patent Application No. 63/286,851, filed December 7, 2021, under 35 U.S.C. § 119(e), the entire contents of which are incorporated herein by reference for all purposes.

Many circuits and systems are designed to receive power supply voltages within a specified range. For example, a simple battery-powered device using two 1.5V batteries might be designed to operate with a power supply voltage between 2.5V and 3.5V. However, when the power supply voltage drops below the minimum specified voltage of 2.5V, the circuitry within this device may no longer operate in a predictable manner, and its behavior may become unstable. To avoid the potential negative effects of low power supply voltage, many circuits and systems include an undervoltage detector, a circuit that monitors the power supply and provides a signal to indicate a low power supply voltage condition. Therefore, the circuit or system can automatically shut down upon receiving a signal indicating a low power supply voltage condition.

Systems such as digital processors may exhibit noisy supply voltages due to interactions between circuit switching behavior and induced power lines. Therefore, a challenge in undervoltage detector design is addressing false triggering caused by transient voltages on the power lines. For example, it is generally desirable to maintain circuit operation when a circuit with otherwise sufficient supply voltage experiences a brief transient or voltage surge on the power supply. However, if brief transients or voltage surges are frequently misinterpreted as undervoltage conditions, the system may unnecessarily shut down.

Such accidental triggering can be avoided by low-pass filtering of the monitored power supply at low power levels. However, low-pass filtering may cause a delay in detecting lower voltage conditions, which could lead to the system operating unstablely for a short period.

According to one embodiment, a circuit includes a plurality of comparators disposed on an integrated circuit, the plurality of comparators having inputs coupled to a monitored power line; and a voting circuit having inputs coupled to the outputs of the plurality of comparators. The output of the voting circuit is configured to provide a signal indicating an undervoltage condition of the power supply coupled to the monitored power line.

According to another embodiment, a method of operating an integrated circuit includes: comparing a first voltage at a first point on a power bus with a first reference voltage; comparing a second voltage at a second point on the power supply with a second reference voltage; transitioning to an undervoltage state when the first voltage is less than the first reference voltage and the second voltage is less than the second reference voltage; and maintaining the undervoltage state after transitioning to the undervoltage state while the first voltage remains less than the first reference voltage or the second voltage remains less than the second reference voltage. The system exits the undervoltage state when the first voltage exceeds the first reference voltage and the second voltage exceeds the second reference voltage. After exiting the undervoltage state, it remains in the undervoltage state as long as the first voltage remains higher than the first reference voltage or the second voltage remains higher than the second reference voltage. It also indicates the undervoltage condition upon transitioning to the undervoltage state.

According to a further embodiment, an integrated circuit includes: a memory circuit; and a conductive power bus coupled between a power node and a power input of the memory circuit; an undervoltage detector coupled to the conductive power bus, the undervoltage detector including: a first comparator having a signal input coupled to the conductive power bus; a second comparator having a signal input coupled to the conductive power bus; and a voting circuit whose input is coupled to the outputs of the first and second comparators, and whose output is coupled to a shutdown input of the memory circuit.

100: Undervoltage Detector

102: Comparator

104: Schmidt trigger

106: Delayed Block

108: Low-pass filter

200: Undervoltage Detector System

202: Undervoltage Detector

204: Comparator

206: Comparator

208: Reference Voltage Generator

210: Voting Circuit

212: Circuit

214: Circuit shutdown

216: Power Supply

218: Conductive Power Bus

300: Undervoltage Detector

302:c component

310: Time

312: Time

320:c component

322:AND Gate

324:OR Gate

326:OR Gate

328: AND Gate

330: Voting Circuit

332:c component

334:c component

336:c component

400: Undervoltage Detector

402: Majority Decision

410: Majority decision-making

412:AND Gate

414:AND Gate

416:AND Gate

418:OR Gate

500: Integrated Circuits

501: Undervoltage Detection Circuit

502: Power pin

503: Star Node

504: Conductive power bus

505: Power Input Node

506: Circuit One

507: Second Circuit

510: First Comparator

512: Second Comparator

514: Additional Comparator

516: Voting Circuit/Comparator

520: Integrated Circuits

521: Undervoltage Detector

530: Integrated Circuits

531: Undervoltage Detection Circuit

535: Power Input Node

540: Integrated Circuits

541: Undervoltage Detector

550: Integrated Circuits

551: Undervoltage Detector

560: Integrated Circuits

561: Undervoltage Detector

562: Single-chip power supply circuit

600: Integrated Circuits

601: Power Pin

602: Column decoder

603: Undervoltage Detector

604: Memory Array

606: Memory controller

610: Sensing Amplifier

612: Line decoder

614:I/O logic

620: Memory Circuit

622: Conductive power cord

700: Method

704, 706, 708, 710: Steps

720, 722, 724: Steps

800: Power Monitoring Circuit

802: Resistor voltage divider

804: Analog Multiplexer

806: Lag Controller

902: Trajectory/Voltage Divider Power Supply Voltage

904: Trace

906: Time

910: trace

912: Sudden Wave

914: Bistate Thixotropy

932: Trace

934: Trace

936: Time

940: trace

952: Trace

954: Trace

956: Trace

958: Trace

960: trace

962: Trace

964: Trace

To gain a more complete understanding of the present invention and its advantages, the following description is now taken in conjunction with the accompanying drawings, in which: [Figure 1] illustrates a schematic diagram of an exemplary undervoltage detector; [Figure 2] illustrates a schematic diagram of an undervoltage detector according to one embodiment; [Figure 3A] illustrates a schematic diagram of an undervoltage detector according to one embodiment; [Figure 3B] illustrates a truth table of a voting circuit according to an embodiment; [Figure 3C] illustrates a timing diagram of a voting circuit according to an embodiment; [Figure 3D] illustrates a schematic diagram of a voting circuit according to an embodiment; [Figure 3E] illustrates a block diagram of a voting circuit according to an embodiment; [Figure 4A] illustrates a schematic diagram of an undervoltage detector according to one embodiment. Figures: [Figure 4B] illustrates a schematic diagram of a voting circuit of one embodiment; [Figures 5A], [Figure 5B], [Figure 5C], [Figure 5D], [Figure 5E], and [Figure 5F] illustrate block diagrams of an integrated circuit using an undervoltage detector of one embodiment; [Figure 6] illustrates a block diagram of the memory of an integrated circuit using an undervoltage detector of one embodiment; [Figures 7A] and [Figure 7B] illustrate block diagrams of a method according to one embodiment; [Figure 8] illustrates a power monitoring circuit according to one embodiment; and [Figures 9A], [Figure 9B], and [Figure 9C] illustrate waveform diagrams related to the performance of the power monitoring system of one embodiment.

Unless otherwise stated, corresponding numbers and symbols in the different figures generally refer to the corresponding parts. The figures are drawn to clearly illustrate relevant aspects of the preferred embodiments and are not necessarily drawn to scale. To further illustrate certain embodiments, letters indicating variations in the same structure, material, or processing steps may follow the figure numbers.

The making and use of the current preferred embodiments are discussed in detail below. However, it should be understood that this invention provides many applicable inventive ideas that can be embodied in a wide variety of specific environments. The specific embodiments discussed are merely illustrative of specific ways of implementing and using this invention and do not limit the scope of this invention.

In one embodiment, a plurality of comparators and a voting circuit are used to implement an undervoltage detector for monitoring a power supply. In some embodiments, the voting circuit indicates an undervoltage condition when most comparators indicate a low power supply voltage. In other embodiments, such as those including two comparators, the voting circuit uses a C element to indicate an undervoltage condition after all comparators indicate a low power supply voltage, or after an undervoltage condition has occurred and at least one of the comparators indicates a low power supply voltage.

Advantages of these embodiments include reduced erroneous undervoltage detection, which can occur when a large transient current momentarily lowers the voltage at the power node. In some embodiments, erroneous detection can be reduced without low-pass filtering at the power node and/or without using a comparator with hysteresis circuitry. This advantageously allows for very fast undervoltage detection using small circuitry, and the ability to quickly detect undervoltage conditions while avoiding erroneous detection. Some embodiments also advantageously avoid power supply double-state thixotropy caused by delay. This phenomenon occurs when an undervoltage detector incorrectly detects a transient undervoltage condition and shuts off the power supply. Once the power supply is shut off, the power voltage recovers rapidly and is detected again by the undervoltage detector, causing the power supply to shut down briefly, depending on the detector's delay. Therefore, whenever the undervoltage detector is incorrectly triggered, the power supply shuts off. In some cases, restarting the circuit may take several milliseconds.

Figure 1 illustrates an exemplary undervoltage detector 100. As shown, the undervoltage detector 100 includes a comparator 102, a Schmitt trigger 104, a hysteresis block 106, and a low-pass filter 108. During operation, the comparator 102 compares the monitored power supply VDD with a reference voltage _VREF . In principle, when the voltage of the monitored power supply VDD is greater than the voltage _VREF , the power status signal _POK is at a high level, indicating that the monitored power supply VDD has a sufficiently high voltage to reliably power the connected circuitry. On the other hand, when the voltage of the monitored power supply VDD is not greater than the voltage _VREF , the power status signal _POK is low, indicating that the monitored power supply VDD is too low to reliably power the connected circuit. The power status signal _POK can be used to shut down the connected circuit under such low power conditions.

In most practical systems, power supply voltages are typically noisy due to the switching behavior of single-chip switches. Therefore, low-pass filtering and hysteresis are often added to undervoltage detection circuits to prevent metastable behavior at the comparator output when the voltage of the monitored power supply VDD is very close to the reference voltage _VREF . To avoid such metastable behavior, hysteresis and low-pass filtering are typically added to undervoltage detection circuits. For example, an exemplary undervoltage detector 100 includes a low-pass filter 108 configured to filter the power supply voltage, thereby attenuating high-frequency transients. The hysteresis block 106 shifts the input voltage to the comparator 102 based on the output of the comparator 102, causing the threshold of the comparator 102 to depend on the output of the comparator 102, thereby reducing the occurrence rate of "flickering" at the output of the comparator 102. Finally, the Schmitt trigger 104 applies a further hysteresis to the output of the comparator 102, which can have a lower slope and/or slower response when the voltage of the monitored power supply VDD is very close to the reference voltage _VREF .

While each of the low-pass filter 108, hysteresis block 106, and Schmitt trigger 104 can effectively reduce the metastable behavior of comparator 102, such reduction may come at the cost of additional circuitry and a slower response.

Figure 2 illustrates an undervoltage detector system 200 according to an embodiment of the present invention. The undervoltage detector system 200 includes an undervoltage detector 202, a reference voltage generator 208, and a powered circuit 212 that receives power from a power source monitored by the undervoltage detector 202.

In embodiments of the present invention, the undervoltage detector 202 includes a plurality of comparators 204 to 206 and a voting circuit 210 to monitor the power supply voltage VDD of the conductive power bus 218. Although only two comparators 204 and 206 are explicitly represented, in some embodiments, the undervoltage detector 202 may include more than two comparators. The voting circuit 210 is configured to indicate an undervoltage condition when a majority of comparators 204 to 206 indicate that an undervoltage condition exists. In some embodiments, the voting circuit 210 indicates an undervoltage condition when a majority of comparators 204 to 206 indicate that the power supply voltage is too low. In other words, each comparator 204 to 206 is given a "vote" regarding the power supply state. Such a majority decision function can be implemented using the majority decision gate described below with respect to Figure 4B.

In some embodiments, such as those using an even number of comparators, an additional "vote" is given to the previous output state of the undervoltage detector 202. For example, in a system with two comparators 202 and 206, the voting circuit indicates the presence of undervoltage condition 206 when both comparators 204 and 206 indicate an undervoltage condition, or when the voting circuit 210 previously indicated an undervoltage condition (e.g., P _OK not asserted) and at least one of comparators 204 and 206 indicates an undervoltage condition (e.g., the voltage at the positive terminal is less than the voltage at the negative terminal). In such an embodiment, the voting circuit 210 can be implemented using a circuit with a Mueller C element, as shown below with respect to Figures 3A-3E.

As shown in the figure, power supply 216 is configured to supply power to circuit 212 via conductive power bus 218. Undervoltage detector 202 is coupled to conductive power bus 218 and configured to monitor the voltage on conductive power bus 218. During operation, when the voltage on conductive power bus 218 is higher than a predetermined voltage, an assertion is made regarding the power status signal P _OK .

In various embodiments, the power status signal P _OK is coupled to the input of the shutdown circuit 214 within circuit 212, such that circuit 212 is in a de-energized state when the power status signal P _OK is not asserted. In some embodiments, such as when circuit 212 is a clock digital circuit, the shutdown circuit 214 can de-energize circuit 212 by controlling a clock. In other embodiments, the shutdown circuit 214 can de-energize circuit 212 by disconnecting circuit 212 from the conductive power bus 218. This disconnection can be achieved, for example, by opening a switch coupled between the conductive power bus 218 and an internal power bus within circuit 212. In an alternative embodiment, the power status signal P _OK may be routed to another circuit separate from circuit 212 (e.g., a controller responsible for managing the power status of various circuits), and/or may be routed to an external pin, status register, or digital interface.

Power supply 216 represents any power source that can be coupled to conductive power bus 218. In some embodiments, power supply 216 may be an external DC power source, such as a regulated DC power supply or a battery. In such embodiments, conductive power bus 218 is electrically connected to bonding pads or other external connections on which integrated circuitry 218 and circuitry 212 are disposed.

The undervoltage detector 202 includes a plurality of comparators 204 and 206 and a voting circuit 210. Comparators 204 and 206 are each configured to compare their respective reference voltage with the voltage VDD of the conductive power bus 218. For example, comparator 204 compares the voltage VDD with the voltage at node _VREF1 , and comparator 206 compares the voltage VDD with the voltage at node _VREFN . Although only two comparators 204 and 206 are described for simplicity, it should be understood that in some embodiments, the undervoltage detector 202 may include more than two comparators. Each comparator 204 and 206 can be implemented using comparator circuits known in the art. For example, in some embodiments, comparators 204 and 206 can be implemented using differential amplifiers, such as a pair of emitter-coupled BJT transistors or a pair of source-coupled MOS transistors, wherein current is supplied to the transistors via a current source or resistor. In some embodiments, comparators 204 and 206 may include one or more level shifters at the positive and/or negative input terminals to shift the measured supply voltage to a lower voltage level.

In an alternative embodiment of the invention, comparators 204 and 206 may be replaced by a separate undervoltage detection circuit, such as the undervoltage detector 100 shown in FIG. 1. In this alternative embodiment, the corresponding undervoltage detector may include a comparator and at least one of a low-pass filter 108, a hysteresis block 106, or a Schmitt trigger 104. Other undervoltage detectors known in the art may also be used.

In some embodiments, the voltages at nodes _VREF1 and _VREF2 can be generated by reference voltage generator 208. The voltages at nodes _VREF1 and _VREF2 may be the same or different, depending on the specific embodiment and its specifications. Reference voltage generator 208 can be implemented using voltage reference circuits known in the art, such as bandgap voltage references. In some embodiments, one or more comparators 204 and 206 are coupled to the same physical reference voltage, but provide different effective comparison thresholds via internal voltage dividers coupled to positive inputs with different voltage division ratios. Therefore, in some embodiments, comparators 204 and 206 can effectively compare the voltage of the conductive power bus 218 with different reference voltages by using different voltage division ratios (e.g., using a resistive voltage divider) to divide the voltage of the conductive power bus 218 and comparing the divided voltage with the same reference voltage. In some embodiments, the voltage divider can be adjusted for performing the voltage division and for applying lag to its corresponding comparator, as discussed below with respect to Figure 8.

Figure 3A illustrates an undervoltage detector 300 that can be used to implement the undervoltage detector 202 shown in Figure 2 according to an embodiment of the present invention. As shown, the undervoltage detector 300 includes two comparators 204 and 206, and a c-element 302 having inputs coupled to the outputs of the comparators 204 and 206.

In one embodiment, comparator 204 is configured to compare the monitored supply voltage VDD with a reference voltage _VREFH , and comparator 206 is configured to compare the monitored supply voltage VDD with a reference voltage _VREFL , wherein the voltage of _VREFH is higher than that of _VREFL . Using two different reference voltages effectively enables the undervoltage detector 300 to provide a fast response and low latency when detecting the monitored supply voltage VDD. In various embodiments, the reference voltage _{VREFL is} used, while _VREFH can be set to be less than the minimum expected operating voltage of a particular circuit or system. For example, in a system with a nominal operating voltage of 3.3V and a minimum operating voltage of 3.0V, the reference voltage _VREFH can be set to 2.85V, and the reference voltage _VREFL can be set to 2.80V. Therefore, when the power supply rises to its nominal value upon startup, the power status signal _POK will not be asserted until the power supply voltage is at least 2.85V. On the other hand, in undervoltage conditions, the power status signal _POK will not be asserted until the power supply voltage reaches at least 2.80V. It should be understood that this is only one specific numerical example among many feasible embodiments. In alternative embodiments, the actual reference voltages _VREFH and _VREFL used may differ. In some embodiments, the values of the reference voltages _VREFH and _VREFL may depend on the details of the circuit system powered by the power supply voltage VDD and its ability to reliably withstand lower voltages.

It should be understood that, in some embodiments, the reference voltages _VREFH and _VREFL are reliably closer than in embodiments that rely on applying lag to a single comparator (e.g., the exemplary undervoltage detector 100 shown in Figure 1). This is because a lag is typically required in the undervoltage detector 100 (which results in a corresponding reduction in the available margin of the circuit) to prevent or mitigate the bi-state thixotropy caused by the aforementioned detection delay. Therefore, in some embodiments, the reduced lag provides a corresponding increase in margin.

In one embodiment, c-element 302 (also referred to in the art as a "Muller c-element") is described with respect to Figures 3B, 3C, and 3E. Figure 3B illustrates the truth table of c-element 302 that implements the following logical equation: Y _{_n} = A．B+(A+B)．Y_{_n-1}, where Y _{_n} is the next output of c-element 302 (e.g., the next value of the power status signal P_{_OK} ), Y _{_n-1} is the previous output of c-element 302, and A and B are the logical inputs of c-element 302 (e.g., the logical outputs of comparators 204 and 206). As shown in Figure 3B, when both A and B are at high levels, _Yn is "1", which means that the power status signal _POK is asserted when comparators 204 and 206 determine that the monitored supply voltage VDD is greater than their respective reference voltage inputs; when both A and B are at low levels, _Yn is "0", which means that the power status signal _POK is not asserted when both comparators 204 and 206 determine that the monitored supply voltage VDD is not greater than their respective reference voltage inputs. However, when the outputs of comparators 204 and 206 are in different states (e.g., A="1" and B="0" or A="0" and B="1"), for example, when one of comparators 204 and 206 determines that the monitored supply voltage VDD is greater than its respective reference voltage and the other of comparators 204 and 206 determines that the monitored supply voltage VDD is not less than its respective reference voltage, the value of the power status signal _POK remains unchanged. Therefore, if the power status signal _POK was previously asserted, the signal remains asserted; and if the power status signal _POK was not previously asserted, the signal remains unasserted.

Figure 3C illustrates the timing diagram of component 302, which is consistent with the truth table in Figure 3B. Specifically, it can be seen that at times 310 and 312, when signals A and B transition from being in the same state to being in different states, the output Y remains in the same state. It is this characteristic of component 302 that allows the comparator output to undergo bi-state triggering without causing the undervoltage detector output _POK to undergo bi-state triggering.

Figure 3D illustrates a schematic diagram of c-element 320, which can be used to implement c-element 302 in Figure 3A. As shown, c-element 320 includes AND gates 322 and 328, and OR gates 324 and 326. The inputs of AND gates 322 and 326 are coupled to inputs A and B. The input of OR gate 324 is coupled to the inputs of AND gates 322 and 328, and the input of AND gate 328 is coupled to the outputs of OR gates 324 and 326, thereby forming a latch. It should be understood that c-element 320 shown in Figure 3D is only one of many possible ways to implement c-element 302. In alternative embodiments, other c-element circuits known in the art may be used.

In some embodiments, c-elements can be used to implement voting circuits with more than two inputs. For example, Figure 3E illustrates a schematic diagram of a voting circuit 330 with four inputs, comprising three c-element circuits 332, 334, and 336. As shown, c-element 332 is coupled to inputs A and B, c-element 334 is coupled to inputs C and D, and c-element 336 is coupled to the outputs of c-elements 332 and 334 to produce output Y. In such an embodiment, inputs A, B, C, and D correspond to the outputs of four different comparators. Cascading c-elements in this manner is particularly suitable for systems with an even number of comparators; however, embodiments can be adapted to systems with an odd number of comparators. For example, in a system with three inputs A, B, and C, element c 334 can be omitted, and the output C of the third comparator can be directly coupled to element c 336.

Figure 4A illustrates an undervoltage detector 400 according to an embodiment of the present invention, which can be used to implement the undervoltage detector 202 shown in Figure 2. As shown, the undervoltage detector 400 includes at least three comparators 204, 205, and 206, and a majority decision gate 402 having at least three inputs coupled to the outputs of the comparators 204, 205, and 206. In various embodiments, the majority decision gate 402 is configured to assert a power status signal P _OK when a majority of its inputs are asserted.

In one embodiment, comparators 204, 205, and 206 are configured to compare the monitored power supply VDD with corresponding reference voltages _VREF1 , _VREF2 , and _VREFN . In some embodiments, these reference voltages are configured to be different, while in other embodiments, two or more of the reference voltages _VREF1 , _VREF2 , and _VREFN may be configured to be the same.

Figure 4B illustrates a schematic diagram of a multiple-delay gate 410, which can be used to implement the multiple-delay gate 402 shown in Figure 4A. The multiple-delay gate 410 includes AND gates 412, 414, and 416 and an OR gate 418. The inputs of AND gate 412 are coupled to inputs A and C, the inputs of AND gate 414 are coupled to inputs B and C, and input 416 of AND gate 414 is coupled to inputs A and B. Therefore, when at least two of the three inputs A, B, and C are asserted, the output signal Y is asserted. It should be understood that the implementation of the multiple-delay gate 410 shown in Figure 4B is only one example of many possible ways to implement a multiple-delay gate. In alternative embodiments, other multiple-delay gate structures or other logically equivalent circuits may be used. For example, in some embodiments, AND gates 412, 414, and 416, and OR gate 418 can each be replaced by a NAND gate. In yet another alternative embodiment, majority gate 410 can be adapted to perform a majority function on more than three inputs.

In the above embodiments, it should be understood that the digital logic circuits described herein represent only a few specific examples of the illustrated logic circuits. In alternative embodiments, other logically equivalent circuits may be used. Furthermore, it should be understood that, using digital logic design techniques known in the art, the disclosed logic circuits using high-level action signals can also be adapted to accept low-level action signals as inputs and/or generate low-level action signals as outputs.

Figures 5A-5F illustrate block diagrams of integrated circuits implementing undervoltage detectors according to various embodiments. Embodiments of the present invention can be implemented in various semiconductor manufacturing processes, including, but not limited to, standard CMOS processes and/or CMOS processes modified to accommodate one or more specific types of non-volatile memory, bipolar processes, or BiCMOS processes. The various components depicted in Figures 5A-5F can be disposed on, for example, a single semiconductor substrate (e.g., a silicon substrate).

Figure 5A illustrates an integrated circuit including a first circuit 506 having a power input node 505 coupled to a power pin 502 via a conductive power bus 504. In various embodiments, the conductive power bus 504 may be implemented on one or more conductive layers (e.g., metal or polysilicon layers) of an integrated circuit 500. The undervoltage detection circuit 501 includes a first comparator 510 and a second comparator 512 having a signal input physically/electrically connected to a point on the conductive power bus 504 near the power input node 505 of the first circuit 506. The outputs of the first comparator 510 and the second comparator 512 are coupled to a voting circuit 516, which may be implemented using one or more C-elements or multiple gates, as described above with respect to the embodiments of Figures 2, 3A-3E, and 4A-4B. In various embodiments, the undervoltage detection circuit 501 is connected to a conductive power bus 504 at a point closer to the power pin 502 and/or closer to the power star node 503 (also referred to as the "star point"), the power star node 503 being a point where the conductive power bus 504 branches into a plurality of power bus segments. In one embodiment, comparators 510 and 512 may have different comparison thresholds, as described above with respect to Figures 2, 3A, and 4A.

As shown in the figure, the power status signal P _OK is coupled to the first circuit 506. In some embodiments, the first circuit 506 is configured to be turned off when the power status signal P _OK is not asserted, as described above with respect to Figure 2.

Figure 5B illustrates an integrated circuit 520, which includes a first circuit 506 having a power input node 505 coupled to a power pin 502 via a conductive power bus 504. An undervoltage detector 521 includes a star node 503 having a signal input connection to the conductive power bus 504 via a first comparator 510, and a second comparator 512 having a signal input connected to the conductive power bus 504 near the power input node 505 of the first circuit 506. In some embodiments, the signal input to the first comparator 510 is connected to the conductive power bus 504 at a point closer to the star node 503 or the power pin 502 than the signal input to the second comparator 512. Therefore, the point on the power bus 504 where the input of the second comparator 512 is connected is physically and electrically closer to the first circuit 506 than the point on the power bus 504 where the input of the first comparator 510 is connected. In various embodiments, the signal input of the second comparator is connected to the conductive power bus 504 via a circuit path that does not include a star node.

The embodiment of Figure 5B can advantageously reduce the incidence of erroneous undervoltage detection by monitoring the conductive power bus 504 at different points and by requiring the signal input voltages of comparators 510 and 512 to be lower than their respective comparison thresholds before canceling the assertion power status signal P _OK . In various embodiments, the comparison thresholds associated with comparators 510 and 512 in the undervoltage detector 521 may be the same or different. During operation, when the local power supply of the first circuit 506 experiences a large current transient (which may occur when the first circuit 506 drives a low-impedance load at a high edge rate), a portion of the local power supply may experience a momentary voltage drop at the point of the power supply bus local to the power input node 505. However, the voltage at the star node 503 or power pin 502 may not experience the same degree of voltage drop due to the inductance between the star node 503 and the power input node 505. Therefore, a voltage drop that is visible only locally in the first circuit 506 but not locally at the power pin 502 or star node 503 is unlikely to trigger the undervoltage detector 521. On the other hand, when the power supply voltage is supplied to the power pin 502 from the outside, the voltage will eventually drop at all points on the conductive power bus 504, which will cause the undervoltage detector 521 to detect the undervoltage condition.

Figure 5C illustrates an integrated circuit 530, which includes a first circuit 506 having a power input node 505 coupled to a power pin 502 via a conductive power bus 504, and a second circuit 507 having a power input node 535 coupled to a power pin 502 via a conductive power bus 504. An undervoltage detection circuit 531 includes a first comparator 510 and a second comparator 512, whose signal inputs are connected to a star node 503 of the conductive power bus 504. In some embodiments, comparators 510 and 512 may have different comparison thresholds and/or may be configured to compare the voltage of the star node 503 with different reference voltages, as described above with respect to Figures 2, 3A, and 4A. The power status signal P _OK is coupled to both the first circuit 506 and the second circuit 507. In some embodiments, one or both of the first circuit 506 and the second circuit 507 are configured to be turned off when the power status signal P _OK is not asserted.

The embodiment of Figure 5C can advantageously reduce the incidence of erroneous undervoltage detection by monitoring the conductive power bus 504 at the star node 503. During operation, when the local power supply of the first circuit 506 or the second circuit 507 experiences a large current transient, portions of the conductive power bus 504 at the local power input node 505 of the first circuit 506 and/or the power input node 535 of the second circuit 507 may experience a momentary voltage drop. However, due to the line inductance between the star node 503 and the power input nodes 505 and 535, the voltage at the star node 503 or the power pin 502 may not experience the same degree of voltage drop. Therefore, when the signal inputs of comparators 510 and 512 are connected to the conductive power bus 504 near the star node 503, a voltage drop that is visible only on the conductive power bus 504 adjacent to the first circuit 506 or the second circuit 507, but invisible near the power pin 502 or the star node 503, is unlikely to trigger the undervoltage detector 521.

Figure 5D illustrates an integrated circuit 540, which includes an embodiment of an undervoltage detector 541 having a first comparator 510 and a second comparator 512. The signal input of the first comparator 510 is connected to a conductive power bus 504 near a power input node 505 of the first circuit 506, while the signal input of the second comparator 512 is connected to a conductive power bus 504 near a power input node 535 of the second circuit 507. The comparison thresholds associated with comparators 510 and 512 may be the same or different.

The embodiment of Figure 5D can advantageously reduce the incidence of erroneous undervoltage detection by monitoring the conductive power bus 504 at the corresponding power input nodes 505 and 535 of the first circuit 506 and the second circuit 507, especially in a system where the first circuit 506 is unlikely to experience a large current transient simultaneously with the second circuit 507. Therefore, even if the second circuit 507 experiences a current transient that causes a corresponding instantaneous drop in the supply voltage at power node 535, the voltage at power input node 505 of the first circuit 506 is unlikely to experience a voltage drop of the same magnitude due to the line inductance of the conductive power bus 504. Therefore, the undervoltage detector 541 is unlikely to detect an undervoltage condition under such circumstances.

Figure 5E illustrates an integrated circuit 550 including an undervoltage detector 551 according to an embodiment of the present invention. The integrated circuit 550 is similar to the integrated circuit 540 discussed above with respect to Figure 5D, except that the undervoltage detector 551 includes an additional comparator 514, whose signal input is coupled to a star node 503 of a conductive power bus 504. The comparison thresholds associated with comparators 510, 512, and 514 may be the same or different. In some embodiments of the embodiment of Figure 5E, the occurrence rate of erroneous undervoltage detection can be further reduced compared to the embodiment of Figure 5D, because the voltages near all three points 503, 505, and 535 will need to be reduced below the corresponding reference voltages of the corresponding comparators 514, 510, and 512 before the undervoltage detector 551 detects the undervoltage condition and clears the assertion power status signal P _OK .

Although the embodiments of Figures 5D and 5E only show their respective undervoltage detectors locally connected to the power nodes of the two circuits (e.g., the first circuit 506 and the second circuit 507), it should be understood that in further embodiments of the invention, additional circuitry may be coupled to the conductive power bus 504. In such embodiments, undervoltage detectors 541 and 551 may include additional comparators coupled to other points on the conductive power bus 504 in the vicinity of these additional circuits.

The embodiment of the undervoltage detection circuit can also be used to monitor a power bus that receives power from a single-chip power supply circuit rather than from an external pin. Figure 5F illustrates an integrated circuit 560, which includes a first circuit 506 having a power input node 505 coupled to a single-chip power supply circuit 562. Comparators 510 and 512 of the undervoltage detector 561 can be coupled to a conductive power bus 504 at various bit points. For example, in various embodiments, the signal inputs of both comparators 510 and 512 may be coupled to the conductive power bus 504 near the power input node 505 of the first circuit 506; the signal inputs of both comparators 510 and 512 may be coupled to the conductive power bus 504 near the output of the single-chip power circuit 562; or the signal input of one of comparators 510 and 512 may be connected to the conductive power bus 504 near the output of the single-chip power circuit 562, while the signal input of the other of comparators 510 and 512 may be connected to the conductive power bus 504 near the power input node 505. Alternatively, the signal inputs of comparators 510 and 512 may be connected to other points on the conductive power bus 504.

The single-chip power supply circuit 562 can be implemented using single-chip power supply circuits known in the art, including, but not limited to, series regulation circuits, mode-switching power supplies, and charge pump circuits.

Figure 6 illustrates an integrated circuit 600 including a memory circuit 620 and an undervoltage detector 603 according to an embodiment of the present invention. As shown, the memory 620 includes a memory array 604, a column decoder 602, a memory controller 606, a sensing amplifier 610, a row decoder 612, and an I/O logic 614, which are coupled to a power pin 601 via a conductive power line 622. The undervoltage detector 603, which can be implemented using any embodiment of the undervoltage detection circuit described herein, has inputs A and B coupled to the conductive power line 622, and an output configured to provide a power status signal P _OK . Inputs A and B may be connected to a single point or multiple points on the conductive power line 622 and/or may have more than two inputs, as described above with respect to the embodiments of Figures 2, 3E, 4A-4B and 5E.

Although Figure 6 shows all functional blocks in memory circuit 620 connected to the same power supply line 622, it should be understood that in other embodiments, more than one power bus and/or power pin may be used to power specific functional blocks within memory circuit 620. In further embodiments, one or more portions of memory circuit 620 may also be powered by a single-chip power supply circuit, as discussed above with respect to Figure 5F. Integrated circuit 600 may also include other circuits besides memory circuit 620, such as those in a processor and/or integrated circuits with single-chip embedded memory.

Memory array 604 includes an array of memory cells, which may include non-volatile memory cells such as floating gate memory cells or SONOS memory cells. Sensing amplifier 610 is coupled to a row of memory array 604 and configured to detect the state of memory cells within memory array 604. During operation, based on the address data ADDR provided at the input of I/O logic 614, the column decoder selects a column of memory cells within memory array 604 that will be read by the sensing amplifier 610, and the row decoder 612 selects the row of the memory array that will be output via the data line DATA through I/O logic 614. Memory controller 606 is a memory controller that controls the operation of the memory. Undervoltage detector 603 provides a power status signal P _OK to memory controller 606 based on the detected voltage of conductive power line 622. In various embodiments, the memory controller 606 is configured to shut down the memory circuit 620 when the power status signal P _OK is not asserted.

Figures 7A and 7B are block diagrams illustrating a method for monitoring a power bus. As shown in Figure 7A, method 700 includes comparing a voltage at a first point on the power bus with a first reference voltage using a first comparator (step 720), and comparing a voltage at a second point on the power bus with a second reference voltage using a second comparator (step 722). The comparators described with respect to the embodiments herein can be used to implement both the first and second comparators. In various embodiments, the first and second reference voltages and/or the comparison thresholds of the comparators may be the same or different. The first and second points of the power bus may be the same or different, and may be located on portions of the power bus, as discussed herein, for example, with respect to embodiments of Figures 5A-5F. In some embodiments, this method may also include comparing the voltage of the power supply with one or more additional reference voltages using one or more additional comparators. In step 724, a voting function is performed on the outputs of the first and second comparators. As described above with respect to Figures 2, 3A-3E, and 4A-4B, the voting function may implement the function of element-wise or majority-wise switching. In various embodiments, steps 720, 722, and 724 may be performed simultaneously.

Figure 7B illustrates a block diagram of voting function step 724 for an embodiment using a c-based voting function. Step 704 represents an undervoltage state, where the power status signal _POK is unasserted, indicating an undervoltage condition to other components in the system. The voting function remains in the undervoltage state and the power status signal _POK remains unasserted as long as either the first or second comparator indicates a low voltage condition (step 706). Step 706 transitions back to step 704 as soon as the voltage at a first point on the power bus is less than a first reference voltage as measured by the first comparator, or the voltage at a second point on the power bus is less than a second reference voltage as measured by the second comparator. When the conditions of step 706 are no longer met (e.g., when the voltage at a first point on the power bus is not less than a first reference voltage as measured by a first comparator, or the voltage at a second point on the power bus is not less than a second reference voltage as measured by a second comparator), the voting function transitions out of the undervoltage state and into the operating power state in step 708. In step 708, the power status signal _POK is asserted, indicating the operating power status to other components in the system.

As long as neither the first comparator nor the second comparator indicates a low voltage condition (step 710), the voting function remains in the power supply state and the power status signal P _OK remains asserted. Step 710 transitions back to step 708 as soon as the voltage at the first point of the power bus is not less than the first reference voltage as measured by the first comparator, or the voltage at the second point of the power bus is not less than the second reference voltage as measured by the second comparator. When the conditions of step 710 are no longer met (for example, when the voltage at the first point of the power bus is less than the first reference voltage as measured by the first comparator and the voltage at the second point of the power bus is less than the second reference voltage as measured by the second comparator), the voting function transitions from the operating power state to the undervoltage state in step 704, and the power status signal P _OK is de-asserted, indicating the undervoltage state to other components in the system.

Figure 8 illustrates a power monitoring circuit 800 that can replace one or more comparators 204, 205, 206, 510, 512, and 516 appearing in Figures 2, 3A, 4A, and 5A-5E. As shown, the power monitoring circuit 800 includes a resistive voltage divider 802, an analog multiplexer 804, a comparator 102, a capacitor _C1 , a Schmitt trigger 104, and a hysteresis controller 806. The comparator 102 has a positive input _VP coupled to the output of the multiplexer 804 and a negative input coupled to a reference voltage _VREF , _which in some embodiments may be a fixed voltage. The resistive voltage divider 802 includes any number of series-connected resistors _R1 , _R2 to _RN coupled to corresponding nodes _V1 , _V2 to _VN , such that the voltages at nodes _V1 , _V2 to _VN correspond to various voltage division ratios of the monitored supply voltage VDD.

During operation, the lag controller 806 and the analog multiplexer 804 select the first of nodes _V1 , _V2 to _VN when the output CMP of comparator 102 is in a first state, and select the second of nodes _V1 , _V2 to VN when the output CMP of comparator 102 is in a second _state . In a specific operational example, when the voltage at node _VP is less than the voltage _VEREF , the output of comparator 102 is low and the lag controller 806 causes the analog multiplexer 804 to couple node _V2 to node _VP , such that the voltage at node _V2 is applied to the positive input _VP of comparator 102. However, when the voltage at node _VP is greater than the voltage _VEREF , the output of comparator 102 is high and the lag controller 806 causes the analog multiplexer 804 to couple node _V1 to node _VP , such that the voltage at node _V1 is applied to the positive input _VP of comparator 102. In such an embodiment, the effective threshold of the power monitoring circuit 800 is higher when the output CMP of comparator 102 is high than when the output CMP of comparator 102 is low.

The analog multiplexer 804 can be implemented using analog multiplexer circuits known in the art, such as selectively coupling corresponding nodes _V1 , _V2 to _VN to a plurality of switching transistors at node _VP . The analog multiplexer 804 can have any number of inputs equal to or greater than two. The hysteresis controller 806 can be implemented, for example, using a logic circuit (such as one or more logic gates) that maps the state of the output CMP of comparator 102 to the corresponding state of the selection signal SEL.

In some embodiments, capacitor _C1, together with resistors _R1 to _RN of resistor divider 802, can be used for low-pass filtering of the monitored power supply node VDD, and Schmitt trigger 104 can be used to reduce metastable effects at the output of comparator 102. In some embodiments, one or both of capacitor _C1 or Schmitt trigger 104 may be omitted.

Figures 9A-9C illustrate waveforms related to the performance of the exemplary power monitoring system. Figure 9A illustrates a waveform diagram showing the simulated performance of an undervoltage detector circuit (e.g., the exemplary undervoltage detector 100 shown in Figure 1). Trace 902 represents the voltage divider power supply voltage VDD, trace 904 represents the reference voltage _VREF , and trace 910 represents the power supply status signal _POK . As shown, at time 906, the power supply voltage experiences a short voltage transient, which causes a corresponding short voltage transient in the voltage divider power supply voltage 902. This causes a corresponding bi-state thixotropic change 914 (trace 910) in the power status signal _POK . For example, surge 912 caused by excessive current consumption can also be seen in the voltage divider (trace 902).

Figure 9B illustrates a waveform diagram showing the simulated performance of an undervoltage detector circuit (e.g., the undervoltage detector system 200 of the embodiment shown in Figure 2). Trace 932 represents the voltage divider supply voltage VDD, trace 934 represents the reference voltage _VREF1 , and trace 940 represents the power status signal _POK . As shown in the figure, at time 936, the power supply voltage experiences a short voltage transient, which causes a corresponding short voltage transient in the voltage divider supply voltage (trace 902). However, unlike the simulation of the exemplary undervoltage detector 100 shown in Figure 9A, the power status signal P _OK (trace 940) does not undergo bi-state thixotropy and no surge is observed on the voltage divider (trace 902).

Figure 9C illustrates a waveform diagram showing the simulated performance of an undervoltage detector circuit (e.g., the undervoltage detector 300 of the embodiment shown in Figure 3A), where comparators 204 and 206 are replaced by corresponding examples of the power monitoring circuit 800 shown in Figure 8. Trace 952 represents the monitored supply voltage, trace 954 represents the power status signal P _OK , trace 956 represents the output of the first instance of the power monitoring circuit 800, trace 958 represents the output of the second instance of the power monitoring circuit 800, trace 960 represents the reference voltage, trace 962 represents the voltage divider input voltage provided to the comparator 102 of the first instance of the power monitoring circuit 800, and trace 964 represents the voltage divider input voltage provided to the comparator 102 of the second instance of the power monitoring circuit 800.

As shown in the figure, the monitored supply voltage (trace 852) is simulated to be from 2.75V to 2.9V, with each step ramp being 10mV. A first instance of the power monitoring circuit 800 has an effective comparison threshold of 2.8V, and another instance of the power monitoring circuit 800 has an effective comparison threshold of 2.825V.

At t=5μs, the voltage divider input voltage of the first comparator (trace 862) exceeds the reference voltage 860, which causes the output of the first comparator to go high (trace 856). Subsequently, at t=8μs, the voltage divider input voltage of the second comparator (trace 864) exceeds the reference voltage 860, which causes the output of the second comparator to go high (trace 858), and causes the power status signal P _OK (trace 854) to be asserted. At t=5μs, the increase in the step size of the voltage divider input voltage of the first comparator (trace 862) and the increase in the step size of the voltage divider input voltage of the second comparator (trace 864) are the result of the lag being applied to the first and second instances of the power monitoring circuit 800.

The embodiments of this invention are summarized here. Other embodiments can also be understood from the entire specification and scope of the claims herein.

Example 1: A circuit includes: a plurality of comparators disposed on an integrated circuit, the plurality of comparators having inputs coupled to a monitored power line; and a voting circuit whose inputs are coupled to the outputs of the plurality of comparators, wherein the output of the voting circuit is configured to provide a signal indicating an undervoltage condition of the power supply coupled to the monitored power line.

Example 2: A circuit similar to Example 1, wherein a first comparator among a plurality of comparators has a first comparison threshold; and a second comparator among a plurality of comparators has a second comparison threshold.

Example 3: A circuit similar to Example 1 or 2, where the first comparison threshold is different from the second comparison threshold.

Example 4: A circuit similar to one of Examples 1 to 3, where the inputs of multiple comparators are connected to a point on a monitored power supply line.

Example 5: The circuit of Example 3 further includes a first circuit connected to a monitored power line via a first conductor extending from a point on the monitored power line, wherein: the input of the first comparator of a plurality of comparators is connected to the point on the monitored power line; and the input of the second comparator of a plurality of comparators is connected to the first conductor via a circuit path excluding the point on the monitored power line.

Example 6: The circuit of Example 5 further includes a second circuit connected to the monitored power line via a second conductor extending from the star point of the monitored power line, wherein: the input of the second comparator among a plurality of comparators is connected to the second conductor via a circuit path excluding the star point and excluding the first conductor.

Example 7: A circuit as described in any of Examples 1 to 6, where the voting circuit includes element c.

Example 8: A circuit as described in any of Examples 1 to 7, wherein the voting circuit comprises: a first c-element having inputs coupled to a first set of comparators among a plurality of comparators; a second c-element having inputs coupled to a second set of comparators among a plurality of comparators; and a third c-element having a first input coupled to the output of the first c-element and a second input coupled to the output of the second c-element.

Example 9: A circuit similar to one of Examples 1 to 8, where the voting circuit includes a majority gate.

Example 10: A circuit as described in Examples 1 through 9, wherein at least one of the plurality of comparators includes a hysteresis circuit.

Example 11: A method of operating an integrated circuit includes: comparing a first voltage at a first point on a power bus with a first reference voltage; comparing a second voltage at a second point on the power supply with a second reference voltage; transitioning to an undervoltage state when the first voltage is less than the first reference voltage and the second voltage is less than the second reference voltage; and maintaining the undervoltage state after transitioning to the undervoltage state while the first voltage remains less than the first reference voltage or the second voltage remains less than the second reference voltage. The system exits the undervoltage state when the first voltage exceeds the first reference voltage and the second voltage exceeds the second reference voltage; after exiting the undervoltage state, it remains in the undervoltage state as long as the first voltage remains higher than the first reference voltage or the second voltage remains higher than the second reference voltage; and it indicates the undervoltage state upon transitioning to the undervoltage state.

Example 12: The method is the same as in Example 11, but further includes shutting down the first circuit connected to the power supply when an undervoltage condition is indicated.

Example 13: Similar to Example 11 or 12, where the first point and the second point of the power bus are the same point.

Example 14: A method as in Example 11 or 13, wherein a power bus is coupled to a first circuit; and a second point of the power bus is electrically closer to the first circuit than a first point of the power bus.

Example 15: A method similar to one of Examples 11 to 14, wherein the first and second voltages are fluctuating; and the first and second reference voltages are programmably fixed.

Example 16: An integrated circuit includes: a memory circuit; a conductive power bus coupled between a power node and a power input of the memory circuit; and an undervoltage detector coupled to the conductive power bus, the undervoltage detector including: a first comparator having a signal input coupled to the conductive power bus; a second comparator having a signal input coupled to the conductive power bus; and a voting circuit having an input coupled to the outputs of the first and second comparators, and an output coupled to a shutdown input of the memory circuit.

Example 17: An integrated circuit as in Example 16, where the voting circuit includes element c.

Example 18: An integrated circuit as in Example 16 or 17, which further includes bonding pads connected to power nodes.

Example 19: An integrated circuit as described in any of Examples 16 to 18, further comprising a reference voltage generator having a first output coupled to a reference voltage input of a first comparator and a second output coupled to a reference voltage input of a second comparator, wherein the reference voltage generator is configured to provide a first reference voltage at the first output and a second reference voltage different from the first reference voltage at the second output.

Example 20: An integrated circuit as described in Examples 16 to 19, wherein the signal input of the first comparator is connected to a first point on a power supply bus; and the signal input of the second comparator is connected to a second point on a power supply bus.

Example 21: An integrated circuit as described in Examples 16 to 20, wherein a first point on the power bus is electrically closer to the power input of the memory circuit than a second point on the power bus.

Example 22: An integrated circuit as described in Examples 16 to 21, wherein the memory circuitry includes a non-volatile memory array based on silicon-oxide-nitride-oxide-silicon (SONOS).

Although the present invention has been described with reference to illustrative embodiments, this description is not intended to be limiting. Various modifications and combinations of the exemplary embodiments, as well as other embodiments of the present invention, will become apparent to those skilled in the art upon reference to this description. Therefore, the appended claims are intended to cover any such modifications or embodiments.

200: Undervoltage Detector System; 202: Undervoltage Detector; 204: Comparator; 206: Comparator; 208: Reference Voltage Generator; 210: Voting Circuit; 212: Circuit; 214: Shutdown Circuit; 216: Power Supply; 218: Conductive Power Bus

Claims (22)

A circuit comprising: a plurality of comparators disposed on an integrated circuit, the plurality of comparators having inputs coupled to a monitored power line; and a voting circuit having inputs coupled to outputs of the plurality of comparators, wherein the outputs of the voting circuit are configured to provide a signal indicating an undervoltage condition of a power supply coupled to the monitored power line, and the voting circuit comprising: at least one C-element, wherein a single C-element has the outputs coupled to at least two of the plurality of comparators, or a majority decision gate having the outputs coupled to at least three of the plurality of comparators. The circuit of claim 1, wherein: a first comparator of the plurality of comparators has a first comparison threshold; and a second comparator of the plurality of comparators has a second comparison threshold. The circuit in claim 2, wherein the first comparison threshold is different from the second comparison threshold. The circuit of claim 1, wherein the input of the plurality of comparators is connected to a point on the monitored power line. The circuit of claim 1 further includes a first circuit connected to the monitored power line via a first conductor extending from a point on the monitored power line, wherein: the input of the first comparator of the plurality of comparators is connected to that point on the monitored power line. The circuit of claim 5 further includes a second circuit connected to the monitored power line via a second conductor extending from the star point of the monitored power line, wherein: the input of the second comparator of the plurality of comparators is connected to the second conductor via a circuit path excluding the star point and excluding the first conductor. The circuit of claim 1, wherein the voting circuit comprises: a first c-element having inputs coupled to a first set of comparators among the plurality of comparators; a second c-element having inputs coupled to a second set of comparators among the plurality of comparators; and a third c-element having a first input coupled to the output of the first c-element and a second input coupled to the output of the second c-element. The circuit of claim 1, wherein at least one of the plurality of comparators includes a lag circuit. The circuit of claim 5, wherein the input of the second comparator of the plurality of comparators is connected to the first conductor via a circuit path that does not include the star point. An integrated circuit includes: a memory circuit; a conductive power bus coupled between a power node and a power input of the memory circuit; and an undervoltage detector coupled to the conductive power bus, the undervoltage detector including: a plurality of comparators disposed on the integrated circuit, the plurality of comparators having inputs coupled to the conductive power bus; and A voting circuit, the input of which is coupled to the outputs of the plurality of comparators, wherein the output of the voting circuit is configured to provide a signal indicating an undervoltage condition of a power supply coupled to the power bus, the output of the voting circuit being coupled to a shutdown input of the memory circuit, and the voting circuit comprising: at least one C-element, wherein a single C-element has the outputs of at least two of the plurality of comparators coupled to the plurality of comparators, or a majority decision, having the outputs of at least three of the plurality of comparators coupled to the plurality of comparators. The integrated circuit of claim 10 further includes a bonding pad connected to the power node. The integrated circuit of claim 10, wherein: the plurality of comparators includes a first comparator having a signal input coupled to the conductive power bus, and a second comparator having a signal input coupled to the conductive power bus; and the integrated circuit further includes a reference voltage generator having a first output coupled to the reference voltage input of the first comparator and a second output coupled to the reference voltage input of the second comparator, wherein the reference voltage generator is configured to provide a first reference voltage at the first output and a second reference voltage different from the first reference voltage at the second output. The integrated circuit of claim 10, wherein: the plurality of comparators includes a first comparator having a signal input coupled to the power supply bus, and a second comparator having a signal input coupled to the power supply bus; the signal input of the first comparator is connected to a first point on the power supply bus; and the signal input of the second comparator is connected to a second point on the power supply bus. As in claim 13, in an integrated circuit, the first point on the power bus is electrically closer to the power input of the memory circuit than the second point on the power bus. The integrated circuit of claim 10, wherein the memory circuit includes a nonvolatile memory array based on silicon-oxide-nitride-oxide-silicon (SONOS). The integrated circuit of claim 10, wherein: the power bus includes a first conductor extending from a point on the power bus to the power input of the memory circuit; and the input of a first comparator of the plurality of comparators is connected to the point on the power bus. The integrated circuit of claim 16, wherein the input of the second comparator of the plurality of comparators is connected to the first conductor via a circuit path that does not include the star point. The integrated circuit of claim 16 further includes a second circuit connected to the conductive bus via a second conductor extending from the star point of the conductive bus, wherein the input of the second comparator of the plurality of comparators is connected to the second conductor via a circuit path that does not include the star point and does not include the first conductor. The integrated circuit of claim 10, wherein at least one of the plurality of comparators includes a lag circuit. A method of operating a circuit, the circuit including a plurality of comparators disposed on an integrated circuit, the plurality of comparators having inputs coupled to a monitored power line; and a voting circuit having inputs coupled to outputs of the plurality of comparators, wherein the output of the voting circuit is configured to provide a signal indicating an undervoltage condition of a power supply coupled to the monitored power line, the method comprising: The plurality of comparators are used to compare the voltage of the monitored power line with a plurality of corresponding threshold values, wherein a first comparator of the plurality of comparators has a first comparison threshold value, a second comparator of the plurality of comparators has a second comparison threshold value, and comparing the voltage of the monitored power line with the plurality of corresponding threshold values includes: comparing a first voltage at a first point on the monitored power line with the first comparison threshold value using the first comparator; and comparing a second voltage at a second point on the monitored power line with the second comparison threshold value using the second comparator; The voting circuit uses the outputs of the plurality of comparators to provide the signal indicating an undervoltage condition of the power supply by: transitioning to an undervoltage state in response to a first voltage being less than a first comparison threshold and a second voltage being less than a second comparison threshold; after transitioning to the undervoltage state, maintaining the undervoltage state in response to either the first voltage remaining less than the first comparison threshold or the second voltage remaining less than the second comparison threshold; exiting the undervoltage state in response to the first voltage exceeding the first comparison threshold and the second voltage exceeding the second comparison threshold; After exiting the undervoltage state, the system remains exiting the undervoltage state in response to either the first voltage remaining above the first comparison threshold or the second voltage remaining above the second comparison threshold; and upon transitioning to the undervoltage state, the system asserts the signal indicating the undervoltage condition. The method of claim 20, wherein the first comparison threshold is different from the second comparison threshold. The method of claim 20, wherein the input of the plurality of comparators is connected to a point on the monitored power line.