TWI905641B - Semiconductor device and method of forming the same - Google Patents

Abstract

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a channel layer, a barrier layer, a gate electrode, a gate field plate, a first buffer layer, and a second buffer layer. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The gate electrode is disposed on the barrier layer. The gate field plate is disposed on the gate electrode. The first buffer layer is disposed on the gate field plate. The second buffer layer is disposed on the first buffer layer. Wherein, the first buffer layer includes a metal, and the second buffer layer includes an oxynitride of the metal.

Description

Semiconductor Device and Its Forming Method

This invention relates to a semiconductor device and a method of forming the same, and more particularly to a semiconductor device comprising a first buffer layer and a second buffer layer and a method of forming the same.

Due to its wide bandgap and strong polarization effect, gallium nitride (GaN) materials are widely used. For example, GaN semiconductors are currently widely used in power devices, such as high electron mobility transistors (HEMTs) with heterojunction structures.

However, during the formation of high electron mobility transistors, the etching process used to create openings can damage the components beneath the openings, leading to problems such as excessive surface roughness and color changes. Therefore, although existing semiconductor devices and their formation methods have gradually met their intended applications, they are not yet completely satisfactory in every aspect. Consequently, some problems regarding semiconductor devices and their formation methods still need to be overcome.

This disclosure prevents damage to the first buffer layer by applying a second buffer layer onto the first buffer layer. For example, a second buffer layer comprising an oxide of the metal can be formed by subjecting the metal in the first buffer layer to nitrogen oxidation. Since the second buffer layer is an oxide of the first buffer layer, it is protected from damage during the etching process. Therefore, the surface of the second buffer layer is flat, and the problem of surface discoloration of the first buffer layer is avoided.

In some embodiments, a semiconductor device is provided. The semiconductor device includes a substrate, a channel layer, a barrier layer, a gate electrode, a gate field plate, a first buffer layer, and a second buffer layer. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The gate electrode is disposed on the barrier layer. The gate field plate is disposed on the gate electrode. The first buffer layer is disposed on the gate field plate. The second buffer layer is disposed on the first buffer layer. The first buffer layer comprises a metal, and the second buffer layer comprises a nitride of the metal.

In some embodiments, a method for forming a semiconductor device is provided. The method includes providing a substrate; forming a channel layer on the substrate; forming a barrier layer on the channel layer; forming a gate electrode on the barrier layer; forming a gate field plate on the gate electrode; forming a first buffer layer on the gate field plate; and forming a second buffer layer on the first buffer layer. The first buffer layer comprises a metal, and the second buffer layer comprises a nitride of the metal.

The semiconductor device and its forming method disclosed herein can be applied to various types of electronic devices and their forming methods. To make the components and advantages of this disclosure more apparent, various embodiments are given below and explained in detail with reference to the accompanying drawings.

The semiconductor devices of various embodiments in this disclosure are described in detail below. It should be understood that the following description provides many different embodiments for implementing different forms of some embodiments of this disclosure. The specific elements and arrangements described below are merely for the simple and clear description of some embodiments of this disclosure. Of course, these are only illustrative and not intended to limit this disclosure. Furthermore, similar and/or corresponding element symbols may be used in different embodiments to identify similar and/or corresponding elements for the clear description of this disclosure. However, the use of these similar and/or corresponding element symbols is only for the simple and clear description of some embodiments of this disclosure and does not imply any relationship between the different embodiments and/or structures discussed.

It should be understood that relative terms, such as "lower," "bottom," "higher," or "top," may be used in the various embodiments to describe the relative relationship of one element in the diagram to another. It is understood that if the device depicted in the diagram is flipped upside down, the element described as being on the "lower" side will become the element on the "higher" side. The embodiments of this disclosure should be understood in conjunction with the diagrams, which are also considered part of the disclosure description.

Furthermore, when it is stated that a first material layer is located on or over a second material layer, this may include situations where the first material layer and the second material layer are in direct contact, or situations where the first material layer and the second material layer are not in direct contact, that is, situations where there may be one or more other material layers between the first material layer and the second material layer. However, if the first material layer is located directly on the second material layer, it indicates that the first material layer and the second material layer are in direct contact.

Furthermore, it should be understood that the use of ordinal numbers such as "first," "second," etc., in the specification and the scope of the patent application to modify components is not intended to imply any prior ordinal number for that component (or those components), nor does it represent the order of one component with another, or the order of manufacture. The use of these ordinal numbers is solely to clearly distinguish one component with a given name from another component with the same name. The scope of the patent application and the specification may not use the same terminology; for example, the first component in the specification may be the second component in the scope of the patent application.

In some embodiments disclosed herein, terms such as "connect," "interconnect," and "bond," unless specifically defined, may refer to two structures being in direct contact, or to two structures not being in direct contact, with another structure disposed between them. Furthermore, these terms may also include situations where both structures are movable or both are fixed. Additionally, the terms "electrical connection" or "electrical coupling" include any direct or indirect electrical connection means.

In this text, the terms "approximately," "about," and "substantially" generally indicate within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range. The given quantity is an approximate quantity; that is, without specific mention of "approximately," "about," or "substantially," the meaning of "approximately," "about," or "substantially" can still be implied. The phrases "between the first and second values" or "first value to second value" indicate that the range includes the first value, the second value, and other values in between. Furthermore, any two values or directions used for comparison may have a certain degree of error. If the first value equals the second value, it implies that there may be an error between the first value and the second value within approximately 10%, or 5%, or 3%, or 2%, or 1%, or 0.5%.

Throughout this disclosure and in the scope of the patent application, certain terms are used to refer to specific components. It will be understood by those skilled in the art that electronic device manufacturers may use different names to refer to the same components. This document is not intended to distinguish between components that have the same function but different names. In the following description and scope of the patent application, words such as "comprise," "containing," and "having" are open-ended terms and should therefore be interpreted as "containing but not limited to...". Therefore, when the terms "comprise," "containing," and/or "having" are used in the description of this disclosure, they specify the presence of corresponding parts, areas, steps, operations, and/or elements, but do not exclude the presence of one or more corresponding parts, areas, steps, operations, and/or elements.

It should be understood that, without departing from the spirit of this disclosure, the components in the following embodiments can be replaced, recombined, or combined to complete other embodiments. Components in each embodiment can be arbitrarily combined and used as long as they do not violate the spirit of the invention or conflict with it.

Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which they pertain. It is understood that these terms, for example, as defined in commonly used dictionaries, should be interpreted in a way consistent with the relevant art and the context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in embodiments of this disclosure.

In this disclosure, the directions are not limited to the three axes of a Cartesian coordinate system, such as the X, Y, and Z axes, and can be interpreted in a broader sense. For example, the X, Y, and Z axes may be perpendicular to each other, or may represent different directions that are not perpendicular to each other, but are not limited thereto. For ease of explanation, in the following text, the X-axis direction is the first direction D1 (length direction), and the Z-axis direction is the second direction D2 (thickness/height direction). In some embodiments, the normal direction of the substrate is the second direction D2.

Figure 1 is a schematic cross-sectional view of different stages of a method for forming a semiconductor device 1 according to an embodiment of the present disclosure. As shown in Figure 1, in some embodiments, a substrate 100 may be provided. In some embodiments, the substrate 100 may include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like. The SOI substrate includes a semiconductor layer formed on an insulator. For example, the insulating layer may include silicon oxide, silicon nitride, polysilicon, or a combination thereof, and the semiconductor substrate may include silicon, aluminum nitride (AlN), or the like. Substrate 100 may be an undoped or doped substrate, such as a substrate doped with p-type or n-type dopants. In some embodiments, substrate 100 may include a multi-layered substrate or a gradient substrate. In some embodiments, substrate 100 may include a semiconductor substrate or a ceramic substrate, such as a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, an aluminum nitride substrate, or a sapphire substrate. In some embodiments, substrate 100 may be a silicon substrate.

As shown in Figure 1, in some embodiments, a buffer layer 200 may be formed on the substrate 100 to improve the compatibility between the substrate 100 and other components disposed on the substrate 100, such as reducing differences in thermal expansion coefficients and/or reducing differences in lattice constants. In some embodiments, the buffer layer 200 may include a III-V compound semiconductor material, such as a group III nitride. For example, the buffer layer 200 may include gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), similar materials, or combinations thereof, but this disclosure is not limited thereto. In some embodiments, the buffer layer 200 may be formed by a deposition process. For example, the deposition process may be chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), similar processes, or combinations thereof, but this disclosure is not limited to these. In some embodiments, a nucleation layer may be further disposed between the substrate 100 and the buffer layer 200 to reduce the lattice difference between the substrate 100 and other layers disposed on the substrate 100, thereby improving epitaxial quality and reliability. In some embodiments, the nucleation layer may include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), similar substances, or combinations thereof, but this disclosure is not limited to these. In some embodiments, the nucleation layer can be formed by a deposition process. In other embodiments, the buffer layer 200 can be omitted.

As shown in Figure 1, in some embodiments, a channel layer 300 may be formed on the substrate 100. Specifically, the channel layer 300 may be formed on the buffer layer 200. In some embodiments, the channel layer 300 may include a III-V compound semiconductor material, such as a group III nitride, but this disclosure is not limited thereto. For example, the channel layer 300 may include gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum gallium nitride (InAlGaN), similar materials, or combinations thereof, but this disclosure is not limited thereto. In some embodiments, the channel layer 300 may be gallium nitride. In some embodiments, the channel layer 300 may be formed by a deposition process.

As shown in Figure 1, in some embodiments, a barrier layer 400 may be formed on the channel layer 300. In some embodiments, the barrier layer 400 may include a III-V compound semiconductor material, such as a group III nitride, but this disclosure is not limited thereto. For example, the barrier layer may include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium aluminum gallium nitride (InAlGaN), similar materials, or combinations thereof, but this disclosure is not limited thereto. In some embodiments, the barrier layer 400 may be aluminum gallium nitride. In some embodiments, the barrier layer 400 may be formed by a deposition process. Because a heterogeneous interface exists between the channel layer 300 and the barrier layer 400, and because there is a difference in lattice constant between the channel layer 300 and the barrier layer 400, a two-dimensional electron gas (2DEG) can be formed near the top surface of the channel layer 300, serving as a current path. As shown in Figure 1, in some embodiments, a capping layer 410 can be formed on the barrier layer 400. In some embodiments, the capping layer 410 may include a nitride, such as silicon nitride.

Figure 2 is a cross-sectional schematic diagram of different stages of a method for forming a semiconductor device 1 according to an embodiment of the present disclosure. In some embodiments, a source electrode 520 and a drain electrode 540 may be formed on a channel layer 300. In some embodiments, the source electrode 520 and the drain electrode 540 may penetrate a barrier layer 400 and contact the channel layer 300. In some embodiments, the source electrode 520 and the drain electrode 540 may include a first conductive material, for example, the first conductive material may include a metal, a metal nitride, a semiconductor material, similar materials thereto, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the metal may include gold (Au), titanium (Ti), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), titanium nitride (TiN), similar substances, or combinations thereof, but this disclosure is not limited thereto. The semiconductor material may include polycrystalline silicon or polycrystalline germanium. The first conductive material may be formed by chemical vapor deposition, sputtering, resistance heating evaporation, electron beam evaporation, similar processes, or combinations thereof, but this disclosure is not limited thereto. In some embodiments, rapid thermal annealing (RTA) is performed on the surfaces of the source electrode 520 and the drain electrode 540 to form a source buffer layer 560 on the source electrode 520 and a drain buffer layer 580 on the drain electrode 540. Since the source buffer layer 560 and the drain buffer layer 580 are formed on the source electrode 520 and the drain electrode 540, respectively, the source electrode 520 and the drain electrode 540 are protected from damage by subsequent etching processes.

Figure 3 is a schematic cross-sectional view of different stages of a method for forming a semiconductor device 1 according to an embodiment of the present disclosure. In some embodiments, a first interlayer dielectric layer 600 may be formed on the capping layer 410, the source buffer layer 560, and the drain buffer layer 580. In some embodiments, the first interlayer dielectric layer 600 may include oxides of silicon oxide, nitrides of silicon nitride, oxides of silicon oxynitride, similar materials, or combinations thereof, but the present disclosure is not limited thereto. For example, the first interlayer dielectric layer 600 may be silicon oxide. In some embodiments, the first interlayer dielectric layer 600 may be formed in a blanket manner, and then patterned to expose a portion of the top surface of the capping layer 410. In some embodiments, the location of subsequently formed gate electrodes may be defined by the first interlayer dielectric layer 600. In some embodiments, the first interlayer dielectric layer 600 may be formed by a deposition process.

As shown in Figure 3, in some embodiments, a gate electrode 700 may be formed on the barrier layer 400. Specifically, a gate electrode 700 may be formed on the capping layer 410. In some embodiments, the material and forming method of the gate electrode 700 may be the same as or different from the material and forming method of the source electrode 520 and the drain electrode 540. In some embodiments, the source electrode 520 and the drain electrode 540 are respectively located on both sides of the gate electrode 700.

Figure 4 is a cross-sectional schematic diagram of different stages of a method for forming a semiconductor device 1 according to an embodiment of the present disclosure. In some embodiments, a conductive stack 800 may be formed on the gate electrode 700 to electrically connect the conductive stack 800 to the gate electrode 700. In some embodiments, the conductive stack 800 may include a gate field plate 840 to adjust the electric field distribution adjacent to the gate electrode 700. In some embodiments, a gate field plate 840 may be formed on the gate electrode 700 to electrically connect the gate field plate 840 to the gate electrode 700. In some embodiments, the gate field plate 840 may extend from the gate electrode 700 toward the source electrode 520 and the drain electrode 540, respectively. In some embodiments, the gate field plate 840 may be narrower at the bottom and wider at the top, for example, a T-shape. In some embodiments, the material and forming method of the gate field plate 840 may be the same as or different from the material and forming method of the gate electrode 700. For example, the gate field plate 840 may include gold (Au).

In some embodiments, the conductive stack 800 may further include a bottom buffer layer 820 disposed between the gate electrode 700 and the gate field plate 840. In some embodiments, the bottom buffer layer 820 may be conformally formed on the first interlayer dielectric layer 600 and the gate electrode 700. In some embodiments, the bottom buffer layer 820 may include a second conductive material. For example, the second conductive material may include a metal. The second conductive material may be formed by chemical vapor deposition, sputtering, resistance heating evaporation, electron beam evaporation, similar processes, or combinations thereof, but this disclosure is not limited thereto. In some embodiments, the metal may include titanium (Ti), zirconium (Zr), yttrium (Hf), aluminum (Al), vanadium (V), niobium (Nb), tungsten (W), tantalum (Ta), analogues thereof, or combinations thereof. For example, the underlayer 820 may include titanium (Ti).

In some embodiments, the conductive stack may further include a first buffer layer 860 disposed on the gate field plate 840, and the gate field plate 840 may be located between the bottom buffer layer 820 and the first buffer layer 860. In some embodiments, the material and forming method of the first buffer layer 860 may be the same as or different from the material and forming method of the bottom buffer layer 820. As shown in Figure 4, in some embodiments, the first buffer layer 860 may have an initial thickness T0 in the second direction D2. In some embodiments, the initial thickness T0 may be 1 kÅ to 50 kÅ, 0.1 μm to 5 μm, or 1 μm to 50 μm, but this disclosure is not limited to these. For example, the initial thickness T0 can be 1 kÅ, 5 kÅ, 10 kÅ, 20 kÅ, 30 kÅ, 40 kÅ, 50 kÅ, 1 μm, 5 μm, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm or any value or range of values between the foregoing values, but this disclosure is not limited thereto.

Figure 5 is a cross-sectional schematic diagram of different stages of a method for forming a semiconductor device 1 according to an embodiment of the present disclosure. In some embodiments, a surface treatment process P1 is performed on a first buffer layer 860 to react the metal (denoted as M) in the first buffer layer 860 into a metal oxynitride ( _denoted as _MxOyNz ) to _form a second buffer layer 880 on the first buffer layer 860. In other _words , while the first buffer layer 860 may include a metal (M), the second buffer layer 880 may include _a metal oxynitride ( _MxOyNz ).

In some embodiments, x is 1 to 100, y is 1 to 100, and z is 1 to 100. For example, x can be 1, y can be 1, and z can be 1. In some embodiments, the metal (M) may include titanium (Ti), zirconium (Zr), yttrium (Hf), aluminum (Al), vanadium (V), niobium (Nb), tungsten (W), tantalum (Ta), other metals easily oxidized by nitrogen, their analogues, or combinations thereof, but this disclosure is not limited thereto. In some embodiments, the metal oxynitride _{( MxOyNz} ) may be TiON, TiAlON, WON, TaON, their analogues, or combinations thereof, but this disclosure is not limited thereto. For example, the first buffer layer 860 may be titanium, _and the second buffer layer 880 may be titanium oxynitride.

In some embodiments, the surface treatment process P1 may be a plasma treatment process using a plasma treatment gas. In some embodiments, the plasma treatment gas may be a gas comprising oxygen atoms and nitrogen atoms, to subject the metal (M) in the first buffer layer 860 to nitrogen oxidation. In some embodiments, the plasma treatment gas may be _NaOb , where _a is 1 to 2 and b is 1 to 5. For example, the plasma treatment gas may be NO, _N₂O , _NO₃ , similar substances or combinations thereof, but this disclosure is not limited thereto. In some embodiments, the flow rate of the plasma treatment gas may be 1 sccm to 3000 sccm. For example, the flow rate of the plasma treatment gas can be 1 sccm, 100 sccm, 500 sccm, 1000 sccm, 1500 sccm, 2000 sccm, 2500 sccm, 3000 sccm, or any value or range of values between the foregoing, but this disclosure is not limited thereto. In some embodiments, the surface treatment process P1 can use a carrier gas such as an inert gas.

As shown in Figure 4, in some embodiments, after performing the surface treatment process P1, the first buffer layer 860 may have a first thickness T1 and the second buffer layer 880 may have a second thickness T2 in the second direction D2. In some embodiments, the first thickness T1 may be 500 Å to 2000 Å and the second thickness T2 may be 100 Å to 1000 Å, but this disclosure is not limited thereto. For example, the first thickness T1 may be 500 Å, 1000 Å, 1500 Å, 2000 Å or any value or range of values between the foregoing values, but this disclosure is not limited thereto. For example, the second thickness T2 can be 100 Å, 500 Å, 1000 Å, or any value or range of values between the aforementioned values, but this disclosure is not limited thereto. When the second thickness T2 is less than 100 Å (or less than 200 Å), the second buffer layer 880 may be insufficient to withstand the damage of the etching process. When the second thickness T2 is greater than 1000 Å, the time required to perform the surface treatment process P1 may be too long, thus increasing costs.

In some embodiments, the second thickness T2 can be 20% to 50% of the sum of the first thickness T1 and the second thickness T2 (T1+T2). For example, it can be 20%, 25%, 30%, 35%, 40%, 45%, 50%, or any value or combination of the aforementioned values, but this disclosure is not limited thereto. In some embodiments, the first thickness T1 can be 20% to 50% of the initial thickness T0. When the second thickness T2 accounts for less than 20% of the sum of the first thickness T1 and the second thickness T2, the second buffer layer 880 may be insufficient to withstand the damage of the etching process. When the second thickness T2 accounts for more than 50% of the sum of the first thickness T1 and the second thickness T2, the time for performing the surface treatment process P1 may be too long, thus increasing costs.

Figure 6 is a cross-sectional schematic diagram of different stages of a method for forming a semiconductor device 1 according to an embodiment of the present disclosure. In some embodiments, a second interlayer dielectric layer 900 may be formed on the first interlayer dielectric layer 600 and the conductive stack 800. Specifically, the second interlayer dielectric layer 900 may be formed on the top surface of the first interlayer dielectric layer 600, the bottom buffer layer 820, the gate field plate 840, the side surfaces of the first buffer layer 860 and the second buffer layer 880, and the top surface of the second buffer layer 880. In some embodiments, the material and formation method of the second interlayer dielectric layer 900 may be the same as or different from those of the first interlayer dielectric layer 600. For example, the second interlayer dielectric layer 900 may be silicon oxide. In some embodiments, the second interlayer dielectric layer 900 is in direct contact with the second buffer layer 880.

Figure 7 is a cross-sectional schematic diagram of different stages of a method for forming a semiconductor device 1 according to an embodiment of the present disclosure. In some embodiments, an etching process is performed to form openings 920, 940, and 960 in the second interlayer dielectric layer 900. In some embodiments, openings 920 and 960 penetrate the second interlayer dielectric layer 900 and the first interlayer dielectric layer 600, respectively, to expose the source buffer layer 560 and the drain buffer layer 580, respectively. Accordingly, the source buffer layer 560 and the drain buffer layer 580 can serve as etch stop layers. In some embodiments, opening 940 penetrates the second inter-dielectric layer 900 to expose the second buffer layer 880 in the conductive stack 800. Accordingly, the second buffer layer 880 can serve as an etch stop layer. As shown in Figure 7, the second buffer layer 880 can be substantially retained after the etching process is performed.

In some embodiments, the etching process may use etching gases such as carbon tetrafluoride ( _CF4 ), trifluoromethane ( _CHF3 ), or combinations thereof. Specifically, without the second buffer layer 880 on the first buffer layer 860, the etching gas used in the etching process will react directly with the first buffer layer 860, causing damage to it. Therefore, once the etching gas comes into direct contact with the first buffer layer 860, it will cause the surface of the first buffer layer 860 to develop titanium tetrafluoride ( _TiF4 ) that is difficult to remove, excessively rough, and discolored.

However, this disclosure avoids contact between the first buffer layer 860 and the etching gas by setting a second buffer layer 880 on top of the first buffer layer 860, thereby preventing the first buffer layer 860 from being damaged by the etching process. For example, metallic oxynitrides such as titanium oxynitride are resistant to etching gases, so that the etching gases do not substantially or only partially damage the metallic oxynitrides. Accordingly, the electrical properties, structural strength, surface flatness, and/or surface color of the first buffer layer 860 and the second buffer layer 880 can be improved, thereby correspondingly improving the reliability of the subsequently formed semiconductor device.

Figure 8 is a cross-sectional schematic diagram of different stages of a method for forming a semiconductor device 1 according to an embodiment of the present disclosure. In some embodiments, contacts 922, 942, and 962 may be formed in openings 920, 940, and 960 respectively to obtain the semiconductor device 1. In some embodiments, contacts 922, 942, and 962 may penetrate a second interlayer dielectric layer 900. In some embodiments, contacts 922, 942, and 962 may include a first conductive material. In some embodiments, contacts 922, 942, and 962 may be electrically connected to a source electrode 520, a gate electrode 700, and a drain electrode 540 respectively. In some embodiments, the contact 942 is in direct contact with the second buffer layer 880. In some embodiments, the interlayer dielectric layer 900 may be in direct contact with the second buffer layer 880 in the area outside the openings 920, 940, and 960 shown in Figure 7. Accordingly, the adhesion between the interlayer dielectric layer 900 and the contact 942 can be increased.

Figure 9 is a schematic cross-sectional view of a semiconductor device 2 according to an embodiment of the present disclosure. In some embodiments, as shown in Figure 9, although the second buffer layer 880 can be removed after the etching process, the first buffer layer 860 can be substantially retained. In some embodiments, the contact 942 is in direct contact with the first buffer layer 860. In some embodiments, even if the second buffer layer 880 corresponding to the opening (not shown) of the contact 942 has been removed by the etching process, the second interlayer dielectric layer 900 can be in direct contact with the second buffer layer 880 in the area outside the openings 920, 940, and 960 shown in Figure 7. Accordingly, it is possible to reduce resistivity and/or improve the flatness of the contact surface to improve roughness.

In some embodiments, since the semiconductor devices 1 and 2 disclosed herein may include a second buffer layer 880, the resistivity of the material can be reduced, thereby improving the electrical properties with respect to resistance by up to 43%.

In other embodiments, the first and second buffer layers disclosed herein can be applied to other semiconductor devices, such as any semiconductor device having a gate field plate, and are not limited to HEMTs. In other embodiments, the surface treatment process disclosed herein can be applied to other semiconductor device forming methods, such as any semiconductor device forming an opening in a gate field plate, and is not limited to HEMT forming methods.

Accordingly, this disclosure involves performing a surface treatment process, such as an oxynitride process, on the first buffer layer to form a second buffer layer comprising a metal oxynitride. This prevents the first buffer layer from being damaged by the etching process (e.g., causing excessive roughness of the surface of the first buffer layer and/or causing discoloration of the surface of the first buffer layer). Accordingly, the reliability of the semiconductor device can be improved.

The scope of protection of this disclosure is not limited to the processes, machines, manufacturing, material composition, apparatus, methods, and steps described in the specific embodiments of this specification. Any processes, machines, manufacturing, material composition, apparatus, methods, and steps that are currently or will be developed can be understood from the content of this disclosure, and can be used according to this disclosure as long as substantially the same function can be implemented or substantially the same result can be obtained in the embodiments described herein. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufacturing, material composition, apparatus, methods, and steps. No embodiment or claim of this disclosure needs to achieve all the purposes, advantages, and/or features described in this disclosure.

The above outlines several embodiments to help those skilled in the art to better understand the viewpoints of these embodiments. Those skilled in the art to which this disclosure pertains should understand that they can design or modify other processes and structures based on these embodiments to achieve the same purpose and/or advantages as the embodiments herein. Those skilled in the art to which this disclosure pertains should also understand that such equivalent processes and structures do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of this disclosure.

1,2: Semiconductor Device 100: Substrate 200: Buffer Layer 300: Channel Layer 400: Barrier Layer 410: Cap Layer 520: Source Electrode 540: Drain Electrode 560: Source Buffer Layer 580: Drain Buffer Layer 600: First Intercalation Dielectric Layer 700: Gate Electrode 800: Conductive Stack 820: Bottom Buffer Layer 840: Gate Field Plate 860: First Buffer Layer 880: Second Buffer Layer 900: Second interlayer dielectric layer 920, 940, 960: Openings 922, 942, 962: Contacts D1: First direction D2: Second direction T0: Initial thickness T1: First thickness T2: Second thickness P1: Surface treatment process

This disclosure will be more fully understood from the following detailed description when read in conjunction with the drawings. It is worth noting that, as is standard industry practice, the components are not drawn to scale. In fact, for clarity, the dimensions of the components may be arbitrarily enlarged or reduced. Figures 1 through 8 are schematic cross-sectional views of different stages of a method for forming a semiconductor device according to an embodiment of this disclosure. Figure 9 is a schematic cross-sectional view of a semiconductor device according to an embodiment of this disclosure.

1: Semiconductor Devices

100:Substrate

200: Buffer Layer

300: Channel Layer

400: Barrier Layer

410: Cover layer

520: Source Electrode

540: Drain Electrode

560: Source Buffer Layer

580: Extreme buffer layer

600: First interlayer dielectric layer

700: Gate Electrode

800: Conductive Stack

820: Bottom Buffer Layer

840: Gate Extreme Field Board

860: First Buffer Layer

880: Second Buffer Layer

900: Second interlayer dielectric layer

922,942,962: Contact objects

D1: First Direction

D2: Second Direction

Claims (10)

A semiconductor device includes: a substrate; a channel layer disposed on the substrate; a barrier layer disposed on the channel layer; a gate electrode disposed on the barrier layer; a gate field plate disposed on the gate electrode; a first buffer layer disposed on the gate field plate; and a second buffer layer disposed on the first buffer layer, wherein the first buffer layer is a metal, and the second buffer layer is a nitride of the metal. The semiconductor device as described in claim 1, wherein the metal includes titanium (Ti), zirconium (Zr), yttrium (Hf), aluminum (Al), vanadium (V), niobium (Nb), tungsten (W), tantalum (Ta), or combinations thereof. The semiconductor device as claimed in claim 1, wherein: the metal of the first buffer layer is M; and the oxynitride of the metal of the second buffer layer is M _x O _y N _z , wherein x is 1~100, y is 1~100, and z is 1~100. The semiconductor device as claimed in claim 1, wherein the first buffer layer has a first thickness, the second buffer layer has a second thickness, and the second thickness is 20% to 50% of the sum of the first thickness and the second thickness. The semiconductor device as described in claim 1 further includes: a dielectric layer disposed on the second buffer layer; and a contact extending through the dielectric layer and electrically connected to the gate electrode, wherein the contact is in contact with the second buffer layer or the first buffer layer. The semiconductor device as described in claim 5, wherein the dielectric layer is in contact with the second buffer layer. The semiconductor device as described in claim 1 further includes: a bottom buffer layer disposed between the gate electrode and the gate field plate. The semiconductor device as described in claim 1 further includes: a source electrode and a drain electrode disposed in the channel layer and located on both sides of the gate electrode; and a source buffer layer and a drain buffer layer disposed on the source electrode and the drain electrode, respectively. A method for forming a semiconductor device includes: providing a substrate; forming a channel layer on the substrate; forming a barrier layer on the channel layer; forming a gate electrode on the barrier layer; forming a gate field plate on the gate electrode; forming a first buffer layer on the gate field plate; and forming a second buffer layer on the first buffer layer, wherein the first buffer layer is a metal, and the second buffer layer is a nitride of the metal. The method of forming as described in claim 9, wherein forming the second buffer layer on the first buffer layer further comprises: performing a surface treatment process on the first buffer layer to react the metal in the first buffer layer into a nitride of the metal to form the second buffer layer.