TWI904877B - Chip resistor and method for manufacturing the same - Google Patents

Abstract

A chip resistor and a method for manufacturing the same are provided. The chip resistor includes a substrate, a resistance layer on the substrate, two electrodes, a barrier layer and a protective layer. The resistance layer has a first surface and a second surface which are opposite to each other, while the substrate is located at the first surface of the resistance layer. Two electrodes are disposed on two opposite ends of the second surface of the resistance layer and spaced from each other. The barrier layer is disposed between the electrodes and covers the second surface of the resistance layer. The protective layer is disposed on the barrier layer and covers the barrier layer and the top surface of each electrode. The barrier layer is located between the protective layer and the second surface of the resistance layer.

Description

Chip Resistors and Their Manufacturing Methods

This disclosure relates to a wafer resistor, and more particularly to an alloy wafer resistor and a method for manufacturing the same.

Existing chip resistors primarily consist of a resistor sheet (e.g., an alloy resistor sheet) bonded to a substrate (e.g., an FR4 glass fiber substrate), with a pair of electrodes formed at both ends of the resistor sheet via electroplating. Furthermore, a resin protective layer is included on the outer surface of the resistor sheet to isolate it from the external environment. Generally, alloy chip resistors are commonly used in low-voltage, high-power electronic products. When these electronic products are operating, the temperature rises due to operation, making it difficult for moisture to adhere to the surface of the chip resistor. However, once the electronic product stops operating, the temperature of the chip resistor decreases accordingly. The surface of the resin protective layer is prone to condensation due to temperature differences, which increases the risk of moisture penetrating from the resin protective layer into the resistor, thereby oxidizing the resistor and affecting the stability of the resistance value.

Therefore, this disclosure provides a chip resistor that helps improve the chip resistor's resistance to moisture and humidity.

This disclosure also provides a method for manufacturing the aforementioned chip resistor.

This disclosure provides at least one embodiment of a chip resistor, which includes a substrate, a resistive layer disposed on the substrate, two first electrodes, a barrier layer, and a protective layer. The resistive layer has a first surface and a second surface opposite to the first surface, and the substrate is located on the first surface of the resistive layer. The two first electrodes are disposed at opposite ends of the second surface of the resistive layer. The barrier layer is disposed between the first electrodes and covers the second surface of the resistive layer. The protective layer is disposed on the barrier layer and covers the top surface of each first electrode and the barrier layer. The barrier layer is located between the protective layer and the second surface of the resistive layer.

In at least one embodiment of this disclosure, the resistance temperature coefficient of the barrier layer is less than that of the resistance temperature coefficient of the resistive layer.

In at least one embodiment of this disclosure, the barrier layer extends between the side surface of each first electrode and the protective layer.

In at least one embodiment of this disclosure, the chip resistor further includes two second electrodes and two solder layers. The second electrodes are respectively disposed on and electrically connected to the first electrode. The second electrodes cover areas of the first electrode exposed by a protective layer, and a portion of the protective layer is located between the second electrodes and the first electrode. Solder layers are respectively disposed on the second electrodes, and the second electrodes are located between the first electrode and these solder layers.

In at least one embodiment of this disclosure, the thickness of the barrier layer is less than 0.003 times the thickness of the resistive layer.

In at least one embodiment of this disclosure, the thickness of the barrier layer ranges from 0.1 µm to 3 µm.

In at least one embodiment of this disclosure, the material of the barrier layer is selected from the group consisting of copper, nickel, chromium, aluminum, titanium, tungsten, tantalum and combinations thereof.

In at least one embodiment of this disclosure, the chip resistor further includes a resistance-reducing region. This resistance-reducing region is located on the second surface of the resistive layer, and a barrier layer covers the resistance-reducing region.

This disclosure also provides a method for manufacturing a chip resistor, comprising: providing a resistor layer having a first surface and a second surface opposite to the first surface; disposing a substrate on the first surface of the resistor layer; after disposing the substrate, depositing two first electrodes on the second surface of the resistor layer, the first electrodes being spaced apart at opposite ends of the second surface; after depositing the first electrodes, depositing a barrier layer on the second surface of the resistor layer, the barrier layer being located between the first electrodes; after depositing the barrier layer, forming a protective layer on the barrier layer, the protective layer covering a top surface of each of the first electrodes and the barrier layer. The barrier layer is located between the protective layer and the second surface of the resistor layer.

In at least one embodiment of this disclosure, the barrier layer is deposited via physical vapor deposition.

In at least one embodiment of this disclosure, the method for manufacturing a chip resistor further includes, after forming a protective layer, depositing a second electrode on the first electrode, wherein the second electrodes cover the area of the first electrode exposed by the protective layer; and after depositing the second electrodes, depositing a solder layer on each of the second electrodes. The second electrode is located between the first electrode and the solder layer.

In at least one embodiment of this disclosure, the method for manufacturing a chip resistor further includes removing a portion of the resistor layer before depositing the barrier layer to form a resistance-modifying region on a second surface of the resistor layer.

Based on the above, this disclosure involves providing at least one barrier layer between the second surface of the resistive layer and the protective layer. Due to the density and amorphous nature of this barrier layer, it not only reduces the possibility of external moisture passing through it, thereby reducing the influence of moisture on the resistance of the chip resistor, but also improves the resistance temperature coefficient of the chip resistor. Therefore, it helps to improve the overall resistance stability of the chip resistor.

This disclosure will be illustrated in detail with reference to the following embodiments. It should be noted that the descriptions of the embodiments in this disclosure are for illustrative purposes only and are not intended to reveal all embodiments in detail or to limit the specific embodiments of this disclosure. For example, the phrase "the first feature is formed on the second feature" includes multiple embodiments, covering situations where the first and second features are in direct contact, and situations where additional features are formed between the first and second features so that they are not in direct contact. Furthermore, the same element symbols used in the drawings and specifications will, to the extent possible, represent the same or similar elements.

In the following text, to clearly illustrate the technical features of this disclosure, the dimensions (e.g., length, width, thickness, and depth) of the elements (e.g., layers, films, substrates, and areas) in the drawings will be enlarged proportionally. Therefore, the descriptions and explanations of the embodiments below are not limited to the dimensions and shapes of the elements presented in the drawings, but should cover dimensions, shapes, and deviations from these due to actual manufacturing processes and/or tolerances. For example, a flat surface shown in the drawings may have rough and/or nonlinear characteristics, and sharp angles shown in the drawings may be rounded. Therefore, the elements presented in the drawings of this disclosure are primarily for illustrative purposes and are not intended to accurately depict the actual shape of the elements, nor are they intended to limit the scope of the claims made in this disclosure.

Please refer to Figures 1A and 1B, where Figure 1A shows a chip resistor 100 according to at least one embodiment of this disclosure, and Figure 1B shows a cross-sectional view of the chip resistor 100 along section A. The chip resistor 100 includes a substrate 110, a resistive layer 120, first electrodes 140a and 140b, a barrier layer 160, and a protective layer 180. The resistive layer 120 is disposed on the substrate 110 and has a first surface 120f and a second surface 120s opposite to the first surface 120f. The substrate 110 is located on the first surface 120f of the resistive layer 120, and the substrate 110 may be, for example, a polyimide (PI) film, a glass-reinforced epoxy resin laminate (e.g., FR4 glass fiber board), or a similar material.

On the other hand, although not shown in the figure, in detail, the resistive layer 120 may include an internal alloy substrate and an oxide layer covering the outside of the alloy substrate. The alloy substrate may include, for example, copper manganese tin (CuMnSn), copper manganese nickel (CuMnNi), copper nickel alloy (CuNi), other suitable alloy materials, or any combination of the above materials, while the oxide layer may include, for example, manganese oxide, nickel oxide, copper oxide, or a combination of the above metal oxides.

As shown in Figure 1B, first electrodes 140a and 140b are disposed at opposite ends of the second surface 120s of resistive layer 120, with the first electrode 140a located at the left end of resistive layer 120 and the first electrode 140b located at the right end of resistive layer 120, and there is a gap between the first electrodes 140a and 140b. The material of the first electrodes 140a and 140b may include copper.

A barrier layer 160 is disposed between the first electrodes 140a and 140b, and covers the second surface 120s of the resistive layer 120. Notably, in this embodiment, the second surface 120s of the resistive layer 120 is completely covered by the barrier layer 160, except for the portion covered by the first electrodes 140a and 140b. In other words, the second surface 120s of the resistive layer 120 can be completely isolated from the protective layer 180.

The material of the barrier layer 160 is selected from the group consisting of copper, nickel, chromium, aluminum, titanium, tungsten, tantalum, and their combinations. For example, the barrier layer 160 may contain copper nickel (CuNi), nickel chromium (NiCr), nickel chromium aluminum (NiCrAl), nickel chromium silicon (NiCrSi), titanium tungsten (TiW), tantalum nitride (TaN), any combination of the above materials, or similar materials. It is worth mentioning that the lattice structure of the barrier layer 160 is an amorphous material. This amorphous lattice structure allows the water vapor transmission rate (WVTR) of the barrier layer 160 to be below 1 mg/ ^m² ·day·atm, which is beneficial for blocking external water vapor from penetrating to the resistive layer 120.

In addition, the amorphous lattice structure also results in a lower temperature coefficient of resistance (TCR). Since the barrier layer 160 and the resistive layer 120 are electrically connected in parallel, when the TCR of the barrier layer 160 is lower than that of the resistive layer 120, the overall TCR of the chip resistor 100 can be reduced through parallel connection. In other words, providing a barrier layer 160 in parallel with the resistive layer 120 in the chip resistor 100 helps to improve the resistance stability of the chip resistor 100.

In the various embodiments disclosed herein, the thickness t1 of the barrier layer 160 is less than 0.003 times the thickness t2 of the resistive layer 120. In short, the relationship between the thickness t1 of the barrier layer 160 and the thickness t2 of the resistive layer 120 is: t1 < 0.003 × t2. It is worth noting that in some embodiments, the thickness t1 of the barrier layer 160 can range from 0.1 µm to 3 µm. Specifically, the number of barrier layers 160 in the embodiments disclosed herein is not limited to one. In other embodiments, the number of barrier layers 160 can also be one or more, such as two layers.

A protective layer 180 is disposed on a barrier layer 160 and covers the top surfaces 142t of the first electrodes 140a and 140b, as well as the barrier layer 160. As shown in FIG1B, the barrier layer 160 is located between the protective layer 180 and the second surface 120s of the resistive layer 120, and the barrier layer 160 extends to the side surfaces 142s of the first electrodes 140a (and 140b) and the protective layer 180. Since the boundary region C1 between the first electrodes 140a and 140b and the resistive layer 120 is also covered by the barrier layer 160, it can further prevent moisture from penetrating from the boundary region C1 to the resistive layer 120. The protective layer 180 may contain organic polymer materials such as polyimide or epoxy resin.

The chip resistor 100 further includes a second electrode 150a and a second electrode 150b, which are respectively disposed on and electrically connected to the first electrode 140a and the first electrode 140b. The second electrode 150a and the second electrode 150b cover the area R1 exposed by the protection layer 180 of the first electrode 140a and the first electrode 140b, and a portion of the protection layer 180 is located between the first electrode 140a and the second electrode 150a, and another portion of the protection layer 180 is located between the first electrode 140b and the second electrode 150b. In other words, the second electrode 150a and the second electrode 150b also partially cover the protective layer 180.

It is worth mentioning that the second electrodes 150a and 150b cover the top surface 180t of the protective layer 180. In this embodiment, the top surface 150t of the second electrodes 150a (and 150b) is higher than the top surface 180t, and the distance d1 between the top surface 150t and the top surface 180t is 5µm or more, but this disclosure is not limited to this. In other embodiments, the distance d1 between the top surface 150t and the top surface 180t may also be less than 5µm. The material of the second electrodes 150a and 150b may include copper.

In addition, the chip resistor 100 also includes a solder layer 170a and a solder layer 170b. Solder layers 170a and 170b are respectively disposed on second electrodes 150a and 150b, wherein these second electrodes are located between the first electrode and the solder layers. Specifically, second electrode 150a is located between the first electrode 140a and solder layer 170a, while second electrode 150b is located between the first electrode 140b and solder layer 170b. The materials of solder layers 170a and 170b may include nickel, tin, similar solder metals, or combinations thereof.

The chip resistor 100 also includes a resistance-repairing region 190. In this embodiment, the resistance-repairing region 190 is located on the second surface 120s of the resistive layer 120, and the barrier layer 160 covers the resistance-repairing region 190. However, the number and location of the resistance-repairing regions 190 in this disclosure are not limited to this embodiment. In other embodiments, the number of resistance-repairing regions 190 may be more than one, and the resistance-repairing regions 190 may be distributed on the first electrode 140a or the first electrode 140b.

The manufacturing method of a chip resistor of at least one embodiment of this disclosure is illustrated by a series of steps shown in Figures 2A to 2D. Referring to Figure 2A, firstly, a resistive layer 120 is provided. Specifically, the method of providing the resistive layer 120 in this embodiment includes: heating an alloy substrate (not shown) in a nitrogen environment with a low oxygen content (e.g., oxygen content ≤ 50 ppm), and maintaining the temperature of the nitrogen environment between 200°C and 400°C, so that the surface of the alloy substrate is oxidized to form an oxide layer (not shown).

Next, as shown in Figure 2A, a substrate 110 can be deposited on the first surface 120f of the resistive layer 120 by means of, for example, hot pressing. Referring to Figure 2B, after the substrate 110 is deposited, the first electrode 140a and the first electrode 140b are deposited on the second surface 120s of the resistive layer 120. For example, a patterned anti-plating protective layer can be first deposited on the resistive layer 120 by printing (or lamination) and photolithography. This anti-plating protective layer can be a material such as photoresist, removable adhesive film, or ink.

Then, a portion of the oxide layer of the resistive layer 120 (i.e., the oxide layer of the area to be electroplated) is removed by chemical etching (e.g., acidic solution etching) to expose the alloy substrate of the area to be electroplated to the second surface 120s. Next, a metal material, such as copper, is deposited on the resistive layer 120 by electroplating, and the patterned anti-electroplating protective layer is removed by using a film-removing solvent or water washing to form the first electrode 140a and the first electrode 140b on the resistive layer 120.

Next, referring to Figure 2C, after depositing the first electrode 140a and the first electrode 140b, a barrier layer 160 can be deposited on the second surface 120s of the resistive layer 120 by means of physical vapor deposition (PVD) such as sputtering. In detail, a patterned sputtering protective layer (not shown) can be first formed on the resistive layer 120 and the first electrodes 140a and 140b by printing (or lamination) and photolithography. This sputtering protective layer covers the top surfaces 142t of the first electrodes 140a and 140b, and exposes the second surface 120s of the resistive layer 120. Then, an initial barrier layer (not shown) is deposited on the second surface 120s of the resistive layer 120 and the surface of the sputtering protective layer by sputtering. Next, the sputtering protective layer and a portion of the initial barrier layer covering the sputtering protective layer can be removed by chemical etching to form a barrier layer 160.

It is worth mentioning that, returning to Figure 2B, the manufacturing method of the chip resistor 100 also includes removing a portion of the resistor layer 120 by means of laser trimming or machining before depositing the barrier layer 160, so as to form a trimming region 190 for resistance adjustment on the second surface 120s of the resistor layer 120, so that the resistor layer 120 obtains the desired target resistance value.

Next, referring to Figure 2D, after depositing the barrier layer 160, a protective layer 180 is formed on the barrier layer 160. Specifically, an initial protective layer can be formed on the barrier layer 160 and the top surfaces 142t of the first electrodes 140a and 140b by means such as lamination, printing, or coating. Then, a portion of the initial protective layer is removed by photolithography to form the protective layer 180, exposing a section R1 of the top surfaces 142t of the first electrodes 140a and 140b.

Please also refer to Figures 1B and 2D. The manufacturing method of the chip resistor 100 further includes: after forming the protective layer 180, the second electrode 150a and the second electrode 150b can be deposited on the first electrode 140a and the first electrode 140b respectively by means such as electroplating, so that the second electrode 150a and the second electrode 150b cover the area R1 exposed by the protective layer 180 of the first electrode 140a and the first electrode 140b.

In addition, after depositing the second electrode 150a and the second electrode 150b, a solder layer 170a and a solder layer 170b are deposited on the second electrode 150a and the second electrode 150b, respectively, to provide the function of soldering and bonding between the chip resistor 100 and the external circuit board. Since the method of depositing the second electrode 150a (and the second electrode 150b) and the solder layer 170a (and the solder layer 170b) is the same as the method of depositing the first electrode 140a (and the first electrode 140b), it will not be repeated here. At this point, the chip resistor 100 of at least one embodiment of this disclosure is substantially complete.

In summary, by providing at least one barrier layer between the second surface of the resistive layer and the protective layer, the density and amorphous nature of this barrier layer not only reduce the possibility of external moisture passing through it, thus minimizing the influence of moisture on the resistance of the chip resistor, but also improve the temperature coefficient of resistance of the chip resistor. This, in turn, helps to improve the stability of the resistance value of the chip resistor.

Although the above-described embodiments have been disclosed in this case, they are not intended to limit this disclosure. Those skilled in the art to which this disclosure pertains may make some modifications and embellishments without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the scope of the attached patent application.

100: Chip Resistor 110: Substrate 120: Resistor Layer 120f: First Surface 120s: Second Surface 140a, 140b: First Electrode 142t, 150t, 180t: Top Surface 142s: Side Surface 150a, 150b: Second Electrode 160: Barrier Layer 170a, 170b: Solder Layer 180: Protective Layer 190: Repair Area A: Cross-section C1: Boundary Area d1: Spacing R1: Block t1, t2: Thickness

The embodiments of this disclosure can be understood from the following detailed description and accompanying figures. It should be noted that many features are not drawn to industry-standard scale. In fact, the dimensions of various features can be arbitrarily increased or decreased for clarity of discussion. Figure 1A shows a perspective view of a chip resistor according to an embodiment of this disclosure. Figure 1B shows a cross-sectional view of the chip resistor of the embodiment of Figure 1A along section A. Figures 2A to 2D show cross-sectional views of a method for manufacturing a chip resistor according to an embodiment of this disclosure.

Domestic Storage Information (Please record in order of storage institution, date, and number) None International Storage Information (Please record in order of storage country, institution, date, and number) None

100: Chip Resistor

110: Substrate

120: Resistive Layer

120f: First surface

120s: Second Surface

140a, 140b: First electrode

142t, 150t, 180t: Top surface

142s: Side surface

150a, 150b: Second electrode

160: Barrier Layer

170a, 170b: Weld layer

180: Protective Layer

190: Repair Zone

C1: Boundary Area

d1: Spacing

R1: Block

t1, t2: Thickness

Claims (10)

A chip resistor includes: a substrate; a resistor layer disposed on the substrate, the resistor layer having a first surface and a second surface opposite to the first surface, wherein the substrate is located on the first surface of the resistor layer; two first electrodes disposed at opposite ends of the second surface of the resistor layer; a barrier layer disposed between the first electrodes and covering the second surface of the resistor layer; and a resistance-reducing region located on the second surface of the resistor layer, wherein the barrier layer covers the resistance-reducing region; and A protective layer is disposed on the barrier layer and covers a top surface of each of the first electrodes and the barrier layer, wherein the barrier layer is located between the second surface of the protective layer and the resistive layer. The chip resistor as claimed in claim 1, wherein the resistance temperature coefficient of the barrier layer is less than the resistance temperature coefficient of the resistor layer. The chip resistor as claimed in claim 1, wherein the barrier layer extends to one side surface of each of the first electrodes and between the protective layer. The chip resistor of claim 1 further comprises: two second electrodes disposed on and electrically connected to the first electrodes, wherein the second electrodes cover areas of the first electrodes exposed by the protective layer, and a portion of the protective layer is located between the second electrodes and the first electrodes; and two solder layers disposed on the second electrodes, wherein the second electrodes are located between the first electrodes and the solder layers. The chip resistor as claimed in claim 1, wherein the thickness of the barrier layer is less than 0.003 times the thickness of the resistor layer. The chip resistor as described in claim 1, wherein the thickness of the barrier layer ranges from 0.1µm to 3µm. The chip resistor as claimed in claim 1, wherein the material of the barrier layer is selected from the group consisting of copper, nickel, chromium, aluminum, titanium, tungsten, tantalum and combinations thereof. A method for manufacturing a chip resistor includes: providing a resistor layer having a first surface and a second surface opposite to the first surface; disposing a substrate on the first surface of the resistor layer; after disposing the substrate, depositing two first electrodes on the second surface of the resistor layer, the first electrodes being spaced apart at opposite ends of the second surface; after depositing the first electrodes, removing a portion of the resistor layer to form a resistance-reducing region on the second surface of the resistor layer; depositing a barrier layer on the second surface of the resistor layer where the resistance-reducing region is formed, the barrier layer being located between the first electrodes; and After the barrier layer is deposited, a protective layer is formed on the barrier layer, and the protective layer covers a top surface of each of the first electrodes and the barrier layer, wherein the barrier layer is located between the protective layer and the second surface of the resistive layer. The method described in claim 8, wherein the deposition of the barrier layer includes physical vapor deposition. The method of claim 8 further comprises: after forming the protective layer, depositing a second electrode on each of the first electrodes, wherein the second electrodes cover the areas of the first electrodes exposed by the protective layer; and after depositing the second electrodes, depositing a solder layer on each of the second electrodes, wherein the second electrodes are located between the first electrodes and the solder layer.