TWI903967B - Driving circuit for power switch device and method thereof - Google Patents

Abstract

A switching device controlled by a driver is described. The driver provides a gate-to-source voltage and a source voltage to a power semiconductor device of the switching device. The source voltage increases with an increment of the gate-to-source voltage, or the source voltage decreases with a decrement of the gate-to-source voltage, such that the gate-to-source voltage exceeds a positive or negative predetermined threshold as early as possible, thereby enhancing switch speed of the power semiconductor device.

Description

Drive circuits and methods for power switching elements

This invention relates to a drive circuit and component employing a switch, and to an electronic device including one or more of such circuits.

Key switch topologies such as half-bridge and full-bridge can be implemented using silicon (Si), silicon carbide (SiC), or gallium nitride (GaN) devices. Silicon insulated gate bipolar transistor (IGBT) technology, used in conjunction with silicon anti-parallel diodes, is widely used in power applications due to its reliable performance and cost-effectiveness. However, newer wide bandgap (WBG) semiconductor technologies such as silicon carbide and gallium nitride offer significant performance advantages, including higher efficiency, faster switching frequencies, and lower power losses, although these advantages come with significantly higher costs.

Silicon carbide technology is particularly well-suited for high-power and high-temperature applications because it offers physical advantages over traditional silicon, including a wide bandgap, high breakdown field strength, high electron drift velocity, and excellent thermal conductivity. These characteristics enable silicon carbide power switches to operate efficiently under extreme conditions, achieving a significantly lower specific on-resistance than silicon-based devices. Therefore, silicon carbide unipolar devices hold promise for replacing silicon-based bipolar switches (such as IGBTs) and rectifiers, with these characteristics offering significant advantages within specific voltage ranges.

However, the unique properties of silicon carbide also present design challenges, especially in high-speed switching applications. During the fast switching transients of bridge circuits, the inherently high voltage-time variation rate (dv/dt) and current-time variation rate (di/dt) of silicon carbide can cause significant crosstalk effects on complementary components. This crosstalk is influenced by the components and parasitic elements within their packages. Furthermore, silicon carbide's lower on-threshold voltage and reduced reverse voltage withstand capability make it susceptible to damage from voltage fluctuations caused by crosstalk. Reducing the impact of these effects is crucial for ensuring the safety and reliability of silicon carbide components, especially in high-frequency applications.

Relevant solutions can be found in US Patent 11,108,388 and US Patent 11,184,003. However, the switching speed may be affected or compromised because the voltage level must be reversed when spikes occur.

This disclosure describes a technique for improving the switching speed of power semiconductor devices while maintaining safe operation during transient turn-on and turn-off. By overdriving the gate of the power semiconductor device, the duration of these transient phases can be shortened, and the gate source voltage can be kept within a safe range by means of the function of the drive control circuit.

In one example, a method for controlling a switching element is disclosed, the method comprising the steps of providing a power semiconductor element controlled by a driver, the driver providing a gate-source voltage and a source voltage to the power semiconductor element. The driver outputs a gate drive signal to a gate of the power semiconductor device, wherein when the gate source voltage rises in response to the gate drive signal, the source voltage is increased to exceed a positive preset threshold, and when the gate source voltage decreases in response to the gate drive signal, the source voltage is decreased to exceed a negative preset threshold. When the gate source voltage exceeds the positive preset threshold or the negative preset threshold, the driver controls the gate source voltage to be within a safe range.

In some examples, a switching element controlled by a driver is disclosed, the driver providing a gate-source voltage and a source voltage to a power semiconductor element of the switching element, the source voltage increasing as the gate-source voltage increases, or the source voltage decreasing as the gate-source voltage decreases, causing the gate-source voltage to exceed a positive preset threshold or a negative preset threshold.

In some examples, a switching element controlled by a driver is disclosed, which provides a gate-source voltage and a source voltage to a power semiconductor element of the switching element, wherein the source voltage decreases when a switching direction of the gate-source voltage changes from positive to negative, and increases when a switching direction of the gate-source voltage changes from negative to positive.

Before delving into the specific embodiments illustrated in the figures, it should be understood that this disclosure is not limited to the particular details or methods described or shown in the figures. Furthermore, the terminology used in this disclosure is for descriptive purposes only and should not be considered restrictive.

Throughout this specification and request, the definitions provided below are for illustrative purposes only and are not intended to impose strict limitations on the terminology. Unless the context clearly indicates otherwise, the terms "a" and "the" should be understood to include the plural form for reference, and "in..." should be interpreted to include both "in..." and "on...". The phrases "in one embodiment," "in one example," and "in one embodiment" used in this disclosure do not necessarily refer to the same embodiment or example, but may in some cases.

A method and circuit are described for use with a power semiconductor device controlled to modulate the current flow from one or more power sources to one or more electrical loads. The power semiconductor device can be a switch made of silicon (Si), silicon carbide (SiC), gallium nitride (GaN), and other wide bandgap (WBG) semiconductor materials. The switch can be an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field-effect transistor (MOSFET), a junction field-effect transistor (JFET), or other power semiconductor devices. In these embodiments, using a metal oxide semiconductor (MOS) transistor as a metal insulated semiconductor field-effect transistor (MISFET) is an example. However, the use of a non-oxide film as the gate insulation film is also applicable.

Figure 1 is a circuit block diagram illustrating a half-bridge switching circuit and its associated drive circuit in an embodiment, commonly used in power electronics applications such as power conversion equipment. The switch shown in Figure 1 is a normally open SiC MOSFET. This half-bridge circuit can have multiple functions, such as serving as a power supply part of a DC-DC converter, a part of a DC-AC converter (which can be expanded into a full-bridge circuit, a three-phase inverter, etc.), or a part of a motor control device.

The half-bridge circuit shown in Figure 1 includes a gate drive control circuit 10, an upper arm side switching element 20, a lower arm side switching element 30, a first gate drive circuit 40, and a second gate drive circuit 50. Each of the upper arm-side switching element 20 and the lower arm-side switching element 30 includes a SiC MOSFET, which is a high-side power transistor 21 and a low-side power transistor 31, respectively. The high-side power transistor 21 and the low-side power transistor 31 can be connected to one or more analog electronic devices. In this example, the high-side power transistor 21 is connected in parallel with three first capacitors 22, and the low-side power transistor 31 is connected in parallel with three second capacitors 32. The first capacitor 22 includes a gate-drain capacitor 221, a gate-source capacitor 222, and a drain-source capacitor 223. The second capacitor 32 includes a gate-drain capacitor 321, a gate-source capacitor 322, and a drain-source capacitor 323. In other examples, the electronic component may be a diode such as a flywheeling diode or a zener diode, a resistor, an inductor, or a combination thereof, depending on the application of the circuit. As shown in Figure 1, the upper arm-side switching element 20 may also be connected to a first inductor 23 and a first resistor 24, while the lower arm-side switching element 30 may be connected to a second inductor 33 and a second resistor 34.

A power supply voltage V _BUS is supplied to a drain of the high-side power transistor 21 and a source of the low-side power transistor 31, with the source of the high-side power transistor 21 connected to the drain of the low-side power transistor 31. The gate drive control circuit 10 receives an upper arm control signal 10a and a lower arm control signal 10b, and outputs an upper arm drive control signal 10c and a lower arm drive control signal 10d. The upper arm drive control signal 10c and the lower arm drive control signal 10d are generated by, for example, a microcontroller or a similar IC chip. The gate drive control circuit 10 performs the functions of voltage level conversion, timing adjustment, noise cancellation, and protection for the upper arm drive control signal 10c and the lower arm drive control signal 10d.

The operation of the high-side power transistor 21 and the low-side power transistor 31 can be controlled by the voltages applied to the source, gate, and drain of the high-side power transistor 21 and the low-side power transistor 31, respectively. Specifically, the source-to-drain current of the high-side power transistor 21 and the low-side power transistor 31 can be controlled by a gate-source voltage _Vgs based on the voltage-current (IV) characteristics of the device. The n-type metal oxide semiconductor field-effect transistor (NMOS FETs) operates under a positive voltage, while the p-type metal oxide semiconductor field-effect transistor (PMOS FETs) operates under a negative voltage. In this disclosure, the n-type metal oxide semiconductor field-effect transistor is used for illustrative purposes only and typically has a positive threshold voltage ( _Vth ) and a positive drain-source voltage.

Figure 2 is a timing diagram illustrating the operation of various parts of the gate drive in one embodiment. Figure 2 shows the conduction cycle diagram 60, in which a high-side switch (the high-side power transistor 21) first turns off (cycle 61), turns on (cycle 62), and then turns off again (cycle 63). Figure 2 also shows an operating waveform 70 to represent the gate source voltage _Vgs of the high-side switch. During startup, the gate drain capacitor 221 of the upper arm-side switching element 20 is charged, causing a current to flow through the gate circuit, thereby increasing the gate source voltage Vgs. A positive overvoltage is generated on the gate switch _(GS) . Once the voltage exceeds a turn-on voltage, the high-side switch will change state. The fast switching characteristics of wide bandgap semiconductors can introduce challenges such as crosstalk, mainly due to overvoltage and ringing during fast switching transitions. As shown in Figure 2, crosstalk occurs during the transition period 71 and is characterized by positive and negative gate voltage spikes. Positive spikes may accidentally trigger a turn-on event, while negative spikes may apply excessive pressure to the gate, especially since the minimum allowable gate voltage of mainstream WBG power devices is limited. The most advanced gate drivers can detect and dynamically control the gate source voltage _Vgs when it exceeds a threshold. Specifically, the most advanced gate drivers will suppress gate voltage spikes when the threshold is reached, thereby protecting the device.

This disclosure describes a method for increasing the switching speed of a switching element when crosstalk occurs on the gate source voltage. Figure 3 illustrates an embodiment of a drive circuit operation method 900, in which the gate drive control circuit 10 alternately receives the upper arm control signal 10a and the lower arm control signal 10b according to a timing diagram. The gate drive control circuit 10 outputs a high-side gate drive signal (the upper arm drive control signal 10a). c) and a low-side gate drive signal (the lower arm drive control signal 10d) to turn on or off the high-side switch (the high-side power transistor 21) and/or a low-side switch (the low-side power transistor 31) (step 901), these signals may be a drive current provided to the gate of the high-side switch and/or the low-side switch. During the process of turning on the high-side switch (or the low-side switch), the current required for charging is supplied to the gate of the high-side switch, thereby causing the gate source voltage _Vgs to rise. As mentioned earlier, an overvoltage and ringing phenomenon will occur at the beginning of the turn-on. In order to improve the switching speed of the high-side switch, the source voltage _Vs of the high-side switch is controlled to increase (step 902) or decrease (step 903) in accordance with the high-side gate drive signal. As shown by line segment 81 in waveform 80 in Figure 2, it represents an example of the rise of the source voltage _Vs.

If the high-side gate drive signal wants to turn on the high-side switch, the source voltage _Vs is increased, causing the gate source voltage _Vgs to rise above a threshold set by the gate drive control circuit 10. When the threshold is exceeded, the gate drive control circuit 10 adjusts the gate source voltage _Vgs of the high-side switch to decrease. In other words, the purpose of increasing the source voltage _Vs is to overdrive the high-side switch, making it exceed the threshold more quickly, thereby improving switching efficiency.

Conversely, if the high-side gate drive signal is intended to turn off the high-side switch, the source voltage _Vs is controlled to decrease, causing the gate source voltage _Vgs to drop below the threshold set by the gate drive control circuit 10. Once below the threshold, the gate drive control circuit 10 adjusts to increase the gate source voltage _Vgs of the high-side switch. In other words, decreasing the source voltage _Vs is intended to overdrive the high-side switch, thereby allowing it to drop below the threshold more quickly.

After overdrive, the source voltage _Vs is adjusted based on the change in the gate source voltage _Vgs . If the change in the gate source voltage _Vgs meets a standard, the source voltage _Vs is adjusted. In one example, the standard may involve monitoring the transition direction of the gate source voltage _Vgs (steps 904 and 905), i.e., at the inflection points 72 and 73 in the voltage-time (VT) operating waveform 70 depicted in Figure 2. In one embodiment, the standard can be any specific change in the switching direction of the gate source voltage _Vgs , i.e., a change from a positive switching rate to a negative switching rate (inflection point 72) or a change from a negative switching rate to a positive switching rate (inflection point 73) to meet the standard. Once the standard is met, the source voltage _Vs is adjusted accordingly to decrease or increase (steps 906 and 907). This adjustment is represented by points 82 and 83 in the waveform 80 shown in Figure 2. Then, the changes in the gate source voltage _Vgs are repeatedly detected and the source voltage _Vs is adjusted (step 908) until the gate source voltage _Vgs reaches a steady state (step 909).

In this example, as shown in Figure 2, the source voltage _Vs can be designed to have three levels, including a first level _Vs1 , a second level _Vs2 , and a third level _Vs3 , wherein the first level _Vs1 is higher than the second level _Vs2 or the third level _Vs3 , and the second level _Vs2 is higher than the third level _Vs3 .

10: Gate drive control circuit 10a: Upper arm control signal 10b: Lower arm control signal 10c: Upper arm drive control signal 10d: Lower arm drive control signal 20: Upper arm side switching element 21: High-side power transistor 22: First capacitor 221: Gate drain capacitor 222: Gate source capacitor 223: Drain capacitor 23: First inductor 24: First resistor 30: Lower arm side switching element 31: Low-side power transistor 32: Second capacitor 321: Gate drain Electrode capacitor 322: Gate source electrode capacitor 323: Drain source electrode capacitor 33: Second inductor 34: Second resistor 40: First gate drive circuit 50: Second gate drive circuit 60: Diagram 61, 62, 63: Period 70: Operating waveform 71: Transition period 72, 73: Inflection point 80: Waveform 81: Line segment 82, 83: Point 900: Operating method 901, 902, 903, 904, 905, 906, 907, 908, 909: Step V _BUS : Power supply voltage _Vgs : Gate source voltage _Vs : Source voltage _Vs1 : First digit _Vs2 : Second digit _Vs3 : Third digit

The embodiments disclosed herein are described with reference to the following accompanying figures: 'Figure 1' is a schematic diagram of the circuit topology in various embodiments of this disclosure. 'Figure 2' is a timing diagram of the signal and voltage changes during the switching of the high-side switch in one embodiment of this disclosure. 'Figure 3' is a schematic diagram of the operation method of the circuit topology disclosed herein.

10: Gate drive control circuit

10a: Upper arm control signal

10b: Lower arm control signal

10c: Upper arm drive control signal

10d: Lower arm drive control signal

20: Upper arm side switching element

21: High-power transistors

22: First capacitor

221: Gate Drain Capacitor

222: Gate Source Electrode Capacitor

223: Source Capacitor

23: First Inductor

24: First Resistor

30: Lower arm side switching element

31: Low-side power transistors

32: Second capacitor

321: Gate Drain Capacitor

322: Gate Source Electrode Capacitor

323: Source Capacitor

33: Second Inductor

34: Second Resistor

40: First gate drive circuit

50: Second gate drive circuit

V _BUS : Power supply voltage

Claims (9)

A method for controlling a switching element includes the following steps: providing a power semiconductor element controlled by a driver, the driver providing a gate source voltage and a source voltage to the power semiconductor element; The driver outputs a gate drive signal to a gate of the power semiconductor device, wherein when the gate source voltage rises in response to the gate drive signal, the source voltage is increased to exceed a positive preset threshold, and when the gate source voltage decreases in response to the gate drive signal, the source voltage is decreased to exceed a negative preset threshold; and when a change in the gate source voltage meets a standard, the source voltage is adjusted. The control method as described in claim 1, wherein the gate drive signal includes an upper bridge trigger signal and a lower bridge trigger signal alternately output to the gate of the power semiconductor element. The control method of claim 1, wherein the source voltage is configured to have at least a high level, a low level, and a middle level, wherein the source voltage is increased by adjusting from the low level to the middle level or from the middle level to the high level, and the source voltage is decreased by adjusting from the middle level to the low level or from the high level to the middle level. The control method as described in claim 1, wherein the source voltage is adjusted when a switching direction of the gate source voltage changes. The control method as described in claim 1, wherein the source voltage decreases when a switching direction of the gate source voltage changes from positive to negative. The control method as described in claim 1, wherein the source voltage increases when a switching direction of the gate source voltage changes from negative to positive. The control method as described in claim 1, wherein the power semiconductor device includes any one of a metal oxide semiconductor field-effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a field-effect transistor (FET), and a gallium nitride (GaN) type transistor. A switching element is controlled by a driver that provides a gate-source voltage and a source voltage to a power semiconductor element of the switching element, wherein the source voltage increases as the gate-source voltage increases, or decreases as the gate-source voltage decreases. The gate source voltage is reduced to exceed a positive preset threshold or a negative preset threshold, and the source voltage decreases when a switching direction of the gate source voltage changes from positive to negative, and increases when the switching direction of the gate source voltage changes from negative to positive. The switching element as described in claim 8, wherein the power semiconductor element includes any one of a metal oxide semiconductor field-effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a field-effect transistor (FET), and a gallium nitride (GaN) type transistor.