TWI902505B - Chip - Google Patents

Abstract

A chip includes a configuration pin, an inner pull-up resistor, an inner pull-down resistor, a logic-level detection circuit (a logic-level detection circuit can be a digital logic buffer, comparator, or other circuits which detect logic levels) and a configuration detection circuit. The configuration pin is electrically connected to a reference voltage terminal through an external resistor. The configuration detection circuit is configured to connect an input terminal of the logic-level detection circuit to the configuration pin, and is further configured to perform the following steps. Disconnect the inner pull-up resistor and the inner pull-down resistor from the configuration pin to output a 0-th detection logic value by the logic-level detection circuit. Sequentially connect the inner pull-up resistor and the inner pull-down resistor to the configuration pin to output a plurality of detection logic values by the logic-level detection circuit. A configuration vector is determined according to the 0-th detection logic value and the detection logic values.

Description

Chips

This case relates to a chip, and more particularly to a chip that can be configured for vector programming via a single pin.

Application-specific integrated circuits (ASICs) are often configured using pin bundling. Pin bundling configurations provide circuit designers using application-specific ASICs with flexibility at the printed circuit board (PCB) level. For example, a circuit designer might configure the chip identifier of an application-specific ASIC in pin-bundled circuitry at the PCB level, allowing multiple instances of the chip to have different identifiers. As another example, pin bundling configurations are used to enable/disable specific chip functions, allowing end users to easily modify DIP switches associated with specific chip functions. However, application-specific integrated circuits often employ multi-bit vector configurations using two or more pins, which increases chip size and material costs. Therefore, providing a chip that solves these problems is an important issue in this field.

This disclosure provides a chip. The chip includes a configuration pin, an internal pull-up resistor, an internal pull-down resistor, a logic detection circuit, and a configuration detection circuit. The logic detection circuit may be a digital logic buffer, a comparator, or other circuit that can be used to detect a logic level or a voltage level equivalent to that logic value. The configuration pin is electrically connected to a reference voltage terminal via an external resistor. The configuration detection circuit is electrically connected to the configuration pin, the internal pull-up resistor, the internal pull-down resistor, and the logic detection circuit, wherein the configuration detection circuit is used to connect the input terminal of the logic detection circuit to the configuration pin, and wherein the configuration detection circuit is further used to perform the following steps. Disconnect the internal pull-up and pull-down resistors from the configuration pin to cause the logic detection circuit to output the zeroth detection logic value. Connect the internal pull-up and pull-down resistors sequentially to the configuration pin to cause the logic detection circuit to output a plurality of detection logic values. Determine the configuration vector based on the zeroth detection logic value and the plurality of detection logic values.

This disclosure provides a chip. The chip includes a configuration pin, an internal pull-up resistor, an internal pull-down resistor, a logic detection circuit, and a configuration detection circuit. The configuration detection circuit is electrically connected to the logic detection circuit, the internal pull-up resistor, and the internal pull-down resistor, wherein the internal pull-up resistor and the internal pull-down resistor are variable resistors, and wherein the configuration detection circuit is used to perform the following steps: progressively adjusting the resistance values of the internal pull-up resistor and the internal pull-down resistor to a plurality of preset resistance values, at which the internal pull-up resistor and the internal pull-down resistor are sequentially connected to the configuration pin, so that the digital logic detection circuit outputs the plurality of detected logic values, and determines a configuration vector based on the plurality of detected logic values.

In summary, the chip disclosed in this document can be configured through a single configuration pin, thereby reducing the number of pins on the chip.

The following are detailed descriptions of embodiments in conjunction with the accompanying drawings. However, the provided embodiments are not intended to limit the scope of this disclosure, and the description of the structural operation is not intended to limit the order of execution. Any device with equivalent functionality produced by the recombination of components falls within the scope of this disclosure. Furthermore, the drawings are for illustrative purposes only and are not drawn to scale. For ease of understanding, the same or similar components will be labeled with the same symbols in the following description.

Unless otherwise specified, all terms used throughout this specification and the scope of the patent application generally have their ordinary meaning in the context of this field, the content disclosed herein, and the specific content. Furthermore, the terms "comprising," "including," "having," "containing," etc., used herein are open-ended terms, meaning "including but not limited to." Additionally, the term "and/or" as used herein includes any one or more of the related listed items and all combinations thereof.

Please refer to Figure 1, which is a schematic diagram of a configuration detection system 100 according to an embodiment of this disclosure. As shown in Figure 1, the configuration detection system 100 includes a chip 110, external resistors Rext1 and/or Rext0. In some embodiments, the chip 110 is an integrated circuit. In some embodiments, the chip 110 is an application-specific integrated circuit or other logical integrated circuit, and this invention is not limited thereto. In some embodiments, function selection, chip startup, address selection, clock configuration, or other actions or functions are performed through the configuration pin 102 of the chip 110. In some embodiments, function selection can be performed by selecting different functions or mode configurations through the configuration pin 102. In some embodiments, chip startup is achieved by configuring pin 102 to start or reset chip 110. In some embodiments, address selection is achieved by configuring pin 102 to select an address or identifier. In some embodiments, clock configuration is achieved by configuring pin 102 to select different clock sources or clock frequencies. In some embodiments, chip 110 has configuration pin 102, and chip 110 can perform two-bit or multi-bit vector configuration through a single configuration pin 102.

In some embodiments, chip 110 is configured by connecting an external pull-up resistor (e.g., external resistor Rext1) or an external pull-down resistor (e.g., external resistor Rext0) to configuration pin 102. In some embodiments, the voltage of reference voltage terminal VDD _ext1 (e.g., 3.3 volts) is higher than the voltage of reference voltage terminal VDD _ext0 (e.g., 0 volts), and the external resistor Rext1 electrically connected to reference voltage terminal VDD _ext1 can be considered as an external pull-up resistor, and the external resistor Rext0 electrically connected to reference voltage terminal VDD _ext0 can be considered as a pull-down resistor. In some embodiments, the voltage of reference voltage terminal VDD _ext1 is 3.3 volts, and the voltage of reference voltage terminal VDD _ext0 is 0 volts. In some embodiments, by connecting an external resistor Rext1 or Rext0 to configuration pin 102, and by detecting the region covering the resistance value of the external resistor Rext1 or Rext0 (e.g., the upper and lower bounds of the region/boundary), the configuration vector is determined based on the region where the resistance value of the external resistor Rext1 or Rext0 is located, thereby configuring the function or behavior of the chip 110.

Chip 110 includes configuration detection circuit 120, internal pull-up resistor R1, internal pull-down resistor R0, output driver 124, switches S0, S1, S2 and S3, and logic detection circuit 126. In some embodiments, the internal pull-up resistor R1 is electrically connected between the reference voltage terminal VDD _int1 and the configuration detection circuit 120, and the internal pull-down resistor R0 is electrically connected between the reference voltage terminal VDD _int0 and the configuration detection circuit 120. In some embodiments, the output driver 124 may be implemented by other circuits that would create a resistive load on the configuration pin 102, and this invention is not limited to this. In some embodiments, the logic detection circuit 126 may be a digital logic buffer, a comparator, or other circuit that can be used to detect logic levels, and this invention is not limited thereto. In some embodiments, the configuration detection circuit 120 determines the configuration vector during the initial setup (configuration vector detection) based on the detected logic value _VLL (e.g., high logic or low logic) in each step. In some embodiments, during initial setup (configuration vector detection), the configuration detection circuit 120 disconnects the output driver 124 from the configuration pin 102 and connects the logic detection circuit 126 (the input terminal) to the configuration pin 102 so that the logic detection circuit 126 detects the potential of the configuration pin 102 and outputs a detection logic value _VLL (e.g., the zeroth detection logic value).

In some embodiments, during the initial setup (configuration vector detection), the configuration detection circuit 120 controls the connection between the internal pull-up resistor R1 and the internal pull-down resistor R0 and the configuration pin 102. In some embodiments, during the initial setup (configuration vector detection), the configuration detection circuit 120 sequentially connects the internal pull-up resistor R1 and the internal pull-down resistor R0 to the configuration pin 102, so that the logic detection circuit 126 detects the potential of the configuration pin 102 and outputs a detection logic value _VLL (e.g., a plurality of detection logic values), and then determines the configuration vector based on the output of the logic detection circuit 126.

In some embodiments, the configuration detection circuit 120 includes a logic circuit 122, which controls switches S0, S1, S2, and S3. In some embodiments, the configuration detection circuit 120 also includes switches S0, S1, and S3. In some embodiments, switch S0 is electrically connected between an internal pull-down resistor R0 and the configuration pin 102. In some embodiments, switch S0 is used to receive a control signal EN_R0 to turn on or off according to the control signal EN_R0. In some embodiments, switch S0 connects or disconnects the internal pull-down resistor R0 from the configuration pin 102 according to the control signal EN_R0. In some embodiments, logic circuit 122 may be implemented as a combinational logic circuit and/or a sequential logic circuit. In some embodiments, logic circuit 122 is electrically connected to internal pull-up resistor R1, internal pull-down resistor R0, the control terminals of switches S0-S3, and the output terminal of logic detection circuit 126. In some embodiments, logic circuit 122 is used to generate and provide control signals EN_R1, EN_R0, EN_OD, and EN_LB to the control terminals of switches S0-S3 to control switches S0-S3 to be turned on or off respectively.

In some embodiments, switch S1 is electrically connected between internal pull-up resistor R1 and configuration pin 102. In some embodiments, switch S1 is used to receive control signal EN_R1 to turn on or off according to control signal EN_R1. In some embodiments, switch S1 connects or disconnects internal pull-up resistor R1 from configuration pin 102 according to control signal EN_R1.

In some embodiments, switch S2 is electrically connected between the output terminal of output driver 124 and configuration pin 102. In some embodiments, switch S2 is used to receive control signal EN_OD to turn on or off according to control signal EN_OD. In some embodiments, switch S2 connects or disconnects the output terminal of output driver 124 from configuration pin 102 according to control signal EN_OD. In some embodiments, during the idle period, switch S2 connects or disconnects the output terminal of output driver 124 from configuration pin 102 according to control signal EN_OD; and during the initial setting (configuration vector detection) period, switch S2 disconnects the output terminal of output driver 124 from configuration pin 102 according to control signal EN_OD.

In some embodiments, switch S3 is electrically connected between the input terminal of logic detection circuit 126 and configuration pin 102. In some embodiments, switch S3 is used to receive control signal EN_LB to turn on or off according to control signal EN_LB. In some embodiments, switch S3 connects or disconnects the input terminal of logic detection circuit 126 from configuration pin 102 according to control signal EN_LB. In some embodiments, during the idle period, switch S3 disconnects the input of logic detection circuit 126 from configuration pin 102 according to control signal EN_LB; and during the initial setup (configuration vector detection) period, switch S3 connects the input of logic detection circuit 126 to configuration pin 102 according to control signal EN_LB.

In some embodiments, the internal pull-up resistor R1 and the internal pull-down resistor R0 are variable resistors, and the logic circuit 122 is used to generate and provide control signals ADJ_R1 and ADJ_R0 to the internal pull-up resistor R1 and the internal pull-down resistor R0, so as to control the resistance values of the internal pull-up resistor R1 and the internal pull-down resistor R0 respectively.

In some embodiments, logic detection circuit 126 detects logic value _VLL to logic circuit 122 based on the potential output of configuration pin 102, so that logic circuit 122 determines the configuration vector based on the output of logic detection circuit 126.

Please refer to Figures 2A through 2D, which are schematic diagrams illustrating vector detection operations 200, 201, 210, and 211 of a chip 110 supporting a two-bit configuration according to some embodiments of this disclosure. In some embodiments, the chip 110 of Figures 2A through 2D corresponds to the chip 110 of Figure 1. In the embodiments of Figures 2A through 2D, the chip 110 is adapted for a two-bit pin strapping configuration. In some embodiments, the two-bit pin strapping configuration allows four configurations (e.g., [00], [01], [10], and [11]).

In a binary configuration embodiment, the resistance value _RR1 of the internal pull-up resistor R1 and the resistance value _RR0 of the internal pull-down resistor R0 of chip 110 can be fixed at a resistance value _RA . In some embodiments, the configuration vector is a binary configuration vector that depends on the resistance value of the external resistor and the voltage of the reference voltage terminal connected to the external resistor. In the embodiments of Figures 2A to 2D, the resistance values of the external resistors Rext00, Rext01, Rext10, and Rext11 are each selected from two given resistance values (e.g., 1 kΩ and 128 kΩ), and the resistance values of the internal pull-down resistor R0 and the internal pull-up resistor R1 are within the range of the two given resistance values. In some embodiments, in a two-bit configuration, each of the external resistors Rext00 shown in Figure 2A and Rext10 shown in Figure 2C is an external pull-down resistor corresponding to external resistor Rext0, and each of the external resistors Rext01 shown in Figure 2B and Rext11 shown in Figure 2D is an external pull-up resistor corresponding to external resistor Rext1. In some embodiments, the resistance value _R00 of external resistor Rext00 and the resistance value _R01 of external resistor Rext01 can be implemented by a given resistance value less than the resistance value _RA , and the resistance values _R10 of external resistor Rext10 and _R11 of external resistor Rext11 can be implemented by another given resistance value greater than the resistance value _RA . Thus, by detecting whether the resistance value of the external resistor connected to the configuration pin 102 of the chip 110 is greater than or less than the resistance value _RA, and whether the external resistor is an external pull-up resistor electrically connected to the reference voltage terminal VDD _ext1 or an external pull-down resistor electrically connected to the reference voltage terminal VDD _ext0 , a two-bit configuration vector (e.g., [00], [01], [10] or [11]) can be detected.

As shown in Figure 2A, in the vector detection operation 200, an external resistor Rext00 electrically connects the configuration pin 102 of the chip 110 to the reference voltage terminal VDD _ext0 . In some embodiments, the vector detection operation 200 can configure the chip 110 with a configuration vector of [00].

In the zeroth step of vector detection operation 200, switches S0 and S1 disconnect the internal pull-down resistor R0 and internal pull-up resistor R1 from the configuration pin 102. Since the external resistor Rext00 connects the configuration pin 102 to the reference voltage terminal VDD _ext0 (e.g., 0 volts), the potential of the configuration pin 102 is pulled down (the external resistor Rext00 can be considered as an external pull-down resistor), and the logic detection circuit 126 outputs the zeroth detection logic value. When the external resistor Rext00 is an external pull-down resistor, the zeroth detection logic value is a low logic level _L.

In the first step of the vector detection operation 200, switch S0 disconnects the internal pull-down resistor R0 from the configuration pin 102, and switch S1 connects the internal pull-up resistor R1 (whose resistance value _RA is the same as R1's resistance value _RA ) to the configuration pin 102. Since the resistance value _R00 of the external resistor Rext00 is less than the resistance value _RA and the external resistor Rext00 connects the configuration pin 102 to the reference voltage terminal _VDDext0 (e.g., 0 volts), the potential of the configuration pin 102 is pulled down, and the logic detection circuit 126 outputs a first detection logic value (e.g., a low logic level _LL ).

In the second step of the vector detection operation 200, switch S1 disconnects the internal pull-up resistor R1 from the configuration pin 102, and switch S0 connects the internal pull-down resistor R0 (whose resistance value _RA is the same as R0's resistance value _RA ) to the configuration pin 102. At this time, external resistor Rext00 connects the configuration pin 102 to the reference voltage terminal _VDDext0 (e.g., 0 volts), which, together with the internal pull-down resistor R0, provides the pull-down function. Therefore, the potential of the configuration pin 102 is pulled down, and the logic detection circuit 126 outputs a second detection logic value (e.g., low logic level _LL ).

In some embodiments, if the external resistor Rext00 is an external pull-down resistor and the resistance value _R00 of the external resistor Rext00 is less than the resistance value _RA , the logic circuit 122 can obtain a triple ( _LL , _LL , _LL ) through the zeroth to the second step of the vector detection operation 200, as shown in Figure 2A. In some embodiments, the configuration vector of the triple ( _LL , _LL , _LL ) is defined as a first binary value, for example, 00. In some embodiments, the first binary value represents that the external resistor Rext00 is an external pull-down resistor and the external resistor Rext00 has a first given resistance value, and wherein the first given resistance value is less than the resistance values of the internal pull-up resistor R1 and the internal pull-down resistor R0 (for example, resistance value _RA ).

As shown in Figure 2B, in the vector detection operation 201, the external resistor Rext01 electrically connects the configuration pin 102 of the chip 110 to the reference voltage terminal VDD _ext1 . In some embodiments, the vector detection operation 201 can configure the chip 110 with the configuration vector of [01].

In the zeroth step of vector detection operation 201, switches S0 and S1 disconnect the internal pull-down resistor R0 and the internal pull-up resistor R1 from the configuration pin 102. Since the external resistor Rext01 connects the configuration pin 102 to the reference voltage terminal VDD _ext1 (e.g., 3.3 volts), the potential of the configuration pin 102 is pulled up (the external resistor Rext01 can be considered as an external pull-up resistor), and the logic detection circuit 126 outputs the zeroth detection logic value. When the external resistor Rext01 is an external pull-up resistor, the zeroth detection logic value is a high logic level _LH .

In the first step of the vector detection operation 201, switch S0 disconnects the internal pull-down resistor R0 from the configuration pin 102, and switch S1 connects the internal pull-up resistor R1 (whose resistance value _R is R_{_A}) to the configuration pin 102. At this time, external resistor Rext01 connects the configuration pin 102 to the reference voltage terminal VDD _ext1 (e.g., 3.3 volts), which, together with the internal pull-up resistor R1, provides the pull-up function. Therefore, the potential of the configuration pin 102 is pulled up, and the logic detection circuit 126 outputs the first detection logic value (e.g., high logic level L_{_H} ).

In the second step of the vector detection operation 201, switch S1 disconnects the internal pull-up resistor R1 from the configuration pin 102, and switch S0 connects the internal pull-down resistor R0 (whose resistance value _R0 is the same as the resistance value _RA ) to the configuration pin 102. Since the resistance value _R01 of the external resistor Rext01 is less than the resistance value _RA and the external resistor Rext01 connects the configuration pin 102 to the reference voltage terminal _VDDext1 (e.g., 3.3 volts), the potential of the configuration pin 102 is pulled up, and the logic detection circuit 126 outputs a second detection logic value (e.g., a high logic level _LH ).

In some embodiments, if the external resistor Rext01 is an external pull-up resistor and the resistance value _R01 of the external resistor Rext01 is less than the resistance value _RA , the logic circuit 122 can obtain a triple ( _LH , _LH , _LH ) through steps zero to two of the vector detection operation 201, as shown in Figure 2B. In some embodiments, the configuration vector of the triple ( _LH , _LH , _LH ) is defined as a second binary value, for example, 01. In some embodiments, the second binary value represents that the external resistor Rext01 is an external pull-up resistor and the external resistor Rext01 has a first given resistance value, and wherein the first given resistance value is less than the resistance values of the internal pull-up resistor R1 and the internal pull-down resistor R0 (for example, resistance value _RA ).

As shown in Figure 2C, in the vector detection operation 210, an external resistor Rext10 electrically connects the configuration pin 102 of the chip 110 to the reference voltage terminal VDD _ext0 . In some embodiments, the vector detection operation 210 can configure the chip 110 with the configuration vector of [10].

In the zeroth step of the vector detection operation 210, switches S0 and S1 disconnect the internal pull-down resistor R0 and the internal pull-up resistor R1 from the configuration pin 102. Since the external resistor Rext10 connects the configuration pin 102 to the reference voltage terminal VDD _ext0 (e.g., 0 volts), the potential of the configuration pin 102 is pulled down (the external resistor Rext10 can be regarded as an external pull-down resistor), and the logic detection circuit 126 outputs the zeroth detection logic value (e.g., low logic level _L ).

In the first step of the vector detection operation 210, switch S0 disconnects the internal pull-down resistor R0 from the configuration pin 102, and switch S1 connects the internal pull-up resistor R1 (whose resistance value _RA is the same as _R10 ) to the configuration pin 102. Since the resistance value _RA is less than the resistance value _R10 of the external resistor Rext10, and the internal pull-up resistor R1 connects the configuration pin 102 to the reference voltage terminal VDD _int1 (e.g., 3.3 volts), the potential of the configuration pin 102 is pulled up, and the logic detection circuit 126 outputs a first detection logic value (e.g., a high logic level _LH ).

In the second step of vector detection operation 210, switch S1 disconnects the internal pull-up resistor R1 from the configuration pin 102, and switch S0 connects the internal pull-down resistor R0 (whose resistance value R_{_R0} is the same as the resistance value R_{_A}) to the configuration pin 102. At this time, external resistor Rext10 connects the configuration pin 102 to the reference voltage terminal VDD_{_ext0} (e.g., 0 volts), and internal pull-down resistor R0 connects the configuration pin 102 to the reference voltage terminal VDD _{_int0} (e.g., 0 volts). Therefore, the potential of the configuration pin 102 is pulled down together, and logic detection circuit 126 outputs a second detection logic value (e.g., low logic level _LL ).

In some embodiments, if the external resistor Rext10 is an external pull-down resistor and the resistance value _R10 of the external resistor Rext10 is greater than the resistance value _RA , the logic circuit 122 can obtain a triple ( _LL , _LH , _LL ) through steps zero to two of the vector detection operation 210, as shown in Figure 2C. In some embodiments, the configuration vector of the triple ( _LL , _LH , _LL ) is defined as a third binary value, for example, 10. In some embodiments, the third binary value represents that the external resistor Rext10 is an external pull-down resistor and the external resistor Rext10 has a second given resistance value, and wherein the second given resistance value is greater than the resistance values (e.g., resistance value _RA ) of the internal pull-up resistor R1 and the internal pull-down resistor R0.

As shown in Figure 2D, in the vector detection operation 211, an external resistor Rext11 electrically connects the configuration pin 102 of the chip 110 to the reference voltage terminal VDD _ext1 . In some embodiments, the vector detection operation 211 can configure the chip 110 with the configuration vector of [11].

In the zeroth step of vector detection operation 211, switches S0 and S1 disconnect the internal pull-down resistor R0 and the internal pull-up resistor R1 from the configuration pin 102. Since the external resistor Rext11 connects the configuration pin 102 to the reference voltage terminal VDD _ext1 (e.g., 3.3 volts), the potential of the configuration pin 102 is pulled up (the external resistor Rext11 can be regarded as an external pull-up resistor), and the logic detection circuit 126 outputs the zeroth detection logic value (e.g., high logic level _LH ).

In the first step of vector detection operation 211, switch S0 disconnects the internal pull-down resistor R0 from the configuration pin 102, and switch S1 connects the internal pull-up resistor R1 (whose resistance value _R is R_{_A}) to the configuration pin 102. At this time, external resistor Rext11 connects the configuration pin 102 to the reference voltage terminal VDD _{_ext1} (e.g., 3.3 volts), and internal pull-up resistor R1 connects the configuration pin 102 to the reference voltage terminal VDD_{_int1} (e.g., 3.3 volts). Therefore, the potential of the configuration pin 102 is pulled up together, and logic detection circuit 126 outputs the first detection logic value (e.g., high logic level L_{_H} ).

In the second step of vector detection operation 210, switch S1 disconnects the internal pull-up resistor R1 from the configuration pin 102, and switch S0 connects the internal pull-down resistor R0 (whose resistance value _RA is the same as R0's resistance value _RA ) to the configuration pin 102. Since the resistance value _RA is less than the resistance value _R11 of the external resistor Rext11, and the internal pull-down resistor R0 connects the configuration pin 102 to the reference voltage terminal VDD _int0 (e.g., 0 volts), the potential of the configuration pin 102 is pulled down, and the logic detection circuit 126 outputs a second detection logic value (e.g., low logic level _LL ).

In some embodiments, if the external resistor Rext11 is an external pull-up resistor and the resistance value _R11 of the external resistor Rext11 is greater than the resistance value _RA , the logic circuit 122 can obtain a triple ( _LH , _LH , _LL ) through steps zero to two of the vector detection operation 211, as shown in Figure 2D. In some embodiments, the configuration vector of the triple ( _LH , _LH , _LL ) is defined as a fourth binary value, for example, 11. In some embodiments, the fourth binary value represents that the external resistor Rext11 is an external pull-up resistor and the external resistor Rext11 has a second given resistance value, and wherein the second given resistance value is greater than the resistance values of the internal pull-up resistor R1 and the internal pull-down resistor R0 (e.g., resistance value _RA ).

Thus, triplets can be obtained through vector detection operations 200, 201, 210 or 211, and binary values can be obtained based on triplets, thereby configuring chip 110 with a binary configuration vector.

Please refer to Figures 1 through 3. Figure 3 is a schematic diagram of the resistance values of the internal pull-up resistor R1, the internal pull-down resistor R0, and the external resistor Rext1 or Rext0 in a configuration detection system 100 supporting two-bit configuration according to some embodiments of this disclosure. In some embodiments, the resistance value _RR1 of the internal pull-up resistor R1 and the resistance value _RR0 of the internal pull-down resistor R0 are fixed to the resistance value _RA , and the resistance value _RA can be implemented with 32 kΩ. In some embodiments, the external resistor Rext1 is an external pull-up resistor (e.g., external resistors Rext01 and Rext11 in Figures 2B and 2D), and the external resistor Rext0 is an external pull-down resistor (e.g., external resistors Rext00 and Rext10 in Figures 2A and 2C). In some embodiments, the resistance value _R00 of external resistor Rext00 and the resistance value _R01 of external resistor Rext01 are implemented by a given resistance value less than the resistance value _RA (e.g., 1 kΩ), and the resistance value _R10 of external resistor Rext10 and the resistance value _R11 of external resistor Rext11 are implemented by a given resistance value greater than the resistance value _RA (e.g., 128 kΩ).

In some embodiments, the two-bit configuration vectors obtained by vector detection operations 200, 201, 210 and 211 based on Figure 1, Figures 2A to 2D and Figure 3 can be represented by the following Table 1. R ₀₀ (1kΩ) R ₀₁ (1kΩ) R ₁₀ (128kΩ) R ₁₁ (128kΩ) Step Zero L _L L _H L _L L _H First step L _L L _H L _H L _H Step 2 L _L L _H L _L L _L Two bits 00 01 10 11 Table 1

Please refer to Figures 4A and 4B, which are schematic diagrams of vector detection operations 400a and 400b of a chip 110 supporting multi-bit configuration according to some embodiments of this disclosure. In some embodiments, the chip 110 of Figures 4A and 4B is adapted to a multi-bit pin strapping configuration. In some embodiments, the multi-bit pin strapping configuration allows at least eight configurations of three bits (e.g., [000], [001], [010], [011], [100], [101], [110], and [111]).

In a multi-bit configuration embodiment, the internal pull-up resistor R1 and internal pull-down resistor R0 of chip 110 are variable resistors, and the resistance values _{RR1 and RR0} of the internal pull-up resistor R1 and internal pull-down resistor _R0 can be adjusted to a plurality of preset resistance values. In some embodiments, the configuration vector is a multi-bit configuration vector that depends on the resistance value of the external resistor and the voltage of the reference voltage terminal connected to the external resistor. In the embodiments of Figures 4A to 4B, the resistance values of the external resistors Rpd and Rpu are selected from one of a plurality of given resistance values, wherein the plurality of given resistance values are 250 ohms, 4 kiloohms, 64 kiloohms, and 1 megaohm. In some embodiments, the resistance values of external resistors Rpd and Rpu are selected from one of a plurality of given resistance value ranges, wherein the plurality of preset resistance values and the plurality of given resistance value ranges are alternately configured, and wherein the upper limit of the largest of the plurality of given resistance value ranges is less than the largest of the plurality of preset resistance values. In some embodiments, the center values of the plurality of given resistance value ranges are 250 ohms, 4 kiloohms, 64 kiloohms, and 1 megaohm, respectively. In some embodiments, the external resistor Rpd in Figure 4A corresponds to the external resistor Rext0 in Figure 1, and the external resistor Rpu in Figure 4B corresponds to the external resistor Rext1 in Figure 1. Thus, by detecting whether the resistance value of the external resistor connected to the configuration pin 102 of the chip 110 is greater than or less than the preset resistance value of the plurality of internal pull-up or pull-down resistors, and whether the external resistor is an external pull-up resistor or an external pull-down resistor, a multi-bit configuration vector can be generated.

As shown in Figure 4A, in vector detection operation 400a, an external resistor Rpd electrically connects the configuration pin 102 of chip 110 to the reference voltage terminal VDD _ext0 . In some embodiments, vector detection operation 400a can configure chip 110 with any of the configuration vectors [000], [010], [100] and [110].

In the zeroth step of the vector detection operation 400a, switches S0 and S1 disconnect the internal pull-down resistor R0 and the internal pull-up resistor R1 from the configuration pin 102. Since the external resistor Rpd connects the configuration pin 102 to the reference voltage terminal VDD _ext0 (e.g., 0 volts), the potential of the configuration pin 102 is pulled down (the external resistor Rpd can be regarded as an external pull-down resistor), and the logic detection circuit 126 outputs a low logic level _LL .

In some embodiments, when switches S0 and S1 disconnect the internal pull-down resistor R0 and internal pull-up resistor R1 from the configuration pin 102, and the logic detection circuit 126 outputs a low logic level _LL , it can be determined that the external resistor connected to the configuration pin 102 is an external pull-down resistor. Furthermore, in subsequent operations, the configuration vector can be determined based on the adjusted resistance value of the internal pull-up resistor R1. Therefore, in subsequent operations, the connection between the internal pull-up resistor R1 and the configuration pin 102 can be maintained, and the open circuit between the internal pull-down resistor R0 and the configuration pin 102 can be maintained.

In some embodiments, when switch S1 connects the internal pull-up resistor R1 to the configuration pin 102 and switch S0 disconnects the internal pull-down resistor R0 from the configuration pin 102, if the resistance value _R1 of the internal pull-up resistor R1 is _less than the resistance value _Rpd of the external resistor Rpd, the potential of the configuration pin 102 is pulled up, and the logic detection circuit 126 outputs a high logic level _LH .

Next, the resistance value _RA1 of the internal pull-up resistor R1 is adjusted to the preset resistance value _RA2 . If the preset resistance value _RA2 is less than the resistance value _Rpd of the external resistor Rpd, the potential of the configuration pin 102 is pulled up, and the logic detection circuit 126 outputs a high logic level _LH .

In some embodiments, the resistance value R_R1 of the internal pull-up resistor R_₁ is gradually adjusted/increased by a plurality of preset resistance values to the resistance value R _{_An} until the logic detection circuit 126 outputs a low logic level _LL . In some embodiments, the low logic level _LL output by the logic detection circuit 126 represents that the resistance value R_{_An} is greater than the resistance value R_{_Rpd} of the external resistor R_{_pd}, causing the potential of the configuration pin 102 to be pulled down.

Thus, if the external resistor Rpd is an external pull-down resistor, through vector detection operation 400a, logic circuit 122 can obtain the configuration vector corresponding to the (n+1) tuple ( _LL , _LH ... _LH , _LL ), as shown in Figure 4A. In some embodiments, based on the adjusted resistance value _RAn of the internal pull-up resistor R1 corresponding to the (n+1) tuple/logic level, the range where the resistance value _RRpd of the external resistor Rpd is located can be obtained (e.g., the upper and lower bounds of this range/boundary). Therefore, the configuration vector is determined based on the range where the resistance value _RRpd of the external resistor _Rpd is located, thereby configuring the function or behavior of chip 110. In some embodiments, the multi-bit configuration vectors obtained by the vector detection operation 400a based on Figure 4A can be represented by Table 2 below. R _Rpd 250Ω 4kΩ 64kΩ 1MΩ Step Zero L _L L _L L _L L _L R _R1 = 1kΩ L _L L _H L _H L _H R _R1 = 16kΩ X L _L L _H L _H R _R1 = 256kΩ X X L _L L _H R _R1 = 4MΩ X X X L _L Three-dimensional 000 010 100 110 Table 2

In some embodiments, the resistance values of 1kΩ, 16kΩ, 256kΩ and 4MΩ are the upper limits of the given resistance values of the external pull-down resistor _Rpd, which are 250Ω, 4kΩ, 64kΩ and 1MΩ, respectively.

As shown in Figure 4B, in the vector detection operation 400b, an external resistor Rpu electrically connects the configuration pin 102 of the chip 110 to the reference voltage terminal VDD _ext1 . In some embodiments, the vector detection operation 400b can configure the chip 110 with any of the configuration vectors [001], [011], [101], and [111].

In step zero of the vector detection operation 400b, switches S0 and S1 disconnect the internal pull-down resistor R0 and the internal pull-up resistor R1 from the configuration pin 102. Since the external resistor Rpu connects the configuration pin 102 to the reference voltage terminal VDD _ext1 (e.g., 3.3 volts), the potential of the configuration pin 102 is pulled up (the external resistor Rpu can be regarded as an external pull-up resistor), and the logic detection circuit 126 outputs a high logic level _LH .

In some embodiments, when switches S0 and S1 disconnect the internal pull-down resistor R0 and internal pull-up resistor R1 from the configuration pin 102, and the logic detection circuit 126 outputs a high logic level _LH , it can be determined that the external resistor connected to the configuration pin 102 is an external pull-up resistor. Furthermore, in subsequent operations, the configuration vector can be determined based on the adjusted resistance value of the internal pull-down resistor R0. Therefore, in subsequent operations, the connection between the internal pull-down resistor R0 and the configuration pin 102 can be maintained, and the connection between the internal pull-up resistor R1 and the configuration pin 102 can be kept open.

In some embodiments, when switch S0 connects the internal pull-down resistor R0 to the configuration pin 102 and switch S1 disconnects the internal pull-up resistor R1 from the configuration pin 102, if the resistance value _R0 of the internal pull-down resistor R0 is less than the resistance value _Rpu of the external resistor Rpu (the default resistance value R1 ₎ , the potential of the configuration pin 102 is pulled down, and the logic detection circuit 126 outputs a low logic level _LL .

Next, the resistance value _RA0 of the internal pull-down resistor R0 is adjusted to the preset resistance value _RA2 . If the preset resistance value _RA2 is less than the resistance value _RApu of the external resistor Rpu, the potential of the configuration pin 102 is pulled down, and the logic detection circuit 126 outputs a low logic level _LL .

In some embodiments, the internal pull-down resistor R0 is gradually adjusted/increased by a plurality of preset resistance values to _{a resistance value RAn ,} until the logic detection circuit 126 outputs a high logic level _LH . In some embodiments, the high logic level _LH output by the logic detection circuit 126 represents that the resistance value _RAn is greater than the resistance value _RRpu of the external resistor Rpu, causing the potential of the configuration pin 102 to be pulled up.

Thus, if the external resistor Rpu is an external pull-up resistor, through vector detection operation 400b, logic circuit 122 can obtain the configuration vector corresponding to the (n+1) tuple (L _H , _LL ... _LL , L _H ), as shown in Figure 4B. In some embodiments, based on the adjusted resistance value R _An of the internal pull-down resistor R0 corresponding to the (n+1) tuple/logic level, the range where the resistance value R _Rpu of the external resistor Rpu is located can be obtained (e.g., the upper and lower bounds of this range/boundary). The configuration vector is then determined based on the range where the resistance value of the external resistor Rpu is located, thereby configuring the function or behavior of chip 110. In some embodiments, the multi-bit configuration vectors obtained by the vector detection operation 400b based on graph 4B can be represented by Table 3 below. R _Rpu 250Ω 4kΩ 64kΩ 1MΩ Step Zero L _H L _H L _H L _H R _R0 = 1kΩ L _H L _L L _L L _L R _R0 = 16kΩ X L _H L _L L _L R _R0 = 256kΩ X X L _H L _L R _R0 = 4MΩ X X X L _H Three-dimensional 001 011 101 111 Table 3

In some embodiments, the resistance values 1kΩ, 16kΩ, 256kΩ, and 4MΩ are the upper bounds of the given resistance values 250Ω, 4kΩ, 64kΩ, and 1MΩ, respectively, where any one of the given resistance values 250Ω, 4kΩ, 64kΩ, and 1MΩ can be the resistance value R _{_pu} of the external pull-up resistor. Thus, the multi-bit configuration vector can be obtained according to Tables 2 and 3 above.

In some embodiments, the configuration detection circuit 120 is further used to progressively adjust the resistance value _RR1 of the internal pull-up resistor R1 and the resistance value _RR0 of the internal pull-down resistor R0 to a plurality of preset resistance values (e.g., preset resistance values _RA1 ~ _RAN ). Under these plurality of preset resistance values, the internal pull-up resistor R1 and the internal pull-down resistor R0 are sequentially connected to the configuration pin 102 so that the logic detection circuit 126 outputs the plurality of detection logic values and determines the configuration vector based on the plurality of detection logic values (and the zeroth detection logic value). In some embodiments, if pin 102 is configured to connect to an external resistor Rpd, the output of the logic detection circuit 126 can be represented by Table 4 below based on the above method. R _Rpd 250Ω 4kΩ 64kΩ 1MΩ Step Zero L _L L _L L _L L _L Internal pull-up resistor (R _R1 = 1kΩ) L _L L _H L _H L _H Internal pull-down (R _R0 = 1kΩ) L _L L _L L _L L _L Internal pull-up resistor (R _R1 = 16kΩ) X L _L L _H L _H Internal pull-down resistor (R _R0 = 16kΩ) X L _L L _L L _L Internal pull-up resistor (R _R1 = 256kΩ) X X L _L L _H Internal pull-down resistor (R _R0 = 256kΩ) X X L _L L _L Internal pull-up resistor (R _R1 = 4MΩ) X X X L _L Internal pull-down resistor (R _R0 = 4MΩ) X X X X Three-dimensional 000 010 100 110 Table 4

In some embodiments, if pin 102 is configured to connect to an external resistor Rpu, the output of the logic detection circuit 126 can be represented by Table 5 below based on the above method. R _Rpu 250Ω 4kΩ 64kΩ 1MΩ Step Zero L _H L _H L _H L _H Internal pull-up (R _R1 = 1kΩ) L _H L _H L _H L _H Internal pull-down (R _R0 = 1kΩ) L _H L _L L _L L _L Internal pull-up resistor (R _R1 = 16kΩ) X L _H L _H L _H Internal pull-down resistor (R _R0 = 16kΩ) X L _H L _L L _L Internal pull-up resistor (R _R1 = 256kΩ) X X L _H L _H Internal pull-down resistor (R _R0 = 256kΩ) X X L _H L _L Internal pull-up resistor (R _R1 = 4MΩ) X X X L _H Internal pull-down resistor (R _R0 = 4MΩ) X X X L _H Three-dimensional 001 011 101 111 Table 5

In some embodiments, when the external resistor is disconnected from configuration pin 102 (i.e., configuration pin 102 is not connected to any external resistor) and configuration pin 102 is a floating pin, configuration detection circuit 120 determines that the configuration vector is a preset value based on the plurality of detection logic values. For example, if configuration pin 102 is not connected to any external resistor, the resistance value of configuration pin 102 is infinitely large, exceeding the largest of the preset resistance values of internal pull-up resistor R1 and/or internal pull-down resistor R0. In this case, the output of logic detection circuit 126 can be represented by Table 6 below. The configuration pins are not connected to any external resistors. Step Zero X Internal pull-up (R _R1 = 1kΩ) L _H Internal pull-down (R _R0 = 1kΩ) L _L Internal pull-up resistor (R _R1 = 16kΩ) L _H Internal pull-down resistor (R _R0 = 16kΩ) L _L Internal pull-up resistor (R _R1 = 256kΩ) L _H Internal pull-down resistor (R _R0 = 256kΩ) L _L Internal pull-up resistor (R _R1 = 4MΩ) L _H Internal pull-down resistor (R _R0 = 4MΩ) L _L Configuration Vector default value Table 6

In this way, by not connecting any external resistors to configuration pin 102, a larger set of configuration vectors (e.g., default values) can be configured, thereby reducing material costs.

Please refer to Figures 1, 4A to 4B, and 5. Figure 5 is a schematic diagram of the resistance values _RR1 of the internal pull-up resistor R1, _RR0 of the internal pull-down resistor R0, _RRpu of the external resistor Rpu, and RRpd of the external resistor _Rpd in a configuration detection system ₁₀₀ supporting multi-bit configuration according to some embodiments of this disclosure. In some embodiments, the internal pull-up resistor R1 and the internal pull-down resistor R0 are variable resistors. In some embodiments, the resistance value _RR1 of the internal pull-up resistor R1 can be maintained at a fixed value or change over time. In some embodiments, the resistance value _RR1 of the internal pull-up resistor R1 is a variable, which can be at least one of a plurality of preset resistance values _RA1 to _RA4 . In some embodiments, the resistance value _RR1 of the internal pull-up resistor R1 can vary within a range between a minimum and a maximum value, said range including a plurality of preset resistance values _RA1 to _RA4 . In some embodiments, the resistance value _RR0 of the internal pull-down resistor R0 can be maintained at a fixed value or vary over time. In some embodiments, the resistance value _RR0 of the internal pull-down resistor R0 is a variable, which can be at least one of a plurality of preset resistance values _RA1 to _RA4 . In some embodiments, the resistance value _RR0 of the internal pull-down resistor R0 can vary within a range between a minimum and a maximum value, said range including a plurality of preset resistance values _RA1 to _RA4 . In some embodiments, the external resistor Rext1 is an external pull-up resistor (e.g., the external resistor Rpu in Figure 4B), and the external resistor Rext0 is an external pull-down resistor (e.g., the external resistor Rpd in Figure 4A). In some embodiments, the resistance value _RRpu of the external resistor Rpu is selected from one of a plurality of given resistance values, and each of the plurality of given resistance values is selected from a corresponding range of given resistance values (as shown in the dashed box in Figure 5). In some embodiments, the resistance value _RRpd of the external resistor Rpd is selected from one of a plurality of given resistance values, and each of the plurality of given resistance values is selected from a corresponding range of given resistance values (as shown in the dashed box in Figure 5). In some embodiments, the plurality of given resistance values (e.g., 250 ohms, 4K ohms, 64K ohms and 1M ohms) and the plurality of given resistance value ranges (such as the numerical range in the dashed box shown in Figure 5) are interleaved with the aforementioned preset resistance values, so that the preset resistance values can respectively become the boundaries of the given resistance values (e.g., the upper and/or lower boundaries of the boundary/range).

Please refer to Figure 6, which is a flowchart of a method 600 for detecting the configuration vector of a chip 110 according to some embodiments of this disclosure. In some embodiments, the detection method 600 includes steps S610 to S660. In some embodiments, steps S610 to S660 can be performed by the configuration detection circuit 120. In some embodiments, the configuration detection circuit 120 can perform steps S610 to S660 through hardware and/or software; this invention is not limited to these.

In step S610, during the idle period, control signals are provided according to the function mode.

In step S620, during the initial setup period, disconnect the output driver from the configuration pin and connect the logic detection circuit to the configuration pin.

In step S630, set or adjust the resistance value of the internal resistor, and set or adjust the connection between the internal resistor and the configuration pin.

In step S640, the detection logic value corresponding to the potential of the configuration pin is detected and recorded.

In step S650, determine whether sufficient information has been collected to determine the configuration vector. If yes, proceed to step S660; otherwise, proceed to step S630.

In step S660, latch the configuration vector.

In summary, the chip 110 of this disclosure can be configured with a single configuration pin 102 in a two-bit or multi-bit configuration vector, thereby reducing the number of chip pins and lowering material costs.

In the multi-bit configuration embodiment, if the internal pull-up resistor R1 of chip 110 is absent or disconnected, this condition is electrically equivalent to the resistance value _RR1 of the internal pull-up resistor R1 being extremely large (or infinitely large). At this time, the resistance value _RR0 of the internal pull-down resistor R0, along with the external resistor Rext1 corresponding to the resistor Rpu in Figure 4B, is detected. Referring to the steps/operations in the aforementioned Table 3 embodiment, the results shown in Table 7 below can be obtained. In this case, the external resistor Rext0 is not needed, and the resistance value of the external resistor Rext0 is equivalent to being extremely large (or infinitely large). A binary configuration can still be obtained under this condition. Therefore, the absence of the internal pull-up resistor R1 and the external resistor Rext0 is a special case and within the scope of this disclosure. R _Rpu 250Ω 4kΩ 64kΩ 1MΩ Step Zero L _H L _H L _H L _H R _R0 = 1kΩ L _H L _L L _L L _L R _R0 = 16kΩ X L _H L _L L _L R _R0 = 256kΩ X X L _H L _L R _R0 = 4MΩ X X X L _H Two bits 00 01 10 11 Table 7

In the multi-bit configuration embodiment, if the internal pull-down resistor R0 of chip 110 is absent or disconnected, this condition is electrically equivalent to the resistance value _RR0 of the internal pull-down resistor being extremely large (or infinitely large). At this time, the resistance value _RR1 of the internal pull-up resistor R1, along with the external resistor Rext0 corresponding to the resistor Rpd in Figure 4A, is detected. Referring to the steps/operations in the aforementioned Table 2 embodiment, the results shown in Table 8 are obtained. In this case, the external resistor Rext1 is not needed, and the resistance value of the external resistor Rext1 is equivalent to being extremely large (or infinitely large). A binary configuration can still be obtained under this condition. Therefore, the absence of the internal pull-down resistor R0 and the external resistor Rext1 is a special case and within the scope of this disclosure. R _Rpd 250Ω 4kΩ 64kΩ 1MΩ Step Zero L _L L _L L _L L _L R _R1 = 1kΩ L _L L _H L _H L _H R _R1 = 16kΩ X L _L L _H L _H R _R1 = 256kΩ X X L _L L _H R _R1 = 4MΩ X X X L _L Two bits 00 01 10 11 Table 8

Although in the embodiments disclosed herein, the configuration detection circuit 120 can control the switch S3 to be connected or disconnected, connecting the input terminal of the logic detection circuit 126 to the configuration pin 102, or disconnecting the input terminal of the logic detection circuit 126 from the configuration pin 102. However, in practice, it can be designed so that the input terminal of the logic detection circuit 126 is always connected to the configuration pin 102, in which case the circuit controlling the switch S3 is not present, or the switch S3 is always connected. In this case, the configuration detection circuit 120 does not need to control the connection or disconnection of the switch S3, and configuration detection is not hindered. Therefore, the description of the existence and function of switch S3 and the configuration of detection circuit 120 to control switch S3 in the embodiments disclosed herein are not intended to limit this disclosure.

Although in the embodiments disclosed herein, the configuration detection circuit 120 can control the switch S2 to be connected or disconnected, so that the output terminal of the output driver 124 is connected or disconnected from the configuration pin 102, in practice, according to the definition and functional requirements of the configuration pin 102, the output driver 124 or other circuits that would cause a resistive load to the configuration pin 102 may not exist, or the output terminal of the output driver 124 may always be disconnected from the configuration pin 102 by design. In this case, the configuration detection circuit 120 does not need to control the connection or disconnection of the switch S2, and configuration detection is not hindered. Therefore, the description of the existence and function of the output driver 124 and the switch S2, and the configuration of the detection circuit 120 to control the switch S2 in the embodiments disclosed herein, are not intended to limit this disclosure.

Referring to the description of the vector detection operation 400a in the aforementioned embodiment, when the resistance value _RR1 of the internal pull-up resistor R1 is equal to the maximum preset resistance value _RA4 , the resistance value _RR1 of the internal pull-up resistor R1 is greater than every given resistance value of the external resistor Rpd. When the logic detection circuit 126 outputs a low logic level _LL , it can be determined that the external resistor connected to the configuration pin 102 is an external pull-down resistor. Therefore, when the resistance value of the internal pull-up resistor R1 is set to the maximum preset resistance value, and this maximum preset resistance value is greater than every given resistance value of the external resistor Rpd, the output of the logic detection circuit 126 is equivalent to the result of step zero, as shown in Table 9 below. R _Rpd 250Ω 4kΩ 64kΩ 1MΩ Step Zero L _L L _L L _L L _L R _R1 = 4MΩ L _L L _L L _L L _L Table 9

Referring to the description of the vector detection operation 400b in the aforementioned embodiment, when the resistance value _RR0 of the internal pull-down resistor R0 is equal to the maximum preset resistance value _RA4 , the resistance value _RR0 of the internal pull-down resistor R0 is greater than every given resistance value of the external resistor Rpu. When the logic detection circuit 126 outputs a high logic level _LH , it can be determined that the external resistor connected to the configuration pin 102 is an external pull-up resistor. Therefore, when the resistance value of the internal pull-down resistor R0 is set to the maximum preset resistance value, and this maximum preset resistance value is greater than every given resistance value of the external resistor Rpu, the output of the logic detection circuit 126 is equivalent to the result of step zero, as shown in Table 10 below. R _Rpu 250Ω 4kΩ 64kΩ 1MΩ Step Zero L _H L _H L _H L _H R _R0 = 4MΩ L _H L _H L _H L _H Table 10

Although this disclosure has been made in practice as described above, it is not intended to limit this disclosure. Anyone skilled in the art may make various modifications and alterations without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the scope of the appended patent application.

To make the above and other objects, features, advantages and embodiments of this disclosure more apparent, the symbols are explained as follows: 100: Configuration detection system; 102: Configuration pin; 110: Chip; 120: Configuration detection circuit; 122: Logic circuit; 124: Output driver; 126: Logic detection circuit; 200, 201, 210, 211, 400a, 400b: Vector detection operation; 600: Detection method; R0, R1, Rpd, Rpu: Resistors; S0, S1, S2, S3: Switches; _VLL : Detection logic value; _LH : High logic level; _LL : Low logic level; ADJ_R0, ADJ_R1: Control signals; EN_R0, EN_R1, EN_OD, EN_LB: Control signal VDD _int1 , VDD _ext1 , VDD _int0 , VDD _ext0 : Reference voltage terminals Rext0, Rext1: External resistors Rext00, Rext01, Rext10, _Rext11 : External resistors _RR1 , _RR0 , _RA , R00, _{R01, R10 , R11} : Resistance values _RA1 , _RA2 , _{RA3 , RA4} , RAAn, Rpd, _Rpu , _RRpd , _RRpu : Resistance values S610, S620, S630 _, S640, S650, S660: Steps

To make the above and other objects, features, advantages, and embodiments of this disclosure more apparent, the accompanying drawings are explained as follows: Figure 1 is a schematic diagram of a configuration detection system according to an embodiment of this disclosure. Figures 2A to 2D are schematic diagrams of vector detection operation of a chip supporting two-bit configuration according to some embodiments of this disclosure. Figure 3 is a schematic diagram of the resistance values of the internal pull-up resistor, internal pull-down resistor, and external resistor in a configuration detection system supporting two-bit configuration according to some embodiments of this disclosure. Figures 4A and 4B are schematic diagrams of vector detection operation of a chip supporting multi-bit configuration according to some embodiments of this disclosure. Figure 5 is a schematic diagram of the resistance values of the internal pull-up resistor, internal pull-down resistor, and external resistor in a configuration detection system supporting multi-bit configuration according to some embodiments of this disclosure. Figure 6 is a flowchart of a method for detecting the configuration vector of a chip according to some embodiments of this disclosure.

Domestic Storage Information (Please record in order of storage institution, date, and number) None International Storage Information (Please record in order of storage country, institution, date, and number) None

100: Configure the detection system

102: Configure headers

110: Chip

120: Configure the detection circuit

122: Logic Circuits

124: Output Driver

126: Logic Detection Circuit

R0, R1: Resistors Practice resistors ...

Rext0, Rext1: External resistors

S0, S1, S2, S3: Switches

_VLL : Detection logic value

ADJ_R0, ADJ_R1: Control signals

EN_R0, EN_R1, EN_OD, EN_LB: Control signals

VDD _int1 , VDD _ext1 , VDD _int0 , VDD _ext0 : Reference voltage terminals

Claims (10)

A chip includes: a configuration pin electrically connected to a reference voltage terminal via an external resistor; an internal pull-up resistor; an internal pull-down resistor; a logic detection circuit; and a configuration detection circuit electrically connected to the configuration pin, the internal pull-up resistor, the internal pull-down resistor, and the logic detection circuit, wherein the configuration detection circuit is used to connect an input terminal of the logic detection circuit to the configuration pin, and wherein the configuration detection circuit is further used to: disconnect the internal pull-up resistor and the internal pull-down resistor from the configuration pin, so that the logic detection circuit outputs a zeroth detection logic value; The internal pull-up resistor and the internal pull-down resistor are sequentially connected to the configuration pin so that the logic detection circuit outputs a plurality of detection logic values; and a configuration vector is determined based on the zeroth detection logic value and the plurality of detection logic values. The chip as described in claim 1, wherein a resistance value of the external resistor is selected from one of two given resistance values, and wherein a resistance value of the internal pull-up resistor and the internal pull-down resistor is within the range of the two given resistance values. The chip as described in claim 1, wherein the configuration vector is a two-bit configuration vector that depends on a resistance value of the external resistor and the voltage of the reference voltage terminal. The chip as described in claim 3, wherein the configuration detection circuit is further configured to: connect the internal pull-up resistor to the configuration pin to cause the logic detection circuit to output a first detection logic value; and connect the internal pull-down resistor to the configuration pin to cause the logic detection circuit to output a second detection logic value, wherein if the zeroth detection logic value, the first detection logic value, and the second detection logic value are, in sequence, a low logic level, a low logic level, and a low logic level, the configuration vector is a first binary value; If the zeroth detection logic value, the first detection logic value, and the second detection logic value are, in sequence, a high logic level, a high logic level, and a high logic level, the configuration vector is a second binary value; if the zeroth detection logic value, the first detection logic value, and the second detection logic value are, in sequence, a low logic level, a high logic level, and a low logic level, the configuration vector is a third binary value; and If the zeroth detection logic value, the first detection logic value, and the second detection logic value are, in sequence, the high logic level, the high logic level, and the low logic level, the configuration vector is a fourth binary value. The chip as described in claim 4, wherein: the first binary value represents that the external resistor is an external pull-down resistor and the external resistor has a first given resistance value, and wherein the first given resistance value is less than the resistance values of the internal pull-up resistor and the internal pull-down resistor; the second binary value represents that the external resistor is an external pull-up resistor and the external resistor has the first given resistance value; the third binary value represents that the external resistor is the external pull-down resistor and the external resistor has a second given resistance value, and wherein the second given resistance value is greater than the resistance values of the internal pull-up resistor and the internal pull-down resistor; and the fourth binary value represents that the external resistor is the external pull-up resistor and the external resistor has the second given resistance value. The chip as described in claim 1, wherein the internal pull-up resistor and the internal pull-down resistor are variable resistors, and wherein the configuration detection circuit is further configured to: progressively adjust the resistance values of the internal pull-up resistor and the internal pull-down resistor to a plurality of preset resistance values, sequentially connect the internal pull-up resistor and the internal pull-down resistor to the configuration pin at the plurality of preset resistance values, so that the logic detection circuit outputs the plurality of detection logic values, and determine the configuration vector based on the plurality of detection logic values. The chip as described in claim 6, wherein the configuration vector is a multi-bit configuration vector that depends on a resistance value of the external resistor and a voltage of the reference voltage terminal. The chip as described in claim 7, wherein the resistance value of the external resistor is selected from one of a plurality of given resistance value ranges, wherein the plurality of preset resistance values and the plurality of given resistance value ranges are interleaved, and wherein the upper limit of the largest of the plurality of given resistance value ranges is less than the largest of the plurality of preset resistance values. A chip includes: a configuration pin electrically connected to a reference voltage terminal via an external resistor; an internal pull-up resistor; an internal pull-down resistor; a logic detection circuit; and a configuration detection circuit electrically connected to the logic detection circuit, the internal pull-up resistor, and the internal pull-down resistor, wherein the internal pull-up resistor and the internal pull-down resistor are variable resistors, and wherein the configuration detection circuit is used to: The resistance values of the internal pull-up resistor and the internal pull-down resistor are gradually adjusted to a plurality of preset resistance values. Under the plurality of preset resistance values, the internal pull-up resistor and the internal pull-down resistor are sequentially connected to the configuration pin so that the digital logic detection circuit outputs a plurality of detection logic values, and a configuration vector is determined based on the plurality of detection logic values. The chip as described in claim 9, wherein a resistance value of the external resistor is selected from one of a plurality of given resistance values, wherein the plurality of preset resistance values and the values of the plurality of given resistance values are interleaved, and wherein the largest of the plurality of given resistance values is less than the largest of the plurality of preset resistance values.