TWI902585B - Three-dimensional coarse-particle reconfigurable array construction system and control method of three-dimensional coarse-particle reconfigurable array construction system - Google Patents

Abstract

The present disclosure provides a three-dimensional coarse-grained reconfigurable array architecture system and its control method. The system includes multiple first arrays and multiple second arrays, wherein each first array includes multiple first processing elements, multiple first storage units, and multiple first switches, and each second array includes multiple second processing elements, multiple second storage units, and multiple second switches. The system employs an interleaved stacking arrangement for the first arrays and second arrays, and dynamically manages the activation and deactivation states of various units through a configuration controller to execute neural network model computation tasks. The technical solution of the present disclosure can significantly improve data transmission efficiency, increase resource utilization flexibility, and achieve optimal allocation of hardware resources.

Description

Three-dimensional coarse-grained reconfigurable array architecture system and its control method

This invention relates to a processor hardware architecture, and more particularly to a three-dimensional hardware architecture system based on a coarse-grained reconfigurable array (CGRA) processor and its control method.

With the rapid development of artificial intelligence technology, especially in the fields of machine learning and deep learning, higher performance and flexibility requirements are being placed on processor hardware architecture. Traditional processor architectures, such as central processing units (CPUs) and graphics processing units (GPUs), may encounter performance bottlenecks and energy consumption problems when faced with large-scale parallel computing and frequent data access.

To address these challenges, researchers have proposed various domain-specific architectures (DSAs) and reconfigurable hardware architectures. Among them, coarse-grained reconfigurable architecture (CGRA) processors have attracted widespread attention due to their flexibility and energy efficiency advantages. CGRAs typically consist of a large number of processing elements (PEs) and interconnected networks, allowing for dynamic adjustments to hardware configurations based on the needs of different applications, thus achieving efficient parallel computing.

However, most current CGRA architectures use a 2D mesh topology, which simplifies the interconnection between processing units, primarily transmitting data in the four adjacent directions (up, down, left, and right). This architecture may suffer from inefficient data access and low utilization of processing units when handling applications with complex data dependencies.

To address the aforementioned technical issues, this disclosure proposes a three-dimensional coarse-grained reconfigurable array architecture system and its control method. The architecture of this disclosure includes staggered stacked computation and storage arrays, achieving more efficient neural network computation through vertical interconnection and a flexible resource allocation mechanism.

One or more embodiments of this disclosure provide a three-dimensional coarse-grained reconfigurable array architecture system for implementing a neural network model. The three-dimensional coarse-grained reconfigurable array architecture system includes: a plurality of first arrays, wherein each first array includes: a plurality of first computation units for performing neural network computation tasks for corresponding nodes of the neural network model; a plurality of first storage units for storing data of the corresponding neural network computation tasks, wherein the number of the plurality of first computation units in each first array is greater than the number of the plurality of first storage units; and a plurality of... First switches, used to perform corresponding routing tasks, wherein each first switch is not directly connected to each other, wherein the plurality of first computation units, the plurality of first storage units, and the plurality of first switches are distributed on the array plane of the first array; a plurality of second arrays, wherein each second array includes: a plurality of second computation units, used to perform neural network computation tasks for corresponding nodes of the neural network model; a plurality of second storage units; A unit for storing data for a corresponding neural network computation task, wherein the number of the plurality of second storage units is greater than the number of the plurality of second computation units; and a plurality of second switches for performing corresponding routing tasks, wherein each second switch is not directly connected to each other, wherein the plurality of second computation units, the plurality of second storage units, and the plurality of second switches are distributed on the array plane of the second array; an input/ An output interface for receiving input data and transmitting processing results; a configuration controller electrically connected to the plurality of first arrays and the plurality of second arrays, wherein each first array and each second array are stacked alternately, wherein the array adjacent to each first array in the vertical direction corresponding to the array plane is a second array, and the array adjacent to each second array in the vertical direction corresponding to the array plane is a first array. The configuration controller is used to: monitor the working status of the plurality of first arrays and the plurality of second arrays; and dynamically manage the enabling and disabling of the plurality of first computation units, the plurality of first storage units, the plurality of first switches, the plurality of second storage units, the plurality of second computation units, and the plurality of second switches according to the computation graph information corresponding to the neural network model, so as to execute the plurality of neural network computation tasks of the neural network model.

One or more embodiments of this disclosure provide a control method for a three-dimensional coarse-grained reconfigurable array architecture system, wherein the three-dimensional coarse-grained reconfigurable array architecture system is used to implement a neural network model. The method includes: monitoring the operating status of a plurality of first arrays and a plurality of second arrays of the three-dimensional coarse-grained reconfigurable array architecture system via a configuration controller, wherein each first array includes: a plurality of first computation units for performing neural network computation tasks corresponding to nodes of the neural network model; a plurality of first storage units for storing data of the corresponding neural network computation tasks, wherein the number of the plurality of first computation units in each first array is greater than the number of the plurality of first storage units; and a plurality of first slices. Each first switch is not directly connected to the others, and the plurality of first computation units, the plurality of first storage units, and the plurality of first switches are distributed on the array plane of the first array; wherein each second array includes: a plurality of second computation units for performing neural network computation tasks for the corresponding nodes of the neural network model; and a plurality of second storage units for storing data for the corresponding neural network computation tasks, wherein the number of the plurality of second storage units is greater than the number of the first array. The system comprises: a plurality of second operation units; and a plurality of second switches for performing corresponding routing tasks, wherein each second switch is not directly connected to the others; wherein the plurality of second operation units, the plurality of second storage units, and the plurality of second switches are distributed on an array plane of the second array; wherein the configuration controller is electrically connected to the plurality of first arrays and the plurality of second arrays, wherein each first array and each second array is stacked alternately, wherein the configuration controller is perpendicular to each first array in the direction corresponding to the array plane. The adjacent array is the second array, wherein the array adjacent to each second array in the vertical direction corresponding to the array plane is the first array; and based on the computation graph information corresponding to the neural network model, the configuration controller dynamically manages the enabling and disabling of the plurality of first computation units, the plurality of first storage units, the plurality of first switches, the plurality of second storage units, the plurality of second computation units, and the plurality of second switches to perform multiple neural network computation tasks of the neural network model.

Based on the above, the three-dimensional coarse-grained reconfigurable array architecture system and its control method provided in this disclosure can achieve the following technical effects: (1) Through the three-dimensional stacked heterogeneous array architecture, the data transmission path is significantly shortened and the data transmission efficiency is improved; (2) Through the functional separation and staggered stacking configuration of the computing array and the storage array, the system can allocate computing resources more efficiently according to the computing characteristics of the neural network model; (3) Through the dynamic management mechanism of the configuration controller, the optimal configuration of the computing unit, storage unit and switch is realized, effectively improving the utilization rate of hardware resources.

To make the above features and advantages of the present invention more apparent and understandable, specific examples are given below, and detailed explanations are provided in conjunction with the accompanying drawings.

Reference will now be made to the embodiments disclosed herein, examples of which are shown in the accompanying drawings. The same reference numerals are used as far as possible in the drawings and description to refer to the same or similar elements.

It should be understood that the terms "system" and "controller" used in this disclosure are often used interchangeably. The term "and/or" in this disclosure describes the relationship between related objects only, meaning that there may be four relationships, such as A and/or B, which could mean four cases: A, B, A and B, or A or B. Additionally, the character "/" in this disclosure generally indicates that related objects are in an "or" relationship.

Figure 1 is a block diagram of a three-dimensional coarse-grained reconfigurable array architecture system according to an embodiment of the present disclosure.

Referring to Figure 1, in one embodiment, the three-dimensional coarse-grained reconfigurable array architecture system 100 includes: an input/output interface 130, a configuration controller 110, a plurality of first arrays 121, and a plurality of second arrays 122. The first arrays 121 and the second arrays 122 are stacked in an alternating manner to form a three-dimensional structure.

In one embodiment, the three-dimensional coarse-grained reconfigurable array architecture system 100 of this invention can be implemented as the following specific semiconductor devices: a reconfigurable neural network processor, particularly suitable for edge computing devices, capable of dynamically adjusting its internal computing resources to handle neural network models of different sizes; an intelligent image processor for real-time image recognition and analysis scenarios, which can flexibly configure the usage of computing and storage units according to the needs of the processing task; and an AI accelerator specifically designed for deep learning inference. The system optimizes inference tasks by using a staggered stacking design of heterogeneous arrays to significantly improve data access efficiency; it also features a programmable tensor processor that supports various matrix and vector operations, making it suitable for the training and inference phases of machine learning models; and an embedded system co-processor that serves as an auxiliary unit to the main processor and can be customized for specific application scenarios.

In one embodiment, the three-dimensional coarse-grained reconfigurable array architecture system 100 of this invention can be integrated into the following electronic devices, such as: 1.) Smartphones and wearable devices. Due to the need to support diverse applications, such as games, photography, AI inference (image enhancement, voice assistants, etc.), and 5G communication, such devices can incorporate an accelerator chip of the reconfigurable array architecture system to perform hardware acceleration for specific workloads (such as image processing, AI inference) while maintaining low power consumption. 2.) Unmanned aerial vehicles (UAVs). UAVs require the performance of highly complex tasks, such as navigation control, object tracking, environmental perception, and image processing; these computational requirements vary depending on the task type. Reconfigurable array architecture systems can reconfigure their computing architecture to meet task requirements, providing the necessary computing power while reducing energy consumption.

3.) Industrial Automation Controllers, used to process large amounts of sensor data in real time and execute complex control algorithms; 4.) Data Center Servers, especially computing servers for training and inference of large-scale neural network models; 5.) Medical Imaging Diagnostic Equipment, used for real-time analysis and diagnosis of high-resolution medical images; and 6.) Advanced Driver-Assistance Systems (ADAS), integrated into the vehicle's computer, used for real-time data analysis and decision-making from multiple sensors. It should be noted that the above-described electronic device is merely an example and this disclosure is not limited thereto. Any electronic device that can be applied to the coarse-grained reconfigurable array architecture system 100 is also applicable to this disclosure.

In this embodiment, the input/output interface 130 is used to receive external input data and output computation results. The input data may include parameters of the neural network model, computation instructions, data to be processed, or any data related to the neural network model. The computation results may include the final output result of a single node of the neural network computation or the entire neural network.

The configuration controller 110 is electrically connected to the input/output interface 130, the plurality of first arrays 121, and the plurality of second arrays 122. The configuration controller 110 is responsible for monitoring the working status of the plurality of first arrays 121 and the plurality of second arrays 122, and dynamically managing the enabling and disabling status of each component in each first array 121 and each second array based on the computational graph information of the corresponding neural network model.

In one embodiment (see Figures 4A-4D), each first array 121 includes multiple first computation units, multiple first storage units, and multiple first switches, wherein the multiple first computation units, multiple first storage units, and multiple first switches are distributed on the array plane of the first array. Specifically, the multiple first computation units are used to perform neural network computation tasks for the nodes of the corresponding neural network model, and the multiple first storage units are used to store the data of the corresponding neural network computation tasks. It is worth noting that in this embodiment, the number of the multiple first computation units in each first array 121 is greater than the number of the multiple first storage units; this design is particularly suitable for handling computationally intensive tasks. In addition, the plurality of first switches are used to perform corresponding routing tasks, wherein each first switch is not directly connected to each other.

Accordingly, in this embodiment (see Figures 4A-4D), each second array 122 includes multiple second operation units, multiple second storage units, and multiple second switches, wherein the multiple second operation units, multiple second storage units, and multiple second switches are distributed on the array plane of the second array. Specifically, the multiple second operation units are used to perform neural network operation tasks of the corresponding nodes of the neural network model, and the multiple second storage units are used to store the data of the corresponding neural network operation tasks. Unlike the first array 121, in the second array 122, the number of multiple second storage units is greater than the number of multiple second operation units. This design is particularly suitable for handling tasks that require large amounts of data storage. Similar to the first array 121, the plurality of second switches are used to perform corresponding routing tasks, wherein each second switch is not directly connected to each other to optimize data transmission efficiency. In other words, in this embodiment, the first array can also be called a computation-enhanced array, which has a stronger overall node computation capability; the second array can also be called a storage-enhanced array, which has a stronger overall data storage capability.

In one embodiment, a vertically interconnected data transmission mechanism is used between the first array 121 and the second array 122. Specifically, the first switch of each first array is vertically connected to the second operation unit or the second storage unit of the adjacent second array, while the second switch of each second array is vertically connected to the first operation unit or the first storage unit of the adjacent first array.

In this embodiment, in each first array 121, each first operation unit and each first storage unit are not directly connected to each other. Instead, each first operation unit and each first storage unit are connected through at least one intermediary first switch.

Similarly, in each second array 122, each second operation unit and each second storage unit are not directly connected to each other. Each second operation unit and each second storage unit must be connected through at least one intermediary second switch. This design further enhances the data transmission management capabilities within the array, making data transmission paths more diverse.

In the vertical direction, this disclosure introduces a vertical connection mechanism for cross-layer communication. A first switch in each first array 121 is vertically connected to a second processing unit or a second storage unit of an adjacent second array 122. This vertical connection allows first data from the first array 121 to be directly transmitted via the first switch to the second processing unit or the second storage unit of the adjacent second array 122, achieving more efficient cross-layer transmission.

Similarly, the second switch of each second array 122 is vertically connected to the first storage unit or the first computing unit of the adjacent first array 121. Through this vertical connection, the second data of the second array 122 can be directly transmitted to the first computing unit or the first storage unit of the adjacent first array 121 via the second switch, completing cross-layer data exchange.

It is worth mentioning that in this embodiment, the switch always acts as the initiator during the cross-layer data transmission process, actively sending the data to the computing unit or storage unit of the adjacent layer.

In one embodiment, the computational unit (including a first computational unit and a second computational unit) can be implemented using a reconfigurable processing unit. Specifically, the computational unit can dynamically adjust its computational mode according to different computational needs. For example, when performing matrix multiplication, the reconfigurable processing unit can be configured as a systolic array architecture; when performing convolution operations, it can be reconfigured as a two-dimensional computational array architecture. Through this flexible configuration, the computational unit is particularly suitable for handling different types of computational needs in deep learning, including high-dimensional matrix multiplication, convolution operations, and vector operations.

In this embodiment, the storage unit (including the first storage unit and the second storage unit) can be implemented using static random-access memory. This memory has high-speed read and write characteristics, making it suitable for storing data for neural network computing tasks, including weight parameters, intermediate computing results, and computing input data. Furthermore, the storage unit can be divided into multiple memory banks according to the data access mode, and each memory bank can perform read and write operations independently. This design can effectively improve the parallelism of data access.

In another embodiment, the switch (including a first switch and a second switch) adopts a distributed routing architecture, comprising multiple routing nodes. Each routing node has a data buffering function, which can temporarily store data packets to be forwarded and select the optimal transmission path based on destination information. Through this distributed routing architecture, the system can achieve more flexible data transmission scheduling and reduce data transmission conflicts. The switch can also implement a multi-layer crossbar architecture, which can simultaneously support the transmission needs of multiple data streams. This architecture includes multiple crossbar layers, each responsible for data transmission in a specific direction. By properly configuring the connection status of the crossbars, the system can establish multiple independent data transmission channels, improving the parallelism of data transmission.

In one embodiment, the switch can process data transmission according to a routing task set by the configuration controller 110. Specifically, the routing task includes: identification information of the destination computing unit or storage unit, data transmission priority information, data packet size information, and relay information of the data transmission path. Based on this routing information, the switch establishes a corresponding data transmission channel and ensures that data can be transmitted according to the specified transmission path.

Figure 2 is a block diagram of the configuration controller of a three-dimensional coarse-grained reconfigurable array architecture system according to an embodiment of the present disclosure.

Referring to Figure 2, in this embodiment, the configuration controller 110 includes a workload configuration storage circuit unit 112 and a task control processor 111.

In this embodiment, the configuration controller 110 controls the data transmission between components through the following mechanism. First, the configuration controller 110 determines the data dependencies between nodes based on the computational graph information stored in the workload configuration storage circuit unit 112. For example, the task control processor 111 of the configuration controller 110 can establish a data transmission schedule, which includes: the timing arrangement of data transmission, the switch configuration sequence of transmission paths, and the access timing of each storage unit.

Specifically, when a specific node's computational task needs to be executed, the configuration controller 110 first sends a routing configuration command to the corresponding switch to set the switch's routing status. These routing statuses determine the forwarding direction of data packets in the switch network. Simultaneously, the configuration controller 110 also sends read or write commands to the relevant storage units to control the data access timing. Once the data transmission path is established, the configuration controller 110 immediately starts the corresponding computational unit, enabling it to begin executing the specified computational task.

During data transmission, the configuration controller 110 continuously monitors the operating status of each switch, including the current data transmission progress and whether data transmission conflicts have occurred. If a potential transmission conflict is detected, the configuration controller 110 can immediately adjust the data transmission priority or replan the transmission path to ensure the reliability and efficiency of data transmission.

In one embodiment, the computing unit and the storage unit, in addition to performing their main computing and storage functions, are also configured to have data forwarding capabilities. Specifically, when a computing unit or storage unit receives data that is not addressed to itself, the unit can independently determine the destination information of the data and directly transmit the data to the next target unit without needing to go through a switch for relay processing. For example, when the computing unit or storage unit performs data forwarding, it first reads the destination marker contained in the data. If the destination marker indicates that the data is not sent to itself, the unit will select the most appropriate transmission direction according to the routing information pre-set by the configuration controller and transmit the data completely to the next node. During this transmission process, the computing unit or storage unit is only responsible for forwarding data and does not modify or process the data content in any way. Through this direct forwarding mechanism of computing and storage units, the system can establish a more direct data transmission path.

Through the aforementioned control mechanism, the controller 110 can ensure that data transmission in the system meets the dependency requirements of the computing tasks while achieving high component resource utilization efficiency. At the same time, the dynamic adjustment characteristics of this control mechanism also enable the system to adapt to the computing needs of neural networks of different scales and types.

It is worth noting that although the computing units, storage units, and switches have the same functions in the first array 121 and the second array 122, their quantity configuration differs between the two arrays. In the first array 121, the number of computing units exceeds the number of storage units; while in the second array 122, the number of storage units exceeds the number of computing units. This differentiated quantity configuration allows the system to achieve an optimal balance between computing performance and memory access efficiency when performing deep learning operations, while simultaneously optimizing resource utilization through the dynamic management of the configuration controller 110.

In this embodiment, the workload configuration storage circuit unit 112 is used to store computational graph information of the neural network model.

Specifically, in one embodiment, the computation graph information includes: (1) dependency level information for each of the plurality of nodes, indicating the execution order of the plurality of nodes in the neural network model. The dependency level information allows nodes at the same execution level to be executed in parallel, while nodes at different execution levels are executed sequentially; (2) connection quantity information between the plurality of nodes, indicating the total number of adjacent nodes connected to each node; (3) data transfer quantity information between the plurality of nodes, indicating the data size on the data transfer path; and (4) computation quantity information for each of the plurality of nodes, indicating the computation quantity of the node operations performed by each node. In another embodiment, the computation graph information may further include information about the parent node of each node. Figure 8 will be used below to illustrate the details of obtaining computation graph information.

In one embodiment, the task control processor 111 dynamically manages the enabling and disabling states of the plurality of first computation units, the plurality of first storage units, the plurality of first switches, the plurality of second storage units, the plurality of second computation units, and the plurality of second switches based on the computation graph information, in order to execute multiple neural network computation tasks of the neural network model.

In one embodiment, the task control processor 111 first determines the execution order of nodes based on the dependency hierarchy information, then selects an appropriate computing unit configuration based on the connection quantity information (to the extent that the number of switches connected to the selected computing unit matches the number of connections of the corresponding node), plans the data transmission path based on the data transfer volume information, and finally allocates computing resources considering the computing volume information and the computing power of each computing unit, thereby achieving optimal allocation of computing resources.

In one embodiment, the configuration controller 110 can be implemented using an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or a programmable logic device (PLD). These implementations offer high performance and low latency, making them particularly suitable for scenarios requiring real-time computing resource configuration.

In another embodiment, the workload configuration storage circuit unit 112 can be implemented using static random-access memory (SRAM), dynamic random-access memory (DRAM), or flash memory. When selecting a suitable memory type, factors such as access speed, power consumption, and cost need to be considered.

In another embodiment, the task control processor 111 may be implemented using a processor core with a Reduced Instruction Set Computing (RISC) architecture or a Very Long Instruction Word (VLIW) architecture. These processor architectures are characterized by high instruction execution efficiency and low power consumption, making them suitable for real-time scheduling of computing resources.

In this embodiment, the data transmission path can be divided into two types: (1) Coplanar path: the transmission path when the idle operation unit and the preceding operation unit are located on the same array plane; (2) Non-coplanar path: the transmission path when the idle operation unit and the preceding operation unit are located on different array planes.

The system (e.g., task control processor 111) prioritizes the transmission path with the fewer total number of components. Specifically, when the shortest non-plane path contains fewer components than the shortest plane path, the system selects a specific idle computation unit corresponding to the shortest non-plane path as the target computation unit. In other words, the architecture disclosed herein provides superior non-plane transmission paths compared to traditional plane transmission paths to enhance data transmission speed and thereby improve the efficiency of the overall neural network computation task.

In one embodiment, the task control processor 111 may, for example, perform the following task scheduling.

Task analysis phase: Based on dependency hierarchy information, select the task nodes to be configured according to the order of each execution level (dependency level) to start executing the corresponding neural network computation task; ensure that the computation units assigned to the same task node can execute the corresponding node computation in parallel; and sort multiple neural network computation tasks according to dependency hierarchy information.

Resource allocation phase: Evaluate the computational load information of each target task node and the computational capacity of each idle computing unit; determine whether there are enough idle computing units to be allocated to the target task nodes; select and enable appropriate target computing units based on computational requirements and the shortest transmission path.

Dynamic adjustment phase: Monitor the working status of each computing unit; when a computing unit completes node calculation, select the storage unit with the shortest transmission path to store the calculation result; reset the completed computing unit as a new idle computing unit; continuously monitor and adjust until all task nodes are configured. In one embodiment, when a computing unit changes from a busy state to an idle computing unit, the configuration controller 110 determines the power management state that the idle computing unit should enter based on the current system workload. If it is predicted that the computing unit may be reconfigured and used in the near future, it is put into standby mode to ensure a quick switch back to operating status. If it is predicted that it will not be used for a longer period of time, it can be put into sleep mode or even deep shutdown mode to reduce the overall system power consumption. This dynamic power management mechanism can effectively balance the system's computing performance and energy efficiency. More specifically, in one embodiment, the first state is standby mode, in which the system continuously supplies clock signals and power, and maintains the basic status information of the computing unit, enabling it to quickly switch back to operating status, but with a relatively moderate level of power consumption. The second state is Sleep Mode, which shuts down the clock supply and reduces the core voltage, retaining only essential configuration information. While it has lower power consumption, it requires a longer wake-up time. The third state is Deep Shutdown Mode, which completely cuts off the power supply and clears all status information, achieving the lowest power consumption but requiring the longest restart time. It is particularly suitable for computing units that are not expected to be used for a long time. When determining the power state of a computing unit, the configuration controller 110 considers multiple factors, including current workload predictions, system power consumption estimates, the geographical location of the computing unit (considering heat dissipation), and the wake-up time requirements of each state, to achieve the best balance between performance and power consumption. "Enabling" a specific computation unit can refer to setting a specific computation unit to a busy/working state to perform corresponding node operations; "disabling" a specific computation unit can refer to setting a specific computation unit from a busy/working state to a "disabled" state or setting it to a standby, sleep, or deeply disabled state to save power consumption to varying degrees.

Resource optimization phase: Select the computing unit configuration based on the number of connections between nodes; ensure that target computing units with a large number of connections have a large number of switch connections; dynamically adjust the data transmission path to minimize transmission latency.

Figure 3A is a schematic diagram of a first staggered stacking configuration of a three-dimensional coarse-grained reconfigurable array architecture system according to an embodiment of the present disclosure. Figure 3B is a schematic diagram of a second staggered stacking configuration of a three-dimensional coarse-grained reconfigurable array architecture system according to an embodiment of the present disclosure.

Referring to Figure 3A, in one embodiment, the three-dimensional coarse-grained reconfigurable array architecture system arranges its array structure using a first staggered stacking method. In the three-dimensional coordinate system (X, Y, Z), the first array 121(1) is located at the top, the second array 122(1) is located directly below it, and the first array 121(2) is located below the second array 122(1). Each array is parallel to the XY plane and stacked along the Z-axis.

Referring to Figure 3B, in another embodiment, the system employs a second staggered stacking method. In this method, the second array 122(1) is located at the top layer, the first array 121(1) is located below it, and the second array 122(2) is located below the first array 121(1). This arrangement ensures that adjacent layers always maintain an alternating configuration of the first array 121 and the second array 122.

In this embodiment, data transmission paths are established between adjacent arrays through a vertical interconnection structure. When the system needs to transmit data between arrays at different levels, the data transmission can be completed directly through the vertical path without having to go through multiple forwardings by arrays at the same level, thus improving data transmission efficiency and computation timeliness.

The main difference between these two staggered stacking methods lies in the type of the top-level array. The configuration controller 110 can select the appropriate stacking method to configure the system architecture based on the characteristics of the computing task requirements.

Figure 4A is a schematic diagram of the first layout of the first and second arrays of a three-dimensional coarse-grained reconfigurable array architecture system according to an embodiment of the present disclosure.

Referring to Figure 4A, in one embodiment, the three-dimensional coarse-grained reconfigurable array architecture system includes a first array 121 and a second array 122, wherein each unit presents a specific arrangement and interconnection.

Specifically, the first array 121 adopts a four-unit configuration, including two operation units (P), one storage unit (M), and one switch (S). The two operation units are located at the upper left and lower right corners of the array, respectively, the storage unit is located at the lower left corner, and the switch is located at the upper right corner. The switch (S) is connected in a straight line to the operation unit (P) to its left and the operation unit (P) below it, and is also connected diagonally to the storage unit (M) at the lower left corner.

In the second array 122, a four-unit configuration is also used, including one operation unit (P), two storage units (M), and one switch (S). The storage units are located in the upper left and lower right corners, the operation unit is located in the upper right corner, and the switch is located in the lower left corner. The switch (S) is connected in a straight line to the storage unit (M) to its right and the operation unit (P) above it, and is also connected diagonally to the operation unit (P) in the upper right corner.

This layout design allows each switch (S) to establish connections with three other units, forming a branch structure. The connections include two straight connections and one diagonal connection, a configuration that makes the data transmission path fixed and predictable.

Figure 4B is a schematic diagram of the second layout of the first and second arrays of a three-dimensional coarse-grained reconfigurable array architecture system according to an embodiment of the present disclosure.

Referring to Figure 4B, in one embodiment, the first array 121 and the second array 122 of the three-dimensional coarse-grained reconfigurable array architecture system adopt a nine-element extended (3x3 matrix elements plus 4 insertion elements) configuration structure (also known as an odd array).

In the first array 121, four operation units (P) are located at the top left, top right, bottom left, and bottom right corners, respectively. Four storage units (M) are located at the top center, left center, right center, and bottom center, respectively. Four switches (S) are arranged in a cross shape in the central area, with one operation unit (P) positioned at the center. The four insertion units are switches (S), and each switch (S) is connected to its two adjacent operation units (P) and two storage units (M). This configuration ensures that each switch (S) is connected to four adjacent units, forming a grid topology. The central operation unit (P) is connected to the four switches (S) in a cross shape.

The second array 122 uses a similar configuration for its components, but the types of components at each position differ from those in the first array 121. Specifically, four storage units (M) are located at the four corners of the array, and four operation units (P) are arranged around the central storage unit (M). Four switches (S) are located at the top center, left center, right center, and bottom center, respectively. Each switch (S) is connected to its two adjacent operation units (P) and two storage units (M). The central storage unit (M) is connected to the four operation units (P) in a cross shape.

In one embodiment, the three-dimensional coarse-grained reconfigurable array architecture system employs an odd-numbered array configuration, where two adjacent layers consist of a storage array (e.g., the second array) and an operation array (e.g., the first array). The switches (S), operation units (P), and storage units (M) in each array are interconnected according to specific rules.

In this embodiment, each switch (S) is connected to at least one computing unit (P) and one storage unit (M). Specifically, the computing unit (P) and storage unit (M) connected to the switch (S) are configured in an interleaved manner to form a uniformly distributed connection architecture.

Referring to the design characteristics of the storage array, the number of storage units (M) connected to each switch (S) is greater than the number of operation units (P). Furthermore, the layout of the storage array can be converted into a data array by the following rules: changing a switch (S) to a storage unit (M), changing a storage unit (M) to an operation unit (P), and changing an operation unit (P) to a switch (S).

In contrast, in a computing array, the number of storage units (M) connected to each switch (S) does not exceed the number of computing units (P). This connection configuration makes computing arrays particularly suitable for performing computationally intensive tasks, while storage arrays are suitable for handling scenarios that require large amounts of data storage.

Figure 4C is a schematic diagram of the third layout of the first and second arrays of a three-dimensional coarse-grained reconfigurable array architecture system according to an embodiment of the present disclosure.

Referring to Figure 4C, in one embodiment, the first array 121 and the second array 122 of the three-dimensional coarse-grained reconfigurable array architecture system adopt a centrally expanded architecture configuration. This configuration is based on a 4x4 matrix array structure with additional components added at the center.

The configuration of the first formation 121 is as follows:

Matrix boundary configuration: Four computational units (P) are located in the middle of the left and right sides respectively, four storage units (M) are located in the four corners, and four switches (S) are located at the four center points of the top, bottom, left, and right.

Central configuration: An additional computational unit (P) is located at the exact center of the array.

Connection architecture: Each switch (S) is connected to two operation units (P) and one storage unit (M), while the central operation unit (P) is connected to the four switches (S) in a cross shape.

The configuration of the second array 122 is as follows:

Matrix boundary configuration: Four storage units (M) are located at the top and bottom center, four switches (S) are located at the four corners, and four operation units (P) are located at the top, bottom, left, and right center points.

Central configuration: An additional switch (S) is located at the very center of the array.

Connection structure: Each corner switch (S) is connected to one operation unit (P) and two storage units (M) respectively, while the central switch (S) forms a cross-shaped connection with the four operation units (P).

This configuration combines the boundary connections of the original 4x4 matrix architecture with the central radial connections, providing more data transmission path options while maintaining a regular connection structure. It should be noted that in one embodiment, since the central computing unit of the first array is connected to the largest number of switches, its computing power can be enhanced, for example, by N times the computing power of other computing units (N greater than 1), to improve the efficiency of handling neural network computing tasks.

In addition, other features of this layout include:

The two operation units at the outermost position of the first array will be adjacent but not connected; the two storage units at the outermost position of the second array will be adjacent but not connected.

Figure 4D is a schematic diagram of the fourth layout of the first and second arrays of a three-dimensional coarse-grained reconfigurable array architecture system according to an embodiment of the present disclosure.

Referring to Figure 4D, in one embodiment, the first array 121 and the second array 122 of the three-dimensional coarse-grained reconfigurable array architecture system adopt an extended layout configuration, which is an extension of the basic unit layout (first layout) shown in Figure 4A.

The layout of the first array 121 includes four sets of switches (S) arranged in a matrix to form a 2x2 switching network architecture. The central switch (S) of each switching network architecture (composed of 2x2 units) connects to eight peripheral units, including four computing units (P) and four storage units (M). Specifically, the computing units (P) are connected to the switches (S) by straight lines, while the storage units (M) are connected to the switches (S) by diagonal lines. Adjacent switches (S) are connected through computing units (P), forming horizontal and vertical data transmission channels.

The second array 122 implements a similar extended layout, and its layout configuration includes:

A central storage unit (M) is configured, surrounded by four switches (S). Each switch (S) is linearly connected to three processing units (P) and diagonally connected to two storage units (M). Additionally, switches (S) are located at the four corners to connect to adjacent storage units (M). These switches (S) are interconnected through the central storage unit (M) and the peripheral processing units (P), forming a complete data transmission network.

This extended layout maintains the connectivity of the basic unit layout while expanding the system's computing and storage capacity by increasing the number of units.

Figure 5 is a schematic diagram of the three-dimensional structure of the first and second arrays corresponding to the first layout, according to an embodiment of the present disclosure.

Referring to Figure 5, in one embodiment, the three-dimensional coarse-grained reconfigurable array architecture system adopts a three-dimensional stacked architecture based on the first layout shown in Figure 4A. The system includes a first array 121 and a second array 122 that are stacked in an interleaved manner, and is provided with vertical connection structures B51 and B52 to realize cross-layer data transmission.

The first array 121 and the second array 122 each maintain their basic layout features in the XY plane. In the first array 121(1), a switch (S) is located in the upper right, two adjacent operation units (P) are located on the left and below respectively, and a storage unit (M) is located in the lower left. Similarly, the first array 121(2) maintains the same planar layout. In the second array 122(1), a switch (S) is located in the lower left, two adjacent storage units (M) are located on the right and above respectively, and an operation unit (P) is located in the upper right.

In the Z-axis direction, the system implements two vertical connection architectures, for example:

(1) Vertical interconnection architecture B51: It includes an upper storage unit (M) that is directly connected to a lower switch (S) via vertical interconnection, and then connected to another lower storage unit (M). That is, in multiple stacked arrays, the components in the lower left corner will present a vertical interconnection architecture of M-S-M-S…

(2) Vertical connection architecture B52: It includes an upper-level switch (S) that is directly connected to the lower-level computing unit (P) via vertical interconnection, and then connected to another lower-level switch (S). That is to say, in multiple stacked arrays, the components in the lower left corner will present an M-S-M-S… vertical connection architecture.

These vertical connection architectures establish direct data transmission channels between adjacent arrays. Specifically, when the switch (S) of the first array 121(1) needs to communicate with the computing unit (P) of the second array 122(1), the data can be transmitted directly through the vertical connection architecture B52 without multiple forwardings in the horizontal direction. Similarly, when data needs to be transmitted between storage units (M) at different levels, direct transmission can be achieved through the vertical connection architecture B51.

In the overall architecture, the adjacent first array 121 and second array 122 form a functionally complementary pair. Through the vertical connection structures B51 and B52, the system can achieve cross-layer data transmission while maintaining the planar layout characteristics of each array. This three-dimensional stacking architecture not only maintains the connection characteristics of the original planar layout, but also provides additional data transmission paths through the vertical connection structure, thereby enhancing the system's data transmission performance.

It is worth mentioning that in this embodiment, when an array needs to perform cross-layer transmission, it will first go through the array's switch to establish a cross-layer transmission path. This is because the correctness of the data transmission path can be ensured by configuring the routing task.

Figure 6 is a schematic diagram of the three-dimensional structure of the first and second arrays corresponding to the third layout, according to an embodiment of the present disclosure.

Please refer to Figure 6. In the embodiment shown in Figure 6, the vertical connection structure presents two staggered arrangement patterns:

(1) Vertical connection architecture B61: The upper storage unit (M) is vertically interconnected to the lower computing unit (P), and then connected to another lower storage unit (M). In the stacked array, the vertical connection architecture B61 presents an alternating arrangement of M-P-M-P...

(2) Vertical interconnection architecture B62: The upper-level switch (S) is vertically interconnected to the lower-level storage unit (M), and then to another lower-level switch (S). In the stacked array, the vertical interconnection architecture B62 presents an alternating arrangement of S-M-S-M...

The stacked structure shown in Figure 6 implements an alternating arrangement of computation units (P), storage units (M), and switches (S) in the vertical direction. Adjacent layers are directly connected through vertical connection structures B61 and B62, forming a tight three-dimensional network.

During data transmission, when the first array 121(1) and 121(2) need to transmit data to the second array 122, cross-layer transmission can be achieved directly through the vertical connection architecture B61. Similarly, when the second array 122(1) needs to transmit data to the second array 122, cross-layer transmission can be achieved directly through the vertical connection architecture B61.

Figure 7 is a flowchart illustrating a control method for a three-dimensional coarse-grained reconfigurable array architecture system according to an embodiment of the present disclosure.

Referring to Figure 7, this invention provides a control method for a three-dimensional coarse-grained reconfigurable array (3D-CGRA) architecture system. The method includes the following steps:

Step S710, via the configuration controller, monitors the operating status of multiple first arrays and multiple second arrays of the three-dimensional coarse-grained reconfigurable array architecture system. Each first array includes multiple first computation units, multiple first storage units, and multiple first switches, while each second array includes multiple second computation units, multiple second storage units, and multiple second switches.

Specifically, the configuration controller 110 continuously and in real-time tracks the usage status of computing units, storage units, and switches in each array. In one embodiment, the operating status includes: idle, computing, accessing, working, and node computing completed. Furthermore, the operating status of a storage unit can include the data/information recorded by that storage unit. By monitoring their operating status, the configuration controller 110 can grasp the real-time allocation status of internal system resources and the data storage status, providing a basis for subsequent dynamic configuration management.

Step S720: Configure controller 110 to dynamically manage the enabling and disabling of multiple first computation units, multiple first storage units, multiple first switches, multiple second storage units, multiple second computation units, and multiple second switches based on the computation graph information of the corresponding neural network model, in order to execute multiple neural network computation tasks of the neural network model.

In this step, the configuration controller 110 schedules various hardware resources in the system based on the structure and computational order of the neural network model itself. It determines whether to enable or disable specific computational units, storage units, and switches based on the current array stack architecture, so that neural network computational tasks can be executed in the original order of the neural network architecture. Furthermore, by configuring the routing tasks of the switches, smooth data transmission across layers can be ensured.

Figure 8 is a schematic diagram illustrating the acquisition of computational graph information corresponding to a neural network model according to an embodiment of the present disclosure.

Referring to Figure 8, in one embodiment, the system generates corresponding data transmission paths CT81 and computational graph information TB81 based on the known neural network model architecture data and corresponding parameters (this data can be recorded in the workload configuration storage circuit unit 112). The data transmission path CT81 is presented in the form of a directed graph, with arrows between nodes indicating the direction of data flow to express the data dependencies between nodes.

In this embodiment, nodes A to I in the diagram represent computational nodes in the neural network model. Each arrow represents a data transmission path, indicating the direction of transmission of computation results. For example, if the computation result of node A needs to be transmitted to nodes B and C, it means that the computations of nodes B and C depend on the computation result of node A.

The system generates computation graph information (as shown in Table TB81) based on the data transmission path shown in CT81. This computation graph information TB81 includes the following information:

(1) Dependency level: indicates the execution order of nodes in the operation sequence; (2) Node: marks the operation node in each dependency level; (3) Number of connections: records the total number of adjacent nodes of each node; (4) Computational complexity: indicates the computational complexity of the node operation processed by each node; (5) Data transfer volume: records the data output between nodes; (6) Parent node: marks the data source node of each node.

As shown in the example in Figure 8, the system (e.g., configuration controller 110 or task control processor 111) analyzes the data transmission path to identify five dependency levels:

Level 1: Node A, with no preceding dependent nodes; Level 2: Nodes B and C, depending on the computation results of node A; Level 3: Nodes D, E, and F, depending on the computation results of nodes B and C; Level 4: Nodes G and H, depending on the computation results of nodes C, D, and E; Level 5: Node I, depending on the computation results of nodes F, G, and H.

The system allocates appropriate computing resources to each node based on the computation graph information:

(1) Connection quantity information is used to determine the number of data transmission channels required by the node; (2) Computation quantity information (OP1-OP9) is used to evaluate the number of computing units required; (3) Data transmission quantity information (DT1-DT9) is used to plan the data transmission path or assign suitable storage units to temporarily store the computation results; (4) Parent node information is used to ensure the correctness of data dependencies, to determine whether the computation results need to be temporarily stored, to plan the data access path, and to optimize the resource allocation of storage units.

In this example, the configuration controller 110 arranges the execution order of nodes based on dependency hierarchy information:

First, configure node A to be independent of other nodes. Next, after node A completes its node operations, nodes B and C can be executed concurrently (because they belong to the same level). Node D must wait for node B to complete its node operations (because node D needs the result of node B's operation), node E must wait for nodes B and C to complete their node operations, and node F must wait for node B to complete its node operations. Node G must wait for nodes C and D to complete their node operations, and node H must wait for node E to complete its node operations. Finally, node I is executed, waiting for nodes F, G, and H to complete their node operations.

This computation graph information enables the system to effectively manage the allocation and scheduling of computational resources, ensuring the correct execution order of neural network computations.

More specifically, in one embodiment, the task control processor 111 performs dynamic configuration of computing resources based on the computation graph information stored in the workload configuration storage circuit unit 112. Specifically, the task control processor 111 first determines multiple neural network computation tasks corresponding to multiple nodes based on dependency hierarchy information. Then, the task control processor 111 monitors the operating status of multiple first arrays 121 and multiple second arrays 122, identifying idle computing units that have not yet been activated.

When task configuration begins, the task control processor 111 sequentially selects unprocessed target neural network computation tasks from multiple neural network computation tasks based on dependency hierarchy information. For each target neural network computation task, the task control processor 111 performs a series of configuration steps: first, it selects a target computation unit suitable for executing the target task node from the available computation units; second, it selects a corresponding target storage unit from the first storage unit and the second storage unit; and finally, it selects a suitable target switch from the first switch and the second switch to establish a connection between the target computation unit and the target storage unit.

After completing the resource selection, the task control processor 111 sequentially enables the selected hardware resources: enables the target computation unit to perform target node computation, enables the target storage unit to store relevant data, and enables the target switch to set the target routing task, thereby establishing a complete data transmission path.

It is worth mentioning that, in the example of Figure 8, a neural network computation task can be defined as: a set of node computations with the same parent node in the same dependency level. For example: the first neural network computation task: performing the computation of node A; the second neural network computation task: simultaneously performing the computations of nodes B and C (with A as the common parent node); the third neural network computation task: performing the computations of nodes D, E, and F (with B or C as the parent node); the fourth neural network computation task: performing the computations of nodes G and H; and the fifth neural network computation task: performing the computation of node I.

These nodes that are divided into the same computing task will be designated as the task nodes of the computing task. The task control processor 111 configures a corresponding number of computing units for these task nodes so that they can execute node operations in parallel. All neural network computing tasks are sorted according to their dependency level information to ensure the correctness of the order of operations. This task design ensures that the execution sequence of computing tasks meets data dependency requirements and supports node operations that can be executed in parallel.

In another embodiment, the task control processor 111 evaluates hardware resources based on data transfer volume and connection quantity information in the computation graph information. Specifically, the task control processor 111 first selects the corresponding target storage unit based on the data transfer volume information of each target computing unit. This selection mechanism ensures that computing units with large data transfer requirements can be allocated sufficient storage resources (or that adjacent storage units have sufficient storage space).

Secondly, the task control processor 111 selects an appropriate target computing unit from multiple available computing units based on the number of connections between target task nodes. For example, if a target task node has a large number of connections, the task control processor 111 will select a computing unit with more switch connections to ensure efficient data transmission. Therefore, when a particular target computing unit needs to handle a large number of task nodes, that computing unit will be configured with more target switch connections.

When performing calculations on the target node, the task control processor 111 needs to process various types of data. In this embodiment, this data includes: calculation parameters used to configure the calculation mode of the target calculation unit; node input data, including calculation results or raw input data from the preceding node; and node calculation results, i.e., the output data generated by the target calculation unit after performing the calculation task. The task control processor 111 may decide, as needed, to directly transmit the node input data to the calculation unit of the corresponding subsequent node, or to temporarily store it in a storage unit to wait for the calculation unit of the corresponding subsequent node to be configured.

Taking the computation graph shown in Figure 8 as an example, when the task control processor 111 processes the computation task of task node E, it will consider the following factors:

(1) Since task node E has 3 connections (input connections from nodes B and C, and output connections to node H), compared to the configuration of the computing unit of task node D (corresponding to fewer connections: 2), the task control processor 111 will select a target task computing unit with more switch connections for task node E.

(2) Based on the input data that needs to be processed for the node operation of the corresponding node E and the size of the corresponding operation parameters, the task control processor 111 can be configured with a target storage unit with sufficient storage capacity to store the corresponding input data.

(3) The task control processor 111 ensures that the selected target switch can establish the shortest complete data transmission path to receive the node operation results from the corresponding nodes B and C, and then perform the node operation of the corresponding node E through the target task operation unit configured for node E.

(4) If the node calculation result of the target task calculation unit of the corresponding node E needs to be temporarily stored, the task control processor 111 decides to temporarily store the node calculation result in a storage unit with sufficient storage space near the target task calculation unit of the corresponding node E based on the data transmission volume information.

In one embodiment, the task control processor 111 employs a computing power assessment mechanism to allocate computing resources. First, the task control processor 111 assesses whether the existing idle computing units are sufficient to meet the computing requirements based on the computing power information of each target task node and the computing power of each idle computing unit [a computing unit whose working status is "idle" (e.g., not performing any computing).

When the number of idle computing units is confirmed to be sufficient, the task control processor 111 will consider three factors to select and enable the target computing unit:

(1) The computational load information of the target task node, used to assess the required computational resource scale; (2) The computational capacity of the idle computing units, to ensure that the selected computing units can effectively handle the specified tasks; (3) The number of relay components in the data transmission path, used to minimize data transmission delay.

For example, when processing the computation task of node E in Figure 8, the task control processor 111 will: evaluate the computational load OP5 of node E; check the computational capacity of available idle computation units; and calculate the transmission path length from nodes B and C to each candidate computation unit.

Based on this information, the task control processor 111 selects the optimal combination of target computational units with the shortest transmission path to optimize computational performance. This is further illustrated below using Figure 9.

Figure 9 is a schematic diagram illustrating the selection of target task computation unit based on transmission path according to an embodiment of the present disclosure.

Referring to Figure 9, in one embodiment, the task control processor 111 selects the target computation unit based on the transmission path information. The upper part of Figure 9 shows the array configuration of the system architecture, including the spatial distribution of computation units (P), storage units (M), and switches (S), as well as their connections. The lower part of Figure 9 presents the relevant information of the transmission path in a table TB91. In this example, it is assumed that the second computation unit P1 is the preceding computation unit that has just completed node computation, and the second computation units P2 and P3 are busy computation units that are currently performing node computation. That is, for the preceding computation unit P1, the available idle computation units are P4, P5, P6, P7, P8, and P9.

In this embodiment, the system analyzes the possible transmission paths between the front-end operation unit P1 and each of the idle operation units P4, P5, P6, P7, P8, and P9. These transmission paths can be divided into two categories:

(1) Coplanar path: such as transmission path TP14, where data transmission from P1 to P4 occurs entirely within the same array plane; and

(2) Non-plane paths: such as transmission paths TP15 to TP19, data transmission needs to cross different array planes.

The task control processor 111 calculates the length of each transmission path. The length of a transmission path can be obtained by subtracting one from the total number of components on that path. For example, since transmission path TP14 (P1→S1→M5→S2→P4) passes through 5 components, the length of transmission path TP14 is 4 (5-1=4).

For example, since the transmission path TP15 (P1→S1→M6→P5) passes through 4 components, the length of the transmission path TP15 is 3 (4-1=3).

The system prioritizes target computation units with shorter transmission path lengths. As shown in Table TB91, except for TP18 (path length 5), the lengths of other non-plane paths (TP15, TP16, TP17, TP19) are all 3, shorter than the length of the plane path TP14 (4). This indicates that in most cases, non-plane transmission paths provide more efficient data transmission (the fewer components passed through, the faster the transmission speed).

When the task control processor 111 determines that the total number of components on the non-plane path TP15 is less than that on the plane path TP14, it will preferentially select the operation unit P5 corresponding to the non-plane path TP15 as the target operation unit (because the transmission path is shorter). That is, in response to the determination that the total number of components contained in the shortest non-plane path is less than the total number of components contained in the shortest plane path, the task control processor 111 selects a specific free operation unit corresponding to the shortest non-plane path as one of the one or more target operation units to be assigned to the target node. This mechanism fully utilizes the characteristics of the three-dimensional architecture, effectively reducing data transmission latency by selecting the shorter vertical transmission path.

It should be noted that when multiple possible transmission paths have the same length, the task control processor 111 will further consider other factors, such as the computing power of the idle computing unit, the current load, the number of other idle computing units around the considered idle computing unit, and the storage capacity of the surrounding storage units, in order to make a final selection. This selection mechanism based on transmission path length helps to minimize data transmission latency and improve the overall system performance.

Figures 10A to 10C are schematic diagrams illustrating, according to an embodiment of the present disclosure, configuring computation units based on computation graph information to perform corresponding neural network computation tasks.

Referring to Figure 10A, in one embodiment, the task control processor 111 configures computing resources according to the computation graph information TB101 to perform neural network computation tasks. Specifically, for node A at dependency level 1, the system performs the following configuration process:

First, the task control processor 111 analyzes the computational characteristics of node A: (1) The computational load is 200, which is higher than the computational capacity of the standard computational unit (P1-P8) of 100. (2) The number of connections is 2, indicating that the computational results need to be sent to two subsequent nodes. (3) The parent node is null, indicating that the computation can start immediately.

Based on the above analysis, as shown by arrow A101, the task control processor 111 selects two operation units P1 and P2 in the first array 121a to be assigned to node A to perform the corresponding node operation.

Once the configuration is complete, computation units P1 and P2 enter a busy state (represented by a grid pattern) and jointly execute the node computation tasks of node A. The task control processor 111 ensures that these two computation units can work together to process the node computation requirements of node A and prepares to send the computation results to other computation units configured for subsequent nodes B and C.

Referring to Figure 10B, continuing from the first array 121a of Figure 10A. Next, in the first array 121b, operation units P1 and P2 complete node operations and become the preceding operation units (represented by a dotted pattern). Based on the operation graph information TB101, the task control processor 111 determines that the subsequent nodes of dependency level 2 are B and C. The task control processor 111 selects operation unit P9 to execute the node operation task of node B, and selects operation unit P3 to execute the node operation task of node C (the selected target task operation units are indicated by thick boxes). The transmission path between these two operation units and the preceding operation nodes P1 and P2 is the shortest.

Next, as indicated by arrow A102, the system enters the state of the first array 121c. In this state, since the node operation for node A has been completed, the node operation result is integrated from operation units P1 and P2 and transmitted to operation units P3 and P9. Operation units P1 and P2 are reset to an idle state (becoming hollow blocks again). Operation units P9 and P3 then enter a busy state (represented by a grid pattern), and based on the received node operation result for node A, they execute the node operation tasks for nodes B and C respectively.

In one embodiment, when the task control processor 111 needs to configure the data transmission path for the target neural network computing task, it executes a systematic resource configuration process. Specifically, the task control processor 111 first monitors the current operating status of multiple first arrays 121 and multiple second arrays 122, and identifies new idle computing units that have not yet been activated.

After identifying the idle computation units, the task control processor 111 determines the next computation task of the target neural network computation task based on the dependency level information. For example, referring to the embodiment in Figure 10B, when the system is in the first array 121c state, the task control processor 111 identifies nodes D, E, and F of dependency level 3 as new target neural network computation tasks. Then, the task control processor 111 evaluates the characteristics of the newly identified idle computation units and the new target neural network computation tasks, and selects an appropriate new target computation unit. In the example above, the task control processor 111 selects computation units P7, P6, P1, and P2 as new target computation units to execute the node computation tasks of nodes D, E, and F. Based on the positional relationship between the currently executing target computation units (P9, P3) and the newly selected target computation units (P7, P6, P1, P2), the task control processor 111 plans the target data transmission path. Finally, the task control processor 111 sets the routing task for the target switch corresponding to this transmission path, ensuring that the node computation results can be correctly transmitted from the current target computation unit to the new target computation unit, thereby supporting the execution of subsequent computation tasks.

As indicated by arrow A103, the system enters the state of the first array 121d. At this time, the node operations of operation unit P9 (execution node B) and operation unit P3 (execution node C) have been completed (represented by a dotted pattern) and become the preceding operation units. According to the operation graph information TB101, the task control processor 111 determines that the nodes of the subsequent dependency level 3 are D, E, and F. Based on the computing power and computational load, the task control processor 111 selects operation unit P7 to execute the node operation task of node D, selects operation unit P6 to execute the node operation task of node F, and selects operation units P1 and P2 to execute the node operation task of node E.

Next, as indicated by arrow A104, the system enters the state of the first array 121e. Since the node calculations for nodes B and C have been completed, the task control processor 111 obtains the corresponding node calculation results. Because the task control processor 111 determines that the node calculations for nodes D, E, and F will not use the node calculation result C of node C, and that the calculation result C will be used in the subsequent node H, the task control processor 111 temporarily stores the calculation result C in storage unit M2. Furthermore, the node calculation result for node B is transmitted to calculation units P1, P2, P6, and P7. In this state, computation units P1, P2, P6, and P7 become busy (represented by a grid pattern) and execute their respective node computation tasks. Specifically, computation unit P7 executes the node computation for node D, computation unit P6 executes the node computation for node F, and computation units P1 and P2 jointly execute the node computation for node E. Then, computation units P9 and P3 are reset to idle computation units.

Referring to Figure 10C, continuing the example from Figure 10B. In the first array 121f, operation units P1, P2 (performing node operations for node E), operation unit P7 (performing node operations for node D), and operation unit P6 (performing node operations for node F) have completed their corresponding node operations (represented by a dotted pattern) and become the preceding operation units. Based on the operation graph information TB101, the task control processor 111 determines that the subsequent nodes of dependency level 4 are G and H, and determines that node G requires the node operation results of nodes C and D, while node H requires the node operation result of node E. In addition, the node operation result of node F will also be used for the subsequent node I. Therefore, the task control processor 111 temporarily stores the node operation result F corresponding to node F in storage unit M4, because this result will be used for the final node operation of the corresponding node I. Next, the task control processor 111 selects operation unit P9 to execute the node operation task of node G, and selects operation unit P3 to execute the node operation task of node H (indicated by bold boxes).

As indicated by arrow A105, the system enters state 121g of the first array. In this state, the node operation results of nodes D and C are transmitted to operation unit P9, and the node operation result of node E is transmitted to operation unit P3. Operation units P9 and P3 enter a busy state (represented by a grid pattern) and execute the node operation tasks of nodes G and H respectively. At the same time, since operation units P1, P2, P6, and P7 have completed data transmission, these operation units are reset to idle operation units (represented by hollow blocks).

Next, continuing from the aforementioned state, as indicated by arrow A106, the system enters the state of the first array 121h. In this state, computation unit P9 (performing node operations for node G) and computation unit P3 (performing node operations for node H) complete their corresponding node operations (represented by a dotted pattern) and become the preceding computation units. Based on the computation graph information TB101, the task control processor 111 determines that the node of the subsequent dependency level 5 is I, and determines that this node requires the node operation results of nodes F, G, and H, with a computational load of 300. Therefore, the task control processor 111 selects three computation units, P4, P5, and P6, to perform the node operation task of node I (represented by a thick box).

Next, as indicated by arrow A107, the system enters the state of the first array 121i. In this state, the node operation results of node F are integrated from storage unit M4, the node operation results of node G from operation unit P9, and the node operation results of node H from operation unit P3 and transmitted to operation units P4, P5, and P6. These three operation units enter a busy state (represented by a grid pattern) and jointly execute the node operation tasks of node I. Since each operation unit has a node operation capacity of 100, the combination of the three operation units is sufficient to meet the 300 operation requirements of node I. In addition, after the data transmission is completed, the preceding operation units P9 and P3 are reset to idle operation units (represented by hollow blocks).

At this point, the system has completed the node computation tasks for all nodes in the computation graph information TB101. Throughout the process, the task control processor 111 configures appropriate node computation resources sequentially according to the dependency hierarchy information, and properly manages the transmission and temporary storage of node computation results to ensure the correct execution of the neural network computation tasks.

It should be understood that in the above embodiments, for the purpose of illustrating the control method provided by this disclosure, the first array 121 of the same array plane is used only as an example to implement multiple neural network computation tasks of computation graph information. However, this example does not constitute a limitation on the scope of this disclosure. In other embodiments, the task control processor 111 may, as shown in FIG9, select computation units of different array planes to perform node computation tasks according to actual computation needs and resource status, thereby achieving more flexible resource configuration.

Before further describing the embodiments of this disclosure, let's explain the handling mechanism when the system faces insufficient computing resources. Specifically, when the task control processor 111 determines that the number of idle computing units is insufficient to process all target task nodes simultaneously, it will adopt a serialized resource allocation strategy.

Referring to the embodiments shown in Figures 11A to 11D, a scenario will be illustrated: when the system needs to perform node operations with a computational capacity of 200, but each computational unit only has a computational capacity of 100, and the number of computational units available in the system is limited (currently only one computational unit in the second row is available). In this case, the task control processor 111 needs to: (1) prioritize allocating limited computational resources to a portion of the target task nodes; (2) continuously monitor the working status of the computational units; (3) select the best temporary storage location for the results of the completed computation; and (4) dynamically allocate the released computational resources.

This resource management mechanism is particularly suitable for situations where system resources are strained when handling large-scale neural network operations. The following sections will explain how the task control processor 111 ensures the completion of all computing tasks in this scenario through dynamic resource allocation.

Figures 11A to 11D are schematic diagrams illustrating, according to another embodiment of the present disclosure, the configuration of computation units based on computation graph information to perform corresponding neural network computation tasks.

Referring to Figure 11A, in this embodiment, the task control processor 111 faces a situation of limited computing resources. According to the computation graph information TB111, node A at dependency level 1 requires 200 computations, but each computation unit (P1-P4) in the second array 122a only has 100 computations, making it impossible for a single computation unit to independently complete the computation task of node A.

In response to this limitation of computing resources, the task control processor 111 first evaluates the available resources in the second array 122a. After evaluation, the task control processor 111 notices that computing units P1 and P2 can not only establish a direct data transmission channel through the switch S5, but their combined computing power (200) also perfectly meets the computing needs of node A. Based on this evaluation result, the task control processor 111 selects computing units P1 and P2 to jointly execute the computing tasks of node A.

As shown by arrow A111, after resource configuration is complete, computation units P1 and P2 enter a busy state (represented by a grid pattern) and begin execution, while computation units P3 and P4 remain idle (represented by hollow squares) for later use. Simultaneously, storage units M1 to M8 also remain idle, ready to receive the results of subsequent node computations. This resource configuration demonstrates how the system, under limited computing power, can complete high-computational-load tasks by coordinating multiple computation units.

Referring to Figure 11B, continuing the aforementioned scenario, in the second array 122b, following the computational configuration of the second array 122a, computational units P1 and P2 complete the node computation (represented by a dotted pattern) for the corresponding node A. Based on the computation graph information TB111, the task control processor 111 determines that dependency level 2 includes nodes B and C, where node B requires 200 computational units and node C requires 100 computational units. However, since each computational unit in the system only has a computational capacity of 100, the task control processor 111 needs to configure multiple computational units for node B.

Based on this computational requirement, the task control processor 111 selects computation units P3 and P4 to execute the node computation task of node B, and selects storage unit M8 to store the node computation result of node A (because the node computation of node C, which has not yet been executed, requires the node computation result of node A). Under this configuration, computation units P3 and P4 become busy (represented by a grid pattern) and jointly execute the node computation task of node B.

As indicated by arrow A112, the system enters the second array 122c state. In this state, computation units P3 and P4 continue to execute node computations for node B, while computation unit P1 is selected to execute node computation tasks for node C with a computational load of 100. At this time, the node computation results for node A stored in storage unit M8 are transmitted to computation unit P1, while other unassigned computation units and storage units remain idle, ready for subsequent computation needs.

Next, as indicated by arrow A113, the system enters the state of the second array 122d. According to the computation graph information TB111, the parent node of node C is A, and it requires 100 computations. Therefore, the task control processor 111 transmits the computation result of node A in the storage unit M8 to the computation unit P1, so that the computation unit P1 enters a busy state (represented by a grid pattern) to execute the node computation of the corresponding node C.

Since there is one idle computation unit, based on the computation graph information TB111, the task control processor 111 can determine that the next node to be processed is D. Since the parent node of node D is B and requires 100 computations, the task control processor 111 selects computation unit P2 to execute the node computation task corresponding to node D. Computation units P3 and P4 remain busy to complete the node computation corresponding to node B.

As indicated by arrow A114, the system enters the second array 122e state. At this time, computation units P3 and P4 complete the node computation for the corresponding node B (represented by a grid pattern) and become the preceding computation units. According to the computation graph information TB111, since the node computation result of node B will be used for the node computation of nodes D, E, and F, and there are currently no free computation units available for configuration, the task control processor 111 first temporarily stores it in storage unit M7 (represented by a grid pattern). At the same time, since the node computation result of node C needs to be used for the subsequent node computation of node G, the task control processor 111 also temporarily stores it in storage unit M8 (represented by a grid pattern). Furthermore, computation unit P1 has now completed the node computation (represented by a dot pattern) for node C, becoming the preceding computation unit. At this point, the neural network computation task corresponding to dependency level 2 is considered complete. The task control processor 111 selects the next neural network computation task to process. Based on the computation graph information TB111, the task control processor 111 determines that dependency level 3 includes nodes D, E, and F. Node E has a computational load of 200 and requires the node computation results of nodes B and C; node D has a computational load of 100 and requires the node computation result of node B; and node F has a computational load of 100 and requires the node computation result of node B.

The computation unit P2 is currently performing node operations (represented by a grid pattern) for the corresponding node D and is in a busy state.

Referring to Figure 11C, continuing the example from Figure 11B. In the second array 122f, since storage unit M7 temporarily stores the node operation result of node B, and storage unit M8 temporarily stores the node operation result of node C, the task control processor 111 can configure operation units P3 and P4 to execute the node operation task corresponding to node E, and configure operation unit P1 to execute the node operation task corresponding to node F. Operation unit P2 continues to execute the node operation task corresponding to node D.

As indicated by arrow A115, the system enters the state of the second array 122g. In this state, the node operation results of node B and node C are transmitted from storage units M7 and M8 to their respective operation units. The node operation results of node B are transmitted to operation unit P1 assigned to node F and operation units P3 and P4 assigned to node E, and subsequent nodes do not require the node operation results of node B. The task control processor 111 can then delete the node operation results of node B from storage unit M7. On the other hand, because the subsequent node G requires the node operation results of node C, the node operation results of node C in storage unit M8 are retained and not deleted.

Operation units P3 and P4 enter a busy state (represented by a grid pattern) to perform node operations for the corresponding node E. Operation unit P1 enters a busy state to perform node operations for the corresponding node F. At the same time, operation unit P2 completes the node operation for the corresponding node D (represented by a dot pattern) and becomes the preceding operation unit. Since the node operation result of node D needs to be used for subsequent node operations and there is currently no idle operation unit, the task control processor 111 temporarily stores it in storage unit M3 (represented by a grid pattern).

Next, as indicated by arrow A116, the system enters the second array 122h state. At this time, computation units P3 and P4 have completed the node computation for the corresponding node E (represented by a dot pattern), and computation unit P1 has also completed the node computation for the corresponding node F (represented by a dot pattern). These computation units have become preceding computation units and are ready to be reset to idle computation units. At this point, dependency level 3 is completed, and the neural network computation task of dependency level 4 (nodes G and H) begins to be processed.

Because the subsequent node G needs the node operation result of node D, the node operation result of node D will be stored in storage unit M3. On the other hand, because the subsequent node I needs the node operation result of node F, the node operation result of node F will be stored in storage unit M8.

Subsequently, as indicated by arrow A117, the system enters the state of the second array 122i. Based on the computation graph information TB111, the task control processor 111 determines that the nodes in dependency level 4 also include nodes G that have not yet been executed. Therefore, the task control processor 111 selects computation units P3 and P4 to execute the node computation tasks corresponding to node G. Computation unit P2 accumulates the node computation tasks for the corresponding node H.

Referring to Figure 11D, continuing the example from Figure 11C, in the second array 122j, the node operation results of nodes C and D are transmitted from storage units M8 and M3 to their corresponding operation units, respectively. Since node G requires the node operation results of nodes C and D, and its computational load is 200, it needs to be executed by two operation units. Therefore, the task control processor 111 configures operation units P3 and P4 to execute the node operation task of the corresponding node G (represented by a grid pattern). At the same time, based on the computation graph information TB111, the task control processor 111 determines that node H requires the node operation result of node E and its computational load is 100. Therefore, it selects operation unit P2 to execute the node operation task of the corresponding node H. Since the node operation result of node H will be used for the subsequent node operation of node I and there is currently no free operation unit, the task control processor 111 temporarily stores it in storage unit M2 (represented by a mesh pattern). In addition, since the node operation result of node F needs to be used for the subsequent node operation of node I, the task control processor 111 continues to temporarily store it in storage unit M8.

Next, as indicated by arrow A118, the system enters the state of the second array 122k. In this state, operation unit P2 has been reset, and operation units P3 and P4 have completed the node operation (represented by a dot pattern) for the corresponding node G, becoming the preceding operation units. Since the node operation result of node G will be used for the subsequent node operation of node I and there is currently no free operation unit sufficient to execute the node operation of node I, the task control processor 111 temporarily stores it in storage unit M7. At the same time, the node operation of node H is still temporarily stored in storage unit M2, because the result still needs to be used for the subsequent node operation of node I. At this point, dependency level 4 is complete, and we are ready to begin processing neural network computation tasks (node I) at dependency level 5.

Continuing from the state of the second array 122k. As indicated by arrow A119, the system enters the state of the second array 122l. In this state, the task control processor 111 determines, based on the computation graph information TB111, that node I at dependency level 5 requires the node computation results of nodes F, G, and H, and its computational load is 300. Since the computational capacity of each computation unit is 100, three computation units are required to jointly execute the node computation task of node I.

Specifically, the node operation results of node F are transmitted from storage unit M8, the node operation results of node G are transmitted from storage unit M7, and the node operation results of node H are transmitted from storage unit M2 to the corresponding operation units. The task control processor 111 configures operation units P1, P2, and P3 to execute the node operation tasks (represented by a grid pattern) of the corresponding node I.

After the data transfer is complete, the node calculation result of node F has been transferred to the calculation unit P1 and no other node needs to use it, so it can be deleted from the storage unit M8; the node calculation result of node G has been transferred to the calculation unit P2 and no other node needs to use it, so it can be deleted from the storage unit M7; the node calculation result of node H has been transferred to the calculation unit P3 and no other node needs to use it, so it can be deleted from the storage unit M2.

At this point, the system has completed the node computation task configuration for all nodes in the computation graph information TB111. The above example describes how to gradually complete complex neural network computation tasks under limited computing resources through dynamic resource configuration and temporary storage management of computation results.

In one embodiment, the three-dimensional coarse-grained reconfigurable array architecture system 100 of the present invention can also implement a dynamic resource capability adjustment mechanism. Specifically, the configuration controller 110 can dynamically adjust the performance parameters of each storage unit and computing unit according to computing needs.

Regarding storage units, the configuration controller 110 can adjust the following parameters: Storage Capacity Allocation, which adjusts the capacity of a single storage unit by dynamically partitioning or merging storage spaces; Access Bandwidth, which changes the data access speed by adjusting the clock frequency and data bus width of the storage unit; and Cache Configuration, which dynamically adjusts the size and organization of the cache to optimize the data access mode for a specific computing task.

Regarding the computing units, the configuration controller 110 can adjust the following parameters: computational precision, for example, switching floating-point operations to fixed-point operations when high-precision operations are not required to improve processing performance; operating frequency, dynamically adjusting the operating clock of the computing unit according to the complexity of the computing task; and processing mode, for example, reconfiguring a single computing unit into multiple smaller computing units to improve parallel processing capabilities.

In practical implementation, these dynamic adjustments can be achieved through the following technologies: Dynamic Voltage and Frequency Scaling (DVFS), used to adjust the operating voltage and frequency in real time; a Reconfigurable Processing Array, supporting the dynamic partitioning and merging of processing units; an Adaptive Memory Controller, capable of dynamically adjusting memory access modes and bandwidth configurations; and a Dynamic Resource Allocation Engine, responsible for determining the optimal resource allocation strategy based on workload characteristics. In other words, when the computing power of the original processing unit is insufficient to handle the computational load of a specific node, the system can dynamically increase the computing power of the processing unit so that it can be allocated to a specific node. In this way, it is not necessary to use multiple computation units to perform node computation tasks for a specific node, which reduces the complexity of data integration and thus improves overall work efficiency.

Based on the above, the three-dimensional coarse-grained reconfigurable array architecture system and its control method provided by one or more embodiments of this disclosure can achieve improved system performance through the following technical features:

1. By using a staggered stacking configuration of heterogeneous arrays, a three-dimensional data transmission architecture is established, optimizing the data transmission path. Specifically, when data needs to be transmitted between different functional arrays, the system can select the shortest vertical transmission path, avoiding the transmission delays that occur in traditional two-dimensional architectures where data has to travel around multiple components.

2. Through a dynamic resource allocation mechanism, the system can flexibly allocate computing resources according to different computing demands. For example, when encountering node operations requiring a large amount of computing power, the system can configure multiple computing units to jointly execute the computing task, ensuring optimal computing performance.

3. Through intelligent temporary storage management of computation results, the system can maintain an efficient computation process even when computing resources are limited. When the computation result of a node needs to be provided to multiple subsequent nodes, and there are not enough computation units at present, the system will temporarily store the result in the storage unit until all related nodes have completed the computation before releasing it.

4. Utilizing dependency hierarchy information for task scheduling enables the system to maximize the efficiency of computing resources while ensuring computational accuracy. The system will reset completed units to an idle state in a timely manner based on the dependencies between nodes, making them available for subsequent computational tasks.

Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone with ordinary skill in the art may make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended patent application.

100: Coarse-grained reconfigurable array architecture system; 110: Configuration controller; 111: Task control processor; 112: Workload configuration storage circuit unit; 121, 121(1), 121(2), 121a-121i: First array; 122, 122(1), 122(2), 122a-122l: Second array; 130: Input/output interface; TB81, TB101, TB111: Operation graph information; CT81: Data transmission path; TB91: Transmission path information; P, P1-P9: Operation unit; M, M1-M8: Storage unit; S, S1-S5: Switch. A, B, C, D, E, F, G, H, I: Nodes A101-A107, A111-A119: Arrows B51, B52, B61, B62: Vertical connection structure TP14-TP19: Transmission paths S710, S720: Steps

Figure 1 is a block diagram of a three-dimensional coarse-grained reconfigurable array architecture system according to an embodiment of the present disclosure. Figure 2 is a block diagram of a configuration controller for a three-dimensional coarse-grained reconfigurable array architecture system according to an embodiment of the present disclosure. Figure 3A is a schematic diagram of a first staggered stacking configuration of a three-dimensional coarse-grained reconfigurable array architecture system according to an embodiment of the present disclosure. Figure 3B is a schematic diagram of a second staggered stacking configuration of a three-dimensional coarse-grained reconfigurable array architecture system according to an embodiment of the present disclosure. Figure 4A is a schematic diagram of a first layout of the first and second arrays of a three-dimensional coarse-grained reconfigurable array architecture system according to an embodiment of the present disclosure. Figure 4B is a schematic diagram of the second layout of the first and second arrays of a three-dimensional coarse-grained reconfigurable array architecture system according to an embodiment of the present disclosure. Figure 4C is a schematic diagram of the third layout of the first and second arrays of a three-dimensional coarse-grained reconfigurable array architecture system according to an embodiment of the present disclosure. Figure 4D is a schematic diagram of the fourth layout of the first and second arrays of a three-dimensional coarse-grained reconfigurable array architecture system according to an embodiment of the present disclosure. Figure 5 is a schematic diagram of the three-dimensional architecture of the first and second arrays corresponding to the first layout according to an embodiment of the present disclosure. Figure 6 is a schematic diagram of the three-dimensional architecture of the first and second arrays corresponding to the third layout according to an embodiment of the present disclosure. Figure 7 is a flowchart illustrating a control method for a three-dimensional coarse-grained reconfigurable array architecture system according to an embodiment of the present disclosure. Figure 8 is a schematic diagram illustrating the acquisition of computation graph information corresponding to a neural network model according to an embodiment of the present disclosure. Figure 9 is a schematic diagram illustrating the selection of target task computation units based on transmission paths according to an embodiment of the present disclosure. Figures 10A to 10C are schematic diagrams illustrating the configuration of computation units to perform corresponding neural network computation tasks based on computation graph information according to an embodiment of the present disclosure. Figures 11A to 11D are schematic diagrams illustrating the configuration of computation units to perform corresponding neural network computation tasks based on computation graph information according to another embodiment of the present disclosure.

100: Coarse-grained reconfigurable array architecture system

110: Configure the controller

121: First Formation

122: Second Formation

130: Input/Output Interface

Claims (24)

A three-dimensional coarse-grained reconfigurable array architecture system for implementing a neural network model includes: a plurality of first arrays, wherein each first array includes: a plurality of first computation units for performing neural network computation tasks for corresponding nodes of the neural network model; a plurality of first storage units for storing data for corresponding neural network computation tasks, wherein the number of the plurality of first computation units in each first array is greater than the number of the plurality of first storage units; and a plurality of first switches for performing corresponding routing tasks, wherein each first switch is not directly connected to each other, wherein the plurality of first computation units, the plurality of first storage units, and the plurality of first switches are distributed on the array plane of the first arrays; The system comprises multiple second arrays, each second array including: multiple second computation units for performing neural network computation tasks for corresponding nodes of the neural network model; multiple second storage units for storing data for corresponding neural network computation tasks, wherein the number of the multiple second storage units is greater than the number of the multiple second computation units; and multiple second switches for performing corresponding routing tasks, wherein each second switch is not directly connected to each other, wherein the multiple second computation units, the multiple second storage units, and the multiple second switches are distributed on the array plane of the second arrays; and an input/output interface for receiving input data and transmitting processing results. A configuration controller is electrically connected to the plurality of first arrays and the plurality of second arrays, wherein each first array and each second array are stacked alternately, wherein the array adjacent to each first array in the vertical direction corresponding to the array plane is a second array, and wherein the array adjacent to each second array in the vertical direction corresponding to the array plane is a first array, wherein the configuration controller is used to: monitor the operating status of the plurality of first arrays and the plurality of second arrays respectively; Based on the computation graph information corresponding to the neural network model, the enabling and disabling of the plurality of first computation units, the plurality of first storage units, the plurality of first switches, the plurality of second storage units, the plurality of second computation units, and the plurality of second switches are dynamically managed to execute multiple neural network computation tasks of the neural network model. The three-dimensional coarse-grained reconfigurable array architecture system as described in claim 1, wherein the neural network computation tasks include matrix computation, convolution computation, and vector computation, wherein the data of the corresponding neural network computation includes: weight parameters, computation results of node computation, and computation input data. The three-dimensional coarse-grained reconfigurable array architecture system as described in claim 1, wherein in each first array: each first operation unit and each first storage unit are not directly connected to each other, and each first operation unit and each first storage unit are connected through at least one first switch; wherein in each second array: each second operation unit and each second storage unit are not directly connected to each other, and each second operation unit and each second storage unit are connected through at least one second switch; Each first switch in the first array is vertically connected to the second processing unit or the second storage unit of the adjacent second array, wherein a first piece of data from each first array is transmitted via the first switch to the second processing unit or the second storage unit of the adjacent second array to perform cross-layer transmission; wherein each second switch in the second array is vertically connected to the first storage unit or the first processing unit of the adjacent first array, wherein a second piece of data from each second array is transmitted via the second switch to the first storage unit or the first processing unit of the adjacent first array to perform cross-layer transmission. The three-dimensional coarse-grained reconfigurable array architecture system as described in claim 1, wherein the configuration controller includes: a workload configuration storage circuit unit for storing the computation graph information of the neural network model, wherein the computation graph information includes: dependency level information of multiple nodes, indicating the execution order of the multiple nodes in the neural network model, wherein nodes at the same execution level can be executed in parallel, and nodes at different execution levels are executed sequentially; connection quantity information between the multiple nodes, indicating the total number of adjacent nodes connected to each node; data transfer quantity information between the multiple nodes, indicating the data size on the data transfer path; and The computational load information of each of the plurality of nodes is used to indicate the computational load of the node computation performed by each node; and a task control processor is used to dynamically manage the enabling and disabling of the plurality of first computation units, the plurality of first storage units, the plurality of first switches, the plurality of second storage units, the plurality of second computation units, and the plurality of second switches according to the computation graph information, so as to execute the plurality of neural network computation tasks of the neural network model. The three-dimensional coarse-grained reconfigurable array architecture system as described in claim 4, wherein the task control processor is further configured to: determine, based on the dependency hierarchy information, multiple neural network computation tasks corresponding to the multiple nodes, wherein each neural network computation task corresponds to one or more task nodes executed in the neural network computation task; obtain multiple idle computation units from the multiple first computation units and the multiple second computation units according to the current working state of each of the multiple first arrays and the multiple second arrays, wherein the multiple idle computation units have not yet been activated; and sequentially select an unprocessed target neural network computation task from the multiple neural network computation tasks according to the dependency hierarchy information, and perform the following steps: Based on the plurality of idle computing units and the target neural network computing task, one or more target computing units corresponding to one or more target task nodes are selected from the plurality of idle computing units; one or more target storage units corresponding to the one or more target computing units are selected from the plurality of first storage units and the plurality of second storage units; and one or more target switches are selected from the plurality of first switches and the plurality of second switches between the one or more target computing units and the one or more target storage units; each target computing unit is enabled to perform the target node computing of the corresponding target task node; Enable each target storage unit to store the data processed by the corresponding target node; enable each target switch to set the target routing task of the target switch, thereby configuring the target data transmission path of the target neural network operation task. The three-dimensional coarse-grained reconfigurable array architecture system as described in claim 5, wherein the task control processor is further configured to: select one or more target storage units based on the data transfer volume information of each of the one or more target computing units; and select, from the plurality of idle computing units, the one or more target computing units corresponding to the one or more target task nodes based on the number of connections between the one or more target task nodes, wherein a particular target computing unit corresponding to a greater number of connections will be connected to a greater number of target switches. The three-dimensional coarse-grained reconfigurable array architecture system as described in claim 5, wherein the data for the corresponding target node operation includes at least one or more of the following: operation parameters for the corresponding target node operation; node input data for the corresponding target node operation; and node operation results for the corresponding target node operation. The three-dimensional coarse-grained reconfigurable array architecture system as described in claim 5, wherein during the operation of configuring the target data transmission path for the target neural network computation task, the task control processor is further configured to: obtain multiple new idle computation units from the multiple first computation units and the multiple second computation units according to the current operating states of the multiple first arrays and the multiple second arrays; and obtain the next neural network computation task as the new target neural network computation task according to the dependency hierarchy information. Based on the plurality of new idle computing units and the new target neural network computing task, select one or more new target computing units corresponding to one or more new target task nodes from the plurality of new idle computing units; determine the target data transmission path based on the one or more target computing units and the one or more new target computing units; set the target routing task of the target switch corresponding to the target data transmission path, so as to transmit the node computing results of the target node computing performed by the one or more target computing units to the one or more new target computing units through the corresponding target switch. The three-dimensional coarse-grained reconfigurable array architecture system as described in claim 5, wherein in determining the operation of the plurality of neural network computation tasks corresponding to the plurality of nodes based on the dependency hierarchy information, the task control processor is further configured to: assign one or more specific nodes belonging to the same execution level to the same neural network computation task based on the dependency hierarchy information, wherein the one or more specific nodes belonging to the same neural network computation task serve as the one or more task nodes corresponding to the neural network computation task, and are configured to be executed in parallel by one or more computation units of the one or more task nodes, wherein the plurality of neural network computation tasks are ordered according to the corresponding dependency hierarchy information. The three-dimensional coarse-grained reconfigurable array architecture system as described in claim 5, wherein the task control processor is further configured to: determine whether the plurality of idle computing units are sufficient to be allocated to the plurality of target task nodes based on the computational load information of each target task node and the computing power of each idle computing unit; and when the plurality of idle computing units are sufficient to be allocated to the plurality of target task nodes, select and enable the one or more target computing units based on the following information: the computational load information of each target task node; the computing power of each idle computing unit; and the total number of relay components required on the transmission path between each idle computing unit and each corresponding front-end node. The three-dimensional coarse-grained reconfigurable array architecture system as described in claim 5, wherein the task control processor is further configured to: when the plurality of idle computational units are insufficient to be allocated to the one or more target task nodes, perform the following steps: allocate all of the plurality of idle computational units to one or more first target task nodes among the one or more target task nodes; monitor the working status of each computational unit to obtain the specific computational unit that has completed the node computation; select a specific storage unit from the plurality of first storage units and the plurality of second storage units that has the shortest transmission path to the specific computational unit, to store the node computation result of the specific computational unit, wherein the total number of components included in the shortest transmission path is the minimum; The specific computation unit is reset to a new idle computation unit; a third target task node is selected from one or more unconfigured second target task nodes of the one or more target task nodes, and the new idle computation unit is configured to the third target task node to perform the node operation corresponding to the third target task node; and the step of monitoring the working status of each computation unit to obtain the specific computation unit that has completed the node operation is continued until all target task nodes are configured. The three-dimensional coarse-grained reconfigurable array architecture system as described in claim 5, wherein the step of selecting one or more target computation units corresponding to one or more target task nodes for the target neural network computation task from the plurality of idle computation units includes: reacting to a determination that a pre-computation unit corresponding to a pre-computation node has completed the node computation; obtaining the transmission path between each idle computation unit and the pre-computation unit, wherein the transmission path includes: a co-plane path, which is the transmission path when the idle computation unit and the pre-computation unit are located in the same array plane; and a non-co-plane path, which is the transmission path when the idle computation unit and the pre-computation unit are located in different array planes; and In response to the determination that the total number of components contained in the shortest non-coplanar path is less than the total number of components contained in the shortest coplanar path, a specific free operation unit corresponding to the shortest non-coplanar path is selected as one of the one or more target operation units. A control method for a three-dimensional coarse-grained reconfigurable array architecture system, wherein the three-dimensional coarse-grained reconfigurable array architecture system is used to implement a neural network model, comprising: monitoring the working status of multiple first arrays and multiple second arrays of the three-dimensional coarse-grained reconfigurable array architecture system via a configuration controller, wherein each first array includes: multiple first computational units for performing neural network computation tasks corresponding to nodes of the neural network model; multiple first storage units for storing data of the corresponding neural network computation tasks, wherein the number of the multiple first computational units in each first array is greater than the number of the multiple first storage units; and A plurality of first switches are used to perform corresponding routing tasks, wherein each first switch is not directly connected to each other, wherein the plurality of first computation units, the plurality of first storage units, and the plurality of first switches are distributed on an array plane of a first array; wherein each second array includes: a plurality of second computation units for performing neural network computation tasks for corresponding nodes of the neural network model; a plurality of second storage units for storing data of the corresponding neural network computation tasks, wherein the number of the plurality of second storage units is greater than the number of the plurality of second computation units; and Multiple second switches are used to perform corresponding routing tasks, wherein each second switch is not directly connected to each other. The multiple second processing units, multiple second storage units, and the multiple second switches are distributed on the array plane of the second array. The configuration controller is electrically connected to the multiple first arrays and the multiple second arrays, wherein each first array and each second array is stacked alternately. The array adjacent to each first array in the vertical direction corresponding to the array plane is a second array, and the array adjacent to each second array in the vertical direction corresponding to the array plane is a first array. Based on the computation graph information corresponding to the neural network model, the configuration controller dynamically manages the enabling and disabling of the plurality of first computation units, the plurality of first storage units, the plurality of first switches, the plurality of second storage units, the plurality of second computation units, and the plurality of second switches to execute multiple neural network computation tasks of the neural network model. The control method as described in claim 13, wherein the neural network computation task includes matrix computation, convolution computation and vector computation, wherein the data of the corresponding neural network computation includes: weight parameters, computation results of node computation and computation input data. The control method as described in claim 13, wherein in each of the first arrays: each of the first computational units and each of the first switches are not directly connected to each other, and each of the first computational units and each of the first switches are connected through at least one of the first switches; wherein in each of the second arrays: each of the second computational units and each of the second switches are not directly connected to each other, and each of the second computational units and each of the second switches are connected through at least one of the second switches; wherein the first switch of each of the first arrays is vertically connected to the second computational units of the adjacent second arrays, wherein first data is transmitted via the first switch to the second computational units of the adjacent second arrays to perform cross-layer transmission; The second switch of each of the second arrays is vertically connected to the first storage unit of the adjacent first array, wherein the second data is transmitted to the first computing unit of the adjacent first array via the second switch to perform cross-layer transmission. The control method of claim 13, wherein the configuration controller comprises: a workload configuration storage circuit unit for storing the computation graph information of the neural network model, wherein the computation graph information includes: dependency level information of a plurality of nodes, indicating the execution order of the plurality of nodes in the neural network model, wherein nodes at the same execution level can be executed in parallel, and nodes at different execution levels are executed sequentially; connection quantity information between the plurality of nodes, indicating the total number of adjacent nodes connected to each node; data transfer quantity information between the plurality of nodes, indicating the data size on the data transfer path; and computational quantity information of the plurality of nodes, indicating the computational quantity of node operations performed by each node; and A task control processor is used to dynamically manage the enabling and disabling of the plurality of first computation units, the plurality of first storage units, the plurality of first switches, the plurality of second storage units, the plurality of second computation units, and the plurality of second switches based on the computation graph information, so as to execute the plurality of neural network computation tasks of the neural network model. The control method as described in claim 16, further comprising: determining, via the task control processor, the plurality of neural network computation tasks corresponding to the plurality of nodes based on the dependency hierarchy information, wherein each neural network computation task corresponds to one or more task nodes executed in the neural network computation task; and, via the task control processor, obtaining a plurality of idle computation units from the plurality of first computation units and the plurality of second computation units based on the current operating state of each of the plurality of first arrays and the plurality of second arrays, wherein the plurality of idle computation units have not yet been activated; The task control processor, based on the dependency hierarchy information, sequentially selects an unprocessed target neural network computation task from the plurality of neural network computation tasks and performs the following steps: Based on the plurality of idle computing units and the target neural network computing task, one or more target computing units corresponding to one or more target task nodes are selected from the plurality of idle computing units; one or more target storage units corresponding to the one or more target computing units are selected from the plurality of first storage units and the plurality of second storage units; and one or more target switches are selected from the plurality of first switches and the plurality of second switches between the one or more target computing units and the one or more target storage units; each of the target computing units is enabled to perform the target node computing of the corresponding target task node; Enable each of the target storage units to store the data processed by the corresponding target node; enable each of the target switches to set the target routing task of the target switch, thereby configuring the target data transmission path of the target neural network operation task. The control method as described in claim 17, further comprising: selecting one or more target storage units via the task control processor based on the data transfer volume information of each of the one or more target computing units; and selecting, via the task control processor, one or more target computing units corresponding to the one or more target task nodes from among the plurality of idle computing units based on the number of connections between the one or more target task nodes, wherein a particular target computing unit corresponding to a greater number of connections will have a greater number of target switches connected to it. The control method as described in claim 17, wherein the data for the corresponding target node operation includes at least one or more of the following: operation parameters for the corresponding target node operation; node input data for the corresponding target node operation; and node operation results for the corresponding target node operation. The control method of claim 17, wherein the step of configuring the target data transmission path of the target neural network computation task includes: obtaining multiple new idle computation units from the multiple first computation units and the multiple second computation units according to the current working state of each of the multiple first arrays and the multiple second arrays via the task control processor; obtaining the next neural network computation task of the target neural network computation task as a new target neural network computation task via the task control processor according to the dependency level information; The task control processor selects one or more new target computing units corresponding to the new target neural network computing task from among the multiple new idle computing units; the task control processor determines the target data transmission path based on the one or more target computing units and the one or more new target computing units; the task control processor sets the target routing task of the target switch corresponding to the target data transmission path, so as to transmit the node computing results of the target node computing performed by the one or more target computing units to the one or more new target computing units through the corresponding target switch. The control method of claim 17, wherein the step of determining the plurality of neural network computation tasks corresponding to the plurality of nodes according to the dependency hierarchy information includes: via the task control processor, assigning one or more specific nodes belonging to the same execution level to the same neural network computation task according to the dependency hierarchy information, wherein the one or more specific nodes belonging to the same neural network computation task are designated as the one or more task nodes corresponding to the neural network computation task, and are configured to be executed in parallel by one or more computation units of the one or more task nodes to perform corresponding node computations, wherein the plurality of neural network computation tasks are ordered according to the corresponding dependency hierarchy information. The control method as described in claim 17, further comprising: determining, via the task control processor, whether the plurality of idle computing units are sufficient to be allocated to the plurality of target task nodes based on the computational load information of each target task node and the computing power of each idle computing unit; and via the task control processor, when the plurality of idle computing units are sufficient to be allocated to the plurality of target task nodes, selecting and enabling the one or more target computing units based on the following information: the computational load information of each target task node; the computing power of each idle computing unit; and the total number of relay components required to pass through the transmission path between each idle computing unit and each corresponding front-end node. The control method of claim 17, further comprising: when the plurality of idle computing units are insufficient to be allocated to the one or more target task nodes, performing the following steps via the task control processor: allocating all the plurality of idle computing units to one or more first target task nodes among the one or more target task nodes via the task control processor; monitoring the working status of each computing unit via the task control processor to obtain the specific computing unit that has completed the node operation; The task control processor selects a specific storage unit from the plurality of first storage units and the plurality of second storage units that has the shortest transmission path to the specific computation unit, to store the node computation result of the specific computation unit, wherein the total number of components included in the shortest transmission path is the minimum; the task control processor resets the specific computation unit to a new idle computation unit; the task control processor selects a third target task node from the plurality of second target task nodes that have not yet been configured, and configures the new idle computation unit to the third target task node to perform the node computation corresponding to the third target task node; and The task control processor then continuously monitors the working status of each computational unit to obtain the steps for completing the node computation of a specific computational unit, until all target task nodes are configured. The control method of claim 17, wherein the step of selecting one or more target computation units corresponding to one or more target task nodes of the target neural network computation task from the plurality of idle computation units includes: responding, via the task control processor, to a determination that a pre-processor computation unit corresponding to a pre-processor node has completed the node computation; and obtaining, via the task control processor, a transmission path between each idle computation unit and the pre-processor computation unit, wherein the transmission path includes: a co-plane path, which is the transmission path when the idle computation unit and the pre-processor computation unit are located in the same array plane; and A non-coplanar path is a transmission path when the idle computation unit and the preceding computation unit are located in different array planes; and the task control processor, in response to determining that the total number of components contained in the shortest non-coplanar path is less than the total number of components contained in the shortest coplanar path, selects a specific idle computation unit corresponding to the shortest non-coplanar path as one of the one or more target computation units.