TWI902414B - Display panel - Google Patents

Abstract

A display panel including a first substrate, a pixel structure and an insulation layer is provided. The pixel structure has a reflective area and a transmissive area. The pixel structure includes an active device, a pixel electrode, a reflective layer, a capacitor electrode, a common electrode and a transparent conductive pattern. The reflective layer overlaps the pixel electrode and is located in the reflective area. The capacitor electrode and the common electrode are located in the reflective area. The capacitor electrode extends from a drain electrode and electrically connects the pixel electrode. The common electrode overlaps the capacitor electrode and located between the first substrate and the capacitor electrode. The transparent conductive electrode is located in the transmissive area and disposed between the first substrate and the pixel electrode. The transparent conductive electrode electrically connects the common electrode. The insulation layer is disposed between the transparent conductive electrode and the pixel electrode.

Description

Display panel

This invention relates to a display technology, and more particularly to a display panel.

A pixel is the smallest driving unit used by a display panel to display images. To ensure the driving signal of the pixel structure remains at a certain level within a predetermined time interval, most pixel structures incorporate storage capacitors. To achieve better display quality, the size of pixel structures has been continuously reduced, further compressing the space available for storing capacitors. Therefore, how to increase the number of storage capacitors within a limited space without affecting the operating electrical properties of other components is a technical challenge that panel manufacturers need to overcome.

The present invention provides a display panel having a large storage capacitance in its pixel structure.

The display panel of the present invention includes a first substrate, a pixel structure, and an insulating layer. The pixel structure is disposed on the first substrate and has a reflective area and a transmissive area. The pixel structure includes an active element, a pixel electrode, a reflective layer, a capacitor electrode, a common electrode, and a transparent conductive pattern. The pixel electrode is electrically connected to the drain electrode of the active element. The reflective layer is located in the reflective area and overlaps with the pixel electrode. The capacitor electrode is located in the reflective area. The capacitor electrode extends from the drain electrode and is electrically connected to the pixel electrode. The common electrode is located in the reflective area. The common electrode overlaps with the capacitor electrode and is located between the first substrate and the capacitor electrode. The transparent conductive pattern is located in the transmissive area and is disposed between the first substrate and the pixel electrode. The transparent conductive pattern is electrically connected to the common electrode. An insulation layer is disposed between the transparent conductive pattern and the pixel electrode.

In one embodiment of the present invention, the display panel further includes a cladding layer disposed between the pixel electrodes and the first substrate, and covering the active components and capacitor electrodes. The cladding layer has a first opening located in a transparent region, and the first opening overlaps with an insulating layer. The pixel electrodes cover the insulating layer through the first opening.

In one embodiment of the present invention, the insulation layer of the display panel extends into the reflective area and is disposed between the common electrode and the capacitor electrode.

In one embodiment of the present invention, the display panel further includes a first passivation layer disposed between the insulating layer and the pixel electrode. The pixel electrode is also covered by the first passivation layer through a first opening.

In one embodiment of the present invention, the first passivation layer of the display panel extends into the reflective area and is disposed between the active element and the coating layer and between the capacitor electrode and the coating layer.

In one embodiment of the present invention, the display panel further includes a second passivation layer disposed between the first passivation layer and the pixel electrode. The pixel electrode also covers the second passivation layer through the first opening.

In one embodiment of the present invention, the second passivation layer of the display panel extends into the reflective area and is disposed between the cladding layer and the pixel electrode.

In one embodiment of the present invention, the first opening of the cladding layer of the display panel does not penetrate the cladding layer. The cladding layer has a first portion overlapping the first opening and a second portion overlapping the reflective area. The thickness of the first portion is less than the thickness of the second portion, and the pixel electrodes also cover the first portion of the cladding layer.

In one embodiment of the present invention, the display panel further includes a second substrate and a liquid crystal layer. The second substrate is overlapped with the first substrate. The liquid crystal layer is disposed between the first substrate and the second substrate. The thickness of the liquid crystal layer in the transmissive region is greater than the thickness of the liquid crystal layer in the reflective region.

In one embodiment of the present invention, the transparent conductive pattern of the display panel extends to the area outside the penetrating area and partially overlaps with the common electrode. The common electrode is directly coupled to the transparent conductive pattern.

In one embodiment of the present invention, the capacitor electrode of the display panel is electrically coupled to the common electrode to form a first storage capacitor. The portion of the pixel electrode located in the transparent area is electrically coupled to the transparent conductive pattern to form a second storage capacitor.

In one embodiment of the present invention, the display panel described above has a first spacing between its capacitor electrodes and common electrode in the normal direction of the substrate surface of the first substrate. The pixel electrodes and the transparent conductive pattern have a second spacing, and the second spacing is different from the first spacing.

Based on the above, in a display panel of one embodiment of the present invention, the capacitor electrode disposed in the reflective area and the common electrode form a storage capacitor for the pixel structure. A transparent conductive pattern is also provided in the area where the pixel electrode does not overlap with the reflective layer. The portion of the pixel electrode that does not overlap with the reflective layer and the transparent conductive pattern can constitute another storage capacitor. Therefore, the overall storage capacity of the pixel structure can be increased, thereby improving the display quality of the display panel.

Reference will now be made to the exemplary embodiments of the present invention, examples of which are illustrated in the drawings. Wherever possible, the same element symbols are used in the drawings and description to represent the same or similar parts.

Figure 1 is a top view of a display panel according to an embodiment of the present invention. Figure 2 is a cross-sectional view of the display panel of Figure 1. Figures 3A to 3H are top views showing the patterns of the various film layers of the display panel of Figure 1. Figures 4A to 4E are cross-sectional views showing the manufacturing process of the display panel of Figure 1. Figure 2 corresponds to section line A-A' in Figure 1. For clarity, the second substrate 200 and the liquid crystal layer 300 in Figure 2 are omitted from the illustration in Figure 1.

Please refer to Figures 1 and 2. The display panel 10 includes a first substrate 100, a second substrate 200, and a liquid crystal layer 300. The liquid crystal layer 300 is disposed between the first substrate 100 and the second substrate 200. That is, the display panel 10 of this embodiment is a liquid crystal display panel, but is not limited thereto.

Furthermore, the first substrate 100 may be provided with multiple scan lines SL, multiple data lines DL, and multiple pixel structures PX. Each pixel structure PX is electrically connected to a scan line SL and a data line DL. It should be noted that Figure 1 only shows one display unit of the display panel 10, but the display panel 10 may be composed of multiple such display units. For example, the multiple data lines DL may be arranged along direction X and each extend in direction Y, and the multiple scan lines SL may be arranged along direction Y and each extend in direction X, wherein direction X is not parallel to direction Y. Direction X may be selectively perpendicular to direction Y, but is not limited thereto. The multiple pixel structures PX may be arranged in multiple rows and columns along directions X and Y, respectively.

The pixel structure PX includes an active element T, a common electrode CE, a capacitor electrode CPE, and a pixel electrode PE. The active element T has a source electrode SE, a drain electrode DE, a gate electrode GE, and a semiconductor pattern SC. The source electrode SE is electrically connected to a corresponding data line DL. The drain electrode DE is electrically connected to the capacitor electrode CPE. The gate electrode GE is electrically connected to a corresponding scan line SL. More specifically, the portion of the scan line SL extending from the pixel structure PX can serve as the gate electrode GE of the active element T, while the portion of the data line DL extending from the pixel structure PX can serve as the source electrode SE of the active element T. The capacitor electrode CPE extends from the drain electrode DE and is electrically connected to the pixel electrode PE (the pixel electrode PE is electrically connected to the capacitor electrode CPE through the contact hole TH of the first passivation layer 121 and the second passivation layer 122).

In this embodiment, the pixel electrode PE is a light-transmitting electrode. The light-transmitting electrode may be composed of a transparent conductive layer, which includes a transparent conductive material. For example, the material of the light-transmitting electrode includes metal oxides, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, or other suitable oxides, or a stack of at least two of the above. For conductivity considerations, the scan line SL, data line DL, capacitor electrode CPE, common electrode CE, and the source, drain, and gate electrode GE of the active element T are generally made of metallic materials, but are not limited thereto.

A common electrode CE is disposed between the capacitor electrode CPE and the first substrate 100, and overlaps the capacitor electrode CPE along the Z direction. Unless otherwise specified below, the overlap relationship between the two components is defined by the Z direction, and the overlap direction will not be described in detail. It should be noted that the common electrode CE can be electrically coupled to the capacitor electrode CPE to form a first storage capacitor C1. More specifically, the first storage capacitor C1 is formed by the common electrode CE, the capacitor electrode CPE, and an insulating layer 110 located between the common electrode CE and the capacitor electrode CPE. In this embodiment, the common electrodes CE of two adjacent pixel structures PX arranged along the X direction can be electrically connected to each other via a common electrode connection line CL, but this is not a limitation.

First, it should be noted that in this embodiment, the pixel structure PX may have a reflective region RA and a transmissive region TA. The pixel structure PX may also include a reflective layer RL located within the reflective region RA, and the reflective layer RL overlaps with and is electrically connected to the pixel electrode PE. Figure 2 illustrates a scenario where a portion of the pixel electrode PE, PEa, is located between the reflective layer RL and the first substrate 100, but this is not a limitation. In other embodiments, the reflective layer RL may be located between a portion of the pixel electrode PE, PEa, and the first substrate 100, and the reflective layer RL and the pixel electrode PE are electrically connected to each other. A portion of the pixel electrode PE, PEa, overlaps with the reflective layer RL in the reflective region RA, while another portion, PEb, overlaps in the transmissive region TA. From another perspective, the reflective area RA of the pixel structure PX can be defined by the distribution range of the reflective layer RL, while the portion of PEb where the pixel electrode PE does not overlap with the reflective layer RL, data line DL, and scan line SL can define the transmissive area TA of the pixel structure PX (as shown in Figure 1). When the display panel 10 displays an image, the reflective layer RL located in the reflective area RA can reflect ambient light AL to form reflected light REL to display the corresponding image. In the case of insufficient ambient light, a backlight module (not shown in Figure 2) can be turned on as an auxiliary light source, and the light from the backlight module can penetrate another portion of PEb of the pixel electrode PE located in the transmissive area TA to form transmissive light TL to display the corresponding image. That is to say, the display panel 10 of this embodiment can be a transflective display panel.

Specifically, the display panel 10 may also include a first passivation layer 121, a second passivation layer 122, and a cladding layer 130. The first passivation layer 121 is disposed between the capacitor electrode CPE and the pixel electrode PE, and covers the capacitor electrode CPE and the source electrode SE and drain electrode DE of the active element T. The cladding layer 130 is disposed between the first passivation layer 121 and the second passivation layer 122. The cladding layer 130 can be used as a planarization layer to reduce the unevenness of the film layer disposed between the cladding layer 130 and the first substrate 100. That is, the unevenness of the upper surface of the cladding layer 130 (i.e. the surface of the cladding layer 130 facing away from the first substrate 100) is less than the unevenness of the upper surface of the first passivation layer 121 (i.e. the surface of the first passivation layer 121 facing away from the first substrate 100). Since the coating layer 130 can be made of an organic insulating material, in order to prevent peeling between the coating layer 130 and the data lines DL, capacitor electrodes CPE, and source and drain electrodes DE of the active element T, a first passivation layer 121 (e.g., an inorganic insulating layer) is provided between the coating layer 130 and the underlying metal film layer. A pixel electrode PE is disposed on the coating layer 130, and a second passivation layer 122 is located between the coating layer 130 and the pixel electrode PE. The coating layer 130 has a first opening OP1 overlapping the transmittance region TA and a second opening OP2 overlapping the reflective region RA. To further improve the adhesion between the coating layer 130 and the pixel electrode PE of the transparent conductive material, a second passivation layer 122 (e.g., an inorganic insulating layer) may be provided between the pixel electrode PE and the coating layer 130 in this embodiment. However, the invention is not limited thereto. In other embodiments, the display panel may not have the second passivation layer 122. Furthermore, in this embodiment, the thickness of the coating layer 130 along the Z direction is greater than the thicknesses of the first passivation layer 121 and the second passivation layer 122 along the Z direction. For example, the thickness of the coating layer 130 may range from 1 micrometer to 5 micrometers, but is not limited thereto.

In this embodiment, the first passivation layer 121 and the second passivation layer 122 have contact holes TH, which are located in the reflective region RA and penetrate the first passivation layer 121 and the second passivation layer 122 to expose a portion of the capacitor electrode CPE. Furthermore, the first passivation layer 121 and the second passivation layer 122 may also have openings CH that overlap with the first opening OP1. That is, the openings CH of the first passivation layer 121 and the second passivation layer 122 overlap in the penetration region TA. The openings CH penetrate the first passivation layer 121 and the second passivation layer 122 to expose the portion 110p of the insulation layer 110 located in the penetration region TA. The portion PEb of the pixel electrode PE directly covers the portion 110p of the insulating layer 110 located in the penetration region TA through the first opening OP1 of the coating layer 130 and the opening CH of the first passivation layer 121 and the second passivation layer 122.

Since the capacitor electrode CPE and the common electrode CE are made of metal, they cannot extend to the transmittance region TA, making it difficult to further increase the storage capacitance of the pixel structure PX due to the presence of the transmittance region TA. To solve this problem, the display panel 10 of this embodiment also includes a transparent conductive pattern TCP disposed between the first substrate 100 and the pixel electrode PE. The transparent conductive pattern TCP may be composed of a transparent conductive layer, which includes a transparent conductive material. For example, the material of the transparent conductive pattern TCP includes metal oxides, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, or other suitable oxides, or a stack of at least two of the above.

The transparent conductive pattern TCP overlaps the through-area TA and is electrically connected to the common electrode CE. For example, in this embodiment, the transparent conductive pattern TCP may be partially located between the first substrate 100 and the common electrode CE, and the common electrode CE may directly cover a portion of the transparent conductive pattern TCP to achieve an electrical connection between the two. However, the invention is not limited to this. In other embodiments not shown, the transparent conductive pattern TCP may be partially disposed between the common electrode CE and the pixel electrode PE, and directly cover a portion of the common electrode CE to achieve an electrical connection between the two. Specifically, in addition to being located in the penetration region TA, the transparent conductive pattern TCP extends further to the area outside the penetration region TA and is directly coupled to the common electrode. That is, a part of the transparent conductive pattern TCP is located in the penetration region TA, and another part of the transparent conductive pattern TCP overlaps with the common electrode CE and is in direct contact with the common electrode CE. Therefore, the transparent conductive pattern TCP and the common electrode CE have the same potential.

It is particularly noteworthy that, since the portion of the pixel electrode PE located within the through-region TA directly covers the portion 110p of the insulation layer 110 located within the through-region TA, the portion of the pixel electrode PE's PEb can be electrically coupled to the transparent conductive pattern TCP and form a second storage capacitor C2. More specifically, the second storage capacitor C2 is formed by the transparent conductive pattern TCP, the portion of the pixel electrode PE's PEb, and the insulation layer 110 located between the transparent conductive pattern TCP and the portion of the pixel electrode PE's PEb.

On the substrate surface 100s of the first substrate 100, in the normal direction (e.g., direction Z), the capacitor electrode CPE and the common electrode CE have a first spacing S1 (i.e., the thickness of the portion 110a of the insulating layer 110 located in the reflective region RA in direction Z), while the portion PEb of the pixel electrode PE and the transparent conductive pattern TCP have a second spacing S2 (i.e., the thickness of the portion 110p of the insulating layer 110 located in the transparent region TA in direction Z). In this embodiment, the thickness of the portion 110p of the insulating layer 110 located in the transparent region TA in direction Z may be equal to or less than the thickness of the portion 110a of the insulating layer 110 located in the reflective region RA in direction Z. Therefore, the first spacing S1 and the second spacing S2 may be equal, or the second spacing S2 may be less than the first spacing S1, but this is not a limitation.

Since the transparent conductive pattern TCP and the pixel electrode PE are electrically connected to the common electrode CE and the capacitor electrode CPE respectively, the overall storage capacitance of the pixel structure PX is formed by the first storage capacitor C1 and the second storage capacitor C2 connected in parallel. In other words, through the setting of the transparent conductive pattern TCP, additional storage capacitance can be formed in the transparent area TA, thereby increasing the overall storage capacitance of the pixel structure PX and the display quality of the display panel 10.

On the other hand, since the cladding layer 130 has a first opening OP1 overlapping the transmissive region TA, the liquid crystal layer 300 can have different thicknesses in the transmissive region TA and the reflective region RA. For example, in direction Z, the liquid crystal layer 300 located in the reflective region RA has a first thickness d1 (e.g., the distance between the portion PEA of the pixel electrode PE located in the reflective region RA in Figure 2 and the common electrode layer CEL), and the liquid crystal layer 300 located in the transmissive region TA has a second thickness d2 (e.g., the distance between the portion PEb of the pixel electrode PE located in the transmissive region TA and the common electrode layer CEL in Figure 2), and the second thickness d2 is greater than the first thickness d1. That is, the thickness of the liquid crystal layer 300 in the transmissive region TA is greater than its thickness in the reflective region RA. Accordingly, the display panel 10 can achieve the best display effect in both the reflective area RA and the transmissive area TA.

Furthermore, the display panel 10 may also include a common electrode layer (CEL) disposed on the surface of the second substrate 200 facing the liquid crystal layer 300, that is, the common electrode layer CEL is located between the second substrate 200 and the liquid crystal layer 300. In other embodiments not shown, the common electrode layer CEL may be disposed on the first substrate 100 and located between the first substrate 100 and the liquid crystal layer 300. The common electrode layer CEL is located in the reflective region RA and the transmissive region TA. The material of the common electrode layer CEL may include a transparent conductive material, which may include, for example, metal oxides (e.g., indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, or other suitable oxides, or a stack of at least two of the above), but is not limited thereto. For example, the electric field formed between the pixel electrode PE and the common electrode layer CEL can control the orientation of the liquid crystal molecules in the liquid crystal layer 300 to display the corresponding image. In this embodiment, the common electrode layer CEL and the common electrode CE can receive a common voltage, but are not limited thereto.

The manufacturing method of the display panel 10 will be described below by way of example.

Referring to Figures 3A and 4A, a transparent conductive pattern TCP is first formed on the first substrate 100. The material of the first substrate 100 is, for example, glass, quartz, polymer, or other suitable substrate. The material of the transparent conductive pattern TCP may include, for example, metal oxides, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, or other suitable oxides, or a stack of at least two of the above.

Referring to Figures 3B to 3D and Figure 4A, a first metal layer ML1 is then formed on the first substrate 100. Figure 3B is a top view of the first metal layer ML1. In this embodiment, the first metal layer ML1 includes a scan line SL (as shown in Figure 1), a gate electrode GE, a common electrode CE, and a common electrode connection line CL. The material of the first metal layer ML1 may include metals (e.g., molybdenum, aluminum, copper, nickel, chromium), alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or other suitable materials, or a stack of metal materials and other conductive materials.

An insulating layer 110 is formed on a first metal layer ML1. The insulating layer 110 is, for example, a gate insulating layer, and its material may include silicon oxide, silicon nitride, or other suitable dielectric materials. A semiconductor pattern SC and a second metal layer ML2 are formed on the insulating layer 110. Figure 3C is a top view of the semiconductor pattern SC, and Figure 3D is a top view of the second metal layer ML2. In this embodiment, the second metal layer ML2 includes a data line DL (as shown in Figure 1), a source SE, a drain DE, and a capacitor CPE. The capacitor CPE overlaps with the common electrode CE of the first metal layer ML1.

A semiconductor pattern SC can serve as the channel layer of the active element T, with the source SE and drain DE electrically connected to two different regions of the semiconductor pattern SC, respectively. Here, the gate GE, source SE, drain DE, and semiconductor pattern SC can constitute the active element T. The material of the semiconductor pattern SC can include amorphous silicon semiconductors, monocrystalline silicon semiconductors, polycrystalline silicon semiconductors, or metal oxide semiconductors. In this embodiment, the active element T is, for example, an amorphous silicon thin film transistor (a-Si TFT), but is not limited thereto. In other embodiments, the active element T can also be a polycrystalline silicon thin film transistor (poly-Si TFT) or a metal oxide semiconductor thin film transistor (metal oxide semiconductor TFT). In some embodiments, an ohmic contact layer may also be present between the source SE and the semiconductor pattern SC, and between the drain DE and the semiconductor pattern SC. The material of the ohmic contact layer may be, for example, a doped amorphous silicon layer, but is not limited thereto.

In this embodiment, the gate GE may be selectively disposed below the semiconductor pattern SC to form a bottom-gate thin-film transistor, but is not limited thereto. In other embodiments, the gate GE may also be disposed above the semiconductor pattern SC to form a top-gate thin-film transistor. The material of the second metal layer ML2 may include metals (e.g., molybdenum, aluminum, copper, nickel, chromium), alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or other suitable materials, or a stack of metal materials and other conductive materials. Next, a first passivation material layer 121M is formed on the second metal layer ML2. The material of the first passivation layer 121M may include, for example, silicon nitride, silicon oxide, or aluminum oxide, but is not limited thereto.

Please refer to Figures 3E, 4B, and 4C. A cladding layer 130 is formed on the first passivation material layer 121M. Figure 3E is a top view of the first opening OP1 and the second opening OP2 of the cladding layer 130. The cladding layer 130 has a first opening OP1 that overlaps with the transparent conductive pattern TCP and a second opening OP2 that overlaps with the capacitor electrode CPE, and the first passivation material layer 121M is exposed at the first opening OP1 and the second opening OP2. For example, in this embodiment, the material of the coating layer 130 may include a photosensitive material (e.g., a photoresist material), and the steps of forming the coating layer 130 include forming a coating material layer 130M on a first passivation material layer 121M and performing an exposure process and a development process on the coating material layer 130M to remove a portion of the coating material layer 130M and form a first opening OP1 and a second opening OP2. That is, the patterning process of the coating material layer 130M can be completed without an etching process, which helps to save the number of process steps. For example, the coating material layer 130M may be an organic material and may be formed on the first passivated material layer 121M by a coating method (such as spin coating or slit coating), but is not limited thereto.

In this embodiment, the coating layer 130 is, for example, an organic insulating layer, the material of which may include polyester, polyolefin, polyacrylic, polycarbonate, polyepoxide, polystyrene, polyether, polyketone, polyol, polyaldehyde, or other suitable materials, or combinations thereof.

Referring to Figure 4D, after the formation of the cladding layer 130 is completed, a second passivation material layer 122M is formed on the cladding layer 130. The second passivation material layer 122M is, for example, an inorganic insulating layer, and its material may include, for example, silicon nitride, silicon oxide, or aluminum oxide, but is not limited thereto.

Referring to Figures 3F, 3G, and 4E, after the formation of the second passivation material layer 122M is completed, the first passivation material layer 121M and the second passivation material layer 122M are etched to generate a first passivation layer 121 and a second passivation layer 122 having contact holes TH and openings CH, wherein the contact holes TH and openings CH respectively penetrate the first passivation layer 121 and the second passivation layer 122. Figure 3F is a top view of the contact holes TH and openings CH of the first passivation layer 121 and the second passivation layer 122, and Figure 3G is a top view of the pixel electrode PE. For example, the steps of etching the first passivation material layer 121M and the second passivation material layer 122M to form contact holes TH and openings CH are performed in the same photolithography etching process. Therefore, in addition to saving the number of process steps, the number of process masks used can also be reduced, but this is not a limitation. In other embodiments not shown, the patterns of contact holes TH and openings CH can be set on two different masks, and the steps of forming contact holes TH and openings CH are performed in two different photolithography etching processes. After etching the first passivation material layer 121M and the second passivation material layer 122M, the thickness of the portion 110p of the insulating layer 110 located in the penetration region TA in the Z direction can be equal to or less than the thickness of the portion 110a of the insulating layer 110 located in the reflection region RA in the Z direction. For example, in an embodiment where the material of the insulating layer 110 is similar to or the same as that of the first passivation material layer 121M and the second passivation material layer 122M, and the steps of forming the contact hole TH and the opening CH are performed in the same photolithography etching process, the portion 110p of the insulating layer 110 located in the transmission region TA may be partially etched, resulting in the thickness of the portion 110p of the insulating layer 110 located in the transmission region TA being less than the thickness of the portion 110a of the insulating layer 110 located in the reflection region RA.

In this embodiment, since the cladding layer 130 is a photosensitive material (e.g., a photoresist material), in order to avoid the first passivation material layer 121M and the second passivation material layer 122M being blocked by the cladding layer 130 during etching, the size of the contact hole TH is preferably smaller than the size of the second opening OP2 of the cladding layer 130, and the contact hole TH is completely located in the second opening OP2 in the top view direction (i.e., the orthographic projection area of the contact hole TH on the first substrate 100 is smaller than the orthographic projection area of the second opening OP2 of the cladding layer 130 on the first substrate 100, and the orthographic projection of the contact hole TH on the first substrate 100 is completely located within the orthographic projection of the second opening OP2 on the first substrate 100), but this is not a limitation.

After the formation of the contact holes TH and openings CH in the first passivation layer 121 and the second passivation layer 122 is completed, the pixel electrode PE is formed on the second passivation layer 122. The pixel electrode PE extends into the second opening OP2 of the coating layer 130 and is electrically connected to the capacitor electrode CPE via the contact hole TH. The pixel electrode PE also extends into the first opening OP1 of the coating layer 130 and directly covers the portion 110p of the insulation layer 110 exposed by the first opening OP1 of the coating layer 130 and the openings CH of the first passivation layer 121 and the second passivation layer 122. That is, the pixel electrode PE overlaps with the reflective region RA and the transmissive region TA in FIG. 1. In this embodiment, the pixel electrode PE is, for example, a light-transmitting electrode, and the material of the light-transmitting electrode may include a transparent conductive material. For example, the transparent conductive material may include, but is not limited to, metal oxides (e.g., indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, or other suitable oxides, or a stack of at least two of the above).

Referring to Figures 3H and 2, in this embodiment, after the step of forming the pixel electrode PE is completed, a reflective layer RL can be formed on the pixel electrode PE, as shown in Figure 2. Figure 3H is a top view of the reflective layer RL. The reflective layer RL directly covers a portion of the pixel electrode PE and forms an electrical connection with it. The reflective layer RL overlaps with the reflective area RA of Figure 1 but does not overlap with the transmissive area TA of Figure 1. Next, the first substrate 100 and the second substrate 200 are assembled, wherein a liquid crystal layer 300 is filled between the first substrate 100 and the second substrate 200. This completes the fabrication of the display panel 10 of this embodiment.

The following are some other embodiments to illustrate this disclosure in detail. The same components will be marked with the same symbols, and the description of the same technical content will be omitted. For the omitted parts, please refer to the foregoing embodiments, and they will not be repeated below.

Figure 5 is a cross-sectional schematic diagram of a display panel according to another embodiment of the present invention. Figure 6 is a cross-sectional schematic diagram of a display panel according to yet another embodiment of the present invention. Figure 7 is a cross-sectional schematic diagram of a display panel according to yet another embodiment of the present invention. Figure 8 is a cross-sectional schematic diagram of a display panel according to yet another embodiment of the present invention. Referring to Figures 5 to 8, the difference between the display panels 10A, 10B, 10C, and 10D of the embodiments of Figures 5 to 8 and the display panel 10 of Figure 2 is that the size of the second storage capacitor is different. Specifically, in the embodiments of Figures 5 to 8, the second distance between the portion of PEb located within the penetration region TA of the pixel electrode PE and the transparent conductive pattern TCP (i.e., the second distances S2-1, S2-2, S2-3, and S2-4 in Figures 5 to 8) can be greater than the second distance S2 in the embodiment of Figure 2, and the second distances S2-1, S2-2, S2-3, and S2-4 in Figures 5 to 8 can each be different from the first distance S1 between the capacitor electrode CPE and the common electrode CE.

In the embodiment shown in Figure 5, the second passivation layer 122 has an opening CH”, the first passivation layer 121A may have a first opening OP1 of the coated layer 130 and a portion 121p of the opening CH” of the second passivation layer 122 exposed, and the portion 121p of the first passivation layer 121A directly covers the portion 110p of the insulating layer 110. That is, the portion PEb of the pixel electrode PE directly covers the portion 121p of the first passivation layer 121A, and does not directly cover the portion 110p of the insulating layer 110. In this embodiment, a portion PEb of the pixel electrode PE can cover a portion 110p of the insulating layer 110 and a portion 121p of the first passivation layer 121A through the first opening OP1 of the coating layer 130 and the opening CH” of the second passivation layer 122, thereby sandwiching a portion 110p of the insulating layer 110 and a portion 121p of the first passivation layer 121A between the portion PEb of the pixel electrode PE and the transparent conductive pattern TCP. In this embodiment, the second storage electrode... Capacitor C2 is formed by a transparent conductive pattern TCP, a portion PEb of the pixel electrode PE, a portion 110p of the insulation layer 110 located between the transparent conductive pattern TCP and the portion PEb of the pixel electrode PE, and a portion 121p of the first passivation layer 121A. More specifically, the second spacing S2-1 between the portion PEb of the pixel electrode PE and the transparent conductive pattern TCP (i.e., the portion 110p of the insulation layer 110 located within the penetration region TA in the Z direction) The sum of the thickness of the portion 121p of the first passivation layer 121A located within the transmission region TA in the Z direction can be greater than the first gap S1 between the capacitor electrode CPE and the common electrode CE (i.e., the thickness of the portion 110a of the insulation layer 110 located within the reflection region RA in the Z direction). The thickness of the portion 121p of the first passivation layer 121A located within the transmission region TA in the Z direction can be less than or equal to the thickness of the portion 121p of the first passivation layer 121A located within the reflection region RA. 1a is the thickness in the Z direction. For example, the steps of forming the contact hole TH and the opening CH” can be performed in the same photolithography etching process. By adjusting the pattern size and pattern density of the contact hole TH and the opening CH”, after etching, the contact hole TH can penetrate the first passivation layer 121A and the second passivation layer 122, while the opening CH” can penetrate the second passivation layer 122 but not be etched or only partially etch the first passivation layer 121A, but is not limited thereto. In other embodiments, the steps of forming the contact hole TH and the opening CH are performed in two different photolithography processes. In this embodiment, the second thickness d2-1 of the liquid crystal layer 300 in the transmissive region TA can be greater than the first thickness d1 of the liquid crystal layer 300 in the reflective region RA.

However, the present invention is not limited thereto. In the embodiment of FIG6, the second passivation layer 122A may also have a portion 122p located in the penetration region TA, and the portion 122p of the second passivation layer 122A is located within the first opening OP1 of the coating layer 130 and directly covers the portion 121p of the first passivation layer 121A. In this embodiment, the portion PEb of the pixel electrode PE may cover the portion 110p of the insulation layer 110, the portion 121p of the first passivation layer 121A, and the portion 122p of the second passivation layer 122A through the first opening OP1 of the coating layer 130. That is, in addition to the portion 110p of the insulation layer 110 and the portion 121p of the first passivation layer 121A between the portion PEb of the pixel electrode PE and the transparent conductive pattern TCP, a portion 122p of the second passivation layer 122A may also be provided. In this embodiment, the second storage capacitor C2 is formed by the transparent conductive pattern TCP, the portion PEb of the pixel electrode PE, and the portion 110p of the insulation layer 110, the portion 121p of the first passivation layer 121A, and the portion 122p of the second passivation layer 122A located between the transparent conductive pattern TCP and the portion PEb of the pixel electrode PE. More specifically, the second spacing S2-2 between the portion PEb of the pixel electrode PE and the transparent conductive pattern TCP is equal to the sum of the thicknesses of the portion 110p of the insulating layer 110, the portion 121p of the first passivation layer 121A, and the portion 122p of the second passivation layer 122A in the Z direction. The second spacing S2-2 between the portion PEb of the pixel electrode PE and the transparent conductive pattern TCP can be greater than the first spacing S1 between the capacitor electrode CPE and the common electrode CE. The thickness of the portion 122p of the second passivation layer 122A located in the penetration region TA in the Z direction can be less than or equal to the thickness of the portion 122a of the second passivation layer 122A located in the reflection region RA in the Z direction. For example, the first passivation layer 121A and the second passivation layer 122A have contact holes TH but not the aforementioned openings CH or "CH". Therefore, a portion 121p of the first passivation layer 121A and a portion 122p of the second passivation layer 122A remain in the transmittance region TA without being etched; or, after forming the second passivation material layer, the portion of the second passivation material layer located in the transmittance region TA can be partially etched to adjust the thickness of the portion 122p of the second passivation layer 122A. In this embodiment, the second thickness d2-2 of the liquid crystal layer 300 in the transmittance region TA can be greater than the first thickness d1 of the liquid crystal layer 300 in the reflective region RA.

In the embodiment of FIG7, the cladding layer 130A may also have a portion 130p located within the penetration region TA, and the portion 130p of the cladding layer 130A directly covers the portion 121p of the first passivation layer 121A. Specifically, compared to the first opening OP1 in FIG2, FIG5 and FIG6, which penetrates the cladding layer 130, the first opening OP1” of the cladding layer 130A in this embodiment does not penetrate the cladding layer 130A, that is, the cladding layer 130A has a portion 130p located within the penetration region TA and overlapping the first opening OP1”. In this embodiment, a portion PEb of the pixel electrode PE can cover a portion 110p of the insulating layer 110, a portion 121p of the first passivation layer 121A, and a portion 130p of the cladding layer 130A through the first opening OP1” of the cladding layer 130A and the opening CH” of the second passivation layer 122. That is, a portion 110p of the insulating layer 110, a portion 121p of the first passivation layer 121A, and a portion 130p of the cladding layer 130A can be provided between the portion PEb of the pixel electrode PE and the transparent conductive pattern TCP. In this embodiment, the second storage capacitor C2 is formed by a transparent conductive pattern TCP, a portion PEb of the pixel electrode PE, and a portion 110p of the insulating layer 110, a portion 121p of the first passivation layer 121A, and a portion 130p of the cladding layer 130A located between the transparent conductive pattern TCP and the portion PEb of the pixel electrode PE. More specifically, the second spacing S2-3 between the portion PEb of the pixel electrode PE and the transparent conductive pattern TCP is equal to the sum of the thicknesses of the portion 110p of the insulating layer 110, the portion 121p of the first passivation layer 121A, and the portion 130p of the cladding layer 130A in the Z direction. The second spacing S2-3 between the pixel electrode PE (part PEb) and the transparent conductive pattern TCP can be greater than the first spacing S1 between the capacitor electrode CPE and the common electrode CE. The thickness of the portion 130p of the cladding layer 130A located in the transmissive region TA in the Z direction can be less than the thickness of the portion 130a of the cladding layer 130A located in the reflective region RA in the Z direction. For example, a cladding layer 130A with multiple regions of different thicknesses can be formed by a gray tone mask or a half tone mask, but it is not limited thereto. In this embodiment, the second thickness d2-3 of the liquid crystal layer 300 in the transmissive region TA can be greater than the first thickness d1 of the liquid crystal layer 300 in the reflective region RA.

In the embodiment shown in Figure 8, compared to the embodiment shown in Figure 7, a portion 122p of the second passivation layer 122A directly covers a portion 130p of the cladding layer 130A. In this embodiment, a portion PEb of the pixel electrode PE can cover a portion 110p of the insulation layer 110, a portion 121p of the first passivation layer 121A, a portion 130p of the cladding layer 130A, and a portion 122p of the second passivation layer 122A via the first opening OP1” of the cladding layer 130A. That is, an insulation layer 11 can be provided between the portion PEb of the pixel electrode PE and the transparent conductive pattern TCP. The components are: portion 110p of the 0 layer, portion 121p of the first passivation layer 121A, portion 130p of the cladding layer 130A, and portion 122p of the second passivation layer 122A. In this embodiment, the second storage capacitor C2 is composed of a transparent conductive pattern TCP, a portion PEb of the pixel electrode PE, and a portion 110 of the insulation layer 110 located between the transparent conductive pattern TCP and the portion PEb of the pixel electrode PE. p, a portion 121p of the first passivation layer 121A, a portion 130p of the cladding layer 130A, and a portion 122p of the second passivation layer 122A are formed. More specifically, the second spacing S2-4 between a portion PEb of the pixel electrode PE and the transparent conductive pattern TCP is equal to a portion 110p of the insulating layer 110, a portion 121p of the first passivation layer 121A, and a portion 130p of the cladding layer 130A. The thickness of portion 122p of the second passivation layer 122A in direction Z is the sum of the thicknesses of the two passivation layers 122A. The second spacing S2-4 between portion PEb of the pixel electrode PE and the transparent conductive pattern TCP can be greater than the first spacing S1 between the capacitor electrode CPE and the common electrode CE. In this embodiment, the second thickness d2-4 of the liquid crystal layer 300 in the transmissive region TA can be greater than the first thickness d1 of the liquid crystal layer 300 in the reflective region RA.

In the embodiments shown in Figures 5 to 8 above, in addition to sandwiching an insulating layer between a portion of the pixel electrode PE (PEb) and the transparent conductive pattern TCP, by sandwiching a first passivation layer or at least one of a second passivation layer and a coating layer, along with the first passivation layer, between the portion of the pixel electrode PE (PEb) and the transparent conductive pattern TCP, the capacitance of the second storage capacitor formed by the electrical coupling between the portion of the pixel electrode PE (PEb) and the transparent conductive pattern TCP can be adjusted. From another perspective, the second thickness of the liquid crystal layer 300 in the transmissive region TA can also be adjusted simultaneously, allowing for finer adjustments to the applied voltage between the pixel electrode PE and the common electrode layer CEL in both the reflective region RA and the transmissive region TA, achieving the best visual effect.

Furthermore, the insulating layer, the first passivation layer, the second passivation layer, and the cladding layer sandwiched between the pixel electrode PE (partial PEb) and the transparent conductive pattern TCP, besides serving as dielectric layers for adjusting the capacitance, can also extend into the reflective region RA. That is, the insulating layer located in the reflective region RA... The first passivation layer, the second passivation layer, and the coating layer are respectively the insulating layer sandwiched between the portion of PEb of the pixel electrode PE and the transparent conductive pattern TCP. The first passivation layer, the second passivation layer, and the coating layer belong to the same film layer. Therefore, no additional process steps are required to form the dielectric layer sandwiched between the portion of PEb of the pixel electrode PE and the transparent conductive pattern TCP, which can save costs.

In summary, in the display panel of one embodiment of the present invention, the capacitor electrode disposed in the reflective area and the common electrode form a storage capacitor for the pixel structure. A transparent conductive pattern is also provided in the area where the pixel electrode does not overlap with the reflective layer. The portion of the pixel electrode that does not overlap with the reflective layer and the transparent conductive pattern can constitute another storage capacitor. Therefore, the overall storage capacity of the pixel structure can be increased, thereby improving the display quality of the display panel.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

10, 10A, 10B, 10C, 10D: Display panel 100: First substrate 100s: Substrate surface 110: Insulation layer 110a, 110p, 121a, 121p, 122a, 122p, 130a, 130p: Partial layer 121, 121A: First passivation layer 121M: First passivation material layer 122, 122A: Second passivation layer 122M: Second passivation material layer 130, 130A: Coated layer 130M: Coated material layer 200: Second substrate 300: Liquid crystal layer AL: Ambient light C1: First storage capacitor C2: Second storage capacitor CE: Common electrode CEL: Common electrode layer CH, CH”: Via CL: Common electrode connection CPE: Capacitor electrode d1: First thickness d2, d2-1, d2-2, d2-3, d2-4: Second thickness DE: Drain electrode DL: Data line GE: Gate electrode ML1: First metal layer ML2: Second metal layer OP1, OP”: First opening OP2: Second opening PE: Pixel electrode PEa, PEb: Partial RA: Reflective area REL: Reflected light RL: Reflective layer S1: First spacing S2, S2-1, S2-2, S2-3, S2-4: Second spacing SC: Semiconductor pattern SE: Source SL: Scan Line T: Active Component TA: Transmitter Area TCP: Transparent Conductive Pattern TH: Contact Hole TL: Transmitting Light X, Y, Z: Direction A-A’: Section Line

Figure 1 is a top view of a display panel according to one embodiment of the present invention. Figure 2 is a cross-sectional view of the display panel of Figure 1. Figures 3A to 3H are top views showing the patterns of the various film layers of the display panel of Figure 1. Figures 4A to 4E are cross-sectional views showing the manufacturing process of the display panel of Figure 1. Figure 5 is a cross-sectional view of a display panel according to another embodiment of the present invention. Figure 6 is a cross-sectional view of a display panel according to yet another embodiment of the present invention. Figure 7 is a cross-sectional view of a display panel according to yet another embodiment of the present invention. Figure 8 is a cross-sectional view of a display panel according to yet another embodiment of the present invention.

10: Display Panel

100: First substrate

100s:Substrate surface

110: Insulation Layer

110a, 110p: Partial

121: First Passivation Layer

122: Second passivation layer

130: Overlapping layer

200: Second substrate

300: Liquid crystal layer

AL: Ambient Light

C1: First storage capacitor

C2: Second storage capacitor

CE: Common Electrode

CEL: Common Electrode Layer

CH: Opening

CPE: Capacitor electrode

d1: First thickness

d2: Second thickness

DE: 汲極

GE: Gate Extreme

ML1: First metal layer

ML2: Second metal layer

OP1: First opening

OP2: Second opening

PE: Pixel Electrode

PEa, PEb: Partial

RA: Reflection Zone

REL: Reflected light

RL: Reflection Layer

S1: First spacing

S2: Second spacing

SC: Semiconductor Pattern

SE: source

T: Active component

TA: Penetration Zone

TCP: Transparent Conductivity Pattern

TH: Contact Hole

TL: Transmitting Light

Z: Direction

A-A’: section line

Claims (9)

A display panel includes: a first substrate; a pixel structure disposed on the first substrate, the pixel structure having a reflective area and a transmissive area, and the pixel structure including: an active element; a pixel electrode electrically connected to a drain of the active element; a reflective layer located in the reflective area and overlapping the pixel electrode; a capacitor electrode located in the reflective area, extending from the drain electrode and electrically connected to the pixel electrode; and a common electrode located in the reflective area, overlapping the capacitor electrode and located between the first substrate and the capacitor electrode; and A transparent conductive pattern is located in the penetration area and disposed between the first substrate and the pixel electrode, and the transparent conductive pattern is electrically connected to the common electrode; an insulating layer is disposed between the transparent conductive pattern and the pixel electrode; a cladding layer is disposed between the pixel electrode and the first substrate and covers the active element and the capacitor electrode, the cladding layer has a first opening located in the penetration area, and the first opening overlaps the insulating layer, wherein the pixel electrode covers the insulating layer through the first opening; A first passivation layer is disposed between the insulating layer and the pixel electrode, wherein the pixel electrode is further covered by the first passivation layer through the first opening; and a second passivation layer is disposed between the first passivation layer and the pixel electrode, wherein the pixel electrode is further covered by the first opening by at least one of the second passivation layer and the cladding layer. The display panel as described in claim 1, wherein the insulating layer extends into the reflective area and is disposed between the common electrode and the capacitor electrode. The display panel as described in claim 1, wherein the first passivation layer further extends into the reflective area and is disposed between the active element and the cladding layer and between the capacitor electrode and the cladding layer. The display panel as described in claim 1, wherein the second passivation layer further extends into the reflective area and is disposed between the cladding layer and the pixel electrode. The display panel as described in claim 1, wherein the first opening does not penetrate the cladding layer, the cladding layer having a first portion overlapping the first opening and a second portion overlapping the reflective area, the thickness of the first portion being less than the thickness of the second portion. The display panel as described in claim 1 further includes: a second substrate, which overlaps with the first substrate; and a liquid crystal layer disposed between the first substrate and the second substrate; wherein the thickness of the liquid crystal layer in the transmissive region is greater than the thickness of the liquid crystal layer in the reflective region. The display panel as described in claim 1, wherein the transparent conductive pattern extends to the area outside the penetration area and partially overlaps the common electrode, and the common electrode is directly coupled to the transparent conductive pattern. The display panel as described in claim 1, wherein the capacitor electrode is electrically coupled to the common electrode to form a first storage capacitor, and the pixel electrode is electrically coupled to the transparent conductive pattern to form a second storage capacitor. The display panel as claimed in claim 1, wherein in the normal direction of the substrate surface of the first substrate, the capacitor electrode and the common electrode have a first distance, the pixel electrode and the transparent conductive pattern have a second distance, and the second distance is different from the first distance.