TWI901858B - Treatments to improve device performance - Google Patents

Abstract

A method of forming a semiconductor structure includes annealing a surface of a substrate in an ambient of hydrogen to smooth the surface, pre-cleaning the surface of the substrate, depositing a high-k dielectric layer on the pre-cleaned surface of the substrate, performing a re-oxidation process to thermally oxidize the surface of the substrate; performing a plasma nitridation process to insert nitrogen atoms in the deposited high-k dielectric layer, and performing a post-nitridation anneal process to passivate chemical bonds in the plasma nitridated high-k dielectric layer.

Description

Processing to improve component performance

This application is a partial continuation of U.S. Application No. 17/092,039, filed November 6, 2020, which is a partial continuation of U.S. Application No. 16/403,312, filed May 3, 2019, which is U.S. Patent No. 10,872,763, published December 22, 2020, and is a partial continuation of U.S. Application No. 17/062,286, filed October 2, 2020, which claims priority to U.S. Provisional Application No. 62/910,974, filed October 4, 2019, the entire disclosure of which is incorporated herein by reference.

The embodiments disclosed herein generally relate to semiconductor devices, systems, processes, equipment, and manufacturing. More specifically, the embodiments relate to treatments for enhancing device performance in gate structures.

As the size of metal-oxide-semiconductor field-effect transistors (MOSFETs) decreases to achieve high device efficiency and low power consumption, the thickness of traditional silicon dioxide ( _SiO₂ ) gate dielectrics has been reduced to its physical limits. Therefore, replacing silicon dioxide gate dielectrics with high-k dielectric materials to achieve further scaling is inevitable. Among various high-k dielectric materials, ruthenium oxide ( _{HfO₂ )} has been used since the 45 nm MOSFET technology node due to its high dielectric constant and excellent thermal stability on silicon substrates. However, in order to further scale down the equivalent oxide thickness (EOT) of 32 nm MOSFET technology nodes and above, it is problematic to simply reduce the thickness of the high dielectric constant dielectric layer due to the increased leakage current through the high dielectric constant dielectric layer.

Therefore, there is a need for systems and methods for forming thin (e.g., EOT less than 1 nm) high dielectric constant dielectric material layers having a chemical structure that can be controlled to ensure desired structure and electrical properties.

One or more embodiments disclosed herein relate to a method for forming a semiconductor device. In one or more embodiments, the method includes: annealing a substrate surface to form a smooth surface; pre-cleaning the smooth surface to form a pre-cleaned surface; depositing a high-k dielectric layer on the pre-cleaned surface; performing a re-oxidation process to thermally oxidize the substrate; performing a plasma nitriding process to insert nitrogen atoms into the high-k dielectric layer to form a plasma-nitrided high-k dielectric layer; and performing a post-nitriding annealing process to passivate the chemical bonds in the plasma-nitrided high-k dielectric layer.

One or more embodiments disclosed herein relate to a method for forming a semiconductor device. In one or more embodiments, the method includes: annealing a substrate surface to form a smooth surface; forming a high-k dielectric layer on the substrate surface; performing a re-oxidation process to thermally oxidize the substrate surface; performing a plasma nitriding process to insert nitrogen atoms into the high-k dielectric layer to form a plasma-nitrided high-k dielectric layer; and performing a post-nitriding annealing process to passivate the chemical bonds in the plasma-nitrided high-k dielectric layer.

Other embodiments disclosed herein relate to processing systems. In one or more embodiments, a processing system includes: a first processing chamber; a second processing chamber; a third processing chamber; a fourth processing chamber; a fifth processing chamber; and a system controller configured to: anneal a substrate surface in the first processing chamber to form a smooth surface; deposit a high-k dielectric layer on the substrate surface in the second processing chamber; expose the deposited high-k dielectric layer to nitrogen plasma in the third processing chamber to form a plasma-nitrided high-k dielectric layer; perform a re-oxidation process in the fourth processing chamber to thermally oxidize the substrate surface; and anneal the plasma-nitrided high-k dielectric layer in the fifth processing chamber, wherein the substrate is passed through the first, second, third, fourth, and fifth processing chambers without disrupting the vacuum environment in the processing system.

Before describing several exemplary embodiments of this disclosure, it will be understood that this disclosure is not limited to the details of the construction or process steps illustrated in the following description. This disclosure can have other embodiments and can be practiced or carried out in various ways.

As gate structures shrink to smaller sizes, new material structures are being sought to provide improvements. Using high-dielectric-constant dielectric materials increases the dielectric constant of the gate structure compared to conventional gate structures utilizing materials such as silicon oxide. However, similar to silicon oxide, leakage current increases as the thickness of the gate structure decreases. For example, gate leakage increases with decreasing effective oxide thickness. Therefore, this inverse relationship between gate leakage and effective oxide thickness can limit the performance of transistors and the resulting devices.

High-k dielectric materials offer greater channel mobility compared to silicon oxide of similar thickness. As industry continues to seek lower effective oxide thicknesses without increasing gate leakage, efforts to maximize the dielectric constant (also known as the "dielectric constant value") of known high-k dielectric materials are reaching their limits due to morphological characteristics. Prior art has striven to overcome the inherent characteristics of high-k dielectric materials, which allow for setting upper limits on dielectric constant values, and subsequent devices attempt to remodel to integrate new films.

The embodiments described herein provide systems and methods for improving the properties of high-k dielectric materials. By producing high-k dielectric materials exhibiting specific morphologies or grain structures, higher dielectric constants and subsequently improved device performance can be achieved. To control grain formation in exemplary devices, processes can be performed to provide an activated substrate surface that can induce specific grain growth, and a stabilizing film after formation, which can result in a higher dielectric constant.

The embodiments described herein provide a hydrogen annealing process that smooths the substrate surface (e.g., silicon) prior to film deposition. During a subsequent high-temperature annealing process, the hydrogen-silicon bonds break, and the hydrogen is depassivated. This differs from a standard hydrogen passivation process, in which the hydrogen-silicon bonds are maintained by forming the final device.

As used in this specification and the accompanying patent application, the term "substrate" refers to a surface or a portion of a surface on which the process takes place. As will also be understood by those skilled in the art, unless the context clearly indicates otherwise, reference to substrate may also refer to only a portion of a substrate. Furthermore, reference to deposition on a substrate may mean a bare substrate or a substrate on which one or more films or features are deposited or formed.

As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which a film treatment is performed during the manufacturing process. For example, depending on the application, substrate surfaces on which treatments can be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. Substrates may be exposed to pretreatment processes such as polishing, etching, reduction, oxidation, hydroxylation, annealing, and/or baking of the substrate surface. In addition to treatment directly on the surface of the substrate itself, any film treatment steps disclosed herein, as will be shown in more detail below, can also be performed on a lower layer formed on the substrate, and the term "substrate surface" is intended to include such a lower layer as indicated by the context. Thus, for example, in the case where a film/layer or part of a film/layer has already been deposited on the substrate surface, the exposed surface of the newly deposited film/layer becomes the substrate surface.

As used in this specification and the accompanying patent application, the terms "precursor," "reactant," "reactive gas," and similar terms may be used interchangeably to refer to any gaseous substance that can react with the surface of the substrate.

Figure 1 is a schematic top view of an example of a multi-chamber processing system 100 according to some embodiments of the present disclosure. The processing system 100 generally includes a factory interface 102, loading gate chambers 104, 106, transfer chambers 108, 110 with corresponding transfer robots 112, 114, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130. As detailed herein, wafers in the processing system 100 can be processed in the individual chambers and transferred between the chambers without exposing the wafers to the surrounding environment outside the processing system 100 (e.g., the ambient atmospheric environment, such as that present in a factory). For example, wafers can be processed in and transferred between chambers under low-pressure (e.g., less than or equal to about 300 Torr) or vacuum environments without disrupting the low-pressure or vacuum environment between the various processes performed on the wafers within the processing system 100. Thus, the processing system 100 provides an integrated solution for some wafer processing.

Examples of processing systems that can be suitably modified based on the teachings provided herein include the Endura®, Producer®, or Centura® integrated processing system, or other suitable processing systems commercially available from Applied Materials, Inc., Santa Clara, California. It will be anticipated that other processing systems (including those from other manufacturers) may be adapted to benefit from the examples described herein.

In the example shown in Figure 1, the factory interface 102 includes a docking station 140 and a factory interface robot 142 to facilitate wafer transfer. The docking station 140 is configured to receive one or more front-opening unified pods (FOUPs) 144. In some embodiments, each factory interface robot 142 generally includes a blade 148 disposed at one end of the corresponding factory interface robot 142, which is configured to transfer wafers from the factory interface 102 to loading gate chambers 104, 106.

The loading gate chambers 104 and 106 have corresponding ports 150 and 152 coupled to the factory interface 102 and corresponding ports 154 and 156 coupled to the transmission chamber 108. The transmission chamber 108 further has corresponding ports 158 and 160 coupled to the holding chambers 116 and 118 and corresponding ports 162 and 164 coupled to the processing chambers 120 and 122. Similarly, the transmission chamber 110 has corresponding ports 166 and 168 coupled to the holding chambers 116 and 118 and corresponding ports 170, 172, 174, and 176 coupled to the processing chambers 124, 126, 128, and 130. Ports 154, 156, 158, 160, 162, 164, 166, 168, 170, 172, 174, and 176 can be, for example, slit valve openings with slit valves. These slit valves are used to allow the transfer robots 112 and 114 to pass through their transfer wafers and to provide a seal between the respective chambers to prevent the transfer of gas between the respective chambers. Generally, any port is opened for passing through its transfer wafer. Otherwise, the port is closed.

Loading gate chambers 104 and 106, transfer chambers 108 and 110, holding chambers 116 and 118, and processing chambers 120, 122, 124, 126, 128, and 130 are fluidly coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system may include one or more gas pumps (e.g., turbine pumps, cryogenic pumps, coarse adjustment pumps), a gas source, valves, and piping fluidly coupled to each chamber. In operation, a factory interface robot 142 transfers wafers from FOUP 144 through port 150 or 152 to loading gate chambers 104 or 106. The gas and pressure control system then evacuates loading gate chambers 104 or 106. The gas and pressure control system further maintains the transfer chambers 108, 110 and holding chambers 116, 118 in an internal low-pressure or vacuum environment (which may include inert gases). Therefore, the evacuation loading gate chambers 104 or 106 facilitate wafer transfer between, for example, the atmospheric environment of the factory interface 102 and the low-pressure or vacuum environment of the transfer chamber 108.

Using the wafers already emptied from loading gate chambers 104 or 106, transfer robot 112 transfers the wafers through ports 154 or 156 from loading gate chambers 104 or 106 to transfer chamber 108. Transfer robot 112 can then transfer the wafers through corresponding ports 162, 164 to either processing chambers 120, 122 and/or between processing chambers 120, 122 for processing, and through corresponding ports 158, 160 to holding chambers 116, 118 for holding in anticipation of further transfer. Similarly, the transfer robot 114 can access wafers in holding chambers 116 or 118 through ports 166 or 168, and can transfer wafers through corresponding ports 170, 172, 174, 176 to any of the processing chambers 124, 126, 128, 130 and/or between any of these processing chambers for processing, and transfer wafers through corresponding ports 166, 168 to holding chambers 116, 118 for holding pending further transfer. The transfer and holding of wafers within and in each chamber can be conducted in a low-pressure or vacuum environment provided by a gas and pressure control system.

Processing chambers 120, 122, 124, 126, 128, and 130 can be any suitable chamber used for processing wafers. In some embodiments, processing chamber 120 can perform an annealing process, processing chamber 122 can perform a cleaning process, and processing chambers 124, 126, 128, and 130 can perform epitaxial growth processes. In some embodiments, processing chamber 122 can perform a cleaning process, processing chamber 120 can perform an etching process, and processing chambers 124, 126, 128, and 130 can perform corresponding epitaxial growth processes. Processing chamber 122 may be a SiCoNi™ pre-cleaning chamber available from Applied Materials, Inc., Santa Clara, California, USA. Processing chamber 120 may be a Selectra ^™ etching chamber available from Applied Materials, Inc., Santa Clara, California, USA.

System controller 190 is coupled to processing system 100 for controlling processing system 100 or its components. For example, system controller 190 may control the operation of processing system 100 by directly controlling chambers 104, 106, 108, 116, 118, 110, 120, 122, 124, 126, 128, and 130 of processing system 100, or by controlling controllers associated with chambers 104, 106, 108, 116, 118, 110, 120, 122, 124, 126, 128, and 130. In operation, system controller 190 performs data collection and feedback from the corresponding chambers to coordinate the performance of processing system 100.

System controller 190 generally includes a central processing unit (CPU) 192, memory 194, and support circuitry 196. CPU 192 can be any type of general-purpose processor used in industrial environments. Memory 194, or a non-transitory computer-readable medium, is accessible by CPU 192 and can be one or more types of memory, such as random-access memory (RAM), read-only memory (ROM), floppy disk, hard disk, or any other form of digital storage (local or remote). Support circuitry 196 is coupled to CPU 192 and may include cache memory, clock circuitry, input/output subsystems, power supply, and the like. The various methods disclosed herein can be implemented generally under the control of CPU 192 by CPU 192 executing computer instruction code (e.g., as software routines) stored in memory 194 (or in the memory of a specific processing chamber). When the computer instruction code is executed by CPU 192, CPU 192 controls the chamber to perform the process according to the various methods.

Other processing systems may be configured differently. For example, more or fewer processing chambers may be coupled to a transfer device. In the illustrated example, the transfer device includes transfer chambers 108, 110 and holding chambers 116, 118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and/or more or fewer holding chambers (e.g., no holding chambers) may be implemented as transfer devices in a processing system.

Figure 2 is a process flow diagram of a method 200 for forming a semiconductor structure 300 according to one or more embodiments of this disclosure. Figures 3A and 3B are cross-sectional views of a portion of the semiconductor structure 300 corresponding to various states of method 200. It should be understood that Figures 3A and 3B only show partial schematic diagrams of the semiconductor structure 300, and the semiconductor structure 300 may contain any number of transistor segments and additional material having the states shown in the figures. It should also be noted that although the method steps shown in Figure 2 are described successively, including one or more method steps that have been omitted and/or added and/or other process sequences that have been rearranged in a different desired order, they fall within the scope of embodiments of the disclosure provided herein.

Method 200 begins in operation 205 with an annealing process. The annealing process may comprise the peak annealing of the substrate in a hydrogen ( _H₂ ) atmosphere at temperatures ranging from 500°C to 700°C. Annealing may comprise a peak thermal annealing process performed in a rapid thermal processing chamber (such as a RADOX ^™ chamber available from Applied Materials, Inc., Santa Clara, California, USA). The RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in Figure 1. Without being theoretically construed, it is believed that peak annealing of the substrate 302 in a hydrogen ( _H₂ ) atmosphere produces a smooth substrate surface prior to film deposition, thereby allowing for better channel mobility. In one or more embodiments, annealing is used for different purposes compared to a passivation annealing process. In one or more embodiments, annealing in a hydrogen ( _H₂ ) atmosphere causes hydrogen ( _H₂ ) to react with the substrate surface (e.g., silicon (Si)) before film deposition, in order to smooth the substrate surface. In one or more embodiments, in a subsequent high-temperature annealing step, the hydrogen-silicon (H-Si) bond breaks, and the hydrogen is intentionally depassivated after film deposition. In a standard passivation process, on the other hand, the hydrogen-silicon (H-Si) bond is maintained at the end of the process.

In some embodiments, after operation 205, a pre-cleaning process is performed in operation 210 to pre-clean the surface of substrate 302. The pre-cleaning process may include ozone ( _O3 ) pre-cleaning or oxidation of the surface of substrate 302 by using a wet process (such as a Standard Clean 1 ( _SC1 ) solution including _NH4OH (ammonium hydroxide), _H2O2 (hydrogen peroxide), and _H2O (water)) or a dry etching process (e.g., a SiConi ^™ remote plasma-assisted dry etching process), wherein the surface of substrate 302 is exposed to _N2 , _NF3 , and _NH3 plasma byproducts. In a specific embodiment, after hydrogen ( _H2 ) annealing, the pre-cleaning process includes ozone ( _O3 ) pre-cleaning or an SC1 wet process to pre-clean the surface of substrate 302. The pre-cleaning process can be performed in a pre-cleaning chamber, such as processing chamber 122 or 120 as shown in Figure 1.

Although not shown in Figure 2, in some embodiments, operation 210 may occur before operation 205.

In operation 220, as shown in Figure 3A, an interface forming process is performed to form an interface layer 304 on a pre-cleaned surface of substrate 302. The interface forming process may include a suitable thermal oxidation process, such as an enhanced in-situ steam generation (eISSG) process utilizing nitrous oxide ( _N₂O ) gas. Corresponding to one or more monolayers of silicon oxide, the interface layer 304 formed in operation 220 is a thin amorphous silicon oxide ( _SiO₂ ) layer having a thickness between about 3 Å and about 10 Å (e.g., about 5 Å). In some embodiments, the interface layer 304 can be formed by an in-situ steam generation (ISSG) process using _H₂ and _O₂ gases or a rapid thermal oxidation (RTO) process using _NH₃ and _O₂ gases. The interface layer 304 can serve as a nucleation layer for a high-k dielectric layer to be deposited thereon and improve the quality of the interface between the substrate 302 and the high-k dielectric layer (e.g., interface state density, accumulated capacitance, frequency dispersion, and leakage current). The interface formation process can be performed in a processing chamber, such as processing chambers 120, 122, 124, 126, 128, or 130 as shown in Figure 1.

In some embodiments, the interface formation process in operation 220 is omitted and the interface layer 304 is not formed before the high-k dielectric material layer is deposited on the substrate 302. In that case, in operation 250 or operation 290 described below, the interface layer 304 is formed by a thermal oxidation process that thermally oxidizes the substrate 302 through the high-k dielectric material layer deposited on the substrate 302. In operation 250 or operation 290, the interface layer 304 formed by the thermal oxidation process may be sufficiently thick to ensure reliable device characteristics (e.g., interface state density, accumulated capacitance, frequency dispersion, and leakage current) and reduce atomic diffusion from the high-dielectric-constant dielectric material layer with a thickness between about 0.3 nm and about 1 nm (e.g., about 0.5 nm) to the substrate 302.

In operation 230, a deposition process is performed to deposit a high-k dielectric layer 306 on the exposed surface of the semiconductor structure 300 (i.e., interface layer 304 if it is formed in operation 220, as shown in Figure 3B, and substrate 302 if it is not formed in operation 220). The high-k dielectric layer 306 may be formed _from a high-k dielectric material, such as ruthenium dioxide ( _HfO2 ), zirconium dioxide ( _ZrO2 ), _yroxide ( _Y2O3 ), or aluminum oxide ( _Al2O3 ). The deposition process may include atomic layer deposition (ALD) processes, in which metal-containing precursors and oxygen-containing precursors are alternately fed to the exposed surfaces of the semiconductor structure 300. In some embodiments, the metal-containing precursor is rinsed before the oxygen-containing precursor is fed. The metal may be a transition metal, such as ruthenium (Hf), zirconium (Zr), or titanium (Ti); a rare earth metal, such as lanthanum (La), lithium (Yb), or thorium (Y); an alkaline earth metal, such as strontium (Sr); or other metals, such as aluminum (Al). For the oxidant, any oxygen-containing precursor that can react with the metal may be used. For example, the oxygen-containing precursor may be or include water, diatomic oxygen, ozone, hydroxyl-containing precursors or alcohols, nitrogen- and oxygen-containing precursors, plasma-enhanced oxygen including locally or distally enhanced oxygen, or any other material including oxygen that can be integrated with a metal to create a metal oxide layer above substrate 302. In one example, the metal-containing precursor is iron tetrachloride ( _HfCl₄ ) and the oxidant is water ( _H₂O ) to form an iron dioxide ( _HfO₂ ) layer. The ALD process can be performed at a temperature between about 200°C and about 400°C, for example, about 270°C. The high-k dielectric layer 306 deposited by the ALD process may be amorphous and have a thickness between about 10 Å and about 30 Å. The deposition process can be performed in a processing chamber, such as processing chambers 120, 122, 124, 126, 128, or 130 as shown in Figure 1.

In operation 240, an optional post-deposition annealing process is performed to harden and densify the deposited high-k dielectric layer 306. Crystallization of the deposited amorphous high-k dielectric layer 306 may occur. The post-deposition annealing process may include thermal annealing performed in an inert atmosphere (such as nitrogen ( _N₂ ) and argon (Ar) atmosphere) in a rapid thermal processing (RTP) chamber (such as a RADOX™ chamber available from Applied Materials, Inc., Santa Clara, California, USA). The RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in Figure 1. The post-deposition annealing process can heat-harden and densify the interface layer 304 and the high dielectric constant dielectric layer 306.

The post-deposition annealing process can be performed at temperatures between approximately 500°C and approximately 800°C and at pressures between approximately 0.01 Torr and 10 Torr for approximately 1 second and approximately 60 seconds, respectively.

In operation 250, instead of the post-deposition annealing process in operation 240, an optional re-oxidation process is performed to thermally oxidize the substrate 302. The re-oxidation process may include a thermal annealing process performed in an oxygen ( _O2 ), nitrous oxide ( _N2O ), and _H2 atmosphere in a rapid thermal processing (RTP) chamber (such as a RADOX™ chamber available from Applied Materials, Inc., Santa Clara, California, USA). The RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in Figure 1. The re-oxidation process in operation 250 can thermally oxidize the lower layer through the high dielectric constant dielectric layer 306, and therefore if the interface layer 304 is formed to a thickness between about 3 Å and about 10 Å in operation 220, the interface layer 304 is thickened, and if the interface layer 304 is not formed in operation 220, the interface layer 304 is formed in the substrate 302 near the interface with the high dielectric constant dielectric layer 306.

The re-oxidation process can be performed at temperatures between approximately 400°C and approximately 900°C and at pressures between approximately 0.01 Torr and 100 Torr for approximately 1 second and approximately 30 seconds, respectively.

In operation 260, a plasma nitriding process is performed to insert nitrogen atoms into vacancies and defects in the high-k dielectric layer 306. The plasma nitriding process can be a DPN process performed in a decoupled plasma nitriding (DPN) chamber (such as a CENTURA® DPN chamber available from Applied Materials, Inc., Santa Clara, California, USA). The DPN chamber can be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in Figure 1. The plasma nitriding process exposes a high-k dielectric layer 306 to nitrogen plasma, allowing nitrogen radicals or nitrogen atoms to be integrated into the high-k dielectric layer 306 throughout its entire thickness. During the plasma nitriding process, nitrogen atoms can form metastable bonds with oxygen (O). Gases that can be used in the plasma process include nitrogen-containing gases, such as nitrogen ( _N₂ ), ammonia ( _NH₃ ), or mixtures thereof. In one example, the nitrogen gas is ammonia ( _NH₃ ) mixed with about 3% to about 8% nitrogen ( _N₂ ). Due to the integration of nitrogen into vacancies and defects in the deposited high-k dielectric layer 306, the plasma nitriding process may not change the thickness of the high-k dielectric layer 306.

The nitriding process can be performed at temperatures between approximately 0°C and approximately 500°C for approximately 10 seconds and approximately 300 seconds, respectively.

In operation 270, an optional thermal nitriding process is performed to further insert nitrogen atoms into vacancies and defects in the plasma-nitrided high-k dielectric layer 306. The thermal nitriding process may include a thermal annealing process in an ammonia (NH3) atmosphere performed in a rapid thermal processing ( _RTP ) chamber (such as a RADOX ^™ chamber available from Applied Materials, Inc., Santa Clara, California, USA). The RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in Figure 1.

The thermal nitriding process can be performed at temperatures between approximately 700°C and approximately 900°C, and at pressures between approximately 10 Torr and 740 Torr, for approximately 10 seconds and approximately 300 seconds, respectively.

In operation 280, a post-nitriding annealing process is performed to passivate the remaining chemical bonds in the plasma-nitrided high-k dielectric layer 306. The post-nitriding annealing process may include a spiked thermal annealing process in a nitrogen ( _N₂ ) and argon (Ar) atmosphere performed in a rapid thermal treatment (RTP) chamber (such as a RADOX ^™ chamber available from Applied Materials, Inc., Santa Clara, California, USA). The RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in Figure 1. The post-nitriding annealing process can passivate the metastable nitrogen bonds formed in the plasma nitriding process during operation 260, and can result in the crystallization of an amorphous high-dielectric-constant dielectric layer 306.

The peak heat annealing process can be performed at temperatures between approximately 700°C and approximately 850°C and at pressures between approximately 10 Torr and 740 Torr for approximately 1 second and approximately 30 seconds, respectively.

In operation 290, instead of the post-nitriding annealing process in operation 280, a post-nitriding annealing and re-oxidation process is performed to simultaneously passivate the remaining chemical bonds in the high-k dielectric layer 306, as in operation 280, and the substrate 302 is thermally oxidized, as in operation 250. The post-nitriding annealing and re-oxidation process in operation 290 is the same as the re-oxidation process in operation 250. Therefore, details of the post-nitriding annealing and re-oxidation process in operation 290 are omitted herein.

In the embodiments described herein, systems and methods are provided for forming high-quality thin high-k dielectric material layers. The properties of such high-k dielectric material layers can be well controlled. For example, the nitriding processes in operations 260 and 270 can be controlled to provide nitrogen integration in the high-k dielectric layer 306 between about 3 atomic% and about 20 atomic% to achieve a higher dielectric constant value compared to higher nitrogen integration and better structural stability compared to lower nitrogen integration. The annealing processes in operations 240, 270, 280, and 290 can also be controlled to provide grains in the high-k dielectric layer 306 having a size greater than about 20 Å, thereby reducing leakage current through the high-k dielectric layer 306.

Figure 4 is a process flow diagram of a method 400 for forming a semiconductor structure 500 according to one or more embodiments of the present disclosure. In one or more embodiments, the operation of method 400 may be performed in one or more chambers integrated on a multi-chamber processing system 100 as previously described.

Method 400 may include one or more operations prior to the method operations mentioned at the beginning, including pretreatment, deposition, etching, polishing, cleaning, or any other operations that may be performed prior to the described operations. The method may include multiple optional operations as indicated in the figures, which may or may not be specifically associated with the method according to the art. For example, many operations are described to provide a broader range of structure formation processes, but such operations are not critical to the art, or may be performed by alternative methods as will be discussed further below. Method 400 describes operations schematically illustrated in Figures 5A through 5F, the description of which will be combined with the operational description of Method 400. It will be understood that Figures 5A through 5F show only partial schematics, and the substrate may contain any number of transistor segments and additional material having the state shown in the figures.

Method 400 may relate to developing alternative operations of a semiconductor structure to a specific manufacturing operation. Although in some embodiments, method 400 may be performed on a substrate structure, in some embodiments, the method may be performed after other materials have been formed. As shown in Figure 5A, semiconductor structure 500 may represent an element after a certain process has been completed. For example, substrate 505 may be a planar material or may be a structured element that may include one or more materials configured or defined as pillars, trenches, or other structures, as will be understood, such structures are similarly covered by the present art. Substrate 505 may include any number of materials, including silicon or silicon-containing materials, such as silicon oxides, nitrides, and carbides, and any other materials that may be integrated within the structure.

One or more material layers may be formed over some or all of the substrate 505, and at least partially within the substrate, to produce a structure that may be a planarized or structured material in the embodiments. As a non-limiting example, the substrate 505 may be or include silicon, or may include a surface amount of silicon formed over additional material (such as silicon oxide), and may be a reduced portion of silicon oxide, leaving the silicon exposed surface. The substrate 505 may include native oxide 510, as shown in Figure 5A. In some embodiments, the material exposed at the surface of the substrate 505 may be etched, planarized, or otherwise treated to produce a discontinuous pattern. Although shown as a single example, it will be understood that the element may include small segments integrated into a larger process, which may include any number of additional segments that may be similar to or different from the object shown. The substrate 505 can be housed or positioned within the processing area of a semiconductor processing chamber, and method 400 can be performed to produce a semiconductor material, such as a high-dielectric-constant dielectric material, on the substrate.

Method 400 may begin an annealing process in operation 405. The annealing process may consist of spike annealing of the substrate in a hydrogen ( _H2 ) atmosphere at a temperature ranging from 500°C to 700°C. Annealing may include a spike thermal annealing process performed in a rapid thermal processing chamber (such as a RADOX ^™ chamber available from Applied Materials Inc., Santa Clara, USA). The RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in Figure 1. Without being theoretically construed, it is believed that spike annealing of the substrate 505 in a hydrogen ( _H2 ) atmosphere produces a smooth substrate surface prior to film deposition, thereby allowing for better channel mobility. In one or more embodiments, annealing is used for different purposes compared to a passivation annealing process. In one or more embodiments, annealing in a hydrogen ( _H₂ ) atmosphere causes hydrogen ( _H₂ ) to react with the substrate surface (e.g., silicon (Si)) before film deposition, in order to smooth the substrate surface. In one or more embodiments, in a subsequent high-temperature annealing step, the hydrogen-silicon (H-Si) bond breaks, and the hydrogen is intentionally depassivated after film deposition. In a standard passivation process, on the other hand, the hydrogen-silicon (H-Si) bond is maintained at the end of the process.

In some embodiments, following operation 405, in operation 410, method 400 may include removing native oxide 510 (as shown in Figure 5A) from substrate 505. Removal of native oxide 510 may be or include flowing fluorinated and hydrogen-containing precursors. The fluorinated precursor may be or include nitrogen trifluoride and any other fluorinated precursor. The hydrogen-containing precursor may be characterized by an amino group [ _-NH₂ ] or other nitrogen- or hydrogen-containing groups. For example, the hydrogen-containing precursor may be or include nitrogen- and hydrogen-containing precursors, such as ammonia as a non-limiting example. Flowing may include flowing the fluorinated and hydrogen-containing precursors into a distal plasma region. The distal plasma region may be fluid-coupled to a substrate processing region. A plasma can be formed to produce a plasma effluent. The flow rates of the fluorine-containing precursor and the hydrogen-containing precursor can be characterized by atomic flow rates of hydrogen and fluorine in a ratio of less than 1:2. The native oxide 510 is removed by flowing the plasma effluent into the substrate processing area while simultaneously forming a solid byproduct on the substrate surface. Unbound by any particular theory, the flow can leave a fluorine layer residue on the substrate surface, which promotes interface formation at operation 415, where fluorine end-capping is used to enhance reliability. The solid byproduct is sublimated by increasing the substrate temperature to a sublimation temperature higher than that of the solid byproduct. After sublimation, the substrate 505 contains no or substantially no native oxide. Removal may be or include the removal of the native oxide to a depth of up to or about 20 Å.

Method 400 may include SiConi ^™ etching in operation 410, which may be a remote plasma-assisted dry etching process involving simultaneous exposure of the substrate (such as substrate 505 in Figure 5A) to _H₂ , _NF₃ , and/or _NH₃ plasma byproducts. Removal of native oxides in operation 410 may be performed by an in-situ dry chemical process, wherein the substrate surface may not be exposed to the atmosphere or an oxygen-containing environment. Removal of native oxides in operation 410 may be performed in a first processing chamber in some embodiments of method 400. Method 400 may include transferring the substrate from the first processing chamber to a second processing chamber prior to forming a high-dielectric-constant dielectric material in operation 420. Method 400 may include performing operations in one or more processing chambers without exposing the substrate surface to the atmosphere or air. Method 400 may include maintaining a vacuum within system 100 during removal in operation 410. Maintaining an integrated vacuum can advantageously reduce surface contamination. Transfer may occur between one or more chambers on a single platform or between chambers on multiple platforms. However, by utilizing a single platform, it is better to ensure that the substrate is not exposed to oxygen and/or moisture environments.

In one or more embodiments, in operation 415, method 400 may include feeding nitrous oxide and thermally annealing the substrate surface to form an oxide-containing interface. As shown in Figure 5B, the nitrous oxide 515 fed to substrate 505 can help control how much of the substrate 505, having a surface free of natural oxides, can be oxidized to form an oxide-containing interface 520, as shown in Figure 5C. Operation 415 may include a heat-based reaction using steam, such as an in-situ steam generation (ISSG) process, whereby oxidation occurs at a lower rate compared to habitual heat techniques utilizing hydrogen and/or oxygen. Nitrogen may be used as a carrier of oxygen and may not be part of the interface or substrate. The resulting oxygen-containing interface may be of high quality and highly ordered, meaning that the crystal structure has no or is substantially free of defects. This provides an interface 520 that prevents nitrogen from approaching the channel region in subsequent operations, thus preventing leakage. The resulting oxide-containing interface may include silicon dioxide. The formed oxide-containing interface 520 may have a thickness of up to or about 5 Å. Method 400 may include removing a thicker native oxide in operation 410, which may be replaced in subsequent operations by a thinner oxide-containing interface 520.

Method 400 may include delivering a pretreatment precursor to a substrate. The pretreatment precursor may be or include a nitrogen-containing precursor or an oxygen-containing precursor. The precursor may contact the substrate and may form or introduce reactive ligands on exposed surfaces of the substrate, such ligands being illustrated as ligand 525 in Figure 5D. Unlike the prior art, this technique utilizes a pretreatment configured to produce the ordered growth of a high-k dielectric material in subsequent operations.

For example, in some embodiments, the substrate may be or include an exposed surface of silicon. The substrate 505 itself may be silicon or some other silicon-containing material that has been reduced or modified to present a silicon surface. As a non-limiting example, the substrate 505 may include silicon oxide, and the initial pretreatment may include removing oxygen from the structure surface, such as using a hydrogen-containing precursor, for example. A thin surface layer of silicon may then be exposed. Without being bound by any particular theory, in some embodiments, silicon may provide improved substrate properties for receiving nitrogen-containing precursors relative to silicon oxide. This can provide excellent formation of certain high-dielectric-constant dielectric materials.

The pretreatment precursor may be or include any nitrogen- or oxygen-containing precursor. Oxygen-containing precursors may be characterized by a hydroxyl group [-OH], which may be integrated on the surface of substrate 505. Nitrogen-containing precursors may be characterized by an amino group [ _-NH₂ ], or other nitrogen-containing groups. For example, nitrogen-containing precursors may be or include nitrogen- and hydrogen-containing precursors (such as ammonia as a non-limiting example), nitrogen- and oxygen-containing precursors, or any other precursor including nitrogen.

In some embodiments, surface end-capping may be hydroxyl or amino end-capped. Method 400 may subsequently include forming a high-dielectric-constant dielectric material on the substrate in operation 420. This technique can cover any formation or deposition of a high-dielectric-constant material, although in some embodiments, formation operation 420 may be or include atomic-layer deposition, or any other atomic-layer deposition chamber. Formation may be performed directly after pretreating the substrate surface and may be performed in the same chamber as pretreating or in an additional chamber, such as an additional chamber integrated on the same system (such as system 100). In some embodiments, vacuum conditions may be maintained while the substrate is transferred from the pretreating chamber to the deposition or formation chamber, which may limit exposure of the substrate to air.

In the case of performing an atomic layer deposition process to form a high dielectric constant dielectric material, a metal-containing precursor can be fed to a substrate to react with a pretreated surface. For example, a precursor containing a transition metal, a metal-depleted precursor, or a lanthanum-containing precursor can be fed to a processing chamber to interact with reactive ligands exposed on the substrate from the pretreatment. An oxygen-containing precursor can then be fed in a second operation, such as after rinsing the metal-containing precursor. This can produce an oxide layer by atomic layer deposition, such as layer 530a as shown in Figure 5E. In a non-limiting example, the inertium-containing precursor may be fed in a first operation and the oxidant may be fed in a second operation for producing an inertium oxide film. Additional metal-containing precursors may include zirconium-containing precursors for producing zirconium-containing materials, and any other amount of metal-containing precursors for producing additional metal oxide structures. For the inertium-containing precursor, and similarly for any alternative metal, the precursor may be or include a halogen-containing precursor, an oxygen-containing precursor, a hydrogen-containing precursor, or a carbon-containing precursor, all of which incorporate inertium.

For the oxidant, any oxygen-containing precursor that can react with the metal-containing material can be used. For example, the oxygen-containing precursor may be or include water, diatomic oxygen, ozone, hydroxyl-containing precursors or alcohols, nitrogen- and oxygen-containing precursors, plasma-enhanced oxygen including locally or distally enhanced oxygen, or any other material that can integrate with a metal (such as iron) to produce a metal oxide material on the substrate. Furthermore, any of the metal-containing materials mentioned above can be used in embodiments of the present invention and may include any of the grouped metals, which may include and may not be limited to iron, zirconium, silicon, lanthanum, aluminum, titanium, strontium, or combinations thereof, such as, for example, iron silicate.

When performing the pretreatment according to embodiments of the present invention, the structure of the metallic material can be formed or deposited in an ordered manner to produce a more uniform grain structure. This can be achieved by forming reactive ligands of the pretreatment precursor over a more structured surface material (such as silicon). Furthermore, additional improvements can be provided by performing pretreatment exposure under certain conditions.

Pretreatment can be performed at temperatures configured to activate precursors and/or substrate surfaces. For example, where nitrogen- and hydrogen-containing precursors can be used as pretreatment precursors, the substrate can be maintained at a temperature greater than or about 300°C while the precursors are fed. Similarly, pretreatment using oxygen-containing precursors can also be performed while maintaining a substrate temperature greater than or about 300°C. For any pretreatment operation, the substrate can also be maintained at temperatures greater than or about 400°C, greater than or about 500°C, greater than or about 600°C, greater than or about 700°C, greater than or about 800°C, or higher. Effectiveness may decrease as the pretreatment temperature is reduced to below or about 500°C. Similarly, increasing the temperature to above or about 700°C may not improve nucleation, and excess precursors may integrate on the surface, which can degrade the migration rate of the elements. Therefore, in some embodiments, the temperature can be maintained between about 500°C and about 700°C during the pretreatment period.

Similarly, exposure time can affect the amount of nitrogen-containing precursor integrated and thus limit the migration rate loss of the resulting components. Precursor exposure can be less than or about 3 minutes, and in some embodiments, the exposure time can be less than or about 2.5 minutes, less than or about 2 minutes, less than or about 1.5 minutes, less than or about 1 minute, less than or about 45 seconds, less than or about 30 seconds, less than or about 15 seconds, or less. Once the appropriate amount of amines has been integrated, formation can be performed. Formation, including atomic layer formation, can be performed at any temperature, but in some embodiments, atomic layer deposition can be performed at temperatures below or about the temperature at which the pretreatment was performed, regardless of whether the operation is performed in the same or different chambers. For example, atomic layer deposition may be performed at a second temperature relative to the pretreatment temperature, and in embodiments the formation temperature may be less than or about 500°C, and may be less than or about 450°C, less than or about 400°C, less than or about 350°C, less than or about 300°C, less than or about 250°C, or even lower.

After a high-dielectric-constant material layer has been formed or deposited, one or more post-processing steps may be performed. In some embodiments, the substrate may be transferred from a deposition chamber to another chamber or assembly of chambers for post-processing material. Similar to the explanation above, the transfer may occur on a single processing system having multiple chambers, and thus transfer may be performed from any of these chambers or between any of these chambers while maintaining vacuum conditions. Method 400 may subsequently include one or more additional post-processing operations. Post-processing operations may include one or more operations performed in one or more chambers (including multiple chambers on the same cluster tool). Post-processing operations may include oxidation, nitriding, and/or thermal annealing 425.

As mentioned above, pretreatment operations can be performed to provide sufficient end-capping portions to achieve the previously described uniform growth while limiting excessive precursor integration with the substrate. For example, an integrated nitrogen interface can reduce the mobility of the generated transistors, or how quickly charge carriers can move through the structure. Although the pretreatment described above can further improve the scaling of high-k dielectric films, if uncontrolled, pretreatment can actually degrade device mobility. However, in some embodiments, a post-treatment may include oxidation of the formed high-k dielectric material using a second oxygen-containing precursor, in contrast to a first oxygen-containing precursor that can be used in the pretreatment operation.

For example, an oxidation operation utilizing any of the oxygen-containing precursors mentioned above can be performed to further oxidize the film after formation. The deposition or formation of a high-k dielectric film can produce a porous film or a film that includes vacancies in its structure. By performing the oxidation operation, oxide materials can permeate the film to fill vacancies, as shown by layer 530b, and oxide materials, such as optional layers (if not formed in the previous operations described above), can be generated at the interface of the high-k dielectric material. This can improve the underlying interface from amine-terminated groups, which can increase the mobility performance of the device. To limit excessive accumulation in the underlying oxide layer, the oxidation operation can be performed for a finite time period and can be performed within any of the previously mentioned time ranges.

Post-processing operation 430 may include, when used, further contacting the substrate with a second nitrogen-containing precursor relative to the pre-treated nitrogen-containing precursor. The second nitrogen-containing precursor may include any nitrogen-containing precursor described above, and may include nitrogen gas, as well as any nitrogen-containing precursor mentioned elsewhere. The second nitrogen-containing precursor may include a plasma-activated or enhanced nitrogen-containing precursor, thermally activated nitrogen, or some other nitrogen precursor, which may allow the integration of nitrogen radicals or nitrogen atoms into a high-dielectric-constant structure, stabilizing the film or bringing it towards an equilibrium state. Unlike oxidation operations, nitriding may not increase the thickness of the underlying layer (such as silicon oxide) and may also slightly increase the dielectric constant of the resulting film.

Nitrogen integration can be controlled to limit integration within the film in order to maintain structural and electrical properties. In some embodiments, post-treatment nitriding can integrate less than or about 20 atomic% nitrogen in the surface region of a high dielectric constant film, and can integrate less than or about 15 atomic% nitrogen, less than or about 10 atomic% nitrogen, less than or about 8 atomic% nitrogen, less than or about 6 atomic% nitrogen, less than or about 4 atomic% nitrogen, less than or about 2 atomic% nitrogen, or even less. In some embodiments, integration between about 3 atomic% and about 7 atomic% can maintain a higher dielectric constant value compared to higher nitrogen integration and can better stabilize the film compared to lower nitrogen integration. Surface region can mean the exposed surface of the material, although nitrogen integration can extend any distance within the film and can be uniform or form a reducing gradient across the material.

Post-treatment oxidation or nitriding can be performed at any of the temperatures mentioned above, although in some embodiments post-treatment oxidation and/or nitriding can be performed at temperatures below or about 500°C, and can be performed at temperatures below or about 400°C, below or about 300°C, below or about 200°C, below or about 100°C, or even lower, depending on the operation performed.

Post-treatment annealing 425, 435 may be performed after any of the operations, including any of the mentioned post-treatment operations. Post-treatment annealing may be performed in any chamber in which the previous operation was performed, or may involve transfer to different chambers, such as chambers configured to perform rapid thermal annealing processes, for example. Furthermore, the chamber may be integrated with other chambers on the same platform, which allows for transfer between chambers while maintaining vacuum conditions. Post-treatment annealing may further align the film bonding and further stabilize the film. In an embodiment, post-treatment annealing may be performed at a third temperature relative to a first temperature, wherein the third temperature may be higher than or approximately equal to the first temperature. For example, post-treatment annealing can be performed at a temperature of 400°C or higher, and in embodiments, it can be performed at temperatures of 500°C or higher, 600°C or higher, 700°C or higher, 800°C or higher, 900°C or higher.

Improved high-dielectric-constant materials can be produced by performing pretreatment and/or post-treatment according to embodiments of the present invention. Layers of high-dielectric-constant materials of any thickness can be produced, including up to or about several nanometers. However, due to the better grain structure produced by the present invention, a thinner effective oxide thickness can be produced without sacrificing gate leakage performance. The high-dielectric-constant materials produced according to the present invention can be characterized by a dielectric constant value greater than or about 10, and can be characterized by dielectric constant values greater than or about 15, greater than or about 20, greater than or about 21, greater than or about 22, greater than or about 23, greater than or about 24, greater than or about 25, or greater.

As mentioned above, this technology allows for a further improvement in dielectric constant compared to conventional techniques. Furthermore, due to the resulting grain structure, the gate leakage current associated with the film can be less than or approximately one-tenth of the gate leakage current of a similar thickness silicon oxide film, and the gate leakage current can be less than or approximately one-hundredth, less than or approximately one-thousandth, and less than or approximately one-thousandth of the gate leakage current of a similar thickness silicon oxide film. The thickness of the film can be 1/5,000 of that of silicon, less than or about 1/10,000 of that of silicon oxide, less than or about 1/20,000 of that of silicon oxide, less than or about 1/50,000 of that of silicon oxide, less than or about 1/100,000 of that of silicon oxide, or even smaller. By producing films according to embodiments of the present invention, films with beneficial morphologies can be produced, which enhances the electrical properties of the films compared to the prior art.

Figure 6 is a process flow diagram of a method 600 for forming a semiconductor structure 700 according to one or more embodiments of this disclosure. Figures 7A and 7B are cross-sectional views of a portion of the semiconductor structure 700 corresponding to various states of method 600. It should be understood that Figures 7A and 7B only show partial schematic diagrams of the semiconductor structure 700, and the semiconductor structure 700 may contain any number of transistor segments and additional material having the states shown in the figures. It should also be noted that although the method steps shown in Figure 6 are described sequentially, one or more method steps that have been omitted and/or added, and/or other process sequences that have been rearranged in a different desired order, fall within the scope of embodiments of the disclosure provided herein.

Method 600 begins in operation 605 with an annealing process. The annealing process may comprise a spiked annealing of the substrate in a hydrogen ( _H₂ ) atmosphere at a temperature ranging from 500°C to 700°C. Annealing may comprise a spiked thermal annealing process performed in a rapid thermal processing chamber (such as a RADOX ^™ chamber available from Applied Materials, Inc., Santa Clara, California, USA). The RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in Figure 1. Without being theoretically construed, it is believed that spiked annealing of the substrate 702 in a hydrogen ( _H₂ ) atmosphere produces a smooth substrate surface prior to film deposition, thereby allowing for better channel mobility. In one or more embodiments, annealing is used for different purposes compared to a passivation annealing process. In one or more embodiments, annealing in a hydrogen ( _H₂ ) atmosphere causes hydrogen ( _H₂ ) to react with the substrate surface (e.g., silicon (Si)) before film deposition, in order to smooth the substrate surface. In one or more embodiments, in a subsequent high-temperature annealing step, the hydrogen-silicon (H-Si) bond breaks, and the hydrogen is intentionally depassivated after film deposition. In a standard passivation process, on the other hand, the hydrogen-silicon (H-Si) bond is maintained at the end of the process.

In some embodiments, after operation 605, a pre-cleaning process is performed in operation 610 to pre-clean the surface of substrate 702. The pre-cleaning process may be performed by oxidizing the surface of substrate 702 using an ozone ( _O3 ) process or a wet process using a solution (such as a Standard Clean 1 (SC1) _solution including _NH4OH (ammonium hydroxide), _H2O2 (hydrogen peroxide), and _H2O (water)), or a dry etching process (e.g., a SiConi ^™ remote plasma-assisted dry etching process), wherein the surface of substrate 702 is exposed to _N2 , _NF3 , and _NH3 plasma byproducts. The pre-cleaning process can be performed in a pre-cleaning chamber, such as treatment chamber 122 or 120 as shown in Figure 1.

Although not shown in Figure 6, in some embodiments, operation 610 may occur before operation 605.

In operation 620, a deposition process is performed to deposit a high-k dielectric layer 704 on the exposed surface of the semiconductor structure 700. The high-k dielectric layer 704 may be formed _of a high-k dielectric material, such as ruthenium dioxide ( _HfO₂ ), zirconium dioxide ( _ZrO₂ ), yroxide ( _Y₂O₃ ), or aluminum oxide ( _Al₂O₃ ). The deposition process may include an atomic layer deposition (ALD) process, in which a metal _- containing precursor and an oxygen-containing precursor are alternately delivered to the exposed surface of the semiconductor structure 700. In some embodiments, the metal-containing precursor is rinsed before the oxygen-containing precursor is delivered. The metal may be a transition metal, such as ruthenium (Hf), zirconium (Zr), or titanium (Ti); a rare earth metal, such as lanthanum (La), lithium (Yb), or thorium (Y); an alkaline earth metal, such as strontium (Sr); or other metals, such as aluminum (Al). For the oxidant, any oxygen-containing precursor that can react with the metal may be used. For example, the oxygen-containing precursor may be or include water, diatomic oxygen, ozone, hydroxyl-containing precursors or alcohols, nitrogen- and oxygen-containing precursors, plasma-enhanced oxygen including locally or distally enhanced oxygen, or any other material including oxygen that can be integrated with the metal to form an oxide layer of the metal above the substrate 702. In one example, the metal precursor is trioxide tetrachloride ( _HfCl₄ ) and the oxidant is water ( _H₂O ) to form a trioxide ( _HfO₂ ) layer. The ALD process can be performed at temperatures between approximately 200°C and approximately 400°C, for example, approximately 270°C. The high-k dielectric layer 704 deposited by the ALD process can be amorphous and have a thickness between approximately 10 Å and approximately 30 Å. The deposition process can be performed in processing chambers, such as processing chambers 120, 122, 124, 126, 128, or 130 as shown in Figure 1.

In operation 630, a re-oxidation process is performed to thermally oxidize substrate 702. The re-oxidation process may include a thermal annealing process performed in an oxygen ( _O2 ), nitrous oxide ( _N2O ), and _H2 atmosphere in a rapid thermal processing (RTP) chamber (such as a RADOX™ chamber available from Applied Materials, Inc., Santa Clara, California, USA). The RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in Figure 1. The re-oxidation process in operation 630 may thermally oxidize the lower layer through the high-k dielectric layer 704 and form an interface layer 706 on substrate 702 close to the interface with the high-k dielectric layer 704.

The re-oxidation process can be performed at temperatures between approximately 400°C and approximately 900°C and at pressures between approximately 0.01 Torr and 100 Torr for approximately 1 second and approximately 30 seconds, respectively.

In operation 640, a plasma nitriding process is performed to insert nitrogen atoms into vacancies and defects in the high-k dielectric layer 704. The plasma nitriding process can be a DPN process performed in a decoupled plasma nitriding (DPN) chamber (such as a CENTURA® DPN chamber available from Applied Materials, Inc., Santa Clara, California, USA). The DPN chamber can be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in Figure 1. The plasma nitriding process exposes the high-k dielectric layer 704 to nitrogen plasma, which allows nitrogen radicals or nitrogen atoms to be integrated into the high-k dielectric layer 704 throughout its entire thickness. During the plasma nitriding process, nitrogen atoms can form metastable bonds with oxygen (O). Gases that can be used in the plasma process include nitrogen-containing gases, such as nitrogen ( _N₂ ), ammonia ( _NH₃ ), or mixtures thereof. In one example, nitrogen is ammonia ( _NH₃ ) mixed with about 3% to about 8% nitrogen ( _N₂ ). Because nitrogen integrates into vacancies and defects in the deposited high-k dielectric layer 704, the plasma nitriding process may not change the thickness of the high-k dielectric layer 704.

The nitriding process can be performed at temperatures between approximately 0°C and approximately 500°C for approximately 10 seconds and approximately 300 seconds, respectively.

In operation 650, an optional thermal nitriding process is performed to further insert nitrogen atoms into vacancies and defects in the plasma-nitrided high-k dielectric layer 704. The thermal nitriding process may include a thermal annealing process in an ammonia (NH3) atmosphere performed in a rapid thermal processing ( _RTP ) chamber (such as a RADOX™ chamber available from Applied Materials, Inc., Santa Clara, California, USA). The RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in Figure 1.

The thermal nitriding process can be performed at temperatures between approximately 700°C and approximately 900°C and at pressures between approximately 10 Torr and 740 Torr for approximately 10 seconds and approximately 300 seconds, respectively.

In operation 660, a post-nitriding annealing process is performed to passivate the remaining chemical bonds in the plasma-nitrided high-k dielectric layer 704. The post-nitriding annealing process may include a spiked thermal annealing process in a nitrogen ( _N₂ ) and argon (Ar) atmosphere performed in a rapid thermal treatment (RTP) chamber (such as a RADOX™ chamber available from Applied Materials, Inc., Santa Clara, California, USA). The RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in Figure 1. The post-nitriding annealing process can passivate the metastable nitrogen bonds formed in the plasma nitriding process during operation 640, and can result in the crystallization of an amorphous high-dielectric-constant dielectric layer 704.

The peak heat annealing process can be performed at temperatures between approximately 700°C and approximately 850°C and pressures between approximately 10 Torr and 740 Torr for approximately 1 second and approximately 30 seconds, respectively.

In the embodiments described herein, a system and method are provided for forming a high-quality, thin, high-k dielectric layer. The properties of this high-k dielectric layer can be well controlled. For example, the nitriding process in operation 640 can be controlled to provide nitrogen integration in the high-k dielectric layer 704 between about 3 atomic% and about 20 atomic% to achieve a higher dielectric constant value compared to higher nitrogen integration and better structural stability compared to lower nitrogen integration. The annealing process in operation 660 can also be controlled to provide grains in the high-k dielectric layer 704 having a size greater than about 20 Å, thereby reducing leakage current through the high-k dielectric layer 704.

Throughout this specification, references to "an embodiment," "some embodiments," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of this disclosure. Therefore, the appearance of phrases such as "in one or more embodiments," "in some embodiments," "in one embodiment," or "in one embodiment" in various places throughout this specification does not necessarily refer to the same embodiment of this disclosure. Furthermore, a particular feature, structure, material, or characteristic may be combined in one or more embodiments in any suitable manner.

Although the disclosure herein has been described with reference to specific embodiments, those skilled in the art will understand that the described embodiments are merely illustrative of the principles and applications of this disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatus disclosed herein without departing from the spirit and scope of this disclosure. Therefore, this disclosure may include modifications and variations within the scope of the appended patent applications and their equivalents.

100: Multi-chamber processing system 102: Factory interface 104: Loading gate chamber 106: Loading gate chamber 108: Transfer chamber 110: Transfer chamber 112: Transfer robot 114: Transfer robot 116: Holding chamber 118: Holding chamber 120: Processing chamber 122: Processing chamber 124: Processing chamber 126: Processing chamber 128: Processing chamber 130: Processing chamber 140: Dating station 142: Factory interface robot 144: Front-opening wafer transfer box (FOUP) 148: Blade 150: Port 152: Port 154: Port 156: Port 158: Port 160: Port 162: Port 164: Port 166: Port 168: Port 170: Port 172: Port 174: Port 176: Port 190: System Controller 192: Central Processing Unit (CPU) 194: Memory 196: Support Circuits 200: Method 205: Operation 210: Operation 220: Operation 230: Operation 240: Operation 250: Operation 260: Operation 270: Operation 280: Operation 290: Operation

300: Semiconductor Structure

302:Substrate

304: Interface Layer

306: High dielectric constant dielectric layer

400: Method

405: Operation

410: Operation

415: Operation

420: Operation

425: Post-treatment annealing

430: Operation

435: Post-treatment annealing

500: Semiconductor Structure

505:Substrate

510: Natural oxides

515: Nitrous oxide

520: Interface

525: Ligand

530a: Layer

530b: Layer

600: Method

605: Operation

610: Operation

620: Operation

630: Operation

640: Operation

650: Operation

660: Operation

700: Semiconductor Structure

702:Substrate

704: High dielectric constant dielectric layer

706: Interface Layer

To gain a more detailed understanding of the features described above in this disclosure, a more specific description of the disclosure, which has been briefly outlined above, can be obtained by referring to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only illustrate common embodiments of this disclosure and are not intended to limit its scope, as other equivalent embodiments are permissible.

Figure 1 is a schematic top view of an example multi-chamber processing system according to one or more embodiments;

Figure 2 is a process flow diagram of a method for forming a semiconductor structure according to one or more embodiments;

Figures 3A and 3B are schematic diagrams of semiconductor structures according to one or more embodiments;

Figure 4 shows a process flow diagram of a method for forming a semiconductor structure according to one or more embodiments;

Figures 5A through 5F show schematic cross-sectional views of exemplary substrates according to one or more embodiments;

Figure 6 is a process flow diagram of a method for forming a semiconductor structure according to one or more embodiments; and

Figures 7A and 7B are schematic diagrams of semiconductor structures according to one or more embodiments.

For ease of understanding, the same component symbols have been used to identify common components in the diagram where possible. It can be expected that the components and features of one embodiment can be advantageously incorporated into other embodiments without further explanation.

600: Method 605: Operation 610: Operation 620: Operation 630: Operation 640: Operation 650: Operation 660: Operation

Claims (9)

A method for forming a semiconductor structure, the method comprising the steps of: annealing a silicon surface of a substrate in a hydrogen ( _H₂ ) atmosphere at a temperature ranging from 500°C to 700°C, such that hydrogen ( _H₂ ) reacts with the silicon surface to form a smooth surface having hydrogen-silicon (H-Si) bonds; then, in a processing system without disrupting the vacuum, the following steps are performed: directly depositing a high-k dielectric layer on the smooth surface, the high-k dielectric layer having vacancies and defects during deposition; and in a temperature ranging from 400°C to 900°C, in an atmosphere of oxygen ( _O₂ ), nitrous oxide ( _N₂O ), and hydrogen (H₂ _). In an atmosphere, a re-oxidation process is performed through the high-k dielectric layer to thermally oxidize the smooth surface and form an oxide-containing interface layer on the silicon surface of the substrate at an interface with the high-k dielectric layer; a plasma nitriding process is performed at a temperature of about 0°C to about 500°C and continued for a period of time ranging from about 10 seconds to about 300 seconds to insert nitrogen atoms into the vacancy in the high-k dielectric layer. A high-k dielectric layer is formed by plasma nitriding in the presence of defects; and a post-nitriding annealing process is performed to passivate the remaining chemical bonds in the plasma-nitrided high-k dielectric layer and break the hydrogen-silicon bonds in the silicon surface of the substrate. The deposition of the high-k dielectric layer, the re-oxidation process, the plasma nitriding process, and the post-nitriding annealing process are performed in the processing system without breaking the vacuum. The method of claim 1, wherein the post-nitriding annealing process comprises the following steps: peak annealing of the high dielectric constant dielectric layer in a nitrogen ( _N2 ) and argon (Ar) atmosphere at a temperature in the range of 700°C to 850°C. The method described in claim 1 further comprises the step of performing a post-deposition annealing process prior to the plasma nitriding process to harden and densify the high-k dielectric layer. The method of claim 3, wherein the post-deposition annealing process comprises the following steps: annealing the high dielectric constant dielectric layer in a nitrogen ( _N2 ) and argon (Ar) atmosphere at a temperature in the range of 500°C to 800°C. The method of claim 1, wherein the high dielectric constant dielectric layer comprises iron oxide. The method of claim 1 further comprises the step of pre-cleaning the silicon surface of the substrate before annealing it. The method described in claim 6, wherein pre-cleaning the silicon surface comprises flowing a fluorine-containing precursor and a hydrogen-containing precursor above the silicon surface to remove a natural oxide and form a pre-cleaned surface. The method described in claim 6, wherein pre-cleaning the silicon surface comprises exposing the silicon surface to a dry etching process including _N2 , _NF3 , and _NH3 plasma byproducts to remove native oxides and form a pre-cleaned surface. The method of claim 1, wherein the oxide-containing interface layer has a thickness in the range of 3 Å to 10 Å.