TWI901315B - Conductive structure, semiconductor device and manufacturing method thereof - Google Patents

Abstract

A conductive structure including a first conductive layer, a second conductive layer, an insulating layer and a conductive plug is provided. The second conductive layer is disposed on the first conductive layer and covers at least a first portion of the first conductive layer. The insulating layer covers the first conductive layer and the second conductive layer. The conductive plug extends from above the insulating layer through the insulating layer to a second portion different from the first portion of the first conductive layer, and the bottom surface of the conductive plug is between a top surface of the first conductive layer and a bottom surface of the first conductive layer.

Description

Conductive structure, semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor structure and a manufacturing method thereof, and more particularly to a conductive structure, a semiconductor device and a manufacturing method thereof.

Recess channel array transistors (RCATs) have improved operating characteristics compared to planar transistors, leading to their widespread use in semiconductor devices, including memory devices such as dynamic random access memory (DRAM). RCATs increase channel length, reducing leakage effects and lowering drive current. The work function of the materials used in RCATs also affects device performance, including gate-induced drain leakage (GIDL).

The present invention provides a conductive structure, a semiconductor device, and a manufacturing method thereof, which can prevent GIDL and thereby improve the reliability of the semiconductor device.

The present invention provides a conductive structure comprising a first conductive layer, a second conductive layer, an insulating layer, and a conductive plug. The second conductive layer is located on the first conductive layer and covers at least a first portion of the first conductive layer. The insulating layer covers the first and second conductive layers. The conductive plug extends from above the insulating layer, through the insulating layer, and into a second portion of the first conductive layer that is different from the first portion. The bottom surface of the conductive plug is located between the top and bottom surfaces of the first conductive layer.

According to one embodiment of the present invention, in the above-mentioned conductive structure, the first conductive layer and the second conductive layer have different work functions.

According to an embodiment of the present invention, in the above conductive structure, the second conductive layer further covers the second portion of the first conductive layer, and the conductive plug penetrates the second conductive layer.

According to one embodiment of the present invention, the conductive structure further includes a metal silicide located between the conductive plug and the second conductive layer.

The present invention provides a semiconductor device comprising a substrate, a gate structure, and a conductive plug. The gate structure is located above the substrate and includes a first conductive layer and a second conductive layer. The first conductive layer is located above the substrate. The second conductive layer is located above the first conductive layer and covers at least a first portion of the first conductive layer. The conductive plug is located above the first conductive layer and is electrically connected to the gate structure. The conductive plug overlaps a second portion of the first conductive layer, and the second portion is different from the first portion.

According to an embodiment of the present invention, in the above-mentioned semiconductor device, the second conductive layer further covers the second portion of the first conductive layer, and the conductive plug penetrates the second conductive layer.

According to one embodiment of the present invention, the semiconductor device further includes a metal silicide located between the conductive plug and the second conductive layer.

According to one embodiment of the present invention, the semiconductor device further includes an isolation structure located between the gate structure and the substrate, and the isolation structure covers a sidewall of the second portion of the first conductive layer away from the first portion.

The present invention provides a method for manufacturing a semiconductor device, comprising the following steps: forming a first conductive layer on a substrate; forming a second conductive layer on the first conductive layer; and forming a conductive plug on the second conductive layer, wherein the conductive plug extends from above the second conductive layer toward the substrate and into the first conductive layer.

According to one embodiment of the present invention, in the method for manufacturing a semiconductor device, the conductive plug penetrates the second conductive layer.

According to one embodiment of the present invention, the method for manufacturing a semiconductor device further includes forming a metal silicide between the conductive plug and the second conductive layer.

According to an embodiment of the present invention, the method for manufacturing a semiconductor device further includes removing a portion of the second conductive layer that overlaps with the conductive plug before forming the conductive plug, so that the conductive plug does not penetrate the second conductive layer.

Based on the above, in the conductive structure, semiconductor device, and manufacturing method proposed in the present invention, the conductive structure may include a first conductive layer and a second conductive layer having different work functions, and the conductive plug may be directly electrically connected to the first conductive layer or electrically connected to the second conductive layer through metal silicide, thereby improving GIDL and thereby enhancing the reliability of the semiconductor device.

In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings.

The following examples are illustrated in detail with accompanying figures. However, these examples are not intended to limit the scope of the present invention. For ease of understanding, identical components will be designated by the same reference numerals throughout the following description. Furthermore, the accompanying figures are for illustrative purposes only and are not drawn to scale. Furthermore, features in the top and cross-sectional views are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity.

FIG1A is a schematic top view of a conductive structure 10 and a semiconductor device 100 according to an embodiment of the present invention. FIG1B is an enlarged schematic view of area I in FIG1A . FIG1C is a schematic cross-sectional view taken along line A-A' in FIG1B . In the top views of FIG1A and FIG1B , some components are omitted from the cross-sectional view of FIG1C to clarify the positional relationships between the components in the top view.

Referring to both FIG. 1A and FIG. 1B , a semiconductor device 100 may include, for example, a plurality of cells CU arranged in an array. Each cell CU may include at least one conductive structure 10. In some embodiments, the plurality of cells CU may be formed on a substrate 20, and each cell CU includes a plurality of conductive structures 10. The substrate 20 may be a semiconductor substrate, such as a silicon substrate.

Referring to both FIG. 1B and FIG. 1C , in some embodiments, the semiconductor device 100 may further include an isolation structure 22. The isolation structure 22 may define an active region (not shown) in the substrate 20. The isolation structure 22 may be a single-layer structure or a multi-layer structure. For example, the isolation structure 22 includes a stacked first insulating layer 22-1, a second insulating layer 22-2, and a third insulating layer 22-3. The second insulating layer 22-2 may be sandwiched between the first insulating layer 22-1 and the third insulating layer 22-3, wherein the first insulating layer 22-1 may function as a shallow trench isolation (STI) structure. In some embodiments, the first insulating layer 22-1 is a silicon oxide layer, the second insulating layer 22-2 is a silicon nitride layer, and the third insulating layer 22-3 is a silicon oxide layer. In some embodiments, the first insulating layer 22-1 has a relatively high stress, and the second insulating layer 22-2 can protect the cell CU from the stress of the first insulating layer 22-1. In addition, the third insulating layer 22-3 can be used to prevent hot electron induced punch through (HEIP).

Conductive structure 10 may be located on isolation structure 22 and/or between isolation structures 22. Conductive structure 10 may include conductive layer 11 and conductive layer 13, wherein conductive layer 13 is stacked on conductive layer 11. In some embodiments, conductive layer 11 and conductive layer 13 may be located in substrate 20. Conductive layer 11 and conductive layer 13 may constitute a gate structure or a word line structure of semiconductor device 100. In some embodiments, semiconductor device 100 may be a DRAM device, and conductive layers 11 and 13 may constitute a buried dual work function word line of semiconductor device 100.

Conductive layer 11 may include portion 11-1 and portion 11-2, wherein portion 11-2 may substantially overlap isolation structure 22, and portion 11-1 may substantially not overlap isolation structure 22. A first insulating layer 22-1 of isolation structure 22 may extend along sidewalls of portion 11-2 of conductive layer 11 remote from portion 11-1 and along bottom surface 11B of conductive layer 11. A second insulating layer 22-2 may cover two opposing outer sidewalls and the bottom surface of first insulating layer 22-1. A third insulating layer 22-3 may cover two opposing outer sidewalls and the bottom surface of second insulating layer 22-2.

Conductive layers 11 and 13 may have a long strip shape, and conductive layers 11 and 13 in multiple conductive structures 10 may extend parallel to each other, as shown in FIG1B . In some embodiments, conductive layer 13 may completely overlap conductive layer 11, but the present invention is not limited thereto. In certain embodiments, conductive layer 131 only overlaps portion 11-1 of conductive layer 11, but does not overlap portion 11-2 of conductive layer 11.

The work function of conductive layer 13 may be different from the work function of conductive layer 11. Conductive layers 11 and 13 may each have a single-layer structure or a multi-layer structure. In some embodiments, the material of conductive layer 11 may include tungsten (W). In some embodiments, the material of conductive layer 13 may include polycrystalline silicon (poly). In some embodiments, conductive layer 13 is composed of n-type doped polycrystalline silicon (e.g., phosphorus-doped polycrystalline silicon), but the present invention is not limited thereto.

Conductive structure 10 may further include a barrier layer 12 positioned between conductive layer 11 and conductive layer 13. In some embodiments, conductive structure 10 may further include a barrier layer 12' positioned between conductive layer 11 and first insulating layer 22-1. The material of barrier layer 12 or barrier layer 12' may include, for example, titanium nitride (TiN), but the present invention is not limited thereto. The work function of conductive layer 13 and barrier layer 12 may be different from the work function of conductive layer 11 and barrier layer 12'. For example, the work function of conductive layer 13 and barrier layer 12 may be lower than the work function of conductive layer 11 and barrier layer 12'.

Conductive structure 10 may further include a capping layer 14, which covers conductive layer 11 and conductive layer 13. Capping layer 14 may have a via V1, which penetrates capping layer 14 and conductive layer 13 to expose conductive layer 11. In some embodiments, via V1 extends into portion 11-2 of conductive layer 11, such that the bottom surface of via V1 is located between top surface 11T and bottom surface 11B of conductive layer 11. In some embodiments, capping layer 14 is made of silicon nitride (SiN).

Conductive structure 10 further includes a barrier layer 15 and a conductive plug 16. Barrier layer 15 may line via V1, and conductive plug 16 may be located on barrier layer 15 in via V1, such that a portion of barrier layer 15 is located between conductive plug 16 and conductive layer 11. Conductive plug 16 may also be located above cover layer 14 and may extend through the entire thickness of cover layer 14 into conductive layer 11. Conductive plug 16 may directly contact barrier layer 15. In some embodiments, if barrier layer 15 is not present, conductive plug 16 may directly contact conductive layer 11. For example, the conductive plug 16 may extend from above the insulating layer 14 (eg, from the upper surface of the insulating layer 38 ) toward the substrate 20 , through the insulating layer 14 and the conductive layer 13 , and into the portion 11 - 2 of the conductive layer 11 .

In some embodiments, bottom surface 16B of conductive plug 16 is located below top surface 11T of conductive layer 11. In other words, bottom surface 16B of conductive plug 16 may be located between top surface 11T and bottom surface 11B of conductive layer 11. Barrier layer 15 may be made of titanium nitride, and conductive plug 16 may be made of tungsten, but the present invention is not limited thereto. In some embodiments, when conductive layer 13 comprises polysilicon, conductive structure 10 further includes a metal silicide 19 (e.g., cobalt silicide (CoSi)) located between conductive layer 13 and conductive plug 16 (or barrier layer 15). The metal silicide 19 can form an ohmic contact between the conductive layer 13 and the conductive plug 16 (or the barrier layer 15 ), thereby reducing the electrical resistance between the conductive layer 13 and the conductive plug 16 (or the barrier layer 15 ).

In some embodiments, the conductive structure 10 further includes a barrier layer 17 and a conductive plug 18. The conductive plug 18 may extend from above the capping layer 14 downward into the substrate 20. The conductive plug 18 may extend substantially parallel to the conductive plug 16. Furthermore, the barrier layer 17 may be located between the conductive plug 18 and the substrate 20 and surround the conductive plug 18. In some embodiments, the conductive plug 18 and the conductive plug 16 are formed from the same film layer. In some embodiments, the barrier layer 17 and the barrier layer 15 are formed from the same film layer. For example, the barrier layer 17 may be made of titanium nitride, and the conductive plug 18 may be made of tungsten, but the present invention is not limited thereto. In some embodiments, when the substrate 20 is a silicon substrate, the conductive structure 10 further includes a metal silicide 19' (e.g., cobalt silicide) between the substrate 20 and the conductive plug 18 (or the barrier layer 17).

Semiconductor device 100 may further include a conductive layer 24 and contacts 26. Conductive layer 24 is located on cover layer 14, and contacts 26 may be located within cover layer 14 and conductive layer 24. A liner 27 may be located on the sidewalls of contact 26 to separate contact 26 from conductive layer 24. Liner 27 may have a single-layer structure or a multi-layer structure. When semiconductor device 100 is a DRAM device, contacts 26 may function as bit line contacts. In some embodiments, the conductive layer 24 includes polysilicon, the contact 26 includes doped polysilicon, and the liner 27 includes a multi-layer structure composed of silicon oxide, silicon nitride, or a combination thereof, but the present invention is not limited thereto.

Semiconductor device 100 may further include a barrier layer 28 on conductive layer 24, a conductive layer 30 on barrier layer 28, and an insulating layer 32, an etch stop layer 34, an insulating layer 36, and an insulating layer 38 sequentially disposed on conductive layer 30. For example, barrier layer 28 may be made of titanium nitride, conductive layer 30 may be made of tungsten, insulating layer 32, etch stop layer 34, and insulating layer 38 may be made of silicon nitride, and insulating layer 36 may be made of silicon oxide, but the present invention is not limited thereto.

Semiconductor device 100 may further include a contact 40. Contact 40 may extend through etch stop layer 34, insulating layer 32, conductive layer 30, barrier layer 28, and conductive layer 24 into cap layer 14 and be separated from etch stop layer 34, insulating layer 32, conductive layer 30, barrier layer 28, and conductive layer 24. When semiconductor device 100 is a DRAM device, contact 40 may serve as a storage node contact. Contact 40 may be made of, for example, doped polysilicon. In some embodiments, the first insulating layer 22 - 1 may also be located in the substrate 20 below the contacts 26 and 40 .

Semiconductor device 100 may further include a barrier layer 44 located on insulating layer 38 and a conductive layer 46 located on barrier layer 44. Barrier layer 44 and conductive layer 46 may penetrate insulating layer 38 to electrically connect to contact 40. Barrier layer 44 may be made of titanium nitride, and conductive layer 46 may be made of tungsten, but the present invention is not limited thereto. In some embodiments, when contact 40 comprises polysilicon, semiconductor device 100 may further include a metal silicide 42 (e.g., cobalt silicide) located between barrier layer 44 and contact 40. Conductive layer 46 may be formed from the same film layer as conductive plug 16. In some embodiments, barrier layer 44 and barrier layer 15 belong to the same film layer.

Semiconductor device 100 may further include an insulating layer 48 covering conductive layer 46. The material of insulating layer 48 may include silicon oxide, silicon nitride, or a combination thereof. When semiconductor device 100 functions as a storage device (e.g., a DRAM), semiconductor device 100 may further include a capacitor structure 50 located above insulating layer 48. Capacitor structure 50 may serve as a storage node of semiconductor device 100. In some embodiments, conductive layer 46 may serve as a landing pad for an electrode of capacitor structure 50, and capacitor structure 50 may be electrically connected to contact 40 via conductive layer 46, barrier layer 44, and metal silicide 42. In FIG. 1C , the capacitor structure 50 is schematically illustrated to simplify the drawing.

Figures 2A, 3A, 4A, 5, 6, and 7 are schematic cross-sectional views illustrating the steps of a method for manufacturing a conductive structure 10 and a semiconductor device 100 according to an embodiment of the present invention. Figures 2B, 3B, and 4B are schematic top views of Figures 2A, 3A, and 4A, respectively. Figures 2A, 3A, and 4A are schematic cross-sectional views taken along lines A-A' in Figures 2B, 3B, and 4B, respectively. Figures 5 through 7 are schematic cross-sectional views taken, for example, along line A-A' in Figure 4B.

Referring to Figures 2A and 2B , a substrate 20 is provided. The substrate 20 may be a semiconductor substrate, such as a silicon substrate. Furthermore, an isolation structure 22 may be formed in the substrate 20. For example, a third insulating layer 22-3 may be formed on the substrate 20, followed by a second insulating layer 22-2 formed on the third insulating layer 22-3, and then a first insulating layer 22-1 formed on the second insulating layer 22-2. The isolation structure 22 may isolate multiple active regions (not shown) formed in the substrate 20 from each other. The third insulating layer 22 - 3 , the second insulating layer 22 - 2 , and the first insulating layer 22 - 1 may be formed, for example, by one or more of a lithography process, an etching process, a chemical vapor deposition (CVD) process, and a chemical mechanical polishing (CMP) process.

Next, a barrier layer 12'L is formed on the isolation structure 22 and the substrate 20, and then a conductive layer 11L is formed on the barrier layer 12'L, such that the barrier layer 12'L is located between the conductive layer 11L and the isolation structure 22, and between the conductive layer 11L and the substrate 20. Next, a barrier layer 12L is formed on the conductive layer 11L, and then a conductive layer 13L is formed on the barrier layer 12L. The barrier layer 12'L, the conductive layer 11L, the barrier layer 12L, and the conductive layer 13L can be formed, for example, by one or more of a physical vapor deposition (PVD) process, a plating process, a lithography process, and an etching process.

Referring to Figures 3A and 3B , the conductive layer 13L is then thinned, and then the barrier layer 12'L, the conductive layer 11L, the barrier layer 12L, and the conductive layer 13L are patterned to form the barrier layer 12', the conductive layer 11, the barrier layer 12, and the conductive layer 13 having the desired pattern (e.g., stripe shape) and thickness. In some embodiments, the conductive layer 13L can be thinned using an etching process or a chemical mechanical polishing process. In some embodiments, the barrier layer 12'L, the conductive layer 11L, the barrier layer 12L, and the conductive layer 13L can be patterned using a lithography process and an etching process. After patterning, portion 11 - 2 of conductive layer 11 may cover isolation structure 22 , while portion 11 - 1 of conductive layer 11 may not cover isolation structure 22 .

4A and 4B , a capping layer 14 may then be formed on the conductive layer 13, the isolation structure 22, and the substrate 20. The capping layer 14 may be deposited on the conductive layer 13, the isolation structure 22, and the substrate 20 by, for example, spin coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), high-density plasma chemical vapor deposition (HDPCVD), thermal oxidation, combinations thereof, and/or the like. In some embodiments, the capping layer 14 may include silicon nitride, but the present invention is not limited thereto.

5 , a conductive layer 24 , a contact 26 , a liner 27 , a barrier layer 28 , a conductive layer 30 , an insulating layer 32 , an etch stop layer 34 , an insulating layer 36 , an insulating layer 38 , a contact 40 and a sacrificial layer SL are then formed on the capping layer 14 . Conductive layer 24, contact 26, liner 27, barrier layer 28, conductive layer 30, insulating layer 32, etch stop layer 34, insulating layer 36, insulating layer 38, contact 40 and sacrificial layer SL can be formed, for example, by one or more of spin coating, chemical vapor deposition (CVD), high-density plasma chemical vapor deposition (HDPCVD), physical vapor deposition (PVD), lithography process, etching process and the like. When semiconductor device 100 is a DRAM device, contact 40 may form, for example, a storage node contact, contact 26 may form, for example, a bit line contact, and conductive layer 30 may form, for example, a bit line.

Next, a mask PR1 may be formed on the sacrificial layer SL, the insulating layer 38, and the substrate 20. Then, using the mask PR1 and using, for example, a dry etching process, a through hole V1 may be formed in the insulating layer 38, the insulating layer 36, the etch-stop layer 34, the capping layer 14, the conductive layer 13, the barrier layer 12, and the conductive layer 11. Furthermore, a through hole V2 may be formed in the insulating layer 38, the etch-stop layer 34, the insulating layer 32, the conductive layer 30, the barrier layer 28, the conductive layer 24, and the substrate 20. Via V1 can extend into conductive layer 11 toward substrate 20, such that the bottom surface of via V1 is located between top surface 11T and bottom surface 11B of conductive layer 11, and via V1 can expose conductive layer 13 and conductive layer 11. Furthermore, via V2 can extend into substrate 20 toward substrate 20, such that via V2 can expose substrate 20.

Referring to FIG. 6 , the mask PR1 and sacrificial layer SL are then removed to expose the contacts 40. The mask PR1 and sacrificial layer SL can be removed, for example, by etching or ashing. Next, a metal layer (not shown) is formed on the substrate 20. The metal layer can be formed, for example, by PVD. In some embodiments, the metal layer is made of cobalt (Co), but the present invention is not limited thereto. When the contact 40 and the conductive layer 13 are made of polysilicon and the substrate 20 is a silicon substrate, the metal layer can simultaneously form metal silicide 42, metal silicide 19, and metal silicide 19' on the exposed portions of the contact 40, the conductive layer 13, and the substrate 20, respectively, while the remaining exposed surfaces remain as a metal layer. In other words, the metal silicide 19 and the metal silicide 42 on the contact 40 are formed using the same process steps, rather than using additional process steps. The metal layer can then be removed using an etching process.

For example, when the metal layer is formed as a cobalt layer, metal silicide 42, metal silicide 19, and metal silicide 19' can all be cobalt silicide. Because metal silicide and the metal layer have different etching selectivities, when an etching process is used to remove the metal layer, metal silicide 42, metal silicide 19, and metal silicide 19' can be retained.

Referring to FIG. 7 , a barrier layer 44 may then be formed on the metal silicide 42, a barrier layer 15 may be formed in the via V1, and a barrier layer 17 may be formed in the via V2. In some embodiments, barrier layers 44, 15, and 17 may be formed from the same film layer. A conductive layer 46 may then be formed on the barrier layer 44, a conductive plug 16 may be formed on the barrier layer 15 in the via V1, and a conductive plug 18 may be formed on the barrier layer 17 in the via V2. In some embodiments, conductive layer 46, conductive plug 16, and conductive plug 18 may be formed from the same film layer. Barrier layer 44, barrier layer 15, barrier layer 17, conductive layer 46, conductive plug 16, and conductive plug 18 may be formed by one or more of, for example, a CVD process, a PVD process, a plating process, a photolithography process, and an etching process. Subsequently, an insulating layer 48 may be formed on conductive layer 46, conductive plug 16, conductive plug 18, and substrate 20.

1C , a capacitor structure 50 may then be formed on the insulating layer 48 so that the semiconductor device 100 can function as, for example, a DRAM device. The process for forming the capacitor structure 50 is well known to those skilled in the art, and thus its description is omitted herein.

Figures 8A, 9A, 10A, 11, 12, and 13 are schematic cross-sectional views illustrating the steps of a method for manufacturing a conductive structure 60 and a semiconductor device 200 according to an embodiment of the present invention. Figures 8B, 9B, and 10B are schematic top views of Figures 8A, 9A, and 10A, respectively. Figures 8A, 9A, and 10A are schematic cross-sectional views taken along lines A-A' in Figures 8B, 9B, and 10B, respectively. Figures 11 to 13 are schematic cross-sectional views taken along, for example, line A-A' in Figure 10B.

The steps of Figures 8A and 8B may, for example, follow the steps of Figures 3A and 3B. Referring to Figures 8A and 8B, after forming barrier layer 12', conductive layer 11, barrier layer 12, and conductive layer 13 having the desired pattern and thickness, a mask PR2 may be formed on conductive layer 13, isolation structure 22, and substrate 20. Mask PR2 may be formed, for example, by a spin-on process, a photolithography process, and an etching process. Mask PR2 may have an opening OP that may expose a portion of conductive layer 13. For example, mask PR2 may cover portion 131 of conductive layer 13, while opening OP may expose portion 132 of conductive layer 13. In some embodiments, the opening OP may partially overlap or completely overlap the isolation structure 22 .

Next, mask PR2 can be used to remove portion 132 of conductive layer 13, while retaining portion 131 of conductive layer 13, to form the structure shown in Figures 9A and 9B. In some embodiments, a portion of barrier layer 12 beneath portion 132 of conductive layer 13 (also referred to as conductive layer 132) can be further removed, exposing portion 112 of conductive layer 11 (also referred to as conductive layer 112). Portion 131 of conductive layer 13 (also referred to as conductive layer 131) can overlap portion 111 of conductive layer 11 (also referred to as conductive layer 111). Conductive layer 132 and the portion of barrier layer 12 beneath it can be removed, for example, by an etching process. Then, mask PR2 can be removed. The mask PR2 may be removed, for example, by an etching process or an ashing process.

10A and 10B , a capping layer 14 may be formed on the conductive layer 131, the conductive layer 112, the isolation structure 22, and the substrate 20. The formation of the capping layer 14 may be described with reference to the relevant descriptions of FIG. 4A and FIG. 4B , and will not be further elaborated here.

11 , a conductive layer 24 , a contact 26 , a liner 27 , a barrier layer 28 , a conductive layer 30 , an insulating layer 32 , an etch stop layer 34 , an insulating layer 36 , an insulating layer 38 , a contact 40 and a sacrificial layer SL are then formed on the capping layer 14 . Conductive layer 24, contact 26, liner 27, barrier layer 28, conductive layer 30, insulating layer 32, etch stop layer 34, insulating layer 36, insulating layer 38, contact 40 and sacrificial layer SL can be formed, for example, by one or more of spin coating, chemical vapor deposition (CVD), high-density plasma chemical vapor deposition (HDPCVD), physical vapor deposition (PVD), lithography process, etching process and the like.

Next, a mask PR3 may be formed over the sacrificial layer SL, the insulating layer 38, and the substrate 20. Mask PR3 is then used to form, for example, a dry etching process in the insulating layer 38, the insulating layer 36, the etch-stop layer 34, the capping layer 14, and the conductive layer 11 to form a via V3. Furthermore, a via V2 may be formed in the insulating layer 38, the etch-stop layer 34, the insulating layer 32, the conductive layer 30, the barrier layer 28, the conductive layer 24, and the substrate 20. The via V3 may overlap the conductive layer 112, such that the conductive layer 112 is exposed from the via V3. The bottom surface of the via V3 may be located between the top surface 11T and the bottom surface 11B of the conductive layer 112. Since the via V3 does not overlap the conductive layer 131, the conductive layer 131 is not exposed from the via V3. In addition, the substrate 20 may be exposed from the via V2.

Referring to Figure 12, the mask PR3 and the sacrificial layer SL are then removed to expose the contact 40. The mask PR3 and the sacrificial layer SL can be removed, for example, by an etching process or an ashing process. Next, a metal layer (not shown) is formed on the substrate 20. In some embodiments, the material of the metal layer includes cobalt (Co), but the present invention is not limited thereto. The metal layer can be formed by, for example, a PVD process. When the contact 40 includes polysilicon and the substrate 20 is a silicon substrate, the above-mentioned metal layer can simultaneously form a metal silicide 42 and a metal silicide 19' with the exposed portions of the contact 40 and the substrate 20, respectively, while the remaining exposed surfaces are still formed as a metal layer. For example, when the metal layer is formed as a cobalt layer, both metal silicide 42 and metal silicide 19' can be cobalt silicide. Next, the metal layer is removed. Because metal silicide and the metal layer have different etching selectivities, an etching process can be used to remove the metal layer while preserving metal silicide 42 and metal silicide 19'. Furthermore, because via V3 does not expose conductive layer 131, even if conductive layer 131 is made of polysilicon, metal silicide will not form in via V3.

Referring to FIG. 13 , a barrier layer 44 may then be formed on the metal silicide 42, a barrier layer 15 may be formed in the via V3, and a barrier layer 17 may be formed in the via V2. In some embodiments, barrier layers 44, 15, and 17 may be formed from the same film layer. A conductive layer 46 may then be formed on the barrier layer 44, a conductive plug 16 may be formed on the barrier layer 15 in the via V3, and a conductive plug 18 may be formed on the barrier layer 17 in the via V2. In some embodiments, conductive layer 46, conductive plug 16, and conductive plug 18 may be formed from the same film layer. The barrier layers 44 , 15 , 17 , the conductive layer 46 , the conductive plugs 16 , and 18 may be formed by one or more of, for example, a CVD process, a PVD process, a photolithography process, and an etching process.

Next, an insulating layer 48 can be formed on conductive layer 46, conductive plugs 16, conductive plugs 18, and substrate 20. In some embodiments, a capacitor structure 50 can also be formed on insulating layer 48, allowing semiconductor device 200 to function as, for example, a DRAM device. The process for forming capacitor structure 50 is well known to those skilled in the art, and therefore, a detailed description thereof is omitted here.

13 is a cross-sectional view of a conductive structure 60 and a semiconductor device 200 according to an embodiment of the present invention. The semiconductor device 200 may include a substrate 20, an isolation structure 22 formed in the substrate 20, and a conductive structure 60 formed on the substrate 20 and a portion of the isolation structure 22.

Conductive structure 60 may include barrier layer 12′, conductive layer 11, barrier layer 12, conductive layer 131, insulating layer 14, barrier layer 15, conductive plug 16, barrier layer 17, conductive plug 18, and metal silicide 19′. Compared to conductive structure 10 of semiconductor device 100 shown in FIG. 1C , conductive structure 60 of semiconductor device 200 shown in FIG. 13 differs primarily in that conductive layer 131 of conductive structure 60 does not cover portion 112 of conductive layer 11, conductive plug 16 does not overlap conductive layer 131, and conductive plug 16 penetrates insulating layer 14 and extends directly into portion 112 of conductive layer 11. Conductive plug 16 or barrier layer 15 may directly contact conductive layer 11. Bottom surface 16B of conductive plug 16 may be located between top surface 11T and bottom surface 11B of conductive layer 11. In addition, metal silicide 19 as shown in FIG1C does not exist between conductive plug 16 and conductive layer 131.

In summary, in the conductive structure, semiconductor device, and manufacturing method thereof of the above-described embodiments, the conductive structure may include a first conductive layer and a second conductive layer having different work functions, thereby improving GIDL and, consequently, enhancing the reliability of the semiconductor device. Furthermore, the conductive plug may be electrically connected to the second conductive layer via metal silicide, thereby forming an ohmic contact between the conductive plug and the second conductive layer. Furthermore, the metal silicide between the conductive plug and the second conductive layer may be formed in the same step as the metal silicide on the storage node contact, thereby eliminating the need for additional process steps.

Although the present invention has been disclosed above by way of embodiments, they are not intended to limit the present invention. Any person having ordinary skill in the art may make slight modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.

10, 60: Conductive structure 11, 11L, 13, 13L, 24, 30, 46: Conductive layer 11B, 16B: Bottom surface 11T: Top surface 11-1: Portion 11-2: Portion 12, 12L, 12', 12'L, 15, 17, 28, 44: Barrier layer 14: Capping layer/insulating layer 16, 18: Conductive plug 19, 19', 42: Metal silicide 20: Substrate 22: Isolation structure 22-1: First insulating layer 22-2: Second insulating layer 22-3: Third insulating layer 26, 40: Contact 27: Liner 32, 36, 38, 48: Insulation layer 34: Etch stop layer 50: Capacitor structure 100, 200: Semiconductor device 111, 112, 131, 132: Portion/conductive layer A-A': Line CU: Cell I: Region OP: Opening PR1, PR2, PR3: Mask SL: Sacrificial layer V1, V2, V3: Via

Figure 1A is a schematic top view of a conductive structure and a semiconductor device according to an embodiment of the present invention. Figure 1B is an enlarged schematic view of area I in Figure 1A. Figure 1C is a schematic cross-sectional view taken along line A-A' in Figure 1B. Figures 2A, 3A, 4A, 5, 6, and 7 are schematic cross-sectional views illustrating the steps of a method for manufacturing a conductive structure and a semiconductor device according to an embodiment of the present invention. Figures 2B, 3B, and 4B are schematic top views of Figures 2A, 3A, and 4A, respectively. Figures 8A, 9A, 10A, 11, 12, and 13 are schematic cross-sectional views illustrating the steps of a method for manufacturing a conductive structure 60 and a semiconductor device 200 according to an embodiment of the present invention. 8B , 9B , and 10B are schematic top views of FIG. 8A , 9A , and 10A , respectively.

10: Conductive structure

11,13,24,30,46: Conductive layer

11B, 16B: Bottom surface

11T: Top surface

11-1, 11-2: Partial

12,12’,15,17,28,44: Barrier layer

14: Covering layer/insulating layer

16,18: Conductive plug

19,19’,42: Metal silicides

20: Base

22: Isolation Structure

22-1: First Insulation Layer

22-2: Second Insulation Layer

22-3: Third Insulation Layer

26,40: Contacts

27: Lining

32,36,38,48: Insulating layer

34: Etch stop layer

50: Capacitor structure

100: Semiconductor devices

V1, V2: Through hole

Claims (5)

A conductive structure includes: a first conductive layer; a second conductive layer located on the first conductive layer and covering the first conductive layer, wherein the first conductive layer and the second conductive layer have different work functions; an insulating layer covering the first conductive layer and the second conductive layer; a conductive plug extending from above the insulating layer, through the insulating layer, and into the first conductive layer, with a bottom surface of the conductive plug located between the top and bottom surfaces of the first conductive layer, wherein the conductive plug penetrates the second conductive layer; and a metal silicide located between the conductive plug and the second conductive layer. A semiconductor device comprises: a substrate; a gate structure located on the substrate and comprising: a first conductive layer located on the substrate; and a second conductive layer located on the first conductive layer and covering the first conductive layer, wherein the first conductive layer and the second conductive layer have different work functions; a conductive plug located on the first conductive layer and electrically connected to the gate structure, wherein the conductive plug overlaps the first conductive layer and penetrates the second conductive layer; and a metal silicide located between the conductive plug and the second conductive layer. The semiconductor device of claim 2 further comprises an isolation structure located between the gate structure and the substrate and covering a bottom surface of the first conductive layer. A method for manufacturing a semiconductor device includes: forming a first conductive layer on a substrate; forming a second conductive layer on the first conductive layer, wherein the first conductive layer and the second conductive layer have different work functions; forming a conductive plug on the second conductive layer, wherein the conductive plug extends from above the second conductive layer toward the substrate and into the first conductive layer, wherein the conductive plug penetrates the second conductive layer; and forming a metal silicide between the conductive plug and the second conductive layer. The method for manufacturing a semiconductor device as described in claim 4 further includes forming a metal layer on the exposed portion of the second conductive layer before forming the conductive plug to form the metal silicide.