TWI901308B - Electrostatic discharge protection device and circuit - Google Patents

Abstract

Embodiments provide an electrostatic discharge protection device and an electrostatic discharge protection circuit. The electrostatic discharge protection device includes a deep N-type well region in a P-type semiconductor substrate, first to fifth well regions, first to fifth P-type doped regions, and first and second N-type doped regions. The first to fifth well regions are disposed on the deep N-shaped well region. The first to fifth P-type doped regions are respectively disposed in the first to fifth well regions. The first and second N-type doped regions are respectively disposed in the fourth and fifth well regions. The conductivity type of the first, third and fourth well regions is P-type. The conductivity type of the second and fifth well regions is N-type. The second and fifth P-type doped regions and the second N-type doped region are electrically connected to the first power pad. The first, third and fourth P-type doped regions and the first N-type doped region are electrically connected to the second power pad.

Description

Electrostatic discharge protection device and electrostatic discharge protection circuit

The present invention relates to an electrostatic discharge protection device, and more particularly to the structure and circuit of an electrostatic discharge protection device.

Component damage caused by electrostatic discharge (ESD) has become one of the most significant reliability issues for integrated circuit products. As device dimensions continue to shrink to sub-micron levels, the gate oxide layer of metal oxide semiconductors (MOS) becomes increasingly thinner, making integrated circuits more susceptible to damage from ESD.

According to general industry standards, the input and output pins (I/O) of integrated circuit products must be able to pass human body model ESD tests exceeding 2000 volts and mechanical model ESD tests exceeding 200 volts. Therefore, ESD protection devices must be installed near all I/O pads in integrated circuit products to protect the core circuits from ESD current.

Some embodiments disclosed herein provide an electrostatic discharge protection device. The electrostatic discharge protection device includes a P-type semiconductor substrate, a deep N-type well region, a first well region, a first P-type doped region, a second well region, a second P-type doped region, a third well region, a third P-type doped region, a fourth well region, a fourth P-type doped region, a first N-type doped region, a fifth well region, a fifth P-type doped region, and a second N-type doped region. The deep N-type well region is disposed in the P-type semiconductor substrate. The first well region is disposed on the deep N-type well region. The first P-type doped region is disposed in the first well region. The second well region is disposed on the deep N-type well region. The second P-type doped region is disposed in the second well region. The third well region is disposed on the deep N-type well region. A third P-type doped region is disposed in the third well region. A fourth well region is disposed above the deep N-type well region. A fourth P-type doped region is disposed in the fourth well region. A first N-type doped region is disposed in the fourth well region. A fifth well region is disposed above the deep N-type well region. A fifth P-type doped region is disposed in the fifth well region. A second N-type doped region is disposed in the fifth well region. The first, third, and fourth well regions are of P-type conductivity, and the second and fifth well regions are of N-type conductivity. The second P-type doped region, the fifth P-type doped region, and the second N-type doped region are electrically connected to the first power pad. The first P-type doped region, the third P-type doped region, the fourth P-type doped region, and the first N-type doped region are electrically connected to the second power pad.

Some embodiments disclosed herein provide an electrostatic discharge protection circuit for protecting core circuits. The electrostatic discharge protection circuit includes a first PNP-type bipolar junction transistor (BJT), a second PNP-type bipolar junction transistor (BJT), a first diode, a third PNP-type bipolar junction transistor (BJT), a first NPN-type bipolar junction transistor (NPN-type bipolar junction transistor), a fourth PNP-type bipolar junction transistor (BJT), a second NPN-type bipolar junction transistor (NPN-type bipolar junction transistor), a first resistor, a second resistor, a third resistor, and a fourth resistor. The emitter of the first PNP-type bipolar junction transistor is coupled to a first power pad. The collector of the first PNP-type bipolar junction transistor is coupled to a second power pad. An emitter of the second PNP bipolar junction transistor is coupled to the second power pad. A collector of the second PNP bipolar junction transistor is coupled to the third power pad. A cathode of the first diode is coupled to the first power pad and the base of the second PNP bipolar junction transistor. An anode of the first diode is coupled to the third power pad. An emitter of the third PNP bipolar junction transistor is coupled to the first power pad. A base of the third PNP bipolar junction transistor is coupled to the base of the first PNP bipolar junction transistor. An emitter of the first NPN bipolar junction transistor is coupled to the second power pad. The base of the first NPN bipolar junction transistor is coupled to the collector of the third PNP bipolar junction transistor. The collector of the first NPN bipolar junction transistor is coupled to the base of the third PNP bipolar junction transistor to form a first semiconductor controlled rectifier. The emitter of the fourth PNP bipolar junction transistor is coupled to the first power pad. The emitter of the second NPN bipolar junction transistor is coupled to the second power pad. The base of the fourth PNP bipolar junction transistor is coupled to the collector of the second NPN bipolar junction transistor. The collector of the fourth PNP bipolar junction transistor is coupled to the base of the second NPN bipolar junction transistor to form a second semiconductor controlled rectifier. The base of the first NPN bipolar junction transistor is coupled to the base of the second NPN bipolar junction transistor. A first resistor is coupled between the first power pad and the base of the first PNP bipolar junction transistor. A second resistor is coupled between the first power pad and the base of the fourth PNP bipolar junction transistor. A third resistor is coupled between the second power pad and the base of the first NPN bipolar junction transistor. The fourth resistor is coupled between the second power pad and the base of the second NPN bipolar junction transistor.

100: Operating System

110, 110-1, 110-2, 110A, 110A-1, 110A-2, 110B, 110B-1, 110B-2: Electrostatic discharge protection circuit

120: Core circuit

121, 122, 123: Circuit

300: P-type semiconductor substrate

310: Deep N-type well area

320: Resistive Protective Oxide

330,340,350: Internal link structure

400A, 400B: Electrostatic discharge protection device

500,510,520: Direction

A-A’,B-B’: Tangent line

D1: Parasitic diode (diode)

DS1, DS2: Width

NPN_1, NPN_2: Parasitic NPN bipolar junction transistor (NPN bipolar junction transistor)

PD_1, PD_2, PD_3: Power pads

P1, P2, P3, P4, P5, P6, N1, N2: Doped Area

PNP_1, PNP_2, PNP_3, PNP_4: Parasitic PNP bipolar junction transistor (PNP bipolar junction transistor)

R_1, R_2, R_3, R_4, R_5, R_6: Parasitic resistance (resistance)

S_1, S_2, S_3, S_4, S_5, S_6, S_7, S_8: Insulation structure

SA1, SA2, SA3, SA4, SA5, SA6, SA7, SA8: Silicide components

SCR_1, SCR_2: Parasitic semiconductor controlled rectifier (Semiconductor controlled rectifier)

VH, VL, VSUB: Operating voltage

W1,W2,W3,W4,W5,W6,W7,W8,W9,W10,W11,W12: well area

Figure 1 is a schematic diagram of an operating system according to some embodiments of the present disclosure.

Figure 2 is a schematic top view of an ESD protection device according to some embodiments of the present disclosure.

FIG3 is a schematic cross-sectional view taken along the A-A' and B-B' lines of the electrostatic discharge protection device shown in FIG2 according to some embodiments of the present disclosure.

Figure 4 is a schematic top view of an ESD protection device according to some embodiments of the present disclosure.

FIG5 is a schematic cross-sectional view taken along the A-A' and B-B' lines of the electrostatic discharge protection device shown in FIG4 according to some embodiments of the present disclosure.

Figure 6 is a schematic diagram of the connections of the equivalent circuit of the electrostatic discharge protection device shown in Figures 2 and 3 according to some embodiments of the present invention in an operating system. It shows the equivalent discharge circuit in which an electrostatic discharge event occurs between the first voltage source and the second voltage source.

Figure 7 shows a schematic diagram of the parasitic elements in the equivalent circuit of Figure 6 and their corresponding positions in the ESD protection device of Figure 3.

Figure 8 is a schematic diagram of the connections of the equivalent circuit of the electrostatic discharge protection device shown in Figures 4 and 5 according to some embodiments of the present invention in an operating system. It shows the equivalent discharge circuit in which an electrostatic discharge event occurs between the first voltage source and the second voltage source.

Figure 9 shows a schematic diagram of the parasitic elements in the equivalent circuit of Figure 8 and their corresponding positions in the ESD protection device of Figure 5.

To make the objects, features, and advantages of the present invention more clearly understood, the following examples are presented and illustrated in detail with accompanying figures. This description of the invention provides various examples to illustrate the technical features of various embodiments of the present invention. The configuration of components in the examples is for illustrative purposes only and is not intended to limit the present invention. In addition, the repetition of reference numerals in the figures of the examples is for simplification and does not indicate a relationship between the different embodiments.

Silicon-controlled rectifiers (SCRs) are popular as ESD protection circuits due to their low trigger voltage (Vt1), holding voltage (V _Hold ), and on-resistance (Ron). They offer excellent performance in both the human body model (HBM) and mechanical model (MM) of discharge. However, SCRs with low holding voltages are susceptible to false conduction due to noise voltage spikes. Therefore, an ESD protection device and circuit are needed to address these issues.

FIG1 is a schematic diagram of an operating system according to some embodiments of the present disclosure. As shown in FIG1 , operating system 100 includes an ESD protection circuit 110 (including ESD protection circuits 110A and 110B in subsequent figures) and a core circuit 120. ESD protection circuit 110 (including ESD protection circuits 110-1 and 110-2) and core circuit 120 are coupled to power pads PD_1, PD_2, and PD_3. In this embodiment, ESD protection circuit 110 protects core circuit 120 from ESD current from any of power pads PD_1, PD_2, and PD_3, which could enter and damage core circuit 120.

In some embodiments, core circuit 120 includes circuit 121, circuit 122, and circuit 123. Circuit 121 is coupled between power pads PD_1 and PD_2. Circuit 122 is coupled between power pads PD_2 and PD_3. Circuit 123 is coupled between power pads PD_1 and PD_3. The present invention is not limited to the number of circuits in core circuit 120. In some embodiments, core circuit 120 has more or fewer circuits. Each circuit is coupled between at least two power pads.

When an ESD event does not occur, operating system 100 operates in normal mode. In normal mode, ESD protection circuit 110 is inactive. At this time, power pad PD_1 may receive operating voltage VH, power pad PD_2 may receive operating voltage VL, and power pad PD_3 may receive operating voltage VSUB. Circuit 121 operates based on operating voltages VH and VL. Circuit 122 operates based on operating voltages VL and VSUB. Circuit 123 operates based on operating voltages VH and VSUB. In some embodiments, operating voltage VH is greater than operating voltage VL, and operating voltage VL is greater than operating voltage VSUB.

When an ESD event occurs, operating system 100 operates in protection mode. In protection mode, ESD protection circuit 110 discharges ESD current from any of power pads PD_1, PD_2, and PD_3 to prevent the ESD current from entering core circuit 120. For example, when an ESD event occurs on power pad PD_1 and power pads PD_2 and PD_3 are coupled to ground, ESD protection circuit 110 provides a conductive path, allowing the ESD current to flow from power pad PD_1, through ESD protection circuit 110, and into power pads PD_2 and PD_3.

FIG2 is a schematic top view of an ESD protection device 400A of the ESD protection circuit 110 according to some embodiments of the present disclosure. FIG3 is a schematic cross-sectional view taken along lines A-A' and B-B' of the ESD protection device 400A according to some embodiments of the present disclosure shown in FIG2. FIG2 also shows the layout of the well regions W2, W5, W8, and W11 and the doped regions P1-P6, N1, and N2 of the ESD protection device 400A. To simplify the diagram, other components in FIG3 are omitted and not shown in FIG2.

As shown in Figures 2 and 3, the ESD protection device 400A includes a P-type semiconductor substrate 300, a deep N-type well (DNW) 310, wells W1, W2, W3, W4, W5, doped regions P1, P2, P3, P4, P5, N1, and N2.

In some embodiments, the P-type semiconductor substrate 300 may be a P-type semiconductor substrate. The semiconductor substrate includes elemental semiconductors such as silicon (Si) and germanium (Ge); compound semiconductors such as gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and indium sulphide (InSb); alloy semiconductors such as silicon germanium (SiGe), gallium arsenide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and gallium indium arsenide (GaInAsP); or combinations thereof. In addition, the P-type semiconductor substrate 300 may also be a P-type semiconductor on insulator (SOI).

A deep N-type well region 310 is disposed in a P-type semiconductor substrate 300. Well regions W1-W5 are all disposed on deep N-type well region 310. Well regions W1 and W2 are arranged side by side and adjacent to each other along a direction substantially parallel to tangent line A-A' (direction 510). Well regions W2 and W3 are arranged side by side and adjacent to each other along direction 510. Furthermore, well regions W1 and W3 are located on opposite sides of well region W2 along direction 510.

Well areas W3 and W4 are arranged side by side and adjacent to each other along the direction substantially parallel to the tangent line B-B' (direction 500). Well areas W4 and W5 are arranged side by side and adjacent to each other along direction 500. Furthermore, well areas W3 and W5 are located on opposite sides of well area W4 along direction 500.

In this embodiment, wells W1, W3, and W4 are P-type, while wells W2 and W5 are N-type. Furthermore, the bottom surfaces of wells W1-W5 are connected to deep N-type well 310. Wells W2 and W5 are electrically connected to each other through deep N-type well 310.

In some embodiments, the impurity concentrations of the well regions W1, W3, and W4 are similar and greater than the impurity concentration of the P-type substrate 300. The impurity concentrations of the well regions W2 and W5 are similar and greater than the impurity concentration of the deep N-type well region 310.

Doped region P1 is disposed in well region W1. Doped region P2 is disposed in well region W2. Doped region P3 is disposed in well region W3. Doped region P4 is disposed in well region W4. Doped region P5 is disposed in well region W5. Furthermore, doped regions P1-P5 extend from the top surface of P-type semiconductor substrate 300 into a portion of P-type semiconductor substrate 300. As shown in FIG2 , opposite sides of doped region P4 are adjacent to doped region P1 and doped region P3, respectively. Doped region P4 is adjacent to doped region P3 and is separated from doped region P2.

In this embodiment, in a direction substantially parallel to the tangent line B-B' (direction 500), doping region P4 is located between doping region P3 (or doping region P1) and doping region N1. Furthermore, doping region N1 is located between doping region P4 and doping region P5.

As shown in Figure 2, in some embodiments, doped regions P1-P3 extend substantially along direction 500 and are arranged parallel to one another. Doped regions P4, P5, and N1 extend substantially along direction 510 and are arranged parallel to one another. Doped region N2 is a ring-shaped structure that surrounds doped regions P1-P5 and doped region N1.

In some embodiments, the conductivity type of the doped regions P1-P5 is P-type. The impurity concentrations of the doped regions P1-P5 are similar and greater than the impurity concentrations of the well regions W1, W3, and W4.

Doped region N1 is disposed in well region W4. Doped region N2 is disposed in well region W5. In some embodiments, the conductivity type of doped regions N1 and N2 is N-type. The impurity concentration of doped regions N1 and N2 is greater than the impurity concentration of well regions W2 and W5.

In some embodiments, the ESD protection device 400A further includes a well region W6 and a doped region P6. The well region W6 is disposed in the P-type semiconductor substrate 300. The doped region P6 is disposed in the well region W6. As shown in FIG. 2 , in some embodiments, the doped region P6 is a ring-shaped structure that surrounds the doped region N2.

In some embodiments, the conductivity type of the well region W6 and the doped region P6 is P-type. The impurity concentration of the doped region P6 is greater than the impurity concentration of the well region W6. The impurity concentration of the well region W6 is similar to the impurity concentration of the well region W1. The impurity concentration of the doped region P6 is similar to the impurity concentration of the doped region P1.

The present invention does not limit the type of well regions W1-W6. When the impurity concentration in well regions W1-W6 is low (e.g., below a threshold), well regions W1-W6 function as high-voltage wells. In this case, the maximum operating voltage VH of ESD protection device 400A can reach a first value. When the impurity concentration in well regions W1-W6 is high (e.g., above the threshold), well regions W1-W6 function as low-voltage wells. In this case, the maximum operating voltage VH of ESD protection device 400A can reach a second value. In this example, the first value is greater than the second value. In other embodiments, the well regions W1-W6 may be of different types. For example, at least one of the well regions W1-W6 is a low-voltage well region, and the remaining well regions are high-voltage well regions. In this example, the maximum value of the operating voltage VH may be between the first value and the second value.

In one possible embodiment, well regions W1, W3, W4, and W6 are referred to as high voltage P-well regions (HVPW), and well regions W2 and W5 are referred to as high voltage N-well regions (HVNW).

In some embodiments, the ESD protection device 400A further includes well region W7, well region W8, well region W9, well region W10, well region W11, and well region W12. Well region W7 is disposed on well region W1 and is located between well region W1 and doped region P1 in a direction substantially perpendicular to the top surface of the P-type semiconductor substrate 300 (direction 520). Furthermore, well region W7 has a P-type conductivity. The impurity concentration of well region W7 is greater than the impurity concentration of well region W1 and less than the impurity concentration of doped region P1. Well region W8 is disposed in well region W2 and is located between well region W2 and doped region P2 in direction 520. Furthermore, well region W8 has an N-type conductivity. The impurity concentration of well region W8 is greater than the impurity concentration of well region W2 and less than the impurity concentration of doped regions N1 and N2. Well region W9 is disposed in well region W3 and is located between well region W3 and doped region P3 in direction 520. Furthermore, well region W3 has a P-type conductivity. The impurity concentration of well region W9 is greater than the impurity concentration of well region W3 and less than the impurity concentration of doped region P3. Well region W10 is disposed in well region W4 and is located between well region W4 and doped region P4 (or between well region W4 and doped region N1) in direction 520. Furthermore, well region W10 has a P-type conductivity. The impurity concentration of well region W10 is greater than that of well region W4 and less than that of doped region P4. Well region W11 is located within well region W5 and, in direction 520, is between well region W5 and doped region P5 (or between well region W5 and doped region N2). Furthermore, well region W11 has an N-type conductivity. The impurity concentration of well region W11 is greater than that of well region W5 and less than that of doped region N1. Well region W12 is located within well region W6 and, in direction 520, is between well region W6 and doped region P6. Furthermore, well region W12 has a P-type conductivity. The impurity concentration in well region W12 is greater than that in well region W6, but less than that in doped region P6.

Wells W7, W9, W10, and W12 have similar impurity concentrations, and wells W8 and W11 have similar impurity concentrations. In one possible embodiment, wells W7, W9, W10, and W12 are referred to as low-voltage P-wells (LVPW), and wells W8 and W11 are referred to as low-voltage N-wells (LVNW). In this example, wells W1, W3, W4, and W6 are referred to as high-voltage P-wells (LVPW), and wells W2 and W5 are referred to as high-voltage N-wells (HVNW).

In some embodiments, when well regions W7-W12 are respectively disposed within well regions W1-W6, the maximum operating voltage VH of the ESD protection device 400A can reach a third value. In this example, the third value is greater than the first value. For example, the third value may be 20V.

In some embodiments, a multi-pass ion implantation process can be used to implant P-type and N-type dopants into the P-type semiconductor substrate 300 to form a deep N-type well region 310, well regions W1-W12, doped regions P1-P6, and doped regions N1 and N2. In some embodiments, the N-type dopant may include phosphorus, arsenic, nitrogen, antimony, or a combination thereof. In some embodiments, the P-type dopant may include boron, gallium, aluminum, indium, boron trifluoride ions (BF ₃ ⁺ ), or a combination thereof. In some embodiments, well regions W1, W3, W4, and W6 may be formed simultaneously using the same ion implantation process or using different ion implantation processes; well regions W2 and W5 may be formed simultaneously using the same ion implantation process or using different ion implantation processes; well regions W7, W9, W10, and W12 may be formed simultaneously using the same ion implantation process or using different ion implantation processes; well regions W8 and W11 may be formed simultaneously using the same ion implantation process or using different ion implantation processes; doped regions P1 to P6 may be formed simultaneously using the same ion implantation process or using different ion implantation processes; and doped regions N1 and N2 may be formed simultaneously using the same ion implantation process or using different ion implantation processes.

In some embodiments, the ESD protection structure 400A further includes a resist protective oxide (RPO) 320. As shown in FIG. 2 , in some embodiments, the RPO 320 overlaps portions of the doped regions P1, P3, and P4. As shown in FIG. 3 , the RPO 320 is disposed on the P-type semiconductor substrate 300, covering a portion of the doped region P3 proximate to the doped region P4 and extending to cover the doped region P4. In some embodiments, the resistive protection oxide 320 is used to shield regions where silicide formation is prohibited, preventing the silicide formation in these regions during the silicidation process. This helps maintain electrical properties in these regions and improve the surface resistance of the P-type semiconductor substrate 300. In some embodiments, the resistive protection oxide 320 is used to cut off silicide features formed on the top surface of the P-type semiconductor substrate 300 at the interface between the doped regions P3 and P4. In some embodiments, the resistive protection oxide 320 can be formed using a chemical vapor deposition (CVD) process or other suitable process. In some embodiments, the material of the resistive protection oxide 320 may include silicon dioxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.

The ESD protection structure 400A further includes silicide components SA1, SA2, SA3, SA4, SA5, SA6, SA7, and SA8 formed on the top surface of the P-type semiconductor substrate 300. Specifically, the silicide component SA1 completely covers the doped region P1. The silicide component SA2 completely covers the doped region P2. The silicide component SA3 covers the portion of the doped region P3 not covered by the resistive protection oxide 320. Silicide feature SA4 covers the portion of doped region P4 not covered by the resistive protection oxide 320 (i.e., the top surface of the P-type semiconductor substrate 300 at the interface between doped region P3 and doped region P4 is not covered by the silicide feature). Silicide feature SA5 completely covers doped region N1. Silicide feature SA6 completely covers doped region P5. Silicide feature SA7 completely covers doped region N2. Silicide feature SA8 completely covers doped region P6. Silicide features SA1-SA8 are isolated from each other.

In some embodiments, the silicide features SA1-SA8 include a metal silicide (e.g., tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide, geron silicide, other suitable metal silicides, or combinations thereof). In some embodiments, the metal layer may be deposited globally using chemical vapor deposition (CVD) (e.g., low-pressure vapor deposition (LPCVD) or plasma-assisted chemical vapor deposition (PECVD)), physical vapor deposition (PVD) (e.g., resistive thermal evaporation, electron beam evaporation, or sputtering), electroplating, atomic layer deposition (ALD), other suitable processes, or a combination thereof. An annealing process is then performed to cause the metal layer on the doped regions P1-P8, N1, and N2 not covered by the resistive protection oxide 320 to react with the semiconductor material, forming silicide features SA1-SA8. The unreacted metal layer is then removed.

In addition, the ESD protection structure 400A further includes isolation members S_1, S_2, S_3, S_4, S_5, S_6, S_7, and S_8. Isolation members S_1-S_8 are formed on the top surface of the P-type semiconductor substrate 300 and extend partially into the P-type semiconductor substrate 300. Specifically, the doped region P1 is located between isolation member S_1 and isolation member S_2. Isolation member S_2 separates doped region P1 from doped region P2. Isolation member S_2 further separates well region W7 from well region W8. Isolation member S_3 separates doped region P2 from doped region P3. Isolation member S_3 further separates well region W8 from well region W9. Isolation component S_4 is located in well W10 and separates doped region P4 from doped region N1. In this embodiment, isolation component S_5 separates doped region N1 from doped region P5. Isolation component S_5 further separates well W10 from well W11. Isolation component S_6 is located in well W11 and separates doped region P5 from doped region N2. Isolation component S_7 separates doped region N2 from doped region P6. Isolation component S_7 further separates well W11 from well W12. Furthermore, doped region P6 is located between isolation component S_7 and isolation component S_8. In some embodiments, there is no isolation component between well region W9 and well region W10.

In some embodiments, isolation components S_1-S_8 are field oxides (FOX) formed using a local oxidation of silicon (LOCOS) process, shallow trench isolation (STI) structures formed using a deposition process, or other suitable isolation structures. In some embodiments, isolation components S_1-S_8 are formed using a thermal oxidation process, including a dry oxidation process, a wet oxidation process, or other suitable thermal oxidation process.

ESD protection device 400A further includes interconnect structures 330, 340, and 350. Interconnect structure 330 is electrically connected to power pad PD_1. Furthermore, interconnect structure 330 is directly connected to silicide components SA2, SA6, and SA7, and electrically connected to doped regions P2, P5, and N1 via silicide components SA2, SA6, and SA7. Interconnect structure 340 is electrically connected to power pad PD_2. Furthermore, interconnect structure 340 is directly connected to silicide components SA1, SA3, SA4, and SA5, and electrically connected to doped regions P1, P3, P4, and N1 via silicide components SA1, SA3, SA4, and SA5. Interconnect structure 350 is electrically connected to power pad PD_3. Furthermore, interconnect structure 350 is directly connected to silicide feature SA8 and electrically connected to doped region P6 via silicide feature SA8. In this example, power pad PD_1 receives operating voltage VH, power pad PD_2 receives operating voltage VL, and power pad PD_3 receives operating voltage VSUB.

FIG4 is a schematic top view of an ESD protection device 400B of an ESD protection circuit 110 according to some embodiments of the present disclosure. FIG5 is a schematic cross-sectional view taken along lines A-A' and B-B' of the ESD protection device 400B according to some embodiments of the present disclosure shown in FIG4. FIG4 also shows the layout of the well regions W2, W5, W8, and W11, doped regions P1-P6, and doped regions N1 and N2 of the ESD protection device 400B. To simplify the diagram, other components in FIG5 are omitted and not shown in FIG4. FIG4 is similar to FIG2 , except that opposite sides of doped region N1 of the ESD protection device 400B are adjacent to doped region P1 and doped region P3, respectively. Doped region N1 is adjacent to doped region P3. Furthermore, doped region N1 is separated from doped region P2. Furthermore, in direction 500 , doped region N1 is located between doped region P3 and doped region P4, and doped region P4 is located between doped region N1 and doped region P5. The resistive protection oxide 320 partially overlaps the doped regions P3 and N1 to cut off the surface silicide features SA3 and SA5 formed at the interface between the doped regions P3 and N1.

Figure 6 is a schematic diagram illustrating the connections of the equivalent circuit of the ESD protection device 400A shown in Figures 2 and 3 according to some embodiments of the present invention within the operating system 100. It illustrates the equivalent circuit where an ESD event occurs between power pads PD_1 and PD_2. Figure 7 is a schematic diagram illustrating the locations of the parasitic elements of the equivalent circuit in Figure 6 at the corresponding locations within the ESD protection device 400A in Figure 3.

As shown in Figures 6 and 7, when an ESD event occurs between power pads PD_1 and PD_2, the equivalent discharge circuit of ESD protection device 400A includes parasitic PNP-type bipolar transistor (BPT) PNP_1, parasitic PNP-type bipolar transistor (BPT) PNP_2, parasitic PNP-type bipolar transistor (BPT) PNP_3, parasitic PNP-type bipolar transistor (BPT) PNP_4, parasitic NPN-type bipolar transistor (BPT) NPN_1, parasitic NPN-type bipolar transistor (BPT) NPN_2, parasitic resistors R_1, R_2, R_3, R_4, and parasitic diode D1.

In ESD protection device 400A, doped region P2, well W8, well W2, deep N-type well 310, doped region P1, well W7, and well W1 form a parasitic PNP bipolar junction transistor PNP_1. Doped region P1, well W7, and well W1 form the collector of parasitic PNP bipolar junction transistor PNP_1. Doped region P2 serves as the emitter of parasitic PNP bipolar junction transistor PNP_1. Deep N-type well 310, well W2, and well W8 form the base of parasitic PNP bipolar junction transistor PNP_1. The equivalent resistance of deep N-type well 310 serves as parasitic resistor R_1.

Doped region P1, well W7, well W1, deep N-type well 310, well W5, well W11, doped region N2, P-type semiconductor substrate 300, well W6, well W12, and doped region P6 form a parasitic PNP bipolar junction transistor PNP_2. Doped region P1, well W7, and well W1 form the emitter of parasitic PNP bipolar junction transistor PNP_2. Deep N-type well 310, wells W5, W11, and doped region N3 form the base of parasitic PNP bipolar junction transistor PNP_2. The P-type substrate 300, well regions W6 and W12, and doped region P6 form the collector of the parasitic PNP bipolar junction transistor PNP_2.

Doped region P2, well region W2, well region W8, deep N-type well region 310, and well region W3 form a parasitic PNP bipolar junction transistor PNP_3. Doped region P2 serves as the emitter of parasitic PNP bipolar junction transistor PNP_3. Well regions W8, W2, and deep N-type well region 310 form the base of parasitic PNP bipolar junction transistor PNP_3. Well region W3 forms the collector of parasitic PNP bipolar junction transistor PNP_3.

Doped region P5, well W5, well W11, deep N-type well 310, and well W4 form a parasitic PNP bipolar junction transistor PNP_4. Doped region P5 serves as the emitter of parasitic PNP bipolar junction transistor PNP_4. Wells W11, W15, and deep N-type well 310 form the base of parasitic PNP bipolar junction transistor PNP_4. Well W4 forms the collector of parasitic PNP bipolar junction transistor PNP_4. The equivalent resistance of deep N-type well 310, wells W5, and W11 serves as parasitic resistor R_2.

Doped region N1, well W10, well W4, well W3, deep N-type well 310, well W5, well W11, and doped region N2 form a parasitic NPN bipolar junction transistor NPN_1. Doped region N1 serves as the emitter of parasitic NPN bipolar junction transistor NPN_1. Wells W10, W4, and W3 form the base of parasitic NPN bipolar junction transistor NPN_1. Deep N-type well 310, wells W5, W11, and doped region N2 form the collector of parasitic NPN bipolar junction transistor NPN_1.

Doped region N1, well W10, well W4, deep N-type well 310, well W5, well W11, and doped region N2 form a parasitic NPN bipolar junction transistor NPN_2. Doped region N1 serves as the emitter of NPN bipolar junction transistor NPN_2. Wells W10 and W4 form the base of NPN bipolar junction transistor NPN_2. Deep N-type well 310, wells W5, W11, and doped region N2 form the collector of NPN bipolar junction transistor NPN_2. The equivalent resistance of well W10 serves as resistors R_3 and R_4.

The P-type semiconductor substrate 300, well W6, well W12, doped region P6, deep N-type well 310, well W5, well W11, and doped region N2 form a parasitic diode D1. Deep N-type well 310, well W5, well W11, and doped region N2 form the cathode of parasitic diode D1. The P-type semiconductor substrate 300, well W6, well W12, and doped region P6 form the anode of parasitic diode D1.

The emitter of the PNP bipolar junction transistor PNP_1 is coupled to the power pad PD_1. The collector of the PNP bipolar junction transistor PNP_1 is coupled to the power pad PD_2. The base of the PNP bipolar junction transistor PNP_1 is coupled to the power pad PD_1 via a parasitic resistor R_1 formed by the deep N-well region 310.

The emitter of the PNP bipolar junction transistor PNP_2 is coupled to the power pad PD_2. The collector of the PNP bipolar junction transistor PNP_2 is coupled to the power pad PD_3. The base of the PNP bipolar junction transistor PNP_2 is coupled to the cathode of the parasitic diode D1. The anode of the parasitic diode D1 is coupled to the power pad PD_3.

The emitter of parasitic PNP bipolar junction transistor PNP_3 is coupled to power pad PD_1. The base of parasitic PNP bipolar junction transistor PNP_3 is coupled to the base of parasitic PNP bipolar junction transistor PNP_1. Furthermore, the base of parasitic PNP bipolar junction transistor PNP_3 is also coupled to power pad PD_1 via parasitic resistor R_1 formed by deep N-well region 310.

The emitter of parasitic NPN bipolar junction transistor NPN_1 is coupled to power pad PD_2. The base of parasitic NPN bipolar junction transistor NPN_1 is coupled to the collector of parasitic PNP bipolar junction transistor PNP_3. The collector of parasitic NPN bipolar junction transistor NPN_1 is coupled to the base of parasitic PNP bipolar junction transistor PNP_3 to form parasitic semiconductor controlled rectifier SCR_1. Furthermore, the collector of parasitic NPN bipolar junction transistor NPN_1 is coupled to power pad PD_1 via parasitic resistor R_1 formed by deep N-well region 310. In this embodiment, the collector of the parasitic PNP bipolar junction transistor PNP_3 and the base of the parasitic NPN bipolar junction transistor NPN_1 are coupled to the power pad PD_2 via the parasitic resistor R_3 formed by the well region W10.

The emitter of parasitic PNP bipolar junction transistor PNP_4 is coupled to power pad PD_1. The base of parasitic PNP bipolar junction transistor PNP_4 is coupled to the collector of parasitic NPN bipolar junction transistor NPN_2. The collector of parasitic PNP bipolar junction transistor PNP_4 is coupled to the base of parasitic NPN bipolar junction transistor NPN_2 to form parasitic semiconductor controlled rectifier SCR_2. Furthermore, the base of parasitic PNP bipolar junction transistor PNP_4 is also coupled to power pad PD_1 via parasitic resistor R_2 formed by deep N-well region 310.

The base of parasitic NPN bipolar transistor NPN_2 is coupled to the base of parasitic NPN bipolar transistor NPN_1. The emitter of parasitic NPN bipolar transistor NPN_2 is coupled to power pad PD_2. Furthermore, the collector of parasitic NPN bipolar transistor NPN_2 is also coupled to power pad PD_1 via parasitic resistor R_2 formed by deep N-well region 310. In this embodiment, the collector of parasitic PNP bipolar transistor PNP_4 and the base of parasitic NPN bipolar transistor NPN_2 are coupled to power pad PD_2 via parasitic resistor R_4 formed by well region W10.

FIG6 can also be viewed as a schematic diagram of an ESD protection circuit 110A (including ESD protection circuits 110A-1 and 110A-2) in an operating system 100 according to some embodiments of the present invention. ESD protection circuit 110A includes PNP-type bipolar transistors (PNP_1), PNP_2, PNP_3, PNP_4, NPN-type bipolar transistors (NPN_1), NPN_2, resistors R_1, R_2, R_3, R_4, and a diode D1. In some embodiments, the PNP bipolar junction transistors PNP_1 to PNP_4, the NPN bipolar junction transistors NPN_1 and NPN_2, the resistors R_1 to R_4, and the diode D1 share the same substrate, such as a P-type semiconductor substrate 300.

The emitter of PNP bipolar junction transistor PNP_1 is coupled to power pad PD_1. The collector of PNP bipolar junction transistor PNP_1 is coupled to power pad PD_2. Resistor R_1 is coupled between power pad PD_1 and the base of PNP bipolar junction transistor PNP_1.

The emitter of the PNP bipolar junction transistor PNP_2 is coupled to the power pad PD_2. The collector of the PNP bipolar junction transistor PNP_2 is coupled to the power pad PD_3.

The cathode of diode D1 is coupled to power pad PD_1 and the base of PNP bipolar junction transistor PNP_2. The anode of diode D1 is coupled to power pad PD_3.

The emitter of the PNP bipolar junction transistor PNP_3 is coupled to the power pad PD_1. The base of the PNP bipolar junction transistor PNP_3 is coupled to the base of the PNP bipolar junction transistor PNP_1.

The emitter of a first NPN bipolar junction transistor NPN_1 is coupled to a power pad PD_2. A resistor R_3 is coupled between the power pad PD_2 and the base of the NPN bipolar junction transistor NPN_1. The base of the NPN bipolar junction transistor NPN_1 is coupled to the collector of the PNP bipolar junction transistor PNP_3. The collector of the first NPN bipolar junction transistor NPN_1 is coupled to the base of the PNP bipolar junction transistor PNP_3 to form a semiconductor controlled rectifier SCR_1.

The emitter of PNP bipolar junction transistor PNP_4 is coupled to power pad PD_1. Resistor R_2 is coupled between power pad PD_1 and the base of PNP bipolar junction transistor PNP_4. The emitter of NPN bipolar junction transistor NPN_2 is coupled to power pad PD_2. Resistor R_4 is coupled between power pad PD_2 and the base of NPN bipolar junction transistor NPN_2. The base of PNP bipolar junction transistor PNP_4 is coupled to the collector of NPN bipolar junction transistor NPN_2. The collector of PNP bipolar junction transistor PNP_4 is coupled to the base of NPN bipolar junction transistor NPN_2 to form semiconductor controlled rectifier SCR_2. Furthermore, the base of NPN bipolar junction transistor NPN_1 is coupled to the base of NPN bipolar junction transistor NPN_2.

FIG8 is a schematic diagram illustrating the connections of the equivalent circuit of the ESD protection device 400B shown in FIG4 and FIG5 in accordance with some embodiments of the present invention within the operating system 100. FIG8 illustrates the equivalent circuit in which an ESD event occurs between power pads PD_1 and PD_2. FIG9 is a schematic diagram illustrating the locations of parasitic elements in the equivalent circuit of FIG8 at corresponding locations within the ESD protection device 400B of FIG5. Figure 8 is similar to Figure 6, except that the equivalent discharge circuit of the ESD protection device 400B includes a parasitic PNP bipolar transistor (BPT) PNP_1, a parasitic PNP bipolar transistor (BPT) PNP_2, a parasitic PNP bipolar transistor (BPT) PNP_3, a parasitic PNP bipolar transistor (BPT) PNP_4, a parasitic NPN bipolar transistor (BPT) NPN_1, a parasitic NPN bipolar transistor (BPT) NPN_2, parasitic resistors R_1, R_2, R_5, R_6, and a parasitic diode D1.

In this embodiment, the collector of parasitic PNP bipolar junction transistor PNP_3 and the base of parasitic NPN bipolar junction transistor NPN_1 are coupled to power pad PD_2 via parasitic resistor R_5 formed by well region W9. Furthermore, the collector of parasitic PNP bipolar junction transistor PNP_4 and the base of parasitic NPN bipolar junction transistor NPN_2 are coupled to power pad PD_2 via parasitic resistor R_6 formed by well region W9.

FIG8 can also be viewed as a schematic diagram of an ESD protection circuit 110B (including ESD protection circuits 110B-1 and 110B-2) in an operating system 100 according to some embodiments of the present invention. The ESD protection circuit 110B includes a PNP-type bipolar transistor (Bipolar Junction Transistor) PNP_1, a PNP-type bipolar transistor (Bipolar Junction Transistor) PNP_2, a PNP-type bipolar transistor (Bipolar Junction Transistor) PNP_3, a PNP-type bipolar transistor (Bipolar Junction Transistor) PNP_4, an NPN-type bipolar transistor (Bipolar Junction Transistor) NPN_1, an NPN-type bipolar transistor (Bipolar Junction Transistor) NPN_2, resistors R_1, R_2, R_5, R_6, and a diode D1. In some embodiments, the PNP bipolar junction transistors PNP_1 to PNP_4, the NPN bipolar junction transistors NPN_1 and NPN_2, the resistors R_1, R_2, R_5, and R_6, and the diode D1 share the same substrate, such as a P-type semiconductor substrate 300.

The ESD protection circuit 110B is similar to the ESD protection circuit 110A, except that the resistor R_5 in the ESD protection circuit 110B is coupled between the power pad PD_2 and the base of the NPN bipolar junction transistor NPN_1. The resistor R_6 is coupled between the power pad PD_2 and the base of the NPN bipolar junction transistor NPN_2.

Because the base of parasitic PNP bipolar transistor PNP_3 in ESD protection devices 400A and 400B is coupled to the base of parasitic PNP bipolar transistor PNP_1, and the base of parasitic NPN bipolar transistor NPN_2 is coupled to the base of parasitic NPN bipolar transistor NPN_1, the equivalent circuit of ESD protection devices 400A and 400B exhibits the characteristics of both a PNP bipolar transistor and a semiconductor controlled rectifier. When an ESD event occurs on power pad PD_1 and power pads PD_2 and PD_3 are coupled to ground, a forward bias is applied to the emitter-base junctions of parasitic PNP bipolar transistors PNP_1, PNP_3, and PNP_4. This also applies a forward bias to the base-emitter junctions of parasitic NPN bipolar transistors NPN_1 and NPN_2 in ESD protection devices 400A and 400B, causing the parasitic PNP bipolar transistors PNP_1, PNP_3, and PNP_4, as well as the parasitic NPN bipolar transistors NPN_1 and NPN_2, to be simultaneously triggered into conduction. Because the parasitic PNP bipolar junction transistors PNP_3 and PNP_4 and the parasitic NPN bipolar junction transistors NPN_1 and NPN_2 of the ESD protection devices 400A and 400B are simultaneously triggered to conduct, the parasitic semiconductor controlled rectifiers SCR-1 and SCR-2 are also triggered to conduct. This causes the ESD current to flow from the power pad PD_1, through the parasitic PNP bipolar junction transistor PNP_1 and the parasitic semiconductor controlled rectifiers SCR-1 and SCR-2 of the ESD protection devices 400A and 400B, and into the power pad PD_2, thus preventing the ESD current from flowing through the protected core circuit 120.

As shown in Figures 6 and 8, when an ESD event occurs at power pad PD_1 and power pads PD_2 and PD_3 are coupled to ground, a forward bias is applied to the emitter-base junctions of PNP bipolar junction transistors PNP_1, PNP_3, and PNP_4 in ESD protection circuits 110A and 110B, and the ESD is reversed. A forward bias is applied to the base-emitter junctions of the NPN bipolar junction transistors NPN_1 and NPN_2 of the protection circuits 110A and 110B, causing the PNP bipolar junction transistors PNP_1, PNP_3, and PNP_4 as well as the NPN bipolar junction transistors NPN_1 and NPN_2 to be simultaneously triggered and turned on. Because the PNP bipolar junction transistors PNP_3 and PNP_4 and the NPN bipolar junction transistors NPN_1 and NPN_2 in the ESD protection circuits 110A and 110B are simultaneously triggered to conduct, the semiconductor controlled rectifiers SCR-1 and SCR-2 are also triggered to conduct. This causes the ESD current to flow from the power pad PD_1, through the PNP bipolar junction transistor PNP_1 and the semiconductor controlled rectifiers SCR-1 and SCR-2 in the ESD protection circuits 110A and 110B, and into the power pad PD_2, preventing the ESD current from flowing through the protected core circuit 120.

As shown in Figures 3, 5, 7, and 9, the isolation member S_4 between doping regions P1 and N1 in the same well W4 (and well W10) has a width DS1. Furthermore, the isolation member S_6 between doping regions P5 and N2 in the same well W5 (and well W11) has a width DS2. In some embodiments, isolation members S_4 and S_6 are related to the performance of ESD protection structures 400A and 400B. For example, in direction 500 (Figures 7 and 9), the width DS1 of isolation member S_4 and the width DS2 of isolation member S_6 are proportional to the resistance values of parasitic resistors R_1 and R_2. Therefore, under appropriate layout areas, the widths DS1 and DS2 can be adjusted to adjust the ratio of the ESD current flowing through the parasitic semiconductor controlled rectifiers SCR-1 and SCR-2 and the parasitic PNP bipolar junction transistor PNP_1. This can further adjust the holding voltage (V _Hold ) of the ESD protection devices 400A and 400B to be greater than the operating voltage of the operating system 100. This makes the ESD protection devices 400A and 400B less susceptible to noise triggering and enables the ESD protection devices 400A and 400B to have better human body discharge mode (HBM) and mechanical discharge mode (MM) performance. For example, when an ESD event occurs on power pad PD_1 and power pads PD_2 and PD_3 are coupled to ground, and width DS1 and width DS2 are 0, ESD protection devices 400A and 400B exhibit the characteristics of a PNP bipolar junction transistor. When an ESD event occurs on power pad PD_1 and power pads PD_2 and PD_3 are coupled to ground, and the widths DS1 and DS2 increase, the parasitic semiconductor controlled rectifiers SCR-1 and SCR-2 are triggered to conduct sooner, causing the ESD current flowing through parasitic semiconductor controlled rectifiers SCR-1 and SCR-2 to increase while the ESD current flowing through parasitic PNP bipolar junction transistor PNP_1 decreases. Furthermore, the holding voltage (V _Hold ) of ESD protection devices 400A and 400B decreases as the widths DS1 and DS2 increase.

Compared to ESD protection device 400A, the collectors of parasitic NPN bipolar junction transistors NPN_1 and NPN_2 in ESD protection device 400B are farther away from power pad PD_1 (parasitic resistor R_2 has a larger resistance). When an ESD event occurs at power pad PD_1 and power pads PD_2 and PD_3 are coupled to ground, parasitic semiconductor controlled rectifiers SCR-1 and SCR-2 in ESD protection device 400B are triggered and turned on earlier, resulting in a larger holding voltage (V _Hold ) for the same layout area.

An embodiment of the present invention provides an electrostatic discharge protection device. The electrostatic discharge protection device includes a P-type semiconductor substrate, a deep N-type well region, a first well region, a first P-type doped region, a second well region, a second P-type doped region, a third well region, a third P-type doped region, a fourth well region, a fourth P-type doped region, a first N-type doped region, a fifth well region, a fifth P-type doped region, and a second N-type doped region. The deep N-type well region is disposed in the P-type semiconductor substrate. The first well region is disposed above the deep N-type well region. The first P-type doped region is disposed in the first well region. The second well region is disposed above the deep N-type well region. The second P-type doped region is disposed in the second well region. The third well region is disposed above the deep N-type well region. A third P-type doped region is disposed in the third well region. A fourth well region is disposed above the deep N-type well region. A fourth P-type doped region is disposed in the fourth well region. A first N-type doped region is disposed in the fourth well region. A fifth well region is disposed above the deep N-type well region. A fifth P-type doped region is disposed in the fifth well region. A second N-type doped region is disposed in the fifth well region. The first, third, and fourth well regions are of P-type conductivity, and the second and fifth well regions are of N-type conductivity. The second P-type doped region, the fifth P-type doped region, and the second N-type doped region are electrically connected to the first power pad. The first P-type doped region, the third P-type doped region, the fourth P-type doped region, and the first N-type doped region are electrically connected to the second power pad.

The second P-type doped region, the second well region, the deep N-type well region, the first doped region, and the first well region form a first parasitic PNP bipolar junction transistor. The first P-type doped region, the first well region, the deep N-type well region, the fifth well region, the second N-type doped region, and the P-type semiconductor substrate form a second parasitic PNP bipolar junction transistor. The second P-type doped region, the second well region, the deep N-type well region, and the third well region form a third parasitic PNP bipolar junction transistor. The fifth P-type doped region, the fifth well region, the deep N-type well region, and the fourth well region form a fourth parasitic PNP bipolar junction transistor. The first N-type doped region, the fourth well region, the third well region, the deep N-type well region, the fifth well region, and the second N-type doped region form a first parasitic NPN bipolar junction transistor. The first N-type doped region, the fourth well region, the deep N-type well region, the fifth well region, and the second N-type doped region form a second parasitic NPN bipolar junction transistor. The P-type semiconductor substrate, the deep N-type well region 310, the fifth well region W5, and the second N-type doped region N2 form a first parasitic diode.

The collector of the first parasitic PNP bipolar junction transistor is coupled to the second power pad. The emitter of the first parasitic PNP bipolar junction transistor is coupled to the first power pad.

The emitter of the second parasitic PNP bipolar junction transistor is coupled to the second power pad. The collector of the second parasitic PNP bipolar junction transistor is coupled to the third power pad. The base of the second parasitic PNP bipolar junction transistor is coupled to the cathode of the first parasitic diode.

The emitter of the third parasitic PNP bipolar junction transistor is coupled to the first power pad. The base of the third parasitic PNP bipolar junction transistor is coupled to the base of the first parasitic PNP bipolar junction transistor.

The emitter of the first parasitic NPN bipolar junction transistor is coupled to the second power pad. The base of the first parasitic NPN bipolar junction transistor is coupled to the collector of the third parasitic PNP bipolar junction transistor. The collector of the first parasitic NPN bipolar junction transistor is coupled to the base of the third parasitic PNP bipolar junction transistor to form a first parasitic semiconductor controlled rectifier.

The emitter of the fourth parasitic PNP bipolar junction transistor is coupled to the first power pad. The base of the fourth parasitic PNP bipolar junction transistor is coupled to the collector of the second parasitic NPN bipolar junction transistor. The collector of the fourth parasitic PNP bipolar junction transistor is coupled to the base of the second parasitic NPN bipolar junction transistor to form a second parasitic semiconductor controlled rectifier.

The base of the second parasitic NPN bipolar junction transistor is coupled to the base of the first parasitic NPN bipolar junction transistor. The emitter of the second parasitic NPN bipolar junction transistor is coupled to the second power pad.

In addition, embodiments of the present invention provide an electrostatic discharge protection circuit for protecting core circuits. The electrostatic discharge protection circuit includes a first PNP-type bipolar junction transistor (BJT), a second PNP-type bipolar junction transistor (BJT), a first diode, a third PNP-type bipolar junction transistor (BJT), a first NPN-type bipolar junction transistor (NPN-type bipolar junction transistor), a fourth PNP-type bipolar junction transistor (BJT), a second NPN-type bipolar junction transistor (NPN-type bipolar junction transistor), a first resistor, a second resistor, a third resistor, and a fourth resistor. The emitter of the first PNP-type bipolar junction transistor is coupled to a first power pad. The collector of the first PNP-type bipolar junction transistor is coupled to a second power pad. An emitter of the second PNP bipolar junction transistor is coupled to the second power pad. A collector of the second PNP bipolar junction transistor is coupled to the third power pad. A cathode of the first diode is coupled to the first power pad and the base of the second PNP bipolar junction transistor. An anode of the first diode is coupled to the third power pad. An emitter of the third PNP bipolar junction transistor is coupled to the first power pad. A base of the third PNP bipolar junction transistor is coupled to the base of the first PNP bipolar junction transistor. An emitter of the first NPN bipolar junction transistor is coupled to the second power pad. The base of the first NPN bipolar junction transistor is coupled to the collector of the third PNP bipolar junction transistor. The collector of the first NPN bipolar junction transistor is coupled to the base of the third PNP bipolar junction transistor to form a first semiconductor controlled rectifier. The emitter of the fourth PNP bipolar junction transistor is coupled to the first power pad. The emitter of the second NPN bipolar junction transistor is coupled to the second power pad. The base of the fourth PNP bipolar junction transistor is coupled to the collector of the second NPN bipolar junction transistor. The collector of the fourth PNP bipolar junction transistor is coupled to the base of the second NPN bipolar junction transistor to form a second semiconductor controlled rectifier. The base of the first NPN bipolar junction transistor is coupled to the base of the second NPN bipolar junction transistor. A first resistor is coupled between the first power pad and the base of the first PNP bipolar junction transistor. A second resistor is coupled between the first power pad and the base of the fourth PNP bipolar junction transistor. A third resistor is coupled between the second power pad and the base of the first NPN bipolar junction transistor. The fourth resistor is coupled between the second power pad and the base of the second NPN bipolar junction transistor.

The equivalent circuit of the electrostatic discharge protection device of the embodiment of the present invention and the electrostatic discharge protection circuit of the embodiment of the present invention simultaneously exhibit the characteristics of a PNP bipolar junction transistor and a semiconductor controlled rectifier. When an ESD event occurs at the first power pad and the second power pad is grounded, the first (parasitic) PNP bipolar junction transistor, the first (parasitic) semiconductor controlled rectifier, and the second (parasitic) semiconductor controlled rectifier are triggered to conduct, causing the ESD current to flow from the first power pad through the equivalent circuit of the ESD protection device or the first (parasitic) PNP bipolar junction transistor, the first (parasitic) semiconductor controlled rectifier, and the second (parasitic) semiconductor controlled rectifier of the ESD protection circuit, and into the second power pad, thereby preventing the ESD current from flowing through the protected core circuit.

In some embodiments, the width of the isolation member between the first P-type doped region P1 and the first N-type doped region N1 in the fourth well region (e.g., width DS1) and the width of the isolation member between the fifth P-type doped region and the second N-type doped region in the fifth well region (e.g., width DS2) can be adjusted to adjust the ratio of the ESD current flowing through the first (parasitic) PNP bipolar junction transistor, the first (parasitic) semiconductor controlled rectifier, and the second (parasitic) semiconductor controlled rectifier, so as to further adjust the holding voltage (V _Hold ) of the ESD protection device (or ESD protection circuit). ) to be greater than the operating voltage of the operating system, making the ESD protection device less susceptible to noise triggering and achieving better performance in both the human body discharge model (HBM) and the mechanical discharge model (MM).

It should be understood that when an element is referred to as being "coupled" to another element, it can be directly coupled or connected to the other element, or it can have other elements intervening therebetween. Conversely, if an element is "connected" to another element, there will be no other elements intervening therebetween.

Unless otherwise defined, all terms used herein (including technical and scientific terms) are generally understood by those skilled in the art to which this invention belongs. Furthermore, unless expressly stated otherwise, dictionary definitions of terms should be interpreted as consistent with their meanings in articles in the relevant art and should not be construed as ideal or overly formal. Although terms such as "first" and "second" may be used to describe various elements, these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. In the claims, terms such as "first" and "second" are used as labels and are not intended to impose numerical requirements on their objects.

Although the present invention is disclosed above with reference to the aforementioned embodiments, they are not intended to limit the present invention. Those skilled in the art may make modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.

300: P-type semiconductor substrate

310: Deep N-type well area

320: Resistive Protective Oxide

330,340,350: Internal link structure

400A: Electrostatic discharge protection device

500,510,520: Direction

A-A’,B-B’: Tangent line

D1: Parasitic diode

DS1, DS2: Width

NPN_1, NPN_2: Parasitic NPN bipolar junction transistors

PD_1, PD_2, PD_3: Power pads

P1, P2, P3, P4, P5, P6, N1, N2: Doped Area

PNP_1, PNP_2, PNP_3, PNP_4: Parasitic PNP bipolar junction transistors

R_1, R_2, R_3, R_4: Parasitic resistance

S_1, S_2, S_3, S_4, S_5, S_6, S_7, S_8: Insulation structure

SA1, SA2, SA3, SA4, SA5, SA6, SA7, SA8: Silicide components

VH, VL, VSUB: Operating voltage

W1,W2,W3,W4,W5,W6,W7,W8,W9,W10,W11,W12: well area

Claims (20)

An electrostatic discharge protection device includes: a P-type semiconductor substrate; a deep N-type well region disposed in the P-type semiconductor substrate; a first well region disposed above the deep N-type well region; a first P-type doped region disposed in the first well region; a second well region disposed above the deep N-type well region; a second P-type doped region disposed in the second well region; a third well region disposed above the deep N-type well region; a third P-type doped region disposed in the third well region; a fourth well region disposed above the deep N-type well region; a fourth P-type doped region disposed in the fourth well region; a first N-type doped region disposed in the fourth well region; and a fifth well region disposed above the deep N-type well region. a fifth P-type doped region disposed in the fifth well region; and a second N-type doped region disposed in the fifth well region, wherein the first well region, the third well region, and the fourth well region are of P-type conductivity, and the second well region and the fifth well region are of N-type conductivity, wherein the second P-type doped region, the fifth P-type doped region, and the second N-type doped region are electrically connected to a first power pad, and wherein the first P-type doped region, the third P-type doped region, the fourth P-type doped region, and the first N-type doped region are electrically connected to a second power pad. The electrostatic discharge protection device as described in claim 1, wherein the fourth P-type doped region is adjacent to the first P-type doped region and the third P-type doped region, and is separated from the second P-type doped region. The electrostatic discharge protection device as described in claim 2, wherein the fourth P-type doped region is located between the third P-type doped region and the first N-type doped region. The electrostatic discharge protection device of claim 2, wherein the first N-type doped region is located between the fourth P-type doped region and the fifth P-type doped region. The electrostatic discharge protection device as described in claim 1, wherein the first N-type doped region is adjacent to the first P-type doped region and the third P-type doped region, and is separated from the second P-type doped region. The electrostatic discharge protection device as described in claim 5, wherein the first N-type doped region is located between the third P-type doped region and the fourth P-type doped region. The electrostatic discharge protection device as described in claim 5, wherein the fourth P-type doped region is located between the first N-type doped region and the fifth P-type doped region. The electrostatic discharge protection device as described in claim 1 further includes: a first isolation component disposed in the fourth well region and separating the fourth P-type doped region and the first N-type doped region; and a second isolation component disposed in the fifth well region and separating the fifth P-type doped region and the second N-type doped region. The electrostatic discharge protection device as described in claim 1 further includes: a first silicide component covering the third P-type doped region; a second silicide component covering the fourth P-type doped region; and a third silicide component covering the first N-type doped region, wherein the first silicide component, the second silicide component and the third silicide component are separated from each other. The ESD protection device of claim 9 further comprises: a fourth silicide component covering the first P-type doped region; a fifth silicide component covering the second P-type doped region; a sixth silicide component covering the fifth P-type doped region; and a seventh silicide component covering the second N-type doped region, wherein the fourth silicide component, the fifth silicide component, the sixth silicide component, and the seventh silicide component are separated from each other; a first interconnect structure directly connecting the first silicide component, the second silicide component, the third silicide component, and the fourth silicide component; and A second interconnect structure directly connects the fifth silicide component, the sixth silicide component, and the seventh silicide component. The electrostatic discharge protection device of claim 1, wherein: the second P-type doped region, the second well region, the deep N-type well region, the first P-type doped region, and the first well region constitute a first parasitic PNP-type bipolar junction transistor; the first P-type doped region, the first well region, the deep N-type well region, the fifth well region, the second N-type doped region, and the P-type semiconductor substrate constitute a second parasitic PNP-type bipolar junction transistor; the second P-type doped region, the second well region, the deep N-type well region, and the third well region constitute a third parasitic PNP-type bipolar junction transistor; The fifth P-type doped region, the fifth well region, the deep N-type well region, and the fourth well region constitute a fourth parasitic PNP bipolar junction transistor. The first N-type doped region, the fourth well region, the third well region, the deep N-type well region, the fifth well region, and the second N-type doped region constitute a first parasitic NPN bipolar junction transistor. The first N-type doped region, the fourth well region, the deep N-type well region, the fifth well region, and the second N-type doped region constitute a second parasitic NPN bipolar junction transistor. The P-type semiconductor substrate, the deep N-type well region, the fifth well region, and the second N-type doped region constitute a first parasitic diode. A collector of the first parasitic PNP bipolar junction transistor is coupled to the second power pad, an emitter of the first parasitic PNP bipolar junction transistor is coupled to the first power pad, an emitter of the second parasitic PNP bipolar junction transistor is coupled to the second power pad, a collector of the second parasitic PNP bipolar junction transistor is coupled to a third power pad, a base of the second parasitic PNP bipolar junction transistor is coupled to a cathode of the first parasitic diode, and an emitter of the third parasitic PNP bipolar junction transistor is coupled to the first power pad. A base of the third parasitic PNP bipolar junction transistor is coupled to a base of the first parasitic PNP bipolar junction transistor. An emitter of the first parasitic NPN bipolar junction transistor is coupled to the second power pad. A base of the first parasitic NPN bipolar junction transistor is coupled to a collector of the third parasitic PNP bipolar junction transistor. A collector of the first parasitic NPN bipolar junction transistor is coupled to the base of the third parasitic PNP bipolar junction transistor to form a first parasitic semiconductor controlled rectifier. An emitter of the fourth parasitic PNP bipolar junction transistor is coupled to the first power pad. A base of the fourth parasitic PNP bipolar junction transistor is coupled to a collector of the second parasitic NPN bipolar junction transistor, and a collector of the fourth parasitic PNP bipolar junction transistor is coupled to a base of the second parasitic NPN bipolar junction transistor to form a second parasitic semiconductor controlled rectifier. The base of the second parasitic NPN bipolar junction transistor is coupled to the base of the first parasitic NPN bipolar junction transistor, and an emitter of the second parasitic NPN bipolar junction transistor is coupled to the second power pad. The electrostatic discharge protection device as described in claim 11, wherein: the base of the first parasitic PNP bipolar junction transistor, the collector of the first parasitic NPN bipolar junction transistor and the base of the third parasitic PNP bipolar junction transistor are coupled to the first power pad through a first parasitic resistor formed by the deep N-type well region. The electrostatic discharge protection device as described in claim 11, wherein: the base of the fourth parasitic PNP bipolar junction transistor and the collector of the second parasitic NPN bipolar junction transistor are connected to the first power pad through a second parasitic resistor formed by the deep N-type well region. The ESD protection device of claim 11 further comprises: a sixth well region disposed in the P-type semiconductor substrate; a sixth P-type doped region disposed in the sixth well region; a seventh well region disposed between the first well region and the first P-type doped region; an eighth well region disposed between the second well region and the second P-type doped region; a ninth well region disposed between the third well region and the third P-type doped region; a tenth well region disposed between the fourth well region, the fourth P-type doped region, and the first N-type doped region; and an eleventh well region disposed between the fifth well region, the fifth P-type doped region, and the second N-type doped region. A twelfth well region is disposed between the sixth well region and the sixth P-type doped region, wherein the sixth well region, the seventh well region, the ninth well region, the tenth well region, and the twelfth well region are of P-type conductivity, and the eighth well region and the eleventh well region are of N-type conductivity. An electrostatic discharge protection device as described in claim 14, wherein: the collector of the third parasitic PNP bipolar junction transistor and the base of the first parasitic NPN bipolar junction transistor are coupled to the second power pad through a third parasitic resistor formed in the tenth well region, and the collector of the fourth parasitic PNP bipolar junction transistor and the base of the second parasitic NPN bipolar junction transistor are coupled to the second power pad through a fourth parasitic resistor formed in the tenth well region. An electrostatic discharge protection device as described in claim 14, wherein: the collector of the third parasitic PNP bipolar junction transistor and the base of the first parasitic NPN bipolar junction transistor are coupled to the second power pad via a fifth parasitic resistor formed in the ninth well region, and the collector of the fourth parasitic PNP bipolar junction transistor and the base of the second parasitic NPN bipolar junction transistor are coupled to the second power pad via a sixth parasitic resistor formed in the ninth well region. The electrostatic discharge protection device as described in claim 11, wherein when an electrostatic discharge event occurs at the first power pad and the second power pad is grounded, the first parasitic PNP bipolar junction transistor, the first parasitic semiconductor controlled rectifier, and the second parasitic semiconductor controlled rectifier are triggered to turn on. An electrostatic discharge protection circuit for protecting a core circuit, the electrostatic discharge protection circuit comprising: the electrostatic discharge protection device of claim 1; a first PNP-type bipolar junction transistor (BJT) formed by the ESD protection device, wherein an emitter of the first PNP-type BJT is coupled to a first power pad, and a collector of the first PNP-type BJT is coupled to a second power pad; a second PNP-type bipolar junction transistor (BJT) formed by the ESD protection device, wherein an emitter of the second PNP-type bipolar junction transistor is coupled to the second power pad, and a collector of the second PNP-type bipolar junction transistor is coupled to a third power pad; a first diode formed by the ESD protection device, having a cathode and an anode, the cathode coupled to the first power pad and a base of the second PNP-type bipolar junction transistor, and the anode coupled to the third power pad; a third PNP bipolar junction transistor (BJT) formed by the ESD protection device, wherein an emitter of the third PNP bipolar junction transistor is coupled to the first power pad, and a base of the third PNP bipolar junction transistor is coupled to a base of the first PNP bipolar junction transistor; a first NPN bipolar junction transistor (BJT) formed by the ESD protection device, wherein an emitter of the first NPN bipolar junction transistor is coupled to the second power pad, a base of the first NPN bipolar junction transistor is coupled to a collector of the third PNP bipolar junction transistor, and a collector of the first NPN bipolar junction transistor is coupled to the base of the third PNP bipolar junction transistor to form a first semiconductor controlled rectifier; a fourth PNP bipolar junction transistor (BJT) formed by the ESD protection device, wherein an emitter of the fourth PNP bipolar junction transistor is coupled to the first power pad; a second NPN bipolar junction transistor (BJT) formed by the ESD protection device, wherein an emitter of the second NPN bipolar junction transistor is coupled to the second power pad, a base of the fourth PNP bipolar junction transistor is coupled to a collector of the second NPN bipolar junction transistor, and a collector of the fourth PNP bipolar junction transistor is coupled to a base of the second NPN bipolar junction transistor to form a second semiconductor controlled rectifier; and the base of the first NPN bipolar junction transistor is coupled to the base of the second NPN bipolar junction transistor. a first resistor formed by the ESD protection device and coupled between the first power pad and the base of the first PNP-type bipolar junction transistor; a second resistor formed by the ESD protection device and coupled between the first power pad and the base of the fourth PNP-type bipolar junction transistor; a third resistor formed by the ESD protection device and coupled between the second power pad and the base of the first NPN-type bipolar junction transistor; and a fourth resistor formed by the ESD protection device and coupled between the second power pad and the base of the second NPN-type bipolar junction transistor. The electrostatic discharge protection circuit as described in claim 18, wherein the first PNP-type bipolar junction transistor, the second PNP-type bipolar junction transistor, the third PNP-type bipolar junction transistor, the fourth PNP-type bipolar junction transistor, the first NPN-type bipolar junction transistor, the second NPN-type bipolar junction transistor, the first resistor, the second resistor and the third resistor share the same substrate. The electrostatic discharge protection circuit as described in claim 18, wherein when an electrostatic discharge event occurs at the first power pad and the second power pad is grounded, the first PNP bipolar junction transistor, the first semiconductor controlled rectifier and the second semiconductor controlled rectifier are triggered to turn on.