TWI901362B - Non-volatile memory structure - Google Patents

Abstract

A non-volatile memory structure including a substrate, a gate dielectric layer, and a floating gate structure is provided. The gate dielectric layer is located on the substrate. The floating gate structure is located on the gate dielectric layer. The floating gate structure includes a buffer polysilicon layer, a carbon-doped polysilicon layer, a doped polysilicon layer, a first nitride layer, and a first oxide layer. The buffer polysilicon layer is located on the gate dielectric layer. The carbon-doped polysilicon layer is located on the buffer polysilicon layer. The doped polysilicon layer is located on the carbon-doped polysilicon layer. The first nitride layer is located between the buffer polysilicon layer and the gate dielectric layer. The first oxide layer is located between the doped polysilicon layer and the carbon-doped polysilicon layer.

Description

Non-volatile memory architecture

The present invention relates to a memory structure, and more particularly to a non-volatile memory structure.

Non-volatile memory (NVM) has become a widely used memory type due to its ability to store, read, and erase data multiple times. It also boasts advantages such as data persistence even when the power supply is interrupted, short data access times, and low power consumption. However, further improving the reliability of NVM remains a constant pursuit.

The present invention provides a non-volatile memory structure with better reliability.

The present invention provides a non-volatile memory structure comprising a substrate, a gate dielectric layer, and a floating gate structure. The gate dielectric layer is located on the substrate. The floating gate structure is located on the gate dielectric layer. The floating gate structure includes a buffer polysilicon layer, a carbon-doped polysilicon layer, a doped polysilicon layer, a first nitride layer, and a first oxide layer. The buffer polysilicon layer is located on the gate dielectric layer. The carbon-doped polysilicon layer is located on the buffer polysilicon layer. The doped polysilicon layer is located on the carbon-doped polysilicon layer. The first nitride layer is located between the buffer polysilicon layer and the gate dielectric layer. The first oxide layer is located between the doped polysilicon layer and the carbon-doped polysilicon layer.

According to an embodiment of the present invention, in the non-volatile memory structure, the dopant in the doped polysilicon layer may include P-type dopant or N-type dopant.

According to an embodiment of the present invention, in the non-volatile memory structure, the total doping concentration of the buffer polysilicon layer may be less than the total doping concentration of the doped polysilicon layer.

According to an embodiment of the present invention, in the non-volatile memory structure, the total doping concentration of the buffer polysilicon layer may be less than the total doping concentration of the carbon-doped polysilicon layer.

According to an embodiment of the present invention, in the non-volatile memory structure, the material of the buffer polysilicon layer can be undoped polysilicon.

According to an embodiment of the present invention, the non-volatile memory structure may further include a control gate and a dielectric layer structure. The control gate is located on the floating gate structure. The dielectric layer structure is located between the control gate and the floating gate structure.

According to an embodiment of the present invention, in the non-volatile memory structure, the material of the control gate may be doped polysilicon.

According to one embodiment of the present invention, in the non-volatile memory structure, the dielectric layer structure may include a second nitride layer, a second oxide layer, a third nitride layer, and a third oxide layer. The second nitride layer is located on the floating gate structure. The second oxide layer is located on the second nitride layer. The third nitride layer is located on the second oxide layer. The third oxide layer is located on the third nitride layer.

According to an embodiment of the present invention, in the non-volatile memory structure, the dielectric layer structure may further include a fourth nitride layer. The fourth nitride layer is located on the third oxide layer.

According to one embodiment of the present invention, the non-volatile memory structure may further include an isolation structure. The isolation structure is located in a substrate. The isolation structure may define an active region in the substrate. A floating gate structure may be located in the active region.

Based on the above, in the non-volatile memory structure proposed by the present invention, the carbon-doped polysilicon layer has a carbon dopant, allowing the carbon-doped polysilicon layer to have a small grain size. This improves the endurance and data retention capacity of the non-volatile memory structure, thereby enhancing the reliability of the non-volatile memory structure. Furthermore, because the non-volatile memory structure includes a buffered polysilicon layer, it reduces sub-threshold swing, thereby enhancing the floating gate structure's ability to control the channel. In addition, the first nitride layer is located between the buffer polysilicon layer and the gate dielectric layer, thereby inhibiting the diffusion of carbon dopants in the carbon-doped polysilicon layer into the gate dielectric layer, thereby improving the quality of the gate dielectric layer. Furthermore, the first oxide layer is located between the doped polysilicon layer and the carbon-doped polysilicon layer, thereby inhibiting the diffusion of dopants in the doped polysilicon layer into the carbon-doped polysilicon layer and the buffer polysilicon layer, thereby effectively controlling the dopant concentration of the carbon-doped polysilicon layer and the dopant concentration of the buffer polysilicon layer. On the other hand, since the first oxide layer is located between the doped polysilicon layer and the carbon-doped polysilicon layer, it can inhibit the carbon dopant in the carbon-doped polysilicon layer from diffusing into the doped polysilicon layer, thereby effectively controlling the dopant concentration of the doped polysilicon layer.

In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings.

The following examples are illustrated in detail with accompanying figures. However, these examples are not intended to limit the scope of the present invention. For ease of understanding, identical components will be designated with the same reference numerals throughout the following description. Furthermore, the accompanying figures are for illustrative purposes only and are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity.

FIG1 is a cross-sectional view of a non-volatile memory structure according to some embodiments of the present invention.

Referring to FIG. 1 , a non-volatile memory structure 10 includes a substrate 100, a gate dielectric layer 102, and a floating gate structure 104. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon substrate. Furthermore, the non-volatile memory structure 10 may further include an isolation structure 106. The isolation structure 106 is located within the substrate 100. The isolation structure 106 may define an active area AA within the substrate 100. In some embodiments, the isolation structure 106 may be made of, for example, silicon oxide.

The gate dielectric layer 102 is located on the substrate 100. In some embodiments, the gate dielectric layer 102 is made of silicon oxide, for example.

The floating gate structure 104 is located on the gate dielectric layer 102. The floating gate structure 104 may be located in the active area AA. The floating gate structure 104 includes a buffer polysilicon layer 108, a carbon-doped polysilicon layer 110, a doped polysilicon layer 112, a nitride layer 114, and an oxide layer 116.

The buffer polysilicon layer 108 is located on the gate dielectric layer 102. The non-volatile memory structure 10 includes the buffer polysilicon layer 108, thereby reducing subcritical swing and improving the channel control capability of the floating gate structure 104. In some embodiments, the total doping concentration of the buffer polysilicon layer 108 may be less than the total doping concentration of the doped polysilicon layer 112. In some embodiments, the total doping concentration of the buffer polysilicon layer 108 may be less than the total doping concentration of the carbon-doped polysilicon layer 110. In some embodiments, the material of the buffer polysilicon layer 108 may be undoped polysilicon.

The carbon-doped polysilicon layer 110 is located on the buffer polysilicon layer 108. Because the carbon-doped polysilicon layer 110 has carbon dopants, the carbon-doped polysilicon layer 110 can have a small grain size. Therefore, the durability and data retention capability of the non-volatile memory structure 10 can be improved, thereby enhancing the reliability of the non-volatile memory structure 10.

The doped polysilicon layer 112 is located on the carbon-doped polysilicon layer 110. In some embodiments, the dopant in the doped polysilicon layer 112 may include P-type dopant or N-type dopant.

The nitride layer 114 is located between the buffer polysilicon layer 108 and the gate dielectric layer 102, thereby inhibiting the diffusion of carbon dopants in the carbon-doped polysilicon layer 110 into the gate dielectric layer 102, thereby improving the quality of the gate dielectric layer 102. In some embodiments, the material of the nitride layer 114 is, for example, silicon nitride.

The oxide layer 116 is located between the doped polysilicon layer 112 and the carbon-doped polysilicon layer 110 , thereby inhibiting the diffusion of dopants in the doped polysilicon layer 112 into the carbon-doped polysilicon layer 110 and the buffer polysilicon layer 108 , thereby effectively controlling the dopant concentration of the carbon-doped polysilicon layer 110 and the dopant concentration of the buffer polysilicon layer 108 . Furthermore, since the oxide layer 116 is located between the doped polysilicon layer 112 and the carbon-doped polysilicon layer 110 , the diffusion of carbon dopants in the carbon-doped polysilicon layer 110 into the doped polysilicon layer 112 can be suppressed, thereby effectively controlling the doping concentration of the doped polysilicon layer 112 .

The non-volatile memory structure 10 may further include a control gate 118 and a dielectric layer structure 120. The control gate 118 is located on the floating gate structure 104. In some embodiments, the material of the control gate 118 may be doped polysilicon. In some embodiments, the dopant of the control gate 118 may include P-type dopant or N-type dopant.

The dielectric layer structure 120 is located between the control gate 118 and the floating gate structure 104. The dielectric layer structure 120 may further be located on the isolation structure 106. The dielectric layer structure 120 may be a single-layer structure or a multi-layer structure. In some embodiments, the dielectric layer structure 120 may include a nitride layer 122, an oxide layer 124, a nitride layer 126, and an oxide layer 128. In other words, the dielectric layer structure 120 may be an oxide layer/nitride layer/oxide layer/nitride layer (ONON) composite layer. The nitride layer 122 is located on the floating gate structure 104. The nitride layer 122 can inhibit carbon dopants in the carbon-doped polysilicon layer 110 from diffusing into the control gate 118. In some embodiments, the material of the nitride layer 122 is, for example, silicon nitride. An oxide layer 124 is located on the nitride layer 122. In some embodiments, the material of the oxide layer 124 is, for example, silicon oxide. A nitride layer 126 is located on the oxide layer 124. The nitride layer 126 can inhibit carbon dopants in the carbon-doped polysilicon layer 110 from diffusing into the control gate 118. In some embodiments, the material of the nitride layer 126 is, for example, silicon nitride. An oxide layer 128 is located on the nitride layer 126. In some embodiments, the material of the oxide layer 128 is, for example, silicon oxide.

In some embodiments, the dielectric layer structure 120 may further include a nitride layer 130. That is, the dielectric layer structure 120 may be a nitride layer/oxide layer/nitride layer/oxide layer/nitride layer (NONON) composite layer. The nitride layer 130 is located on the oxide layer 128. The nitride layer 130 can inhibit the diffusion of carbon dopants in the carbon-doped polysilicon layer 110 into the control gate 118. In some embodiments, the material of the nitride layer 130 is, for example, silicon nitride.

In some embodiments, the dielectric layer structure 120 may include an oxide layer 124, a nitride layer 126, and an oxide layer 128, but does not include a nitride layer 122 and a nitride layer 130. That is, the dielectric layer structure 120 may be an oxide layer/nitride layer/oxide layer (ONO) composite layer.

Based on the above embodiments, it can be seen that in the non-volatile memory structure 10, since the carbon-doped polysilicon layer 110 can have a small grain size, the endurance and data retention of the non-volatile memory structure 10 can be improved, thereby enhancing the reliability of the non-volatile memory structure 10. In addition, the buffer polysilicon layer 108 can reduce the subcritical swing, thereby improving the channel control capability of the floating gate structure 104. In addition, the nitride layer 114 can inhibit the diffusion of carbon dopants in the carbon-doped polysilicon layer 110 into the gate dielectric layer 102, thereby improving the quality of the gate dielectric layer 102. Furthermore, the oxide layer 116 can effectively control the doping concentration of the carbon-doped polysilicon layer 110, the doping concentration of the buffer polysilicon layer 108, and the doping concentration of the doped polysilicon layer 112.

In summary, in the non-volatile memory structure of the above-described embodiment, the floating gate structure includes a buffer polysilicon layer, a carbon-doped polysilicon layer, a doped polysilicon layer, a first nitride layer, and a first oxide layer. Because the carbon-doped polysilicon layer contains carbon dopants, the carbon-doped polysilicon layer can have a small grain size. This improves the durability and data retention capabilities of the non-volatile memory structure, thereby enhancing the reliability of the non-volatile memory structure. Furthermore, the non-volatile memory structure's buffered polysilicon layer reduces subcritical swing, enhancing the floating gate structure's channel control capability. Furthermore, the first nitride layer, located between the buffered polysilicon layer and the gate dielectric layer, inhibits the diffusion of carbon dopants from the carbon-doped polysilicon layer into the gate dielectric layer, thereby improving the quality of the gate dielectric layer. Furthermore, the first oxide layer is located between the doped polysilicon layer and the carbon-doped polysilicon layer, thereby inhibiting the diffusion of dopants in the doped polysilicon layer into the carbon-doped polysilicon layer and the buffer polysilicon layer, thereby effectively controlling the dopant concentration of the carbon-doped polysilicon layer and the dopant concentration of the buffer polysilicon layer. On the other hand, since the first oxide layer is located between the doped polysilicon layer and the carbon-doped polysilicon layer, it can inhibit the carbon dopant in the carbon-doped polysilicon layer from diffusing into the doped polysilicon layer, thereby effectively controlling the dopant concentration of the doped polysilicon layer.

Although the present invention has been disclosed above by way of embodiments, they are not intended to limit the present invention. Any person having ordinary skill in the art may make slight modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.

10: Non-Volatile Memory Structure 100: Substrate 102: Gate Dielectric Layer 104: Floating Gate Structure 106: Isolation Structure 108: Buffer Polysilicon Layer 110: Carbon-Doped Polysilicon Layer 112: Doped Polysilicon Layer 114, 122, 126, 130: Nitride Layer 116, 124, 128: Oxide Layer 118: Control Gate 120: Dielectric Layer Structure AA: Active Region

FIG1 is a cross-sectional view of a non-volatile memory structure according to some embodiments of the present invention.

10: Non-volatile memory structure

100: Base

102: Gate dielectric layer

104: Floating Gate Structure

106: Isolation Structure

108: Buffering polysilicon layer

110: Carbon-doped polysilicon layer

112: Doped polysilicon layer

114,122,126,130: Nitride layer

116,124,128: Oxide layer

118: Control Gate

120: Dielectric layer structure

AA: Active Area

Claims (10)

A non-volatile memory structure comprises: a substrate; a gate dielectric layer disposed on the substrate; and a floating gate structure disposed on the gate dielectric layer and comprising: a buffer polysilicon layer disposed on the gate dielectric layer; a carbon-doped polysilicon layer disposed on the buffer polysilicon layer; a doped polysilicon layer disposed on the carbon-doped polysilicon layer; a first nitride layer disposed between the buffer polysilicon layer and the gate dielectric layer; and The first oxide layer is located between the doped polysilicon layer and the carbon-doped polysilicon layer. The non-volatile memory structure of claim 1, wherein the dopant of the doped polysilicon layer includes P-type dopant or N-type dopant. The non-volatile memory structure of claim 1, wherein the total doping concentration of the buffer polysilicon layer is less than the total doping concentration of the doped polysilicon layer. The non-volatile memory structure of claim 1, wherein the total doping concentration of the buffer polysilicon layer is less than the total doping concentration of the carbon-doped polysilicon layer. The non-volatile memory structure as described in claim 1, wherein the material of the buffer polysilicon layer includes undoped polysilicon. The non-volatile memory structure of claim 1 further comprises: a control gate located on the floating gate structure; and a dielectric layer structure located between the control gate and the floating gate structure. The non-volatile memory structure of claim 6, wherein the material of the control gate comprises doped polysilicon. The non-volatile memory structure of claim 6, wherein the dielectric layer structure comprises: a second nitride layer disposed on the floating gate structure; a second oxide layer disposed on the second nitride layer; and a third nitride layer disposed on the second oxide layer; and a third oxide layer disposed on the third nitride layer. The non-volatile memory structure of claim 8, wherein the dielectric layer structure further comprises: A fourth nitride layer disposed on the third oxide layer. The non-volatile memory structure of claim 1 further comprises: An isolation structure disposed in the substrate and defining an active region in the substrate, wherein the floating gate structure is disposed in the active region.