TWI901192B - Input buffer - Google Patents

Abstract

An input buffer includes first to second amplifiers. The first amplifier includes a first front-end circuit, a first transistor, and a second transistor. The first front-end circuit is configured to receive a first voltage and a second voltage. First terminals of the first transistor and the second transistor are coupled with the first front-end circuit at a first node and a second node, respectively. Second terminals of the first transistor and the second transistor are coupled with each other at a reference node. The first amplifier outputs, in response to the first voltage and second voltage, a third voltage and a fourth voltage at the first node and the second node, respectively. The second amplifier includes third to fourth transistors. Control terminals of the third transistor and the fourth transistor are coupled with the first amplifier at the first node and the second node, respectively. The second amplifier generates a fifth voltage in response to the third voltage and the fourth voltage.

Description

input buffer

This application relates to an input buffer and an operating method thereof, and more particularly to an input buffer having multiple amplifiers and capable of receiving broadband signals and an operating method thereof.

Signals attenuate along the path from a transmitter to a receiver. When channel attenuation cannot be compensated for, another approach to addressing this problem is to amplify the signal before use. Furthermore, according to the Shannon-Hartley theorem, the signal rate for reliable communication is directly proportional to the communication bandwidth. For high-speed signal transmission, insufficient bandwidth prevents the signal from being fully received. Increasing bandwidth is also a key issue in the field of communications. Therefore, this invention is dedicated to developing a broadband buffer to address the problems of channel attenuation and insufficient bandwidth.

Some embodiments of the present invention provide an input buffer comprising a first to second amplifier. The first amplifier comprises a first front-end circuit, a first transistor, and a second transistor. The first front-end circuit is used to receive a first voltage and a second voltage. The first end of the first transistor is coupled to the first front-end circuit at a first node. The first end of the second transistor is coupled to the first front-end circuit at a second node. The second end of the second transistor is coupled to the second end of the first transistor at a reference node. The first amplifier is used to output a third voltage and a fourth voltage at a first node and a second node, respectively, in response to the first voltage and the second voltage. The second amplifier comprises a third transistor and a fourth transistor. The control end of the third transistor and the control end of the fourth transistor are coupled to the first amplifier at a first node and a second node, respectively. The second amplifier is used to generate a fifth voltage in response to the third voltage and the fourth voltage.

In some embodiments, the first amplifier further includes a first resistor coupled between the first node and the control terminal of the first transistor and a second resistor coupled between the second node and the control terminal of the second transistor.

In some embodiments, the first transistor and the second transistor have the same conductivity state.

In some embodiments, the first transistor and the second transistor both have a first threshold voltage.

In some embodiments, the first front-end circuit includes a transistor pair, wherein a plurality of control terminals of the transistor pair are configured to receive a first voltage and a second voltage, and a plurality of first terminals of the transistor pair are coupled to each other.

In some embodiments, the second threshold voltage of each transistor of the transistor pair is greater than the first threshold voltage.

In some embodiments, the third transistor and the fourth transistor have the same conductivity state.

Some embodiments of the present invention provide an input buffer comprising a front-end circuit coupled to a current source, first to fourth transistors, and a current control unit. The drain of the first transistor is coupled to the front-end circuit at a first node. The drain of the second transistor is coupled to the front-end circuit at a second node. Moreover, the source of the second transistor and the source of the first transistor are coupled to each other at a reference node. The gate of the third transistor is coupled to the first node. The drain of the third transistor is coupled to the first output terminal of the bias supply circuit at a third node. The gate of the fourth transistor is coupled to the second node. The drain of the fourth transistor is coupled to the second output terminal of the bias supply circuit at a fourth node. The current control unit is coupled to the source of the third transistor and the source of the fourth transistor at a fifth node to control the total current flowing through the third transistor and the fourth transistor.

In some embodiments, the first to fourth transistors have the same conductivity state.

In some embodiments, the first transistor and the second transistor both have a first size, and the third transistor and the fourth transistor both have a second size different from the first size.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description that follows, the formation of a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, the disclosure may refer to numbers and/or letters repeatedly in various examples. This repetition is for the sake of simplicity and clarity and does not, in itself, dictate a relationship between the various embodiments and/or configurations discussed.

The terms used in this specification generally have their ordinary meanings in the art and in the specific context in which they are used. The use of examples in this specification (including examples of any term discussed herein) is illustrative only and in no way limits the scope or meaning of an embodiment of this disclosure or any of the exemplified terms. Similarly, an embodiment of this disclosure is not limited to the various embodiments presented in this specification.

Reference throughout this specification to "one embodiment," "an embodiment," or "some embodiments" means that a particular feature, structure, implementation, or characteristic described in connection with that embodiment(s) is included in at least one embodiment of the disclosure. Thus, the use of the phrase "in one embodiment," "in an embodiment," or "in some embodiments" in various places throughout this specification is not necessarily referring to the same embodiment. Furthermore, the particular features, structures, implementations, or characteristics may be combined in any suitable manner in one or more embodiments.

As used herein, "approximately," "about," "substantially," or "substantially" shall generally refer to any approximation of a given value or range, which may vary depending on the various technologies to which it pertains, and its scope shall be consistent with the broadest interpretation understood by those skilled in the art to which it pertains so as to encompass all such modifications and similar structures. In some embodiments, it shall generally mean within 20%, preferably within 10%, and more preferably within 5% of a given value or range. The numerical values given herein are approximate, meaning that if the term "approximately," "about," "substantially," or "substantially" is not expressly stated, it may be inferred or may mean another approximate value.

Referring now to Figure 1, Figure 1 is a schematic diagram illustrating signal transmission between a transmitter device Tx and a receiver device Rx according to some embodiments of the present disclosure. As shown in Figure 1, the transmitter device Tx is configured to transmit signal(s) to the receiver device Rx. The receiver device Rx includes an input buffer 100 and an operating circuit 200 electrically connected to the input buffer 100. In some embodiments, the operating circuit 200 includes a logic operation circuit, an analog circuit, or other suitable internal integrated circuitry.

In some embodiments, the input buffer 100 is used to amplify the signal from the transmitter Tx and then transmit it to the working circuit 200 to solve the signal reduction problem caused by channel loss LOSS.

Now referring to FIG. 2A , FIG. 2A is a circuit diagram of an input buffer 100A according to some embodiments of the present disclosure. In some embodiments, the input buffer 100A corresponds to, for example, the configuration of the input buffer 100 in FIG. 1 . As shown in FIG. 2A , the input buffer 100A includes an amplifier 110A and an amplifier 120A. Specifically, the amplifier 110A includes a front-end circuit 111, an active inductor circuit 112, an active inductor circuit 113, and a current source 114 coupled to the front-end circuit 111. The active inductor circuit 112 and the active inductor circuit 113 are coupled to the front-end circuit 111 at nodes n1 and n2, respectively. Amplifier 120A includes a bias supply circuit 121, transistors M3 and M4, a current control unit 122, and a voltage source 123 coupled to bias supply circuit 121. The drains of transistors M3 and M4 are coupled to bias supply circuit 121 at nodes n4 and n5, respectively. Current control unit 122 is coupled to the sources of transistors M4 and M3 at node n7. Furthermore, active inductor circuit 112, active inductor circuit 113, and current control unit 122 are coupled at one end to a reference node R having a voltage _V− . In some embodiments, reference node R is ground, and voltage _V− is ground.

In some embodiments, transistor M3 and transistor M4 have the same conductivity state, for example, N-type Metal-Oxide-Semiconductor Field-Effect Transistor (MOS).

In some embodiments, as shown in FIG. 2A , a front-end circuit 111 is configured to receive voltages V1 and V2 corresponding to signals from a transmitter Tx. Specifically, the front-end circuit 111 includes a transistor pair MM1 consisting of a transistor MP1 and a transistor MP2. The two gates (i.e., control terminals) of the transistor pair MM1 are configured to receive voltages V1 and V2. In some embodiments, transistors MP1 and MP2 have the same conductivity, for example, P-type MOS transistors.

As shown in FIG2A , the active inductor circuit 112 includes a resistor R1 and a transistor M1. The resistor R1 is coupled between the gate and drain of the transistor M1. The drain of the transistor M1 is coupled to the front-end circuit 111 at a node n1.

The active inductor circuit 113 includes a resistor R2 and a transistor M2. The resistor R2 is coupled between the gate and drain of the transistor M2. The drain of the transistor M2 is coupled to the front-end circuit 111 at a node n2.

In some embodiments, transistors M1 and M2 have the same conductivity state, for example, N-type MOS. In some embodiments, transistors M1 to M4 have the same conductivity state.

As shown in Figure 2A , amplifier 110A is coupled to amplifier 120A via nodes n1 and n2. Specifically, front-end circuit 111 and active inductor circuit 112 are coupled to the gate of transistor M3 at node n1. Front-end circuit 111 and active inductor circuit 113 are coupled to the gate of transistor M4 at node n2. In other words, the connection relationship between amplifiers 110A and 120A is as follows: the gate of transistor M3 is coupled to the drain of transistor M1 at node n1, and the gate of transistor M4 is coupled to the drain of transistor M2 at node n2.

With this configuration, amplifier 110A generates voltages V3 and V4 at nodes n1 and n2, respectively, based on received voltages V1 and V2. Voltages V3 and V4 are then output to the gates of transistors M3 and M4, respectively. Amplifier 120A then generates voltage V5 at node n5 based on received voltages V3 and V4.

Specifically, transistors MP1 and MP2 respond to voltages V1 and V2, respectively, to generate currents I1 and I2 through transistor M1 and M2, respectively, based on current Ic. Amplifier 110A then outputs a voltage V3 related to current I1 to transistor M3, thereby controlling current I3 through transistor M3. Similarly, amplifier 110A outputs a voltage V4 related to current I2 to transistor M4, thereby controlling current I4 through transistor M4. Amplifier 120A then outputs a voltage V5 related to current I4.

Compared to some embodiments, the configuration provided in this embodiment increases the bandwidth of the signal transmitted by input buffer 100A. The gate of transistor M3 provides a capacitor C _L (not shown) connected in parallel between the drain and source of transistor M1. Transistor M1's own parasitic capacitance provides a capacitor C gs (not shown) connected in parallel between its gate and source. The combination of capacitor C _L and resistor R1 creates a pole, while the combination of capacitor C gs and resistor R1 creates a zero. Pole-zero compensation increases bandwidth. Similarly, the configurations associated with transistors M4 and M2 also increase bandwidth.

In this way, bandwidth can be increased by a factor of 2-3. In some embodiments, the original bandwidth range is 1-2 GHz, but after zero-to-zero compensation, the bandwidth increases to 3-5 GHz. On the other hand, when resistors R1 and R2 are zero, zero-to-zero compensation disappears, and the bandwidth is not increased. Therefore, in some embodiments, adjustable resistors can be used as resistors R1 and R2, and the resistance values of resistors R1 and R2 can be adjusted as needed to change the bandwidth to the desired value.

Furthermore, with the configuration provided in this embodiment, the current I3 flowing through the transistor M3 is limited by the current I1 flowing through the transistor M1, and the current I4 flowing through the transistor M4 is limited by the current I2 flowing through the transistor M2. Thus, excessive power consumption of the amplifier 120A is avoided.

In more detail, the bias supply circuit 121 includes a transistor M5 and a transistor M6. The drain of transistor M5 is coupled to the drain of transistor M3 at node n4. The drain of transistor M6 is coupled to the drain of transistor M4 at node n5. The source of transistor M5 and the source of transistor M6 are coupled to each other at node n6. The bias supply circuit 121 receives a voltage V ₊ provided by a voltage source 123 at node n6 and correspondingly outputs a bias voltage between the drains of transistor M3 and transistor M4. In some embodiments, the voltage V ₊ is greater than the voltage V- at the reference node R. Furthermore, in some embodiments, the transistor M5 and the transistor M6 have the same conductivity state, for example, P-type MOS.

More specifically, current control unit 122 is used to control the sum of currents I3 and I4, that is, the total current It flowing through transistors M3 and M4. In some embodiments, current control unit 122 includes transistor M7. The drain, source, and gate of transistor M7 are coupled to node n7, reference node R, and node n4, respectively. In some embodiments, the gate of transistor M7 is coupled to the gates of transistor M5 and transistor M6 at node n4. Furthermore, in some embodiments, transistor M7 is an N-type MOS transistor.

Referring now to FIG. 2B , FIG. 2B is a circuit diagram of an input buffer 100B according to some embodiments of the present disclosure. In some embodiments, input buffer 100B corresponds to, for example, the configuration of input buffer 100 in FIG. 1 . For ease of understanding, similar components in FIG. 2B are numbered with the same reference numbers as those in the embodiment of FIG. 2A . For the sake of brevity, the detailed operation of similar components discussed in detail in the preceding paragraphs will be omitted herein unless necessary to explain their cooperative relationship with the components in FIG. 2B .

Compared to the embodiment of FIG. 2A , transistors MN1, MN2, M5, and M6 of input buffer 100B are N-type, and transistors M1, M2, M3, M4, and M7 are P-type. Reference node R has a voltage V ₊ . Node n6 receives a voltage _V− . In some embodiments, voltage _V− is less than voltage V ₊ . In other embodiments, reference node R is a ground terminal, and voltage _V− is ground.

The above embodiments are only for facilitating understanding of the main concept of the present disclosure and are not intended to limit the scope of the present disclosure. The conduction state of each transistor of the input buffer 100 can be determined according to requirements.

Furthermore, the size of each transistor of the input buffer 100 may be determined as required, for example, by selecting the gate width of each transistor as its size. In some embodiments, transistor M1 and transistor M2 are the same size, both having a size W1. In some embodiments, transistor M3 and transistor M4 are the same size, both having a size W2. In some embodiments, transistor M1 and transistor M2 both have a size W1, and transistor M3 and transistor M4 both have a size W2. In some embodiments, size W2 is equal to size W1. In other embodiments, size W2 is further greater than size W1, for example, size W2 is 1 to 2 times size W1. The size ratio of size W2 to size W1 limits the maximum current ratio of current I3 to current I1 and the maximum current ratio of current I4 to current I2. For example, when dimension W2 is equal to dimension W1, current I3 is no greater than current I1, and current I4 is no greater than current I2. For another example, when dimension W2 is twice dimension W1, current I3 is no greater than twice current I1, and current I4 is no greater than twice current I2. In some embodiments, transistor M1, transistor M2, transistor M3, and transistor M4 have dimensions W1-1, W1-2, W2-1, and W2-2, respectively, and dimensions W1-1, W1-2, W2-1, and W2-2 may be different from one another. Similarly, the ratio of dimension W2-1 to dimension W1-1 limits the maximum value of the ratio of current I3 to current I1, and the ratio of dimension W2-2 to dimension W1-2 limits the maximum value of the ratio of current I4 to current I2. In other words, the ratio of current I3 to current I1 is related to the ratio of dimension W2-1 to dimension W1-1, and the ratio of current I4 to current I2 is related to the ratio of dimension W2-2 to dimension W1-2.

In some embodiments, transistor M1 and transistor M2 both have a threshold voltage Vth1. In some embodiments, the threshold voltage Vth2 of each transistor in transistor pair MM1 is greater than threshold voltage Vth1. In some embodiments, threshold voltage Vth2 is greater than threshold voltage Vth1 by 200 millivolts. In some embodiments, threshold voltage Vth2 is 0.7 volts and threshold voltage Vth1 is 0.4 or 0.5 volts. As shown in the embodiment of FIG. 2A , when transistors MP1 and MP2 are turned on, voltage V3 (i.e., the voltage at node n1) and voltage V4 (i.e., the voltage at node n2) must be greater than threshold voltage Vth1 to turn on transistors M1 and M2. Furthermore, as threshold voltage Vth1 decreases, the amplitudes of voltages V3 and V4 increase, and the offset between voltages V3 and V4 decreases.

As shown in the embodiment of Figure 2B , when transistors MN1 and MN2 are conducting, voltage V3 (i.e., the voltage at node n1) and voltage V4 (i.e., the voltage at node n2) must be less than (voltage V ₊ - threshold voltage Vth1) to turn on transistors M1 and M2. Furthermore, as threshold voltage Vth1 decreases, the amplitudes of voltages V3 and V4 increase, and the offset between voltages V3 and V4 decreases.

The resistance value of each resistor of the input buffer 100 can also be determined according to requirements. In some embodiments, the resistor R1 and the resistor R2 have the same resistance value.

Furthermore, as previously mentioned, the key element used by the input buffer to limit current magnitude essentially involves the connection of four transistors M1, M2, M3, and M4. The connection method of these transistors M1, M2, M3, and M4 effectively limits the current ratio. A current control unit 122 can be added to determine the total current to limit the maximum values of currents I3 and I4. The application of this connection method is not limited to processing amplifier power dissipation. For example, it can be used in the manufacture of circuit protection devices to limit the current flowing through the desired protection circuit to prevent circuit damage.

Referring now to FIG. 3 , FIG. 3 is a schematic diagram of an input buffer 100C according to some embodiments of the present disclosure. In some embodiments, as shown in FIG. 3 , input buffer 100C includes multiple amplifiers 110A_1, 110A_2, ..., 110A_f. In some embodiments, amplifiers 110A_1, 110A_2, ..., 110A_f are configured corresponding to amplifier 110A in FIG. 2A . For example, amplifier 110A_1 includes a front-end circuit 111_1, resistors R3-R4, and transistors M8-M9, wherein front-end circuit 111_1 includes transistors MP3-MP4. Front-end circuit 111_1 is configured similarly to front-end circuit 111 in FIG. 2A . Transistors MP3-MP4 are configured similarly to transistors MP1-MP2 in FIG. 2A . Resistors R3-R4 are configured similarly to resistors R1-R2 in FIG. 2A Transistors M8-M9 are configured similarly to transistors M1-M2 in FIG. 2A The configuration of amplifiers 110A_2 . . . 110A_f is the same as that of amplifier 110A_1 and will not be further described.

As shown in FIG3 , amplifiers 110A_1, 110A_2, etc. are sequentially coupled to amplifier 110A_f via corresponding nodes (e.g., nodes n8, n9, n10, n11, etc. in FIG3 ). For example, the drains of transistors MP3-MP4 of amplifier 110A_1 are coupled to the gates of transistors MP5-MP6 of amplifier 110A_2 at nodes n8-n9, and so on.

Furthermore, the amplifier 110A_f is coupled to the amplifier 120A via nodes n_f1 and n_f2. Specifically, the front-end circuit 111_f of the amplifier 110A_f is coupled to the gates of transistors M3 and M4 in the amplifier 120A at nodes n_f1 and n_f2, respectively.

In operation, the front-end circuit 111_1 of the amplifier 110A_1 receives voltages V1 and V2 from the transmitter Tx. In response to voltages V1 and V2, the amplifier 110A_1 generates voltages V8 and V9, which are then passed to the amplifier 110A_2. The front-end circuit 111_2 of the amplifier 110A_2 receives voltages V8 and V9, and in response to voltages V8 and V9, the amplifier 110A_2 generates voltages V10 and V11, which are then passed to the next amplifier stage, and so on. In other words, two adjacent amplifiers among the amplifiers 110A_1, 110A_2, ..., 110A_f generate signals related to the voltages V1 and V2 in the same manner as the amplifiers 110A_1 and 110A_2.

After passing through multiple stages of amplifiers 110A_1, 110A_2, and so on, voltages V_f1 and V_f2 are ultimately generated and transmitted to front-end circuit 111_f of amplifier 110A_f. After receiving voltages V_f1 and V_f2, amplifier 110A_f, in conjunction with amplifier 120A, outputs voltage V5 at node n5, as described above for input buffer 100A.

In some embodiments, the signal is further amplified through the amplifier 110A_1, the amplifier 110A_2, ..., and the amplifier 110A_f, thereby increasing the gain.

In some embodiments, transistors M8-M11, M_f1, M_f2, transistor M3, and transistor M4 have the same conductivity state, being either P-type or N-type transistors. In some embodiments, amplifiers 110A_1, 110A_2, ..., 110A_f are configured corresponding to amplifier 110B in FIG. 2B , and accordingly, amplifier 120A in FIG. 3 is replaced by amplifier 120B.

Referring now to FIG. 4 , FIG. 4 is a flow chart of a method 400 for operating the input buffer of FIG. 1 through FIG. 3 according to some embodiments of the present disclosure. It should be understood that additional operations may occur before, during, or after the process illustrated in FIG. 4 , and that some operations described below may be replaced or eliminated for additional embodiments of the method 400. The method 400 for operating the input buffer includes operations 401 and 402 described below with reference to FIG. 2A through FIG. 3 .

In operation 401, as shown in FIG. 2A , a current Ic is applied to the front-end circuit 111 of the amplifier 110A, and the front-end circuit 111 generates a current I1 flowing through the transistor M1 and a current I2 flowing through the transistor M2 in response to the voltage V1 and the voltage V2, respectively.

In operation 402, a current I3 flowing through transistor M3 and a current I4 flowing through transistor M4 are generated by amplifier 120A according to voltage V3 associated with current I1 and voltage V4 associated with current I2, and a voltage V5 is outputted by amplifier 120A according to current I4.

In some embodiments, the input buffer operating method 400 further includes applying a voltage supplied by the voltage source 123 to the bias supply circuit 121 to output a bias voltage between the drain terminal of the transistor M3 and the drain terminal of the transistor M4.

In summary, the present disclosure provides an input buffer that can increase bandwidth and limit current by introducing a connection method between amplifiers, thereby solving the problems of insufficient bandwidth and high power loss.

Although the present invention has been disclosed above in the form of implementation, it is not intended to limit the present invention. Anyone with ordinary skill in the art may make various modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the patent application attached hereto.

100: Input buffer 100A: Input buffer 100B: Input buffer 100C: Input buffer 110A_1, 110A_2: Amplifier 110A_f: Amplifier 110A: Amplifier 110B: Amplifier 111: Front-end circuit 111_1, 111_2: Front-end circuit 111_f: Front-end circuit 112: Active inductor circuit 113: Active inductor circuit 114: Current source 120A: Amplifier 120B: Amplifier 121: Bias supply circuit 122: Current control unit 123: Voltage source 200: Working circuit 400: Input buffer operation Methods 401-402: Operations I1-I4: Current Ic: Currents Ic_1, Ic_2: Current Ic_f: Current It: Total current LOSS: Channel loss M1-M11: Transistor MM1: Transistor pair MN1, MN2: Transistors MP1-MP6: Transistors MP_f1-MP_f2: Transistors M_f1, M_f2: Transistors n1-n11: Nodes n_f1, n_f2: Nodes R1-R6: Resistors Rf1-Rf2: Resistor R: Reference node Rx: Receiver Tx: Transmitter V1-V11: Voltages V_f1, V_f2: Voltages V ₊ , _V- : Voltages

To facilitate understanding of the above and other objects, features, advantages, and embodiments of the present invention, the accompanying drawings are described as follows: Figure 1 is a schematic diagram illustrating signal transmission between a transmitter and a receiver according to certain embodiments of the present disclosure; Figure 2A is a circuit diagram of an input buffer according to certain embodiments of the present disclosure; Figure 2B is a circuit diagram of an input buffer according to certain embodiments of the present disclosure; Figure 3 is a schematic diagram of an input buffer according to certain embodiments of the present disclosure; and Figure 4 is a flow chart illustrating a method for operating the input buffer described in Figures 1 through 3 according to certain embodiments of the present disclosure.

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100A: Input buffer

110A: Amplifier

111: Front-end circuit

112: Active inductor circuit

113: Active Inductor Circuit

114: Current Source

120A:Amplifier

121: Bias supply circuit

122: Current control unit

123: Voltage Source

I1~I4: Current

It:Total current

Ic: Current

MP1, MP2: Transistors

M1~M7: Transistors

MM1: Transistor pair

n1~n7: nodes

R1, R2: resistors

R: Reference node

V1~V5: Voltage

V _+, V _- : Voltage

Claims (10)

An input buffer comprises: A first amplifier comprising: A first front-end circuit for receiving a first voltage and a second voltage; A first transistor, a first terminal of the first transistor coupled to the first front-end circuit at a first node; and A second transistor, a first terminal of the second transistor coupled to the first front-end circuit at a second node, and a second terminal of the second transistor coupled to a second terminal of the first transistor at a reference node, Wherein a control terminal of the first transistor and a control terminal of the second transistor are separated from each other, Wherein the first amplifier is configured to output a third voltage and a fourth voltage at the first node and the second node, respectively, in response to the first voltage and the second voltage; and A second amplifier comprising: A third transistor and a fourth transistor, wherein a control terminal of the third transistor and a control terminal of the fourth transistor are coupled to the first amplifier at the first node and the second node, respectively. The second amplifier is configured to generate a fifth voltage in response to the third voltage and the fourth voltage. The input buffer of claim 1, wherein the first amplifier further comprises: a first resistor coupled between the first node and the control terminal of the first transistor; and a second resistor coupled between the second node and the control terminal of the second transistor. The input buffer of claim 1, wherein the first transistor and the second transistor have the same conductivity state. The input buffer of claim 3, wherein the first transistor and the second transistor both have a first threshold voltage. The input buffer of claim 4, wherein the first front-end circuit comprises: A transistor pair, wherein a plurality of control terminals of the transistor pair are configured to receive the first voltage and the second voltage, and a plurality of first terminals of the transistor pair are coupled to each other. The input buffer of claim 5, wherein a second threshold voltage of each transistor of the transistor pair is greater than the first threshold voltage. The input buffer of claim 1, wherein the third transistor and the fourth transistor have the same conductivity state. An input buffer comprises: a front-end circuit coupled to a current source; a first transistor, a drain of the first transistor coupled to the front-end circuit at a first node; a second transistor, a drain of the second transistor coupled to the front-end circuit at a second node, wherein a source of the second transistor and a source of the first transistor are coupled to each other at a reference node; a third transistor, a gate of the third transistor coupled to the first node, and a drain of the third transistor coupled to a first output terminal of a bias supply circuit at a third node; a fourth transistor, a gate of the fourth transistor coupled to the second node, and a drain of the fourth transistor coupled to a second output terminal of the bias supply circuit at a fourth node; and A current control unit is coupled to a source of the third transistor and a source of the fourth transistor at a fifth node to control a total current flowing through the third transistor and the fourth transistor. The input buffer of claim 8, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are of the same conduction state. The input buffer of claim 8, wherein the first transistor and the second transistor both have a first size and the third transistor and the fourth transistor both have a second size different from the first size.