TWI900921B - Multi-phase switching converter and control method thereof - Google Patents

Abstract

The present invention provides a multi-phase switching converter, which includes: first and second sub-switching converters; wherein plural switching signals operate a first fore-capacitor of a first fore-switched capacitor switching converter and a first rear-capacitor of a first rear-switched capacitor switching converter and a second fore-capacitor of a second fore-switched capacitor switching converter and a second rear-capacitor of a second rear-switched capacitor switching converter among plural electrical connection states to perform a switched capacitor switching to a first voltage, so as to switch a first or second switching node between a first or second divided voltage of the first voltage obtained from the switched capacitor switching and a reference voltage level respectively, such that a power conversion between a first power node and a second power node can be performed.

Description

Multi-phase conversion circuit and control method thereof

The present invention relates to a multi-phase converter circuit, and more particularly to a multi-phase converter circuit capable of supporting more voltage conversion ratios and a control method thereof.

Figure 1 shows a schematic diagram of a conventional two-phase converter circuit. This conventional two-phase converter circuit requires a high voltage rating due to its use of flying capacitors. For example, the DC bias voltage of capacitors C1 and C4 is three times the output voltage Vout, resulting in a low effective capacitance. Therefore, more flying capacitors are required to compensate for the high DC bias voltage. Furthermore, this conventional two-phase converter circuit has a large number of switches, and if resonant inductors are required, they will also require a considerable number, resulting in a low conversion ratio flexibility.

In view of this, the present invention proposes a multi-phase conversion circuit and a control method thereof that can support more voltage conversion ratios.

In one aspect, the present invention provides a multi-phase conversion circuit for performing power conversion between a first voltage of a first power node and a second voltage of a second power node. The multi-phase conversion circuit includes: a first sub-conversion circuit including: a first switch coupled to the first power node; a first front-switching capacitive conversion circuit coupled between the first switch and a first switching node; and a first rear-switching capacitive conversion circuit coupled to the first switching node. and the second power node; wherein the first switch, the first front switching capacitive conversion circuit and the first rear switching capacitive conversion circuit are sequentially connected in series between the first power node and the second power node; wherein the first front switching capacitive conversion circuit includes a first front cross-connect switch, a first front lower bridge switch, a first front slave switch and a first front capacitor; wherein the first rear switching capacitive conversion circuit includes a first rear cross-connect switch, a first rear lower bridge switch, a first rear slave switch and a first rear capacitor; a second sub-conversion circuit comprising: a second switch coupled to the first power node; a second front-switching capacitive conversion circuit coupled between the second switch and a second switching node; and a second rear-switching capacitive conversion circuit coupled between the second switching node and the second power node; wherein the second switch, the second front-switching capacitive conversion circuit and the second rear-switching capacitive conversion circuit are sequentially connected in series. between the first power node and the second power node; wherein the second front switching capacitive conversion circuit includes a second front crossover switch, a second front lower bridge switch, a second front slave switch, and a second front capacitor; wherein the second rear switching capacitive conversion circuit includes a second rear crossover switch, a second rear lower bridge switch, a second rear slave switch, and a second rear capacitor; and a control circuit for generating a plurality of switching signals; wherein the first sub-converter circuit and the second The sub-converter circuit is used to periodically switch the electrical connection relationship of the first front capacitor, the first rear capacitor, the second front capacitor and/or the second rear capacitor between a plurality of electrical connection states based on the plurality of switching signals and a switching frequency; wherein the plurality of switching signals operate the first front capacitor, the first rear capacitor, the second front capacitor and/or the second rear capacitor to perform capacitive voltage division on the first voltage between the plurality of electrical connection states to respectively divide the first voltage into the first and second voltages. A switching node is switched between a first divided voltage of the first voltage obtained by the switching capacitor voltage division and a first reference potential, and a second switching node is switched between a second divided voltage of the first voltage obtained by the switching capacitor voltage division and a second reference potential, thereby performing power conversion between the first power node and the second power node; wherein the first reference potential and the second reference potential are respectively related to the first voltage or its divided voltage, a ground potential, the first front The cross-voltage of the capacitor, the cross-voltage of the first rear capacitor, the cross-voltage of the second front capacitor and/or the cross-voltage of the second rear capacitor; wherein the first front slave switch is coupled between the first front capacitor and the first switching node to determine whether the first front capacitor and the first switching node are electrically connected according to the corresponding switching signal; wherein the first rear slave switch is coupled between the first rear capacitor and the second power node to determine whether the first front capacitor and the first switching node are electrically connected according to the corresponding switching signal. The first rear capacitor and the second power node are electrically connected; wherein the second front slave switch is coupled between the second front capacitor and the second switching node and is used to determine whether the second front capacitor and the second switching node are electrically connected according to the corresponding switching signal; wherein the second rear slave switch is coupled between the second rear capacitor and the second power node and is used to determine whether the second rear capacitor and the second power node are electrically connected according to the corresponding switching signal.

In another aspect, the present invention provides a multi-phase conversion circuit control method, comprising: generating a plurality of switching signals and periodically switching the electrical connection relationship of a first front capacitor and/or a first rear capacitor corresponding to a first sub-conversion circuit and a second front capacitor and/or a second rear capacitor of a second sub-conversion circuit in a multi-phase conversion circuit between a plurality of electrical connection states based on a switching frequency, so as to perform a first power saving operation. The first sub-conversion circuit includes a first switch, a first front-switching capacitive conversion circuit, and a first rear-switching capacitive conversion circuit connected in series, wherein the first switch is coupled to the first power node, the first front-switching capacitive conversion circuit is coupled between the first switch and a first switching node, and the first rear-switching capacitive conversion circuit is coupled between the first switching node and the first switching node. The first front-switched capacitive conversion circuit includes a first front crossover switch, a first front lower bridge switch, a first front slave switch, and a first front capacitor; the first rear-switched capacitive conversion circuit includes a first rear crossover switch, a first rear lower bridge switch, a first rear slave switch, and a first rear capacitor; the second sub-conversion circuit includes a second switch, a second front-switched capacitive conversion circuit, and a first rear capacitor connected in series. The second rear-switched capacitive conversion circuit comprises a second front cross-connect switch, a second front lower bridge switch, a second front slave switch, and a second front capacitor. The second rear switching capacitive conversion circuit includes a second rear cross-connect switch, a second rear lower bridge switch, a second rear slave switch, and a second rear capacitor; and the plurality of switching signals operate the first front capacitor, the first rear capacitor, the second front capacitor, and/or the second rear capacitor to perform switching capacitive voltage division on the first voltage between the plurality of electrical connection states, so as to respectively switch the first switching node to the voltage obtained by the switching capacitive voltage division. The first power node is connected to the first power node by switching the second switching node between a first divided voltage of the first voltage obtained by the switching capacitive voltage division and a first reference potential, thereby performing power conversion between the first power node and the second power node; wherein the first reference potential and the second reference potential are respectively related to the first voltage or its divided voltage, a ground potential, the voltage across the first front capacitor, the first back capacitor, and the like. The first front slave switch is coupled between the first front capacitor and the first switching node to determine whether the first front capacitor and the first switching node are electrically connected according to the corresponding switching signal; the first rear slave switch is coupled between the first rear capacitor and the second power node to determine whether the first rear capacitor is electrically connected according to the corresponding switching signal. The second front slave switch is coupled between the second front capacitor and the second switching node to determine whether the second front capacitor is electrically connected to the second switching node according to the corresponding switching signal; the second rear slave switch is coupled between the second rear capacitor and the second power node to determine whether the second rear capacitor is electrically connected to the second power node according to the corresponding switching signal.

In one embodiment, the plurality of electrical connection states include: a first electrical connection state having: the first front capacitor and the first rear capacitor connected in series between the first power node and the second power node, and the first power source charging the first front capacitor and the first rear capacitor; the second front capacitor and the first rear capacitor connected in series between the second power node and the ground potential, and the ground potential discharging the second front capacitor to the second power source via the first rear capacitor; and the second rear capacitor connected in series between the second power node and the ground potential. The second back capacitor is electrically connected between the second power source and the ground potential, and the ground potential discharges the second back capacitor to the second power source; and a second electrical connection state has: the second front capacitor and the second back capacitor are connected in series between the first power node and the second power node, and the first power source charges the second front capacitor and the second back capacitor; the first front capacitor and the second back capacitor are connected in series between the second power node and the ground potential, and the ground potential The first front capacitor is discharged to the second power source via the second back capacitor; and the first back capacitor is electrically connected between the second power source and the ground potential, and the ground potential discharges the first back capacitor to the second power source; wherein the plurality of switching signals operate the first sub-conversion circuit and the second sub-conversion circuit between the first electrical connection state and the second electrical connection state to switch the first voltage capacitively to switch the first switching node to the switching state of the first switching node. The first power source is converted into the second power source by switching the second switching node between the first divided voltage of the first voltage obtained by the switching capacitive voltage division and the first reference potential, wherein the first reference potential and the second reference potential are the cross-voltage of the first post-capacitor and the cross-voltage of the second post-capacitor, respectively, and the first divided voltage and the second divided voltage are both half of the first voltage.

In one embodiment, the duty cycle of the plurality of switching signals is 50%, the voltage across the first front capacitor and the voltage across the second front capacitor are both half of the first voltage, and the voltage across the first rear capacitor and the voltage across the second rear capacitor are both one-quarter of the first voltage.

In one embodiment, the first sub-converter circuit further includes a first inductor, and the second sub-converter circuit further includes a second inductor, wherein the first inductor is coupled between the first post-capacitor and the second power node, and wherein the second inductor is coupled between the second post-capacitor and the second power node.

In one embodiment, the plurality of electrical connection states include: a first electrical connection state having: the first front capacitor and the first rear capacitor connected in series between the first power node and the second power node, and the first power source charging the first front capacitor and the first rear capacitor via the first inductor; the second front capacitor and the first front capacitor connected in series between the first power node and the ground potential, and the ground potential discharging the second front capacitor to the second power source via the first inductor and the first rear capacitor; and The second back capacitor and the second inductor are connected in series between the second power source and the ground potential, and the ground potential discharges the second back capacitor to the second power source via the second inductor; and a second electrical connection state has: the second front capacitor and the second back capacitor are connected in series between the first power node and the second power node, and the first power source charges the second front capacitor and the second back capacitor via the second inductor; the first front capacitor and the second front capacitor are connected in series between the first power node and the ground potential. and the ground potential discharges the first front capacitor to the second power source via the second inductor and the second back capacitor; and the first back capacitor and the first inductor are connected in series between the second power source and the ground potential, and the ground potential discharges the first back capacitor to the second power source via the first inductor; wherein the plurality of switching signals operate the first sub-conversion circuit and the second sub-conversion circuit between the first electrical connection state and the second electrical connection state to switch the first voltage capacitively to divide the first voltage, respectively The first switching node is switched between the first divided voltage of the first voltage obtained by the switching capacitive voltage division and the first reference potential, and the second switching node is switched between the second divided voltage of the first voltage obtained by the switching capacitive voltage division and the second reference potential, thereby converting the first power source into the second power source; wherein the first reference potential and the second reference potential are the cross-voltage of the first post-capacitor and the cross-voltage of the second post-capacitor, respectively, and the first divided voltage and the second divided voltage are both half of the first voltage.

In one embodiment, the duty cycle of the plurality of switching signals is 50%, the voltage across the first front capacitor and the voltage across the second front capacitor are both half of the first voltage, and the voltage across the first rear capacitor and the voltage across the second rear capacitor are both one-quarter of the first voltage.

In one embodiment, the switching frequency includes a first resonant frequency associated with the resonance between the first inductor and the first post-capacitor, and a second resonant frequency associated with the resonance between the second inductor and the second post-capacitor.

In one embodiment, the control circuit further generates the switching signal to switch the electrical connection state based on a zero current detection signal indicating at least one of the following: a first inductor current flowing through the corresponding first inductor is zero current; or a second inductor current flowing through the corresponding second inductor is zero current.

In one embodiment, the time point when the first inductor current reaches zero current is a first zero-current time point, and the time point when the second inductor current reaches zero current is a second zero-current time point. After the first zero-current time point and/or the second zero-current time point, the control circuit waits for a corresponding first dead-time and/or a second dead-time before generating the switching signal to switch the electrical connection state.

In one embodiment, the first inductor and the second inductor are electrically counter-electromagnetically coupled via a magnetic object.

In one embodiment, a single inductor serves as both the first inductor and the second inductor.

In one embodiment, the control circuit adjusts the duty cycles of the plurality of switching signals respectively according to a conversion ratio.

In one embodiment, the first pre-capacitor and the second pre-capacitor are alternately coupled between the first power source and the ground potential during a specific period to achieve charge balance.

In one embodiment, the switching frequency is related to a resonant frequency, so that the multi-phase converter circuit operates in a resonant mode to control a voltage ratio of the second voltage to the first voltage to be related to a voltage division ratio of the first voltage to the first voltage or the second voltage division of the first voltage, wherein the resonant frequency is related to the capacitance of the first front capacitor and/or the first rear capacitor and the inductance of the first inductor, or the capacitance of the second front capacitor and/or the second rear capacitor and the inductance of the second inductor.

In one embodiment, the switching frequency is much higher than a resonant frequency, causing the multi-phase converter circuit to operate in a non-resonant mode, thereby regulating the second voltage at a preset level, or regulating the first voltage at a preset level, wherein the resonant frequency is related to the capacitance of the first front capacitor and/or the first rear capacitor and the inductance of the first inductor, or the capacitance of the second front capacitor and/or the second rear capacitor and the inductance of the second inductor.

In one embodiment, the method further includes: generating the switching signal to switch the electrical connection state according to a zero current detection signal indicating at least one of the following: a first inductor current flowing through the corresponding first inductor is zero current; or a second inductor current flowing through the corresponding second inductor is zero current.

In one embodiment, the time point when the first inductor current reaches zero current is a first zero-current time point, and the time point when the second inductor current reaches zero current is a second zero-current time point. The multi-phase conversion circuit control method further includes: after the first zero-current time point and/or the second zero-current time point, waiting for a corresponding first dead-time and/or a second dead-time, and then generating the switching signal to switch the electrical connection state.

In one embodiment, the method further includes adjusting duty cycles of the plurality of switching signals respectively according to a conversion ratio.

In one embodiment, the method further includes: the first pre-capacitor and the second pre-capacitor are alternately coupled between the first power source and the ground potential during a specific period to achieve charge balance.

The advantages of the present invention are that it can achieve low voltage stress, low component count, support more voltage conversion ratios, support resonant mode, regulation mode operation and resonant operation with flexible switching to reduce power consumption.

The following detailed description is based on specific embodiments to make it easier to understand the purpose, technical content, features and effects achieved by the present invention.

The figures in the present invention are schematic, primarily intended to illustrate the coupling relationships between circuits and the relationships between signal waveforms. Circuits, signal waveforms, and frequencies are not drawn to scale.

FIG2A is a schematic circuit diagram of a multiphase conversion circuit according to one embodiment of the present invention. As shown in FIG2A , the multiphase conversion circuit 20 of the present invention is used to perform power conversion between a first voltage V1 at a first power node N1 and a second voltage V2 at a second power node N2. Referring to FIG2A , the multiphase conversion circuit 20 includes a first sub-conversion circuit 201a, a second sub-conversion circuit 201b, and a control circuit 202. The first sub-conversion circuit 201a includes a switch Q1, a front-switching capacitive conversion circuit 2011a, and a rear-switching capacitive conversion circuit 2012a. The switch Q1 is coupled to the first power node N1. The front-switching capacitive conversion circuit 2011a is coupled between the switch Q1 and the first switching node VM1, while the rear-switching capacitive conversion circuit 2012a is coupled between the first switching node VM1 and the second power node N2. The switch Q1, the front-switching capacitive conversion circuit 2011a, and the rear-switching capacitive conversion circuit 2012a are sequentially connected in series between the first power node N1 and the second power node N2.

As shown in FIG2A , the front-switched capacitive converter circuit 2011a includes a front crossover switch Qcrf1, a front lower bridge switch QLf1, a front slave switch Qsuf1, and a front capacitor Cf1. The rear-switched capacitive converter circuit 2012a includes a rear crossover switch Qcrr1, a rear lower bridge switch QLr1, a rear slave switch Qsur1, and a rear capacitor Cr1. The second sub-converter circuit 201b includes a switch Q2, the front-switched capacitive converter circuit 2011b, and the rear-switched capacitive converter circuit 2012b. Switch Q2 is coupled to the first power node N1. The front-switching capacitive conversion circuit 2011b is coupled between the switch Q2 and the second switching node VM2, while the rear-switching capacitive conversion circuit 2012b is coupled between the second switching node VM2 and the second power node N2. The switch Q2, the front-switching capacitive conversion circuit 2011b, and the rear-switching capacitive conversion circuit 2012b are sequentially connected in series between the first power node N1 and the second power node N2. The output capacitor Co is coupled between the second power node N2 and ground.

The front-switched capacitive converter circuit 2011b includes a front crossover switch Qcrf2, a front lower bridge switch QLf2, a front slave switch Qsuf2, and a front capacitor Cf2. The rear-switched capacitive converter circuit 2012b includes a rear crossover switch Qcrr2, a rear lower bridge switch QLr2, a rear slave switch Qsur2, and a rear capacitor Cr2.

The control circuit 202 is configured to generate a plurality of switching signals S1, Scrr1, Slf1, Slr1, Ssuf1, Ssur1, S2, Scrf2, Scrr2, Slf2, Slr2, Ssuf2, and Ssur2. The first sub-converter circuit 201a and the second sub-converter circuit 201b are configured to periodically switch the electrical connection relationship of the front capacitor Cf1, the rear capacitor Cr1, the front capacitor Cf2, and/or the rear capacitor Cr2 between a plurality of electrical connection states based on a switching frequency according to the plurality of switching signals S1, Scrr1, Slf1, Slr1, Ssuf1, Ssur1, S2, Scrf2, Scrr2, Slf2, Slr2, Ssuf2, and Ssur2.

The multiple switching signals S1, Scrf1, Scrr1, Slf1, Slr1, Ssuf1, Ssur1, S2, Scrf2, Scrr2, Slf2, Slr2, Ssuf2 and Ssur2 operate the front capacitor Cf1, the rear capacitor Cr1, the front capacitor Cf2 and/or the rear capacitor Cr2 to perform switching capacitive voltage division on the first voltage V1 between the multiple electrical connection states, so as to respectively switch the first switching node VM1 between the first divided voltage of the first voltage V1 obtained by switching the capacitive voltage division and the first reference potential, and switch the second switching node VM2 between the second divided voltage of the first voltage V1 obtained by switching the capacitive voltage division and the second reference potential, thereby performing power conversion between the first power node N1 and the second power node N2.

The first reference potential and the second reference potential are each related to a first voltage V1 or a divided voltage thereof, ground, a voltage across the front capacitor Cf1, a voltage across the rear capacitor Cr1, a voltage across the front capacitor Cf2, and/or a voltage across the rear capacitor Cr2. A front slave switch Qsuf1 is coupled between the front capacitor Cf1 and the first switching node VM1 and is configured to determine whether the front capacitor Cf1 and the first switching node VM1 are electrically connected based on a corresponding switching signal Ssuf1. A rear slave switch Qsur1 is coupled between the rear capacitor Cr1 and the second power node N2 and is configured to determine whether the rear capacitor Cr1 and the second power node N2 are electrically connected based on a corresponding switching signal Ssur1.

The front slave switch Qsuf2 is coupled between the front capacitor Cf2 and the second switching node VM2 and determines whether the front capacitor Cf2 and the second switching node VM2 are electrically connected based on a corresponding switching signal Ssuf2. The rear slave switch Qsur2 is coupled between the rear capacitor Cr2 and the second power node N2 and determines whether the rear capacitor Cr2 and the second power node N2 are electrically connected based on a corresponding switching signal Ssur2. The front capacitors Cf1 and Cf2 alternately couple between the first power node N1 and ground during specific periods to achieve charge balance.

FIG2B is a schematic diagram of a control circuit for a multi-phase converter circuit according to an embodiment of the present invention. As shown in FIG2B , control circuit 202 generates switching signals S1, S2, Slf1, Slf2, Slr1, Slr2, Scrf1, Scrf2, Scrr1, Scrr2, Ssuf1, Ssuf2, Ssur1, and Ssur2 to switch electrical connection states based on a first voltage V1, a second voltage V2, currents I1 and I2, and a load level (i.e., the power consumption or current of the load circuit). Control circuit 202 includes zero-current detection circuits 2021 a and 2021 b, a phase control logic circuit 2022, and on-time control circuits 2023 a through 2023 n.

Zero-current detection circuit 2021a is coupled between phase control logic circuit 2022 and second voltage V2 to detect current I1. Zero-current detection circuit 2021b is coupled between phase control logic circuit 2022 and second voltage V2 to detect current I2. When zero-current detection circuit 2021a detects that current I1 is zero, it generates a zero-current detection signal ZCD1 to phase control logic circuit 2022. When zero-current detection circuit 2021b detects that current I2 is zero, it generates a zero-current detection signal ZCD2 to phase control logic circuit 2022. In this embodiment, zero-current detection circuits 2021a and 2021b include current flow detection circuits 20211a and 20211b, respectively, for sensing currents I1 and I2. Zero-current detection circuits 2021a and 2021b further include comparators 20212a and 20212b, respectively, for comparing the sensed currents I1 and I2 with reference signals Vref1 and Vref2, respectively, to generate zero-current detection signals ZCD1 and ZCD2, respectively.

Phase control logic circuit 2022 is configured to generate phase control signals Spc1-Spc14 based on first voltage V1, second voltage V2, and zero current detection signals ZCD1 and/or ZCD2. On-time control circuits 2023a-2023n are configured to generate switching signals S1, S2, Slf1, Slf2, Slr1, Slr2, Scrf1, Scrf2, Scrr1, Scrr2, Ssuf1, Ssuf2, Ssur1, and Ssur2 based on phase control signals Spc1-Spc14 and first voltage V1 and second voltage V2, respectively.

FIG2C is a schematic circuit diagram of a control circuit for a multi-phase converter circuit according to another embodiment of the present invention. The control circuit 202′ of this embodiment is similar to the control circuit 202 of FIG2B , except that the on-time control circuits 2023a-2023n and the phase control signals Spc1-Spc14 are omitted. In other words, the phase control logic circuit 2022 directly generates the switching signals S1, S2, Slf1, Slf2, Slr1, Slr2, Scrf1, Scrf2, Scrr1, Scrr2, Ssuf1, Ssuf2, Ssur1, and Ssur2 based on the zero current detection signal ZCD1 or ZCD2.

FIG3 is a schematic circuit diagram of a multi-phase converter circuit according to another embodiment of the present invention. This embodiment differs from the embodiment of FIG2A in that the first sub-converter circuit 201a further includes an inductor L1, and the second sub-converter circuit 201b further includes an inductor L2. As shown in FIG3 , inductor L1 is coupled between the post-capacitor Cr1 and the second power node N2, while inductor L2 is coupled between the post-capacitor Cr2 and the second power node N2. More specifically, inductor L1 is coupled between the post-capacitor Cr1 and the post-slave switch Qsur1, while inductor L2 is coupled between the post-capacitor Cr2 and the post-slave switch Qsur2.

FIG4 is a schematic circuit diagram of a multi-phase converter circuit according to yet another embodiment of the present invention. This embodiment differs from the embodiment of FIG3 in that the inductor L1 is coupled between the rear slave switch Qsur1 and the second power node N2, while the inductor L2 is coupled between the rear slave switch Qsur2 and the second power node N2.

FIG5 is a circuit diagram showing a multi-phase converter circuit according to another embodiment of the present invention. This embodiment differs from the embodiment of FIG4 in that this embodiment uses a single inductor L as both the inductor L1 and the inductor L2.

FIG6 is a circuit diagram showing a multi-phase converter circuit according to another embodiment of the present invention. This embodiment differs from the embodiment of FIG4 in that the inductor L1 and the inductor L2 are electrically reversely coupled to each other by a magnetic object.

Figures 7A through 7P are schematic circuit diagrams and operational diagrams of a multi-phase conversion circuit according to an embodiment of the present invention. Figures 8A through 8C are a table showing different switching states of Figures 7A through 7P according to an embodiment of the present invention. A "V" symbol indicates that the corresponding switch is conducting, while a blank indicates that the corresponding switch is not conducting. A voltage Vcf1 indicates the voltage across the front capacitor Cf1; a voltage Vcf2 indicates the voltage across the front capacitor Cf2; a voltage Vcr1 indicates the voltage across the rear capacitor Cr1; and a voltage Vcr2 indicates the voltage across the rear capacitor Cr2. As shown in FIG7A and FIG8A, in the first electrical connection state (ST1), the switch Q2, the front crossover switch Qcrf1, the front lower bridge switch QLf1, the front slave switch Qsuf2, the rear lower bridge switch QLr1, the rear crossover switch Qcrr1, and the rear slave switch Qsur2 are switched to non-conduction, while the switch Q1, the front slave switch Qsuf1, the front crossover switch Qcrf2, the front lower bridge The switch QLf2, the rear slave switch Qsur1, the rear crossover switch Qcrr2, and the rear lower bridge switch QLr2 are respectively switched on according to the switching signals S1, Ssuf1, Ssur1, Scrf2, Scrr2, Slf2, and Slr2, so that the front capacitor Cf1 and the rear capacitor Cr1 are connected in series between the first power node N1 and the second power node N2, and the front capacitor The series circuit of Cf1 and the rear capacitor Cr1 is further connected in series with the output capacitor Co between the first power node N1 and the ground potential, and the first power source charges the front capacitor Cf1 and the rear capacitor Cr1. The front capacitor Cf2 and the rear capacitor Cr1 are connected in series between the second power node N2 and the ground potential, and the ground potential discharges the front capacitor Cf2 to the second power source through the rear capacitor Cr1. The rear capacitor Cr2 is electrically connected between the second power node N2 and the ground potential, and the ground potential discharges the rear capacitor Cr2 to the second power source, wherein the rear capacitor Cr2 and the output capacitor Co are connected in parallel between the second power node N2 and the ground potential. The front capacitor Cf1 and the front capacitor Cf2 are connected in series between the first power node N1 and the ground potential to perform capacitive voltage division on the first power source.

As shown in FIG7B and FIG8A, in the second electrical connection state (ST2), the switch Q1, the front slave switch Qsuf1, the front crossover switch Qcrf2, the front lower bridge switch QLf2, the rear slave switch Qsur1, the rear crossover switch Qcrr2, and the rear lower bridge switch QLr2 are switched to non-conduction, and the switch Q2, the front crossover switch Qcrf1, the front lower bridge switch QLf1, the front slave switch The switch Qsuf2, the rear lower bridge switch QLr1, the rear crossover switch Qcrr1, and the rear slave switch Qsur2 are respectively switched on according to the switching signals S2, Ssuf2, Ssur2, Scrf1, Scrr1, Slf1, and Slr1, so that the front capacitor Cf2 and the rear capacitor Cr2 are connected in series between the first power node N1 and the second power node N2, and the front capacitor The series circuit of Cf2 and the rear capacitor Cr2 is further connected in series with the output capacitor Co between the first power node N1 and the ground potential, and the first power source charges the front capacitor Cf2 and the rear capacitor Cr2. The front capacitor Cf1 and the rear capacitor Cr2 are connected in series between the second power node N2 and the ground potential, and the ground potential discharges the front capacitor Cf1 to the second power source via the rear capacitor Cr2. The rear capacitor Cr1 is electrically connected between the second power node N2 and the ground potential, and the ground potential discharges the rear capacitor Cr1 to the second power source, wherein the rear capacitor Cr1 and the output capacitor Co are connected in parallel between the second power node N2 and the ground potential; wherein the front capacitor Cf2 and the front capacitor Cf1 are connected in series between the first power node N1 and the ground potential to perform capacitive voltage division on the first power source.

In one embodiment, a plurality of switching signals S1, Ssuf1, Ssur1, Scrf2, Scrr2, Slf2, Slr2, Scrf1, Scrr1, Slf1, Slr1, S2, Ssuf2, and Ssur2 operate the first sub-conversion circuit 201a and the second sub-conversion circuit 201b between a first electrical connection state and a second electrical connection state to switch capacitive voltage division on the first voltage V1, so as to respectively switch the first switching node VM1 between a first divided voltage of the first voltage V1 obtained by switching the capacitive voltage division and a first reference potential, and switch the second switching node VM2 between a second divided voltage of the first voltage V1 obtained by switching the capacitive voltage division and a second reference potential, thereby converting the first power supply into a second power supply. In one embodiment, the first reference potential and the second reference potential are the voltage across the rear capacitor Cr1 and the voltage across the rear capacitor Cr2, respectively, and the first divided voltage and the second divided voltage are both half of the first voltage V1. In one embodiment, the duty cycle of the plurality of switching signals S1, Ssuf1, Ssur1, Scrf2, Scrr2, Slf2, Slr2, Scrf1, Scrr1, Slf1, Slr1, S2, Ssuf2, and Ssur2 is 50%, and the voltage across the front capacitor Cf1 and the voltage across the front capacitor Cf2 are both half of the first voltage V1, and the voltage across the rear capacitor Cr1 and the voltage across the rear capacitor Cr2 are both one-quarter of the first voltage V1.

As shown in FIG7C and FIG8A, in the third electrical connection state (ST3), the front jumper switch Qcrf1, the front lower bridge switch QLf1, the front jumper switch Qcrf2, the front lower bridge switch QLf2, the rear jumper switch Qcrr1, the rear lower bridge switch QLr1, the rear jumper switch Qcrr2, and the rear lower bridge switch QLr2 are switched to non-conduction, and the switch Q1, the switch Q2, the front slave switch Qsuf1, the front slave switch Qsuf2, the rear slave switch Qsur1, and the rear slave switch Qsur2 are switched to conduction according to the switching signals S1, S2, Ssuf1, Ssuf2, Ssur1, and Ssur2, respectively, so that the front circuit is connected. Capacitor Cf1 and rear capacitor Cr1 are connected in series between the first power node N1 and the second power node N2, and the series connection between the front capacitor Cf1 and the rear capacitor Cr1 is further connected in series with an output capacitor Co between the first power node N1 and the ground potential. The front capacitor Cf2 and the rear capacitor Cr2 are connected in series between the first power node N1 and the second power node N2, and the first power source charges the front capacitor Cf1 and the rear capacitor Cr1, and the series connection between the front capacitor Cf2 and the rear capacitor Cr2 is further connected in series with an output capacitor Co between the first power node N1 and the ground potential, and the first power source charges the front capacitor Cf2 and the rear capacitor Cr2.

As shown in FIG7D and FIG8A, in the fourth electrical connection state (ST4), the switch Q1, the switch Q2, the front slave switch Qsuf1, the front slave switch Qsuf2, the rear slave switch Qsur1, and the rear slave switch Qsur2 are switched to non-conduction, and the front jumper switch Qcrf1, the front jumper switch Qcrf2, the front lower bridge switch QLf1, the front lower bridge switch QLf2, the rear jumper switch Qcrr1, the rear jumper switch Qcrr2, the rear lower bridge switch QLr1, and the rear lower bridge switch QLr2 are switched to conduction according to the switching signals Scrf1, Scrf2, Slf1, and Slf2, respectively. 2. Scrr1, Scrr2, Slr1, and Slr2 are switched on, so that the front capacitor Cf2 is coupled between the second power node N2 and the ground potential, and the ground potential discharges the front capacitor Cf2 to the second power source, wherein the front capacitor Cf2 and the output capacitor Co are connected in parallel between the second power node N2 and the ground potential; and the rear capacitor Cr1 is electrically connected between the second power node N2 and the ground potential, and the ground potential discharges the rear capacitor Cr1 to the second power source, wherein the rear capacitor Cr1 and the output capacitor Co are connected in parallel between the second power node N2 and the ground potential. In addition, the front capacitor Cf1 is coupled between the second power node N2 and the ground potential, and the ground potential discharges the front capacitor Cf1 to the second power source, wherein the front capacitor Cf1 and the output capacitor Co are connected in parallel between the second power node N2 and the ground potential; and the rear capacitor Cr2 is electrically connected between the second power node N2 and the ground potential, and the ground potential discharges the rear capacitor Cr2 to the second power source, wherein the rear capacitor Cr2 and the output capacitor Co are connected in parallel between the second power node N2 and the ground potential.

As shown in FIG7E and FIG8A, in the fifth electrical connection state (ST5), the switch Q2, the front crossover switch Qcrf1, the front lower bridge switch QLf1, the front slave switch Qsuf2, the rear lower bridge switch QLr1, the rear crossover switch Qcrr1, and the rear slave switch Qsur2 are switched to non-conduction, and the switch Q1, the front slave switch Qsuf1, the front crossover switch Qcrf2, the front lower bridge switch QLf2, The rear slave switch Qsur1, the rear cross-connect switch Qcrr2, and the rear lower bridge switch QLr2 are respectively switched on according to the switching signals S1, Ssuf1, Ssur1, Scrf2, Scrr2, Slf2, and Slr2, so that the front capacitor Cf1 and the rear capacitor Cr1 are connected in series between the first power node N1 and the second power node N2, and the series circuit of the front capacitor Cf1 and the rear capacitor Cr1 is further connected in series with the output capacitor Co between the first power node N1 and the ground potential, and the first power source charges the front capacitor Cf1 and the rear capacitor Cr1 through the inductor L1, and the front capacitor Cf2 and the rear capacitor Cr1 are connected in series between the second power node N2 and the ground potential, and the ground potential discharges the front capacitor Cf2 to the second power source through the inductor L1 and the rear capacitor Cr1, and the rear capacitor Cr2 It is connected in series with the inductor L2 between the second power node N2 and the ground potential, and the ground potential discharges the rear capacitor Cr2 to the second power source through the inductor L2, wherein the rear capacitor Cr2 and the output capacitor Co are connected in parallel between the second power node N2 and the ground potential; wherein the front capacitor Cf1 and the front capacitor Cf2 are connected in series between the first power node N1 and the ground potential to perform capacitive voltage division on the first power source.

As shown in FIG7F and FIG8A, in the sixth electrical connection state (ST6), the switch Q1, the front slave switch Qsuf1, the front crossover switch Qcrf2, the front lower bridge switch QLf2, the rear slave switch Qsur1, the rear crossover switch Qcrr2, and the rear lower bridge switch QLr2 are switched to non-conduction, and the switch Q2, the front crossover switch Qcrf1, the front lower bridge switch QLf1, the front slave switch Qsuf2, The rear lower bridge switch QLr1, the rear cross-connect switch Qcrr1, and the rear slave switch Qsur2 are switched on according to the switching signals S2, Ssuf2, Ssur2, Scrf1, Scrr1, Slf1, and Slr1, respectively, so that the front capacitor Cf2 and the rear capacitor Cr2 are connected in series between the first power node N1 and the second power node N2, and the series line of the front capacitor Cf2 and the rear capacitor Cr2 is further connected in series with the output capacitor Co between the first power node N1 and the ground potential, and the first power source charges the front capacitor Cf2 and the rear capacitor Cr2 through the inductor L2, and the front capacitor Cf1 and the rear capacitor Cr2 are connected in series between the second power node N2 and the ground potential, and the ground potential discharges the front capacitor Cf1 to the second power source through the inductor L2 and the rear capacitor Cr2, and the rear capacitor Cr1 It is connected in series with the inductor L1 between the second power node N2 and the ground potential, and the ground potential discharges the rear capacitor Cr1 to the second power source through the inductor L1, wherein the rear capacitor Cr1 and the output capacitor Co are connected in parallel between the second power node N2 and the ground potential; wherein the front capacitor Cf2 and the front capacitor Cf1 are connected in series between the first power node N1 and the ground potential to perform capacitive voltage division on the first power source.

In one embodiment, a plurality of switching signals S1, Ssuf1, Ssur1, Scrf2, Scrr2, Slf2, Slr2, Scrf1, Scrr1, Slf1, Slr1, S2, Ssuf2, and Ssur2 operate the first sub-conversion circuit 201a and the second sub-conversion circuit 201b between the fifth electrical connection state and the sixth electrical connection state to switch the capacitive voltage division of the first voltage V1, so as to respectively switch the first switching node VM1 between the first divided voltage of the first voltage V1 obtained by switching the capacitive voltage division and the first reference potential, and switch the second switching node VM2 between the second divided voltage of the first voltage V1 obtained by switching the capacitive voltage division and the second reference potential, thereby converting the first power supply into the second power supply. In one embodiment, the first reference potential and the second reference potential are the voltage across the post-capacitor Cr1 and the voltage across the post-capacitor Cr2, respectively, and the first divided voltage and the second divided voltage are both half of the first voltage V1.

In one embodiment, the duty cycle of the plurality of switching signals S1, Ssuf1, Ssur1, Scrf2, Scrr2, Slf2, Slr2, Scrf1, Scrr1, Slf1, Slr1, S2, Ssuf2, and Ssur2 is 50%, the voltage across the front capacitor Cf1 and the voltage across the front capacitor Cf2 are both half of the first voltage V1, and the voltage across the rear capacitor Cr1 and the voltage across the rear capacitor Cr2 are both one-quarter of the first voltage V1. In one embodiment, the switching frequency includes a first resonant frequency associated with the resonance between the inductor L1 and the rear capacitor Cr1, and a second resonant frequency associated with the resonance between the inductor L2 and the rear capacitor Cr2.

As shown in FIG7G and FIG8A, in the seventh electrical connection state (ST7), the switch Q1, the switch Q2, the front crossover switch Qcrf1, the front lower bridge switch QLf1, the front slave switch Qsuf1, the front crossover switch Qcrf2, the front lower bridge switch QLf2, the front slave switch Qsuf2, the rear crossover switch Qcrr1, and the rear crossover switch Qcrr2 are switched to non-conduction, and the rear slave switch Qsur1, the rear lower bridge switch QLr1, the rear slave switch Qsur2, and the rear lower bridge switch QLr2 are switched to non-conduction according to the switching signal. Signals Ssur1, Slr1, Ssur2, and Slr2 are switched on, so that the inductor L1 is coupled between the ground potential and the second power node N2, and the inductor L1 and the output capacitor Co are connected in parallel between the second power node N2 and the ground potential, and the inductor L2 is coupled between the ground potential and the second power node N2, and the inductor L2 and the output capacitor Co are connected in parallel between the second power node N2 and the ground potential, so that the inductor current iL1 continues to flow toward the second power supply, and the inductor current iL2 continues to flow toward the second power supply.

As shown in FIG7H and FIG8A, in the eighth electrical connection state (ST8), the front slave switch Qsuf1, the front lower bridge switch QLf1, the front slave switch Qsuf2, the front lower bridge switch QLf2, the rear slave switch Qsur1, the rear lower bridge switch QLr1, the rear slave switch Qsur2, and the rear lower bridge switch QLr2 are switched to non-conduction, and the switch Q1, the switch Q2, and the front crossover switch Qcrf 1. The front jumper switch Qcrf2, the rear jumper switch Qcrr1, and the rear jumper switch Qcrr2 are turned on according to switching signals S1, S2, Scrf1, Scrf2, Scrr1, and Scrr2, respectively, so that the inductor L1 is coupled between the first power node N1 and the second power node N2, and the inductor L2 is coupled between the first power node N1 and the second power node N2.

As shown in FIG7I and FIG8B, in the ninth electrical connection state (ST9), the front jumper switch Qcrf1, the front lower bridge switch QLf1, the front jumper switch Qcrf2, and the front lower bridge switch QLf2 are switched to non-conduction, the rear jumper switch Qcrr1 and the rear jumper switch Qcrr2 are kept in conduction, and the rear slave switch Qsur1 and the rear slave switch Qsur2 are kept in non-conduction. The switch Q1, the switch Q2, the front slave switch Qsuf1, the front slave switch Qsuf2, the rear lower bridge switch QLr1, and the rear lower bridge switch QLr2 are respectively switched on according to the switching signals S1, S2, Ssuf1, Ssuf2, Slr1, and Slr2, so that the front capacitor Cf1 is coupled between the first power node N1 and the second power node N2. The front capacitor Cf1 and the output capacitor Co are connected in series between the first power node N1 and the ground potential; the rear capacitor Cr1 is coupled between the ground potential and the second power node N2, and the rear capacitor Cr1 and the output capacitor Co are connected in parallel between the second power node N2 and the ground potential; the front capacitor Cf2 is coupled between the first power node N1 and the second power node N2, and the front capacitor Cf2 and the output capacitor Co are connected in series between the first power node N1 and the ground potential; the rear capacitor Cr2 is coupled between the ground potential and the second power node N2, and the rear capacitor Cr2 and the output capacitor Co are connected in parallel between the second power node N2 and the ground potential; thereby charging the front capacitors Cf1 and Cf2 and discharging the rear capacitors Cr1 and Cr2.

As shown in FIG7J and FIG8B, in the tenth electrical connection state (ST10), the switch Q1, the switch Q2, the front slave switch Qsuf1, and the front slave switch Qsuf2 are switched to non-conduction, the rear jumper switch Qcrr1 and the rear jumper switch Qcrr2 are kept in constant conduction, the rear slave switch Qsur1 and the rear slave switch Qsur2 are kept in constant non-conduction, and the front jumper switch Qc rf1, the front lower bridge switch QLf1, the front crossover switch Qcrf2, the front lower bridge switch QLf2, the rear lower bridge switch QLr1, and the rear lower bridge switch QLr2 are respectively switched on according to the switching signals Scrf1, Slf1, Scrf2, Slf2, Slr1, and Slr2, so that the front capacitor Cf1 is coupled between the ground potential and the second power node N2. , the front capacitor Cf1 and the output capacitor Co are connected in parallel between the second power node N2 and the ground potential; the front capacitor Cf2 is coupled between the ground potential and the second power node N2, wherein the front capacitor Cf2 and the output capacitor Co are connected in parallel between the second power node N2 and the ground potential; the rear capacitor Cr1 is coupled between the ground potential and the second power node N2, wherein the rear capacitor Cr1 and the output capacitor Co are connected in parallel between the second power node N2 and the ground potential; the rear capacitor Cr2 is coupled between the ground potential and the second power node N2, wherein the rear capacitor Cr2 and the output capacitor Co are connected in parallel between the second power node N2 and the ground potential; thereby discharging the front capacitor Cf1, the front capacitor Cf2, the rear capacitor Cr1 and the rear capacitor Cr2.

As shown in FIG7K and FIG8B , in the eleventh electrical connection state (ST11), the rear crossover switch Qcrr1, the rear lower bridge switch QLr1, the rear crossover switch Qcrr2, and the rear lower bridge switch QLr2 are switched to non-conducting, the switch Q1, the switch Q2, the front lower bridge switch QLf1, and the front lower bridge switch QLf2 are kept constantly conducting, the front slave switch Qsuf1 and the front slave switch Qsuf2 are kept constantly non-conducting, and the front crossover switch Qcrf1, the front crossover switch Qcrf2, the rear slave switch Qsur1, and the rear slave switch Qsur2 are switched to conducting according to the switching signals Scrf1, Scrf2, Ssur1, and Ssur2, respectively, so that the rear capacitor Cr1 is coupled to the first A power node N1 and a second power node N2 are connected, and a rear capacitor Cr1 and an output capacitor Co are connected in series between the first power node N1 and the ground potential; a rear capacitor Cr2 is coupled between the first power node N1 and the second power node N2, and the rear capacitor Cr2 and the output capacitor Co are connected in series between the first power node N1 and the ground potential; a front capacitor Cf1 and an input capacitor Cin are connected in parallel between the ground potential and the first power node N1, and a front capacitor Cf2 and an input capacitor Cin are connected in parallel between the ground potential and the first power node N1, thereby charging the rear capacitors Cr1 and Cr2.

As shown in FIG7L and FIG8B, in the twelfth electrical connection state (ST12), the front jumper switch Qcrf1, the front jumper switch Qcrf2, the rear slave switch Qsur1, and the rear slave switch Qsur2 are switched to non-conduction, the switch Q1, the switch Q2, the front lower bridge switch QLf1, and the front lower bridge switch QLf2 are kept in a constant conduction state, the front slave switch Qsuf1 and the front slave switch Qsuf2 are kept in a constant non-conduction state, and the rear jumper switch Qcrr1, the rear lower bridge switch QLr1, the rear jumper switch Qcrr2, and the rear lower bridge switch QLr2 are switched according to the switching signals Scrr1, Slr1, Scrr2, and Slr2, respectively. To be conductive, the rear capacitor Cr1 is coupled between the ground potential and the second power node N2, and the rear capacitor Cr1 and the output capacitor Co are connected in parallel between the second power node N2 and the ground potential; and the rear capacitor Cr2 is coupled between the ground potential and the second power node N2, and the rear capacitor Cr2 and the output capacitor Co are connected in parallel between the second power node N2 and the ground potential; and the front capacitor Cf1 and the input capacitor Cin are connected in parallel between the ground potential and the first power node N1, and the front capacitor Cf2 and the input capacitor Cin are connected in parallel between the ground potential and the first power node N1, thereby discharging the rear capacitors Cr1 and Cr2.

As shown in FIG7M and FIG8C , in the thirteenth electrical connection state (ST13), the switch Q2, the front lower bridge switch QLf1, the front crossover switch Qcrf1, the front slave switch Qsuf2, the rear lower bridge switch QLr1, the rear crossover switch Qcrr1, and the rear crossover switch Qcrr2 are switched to non-conducting, and the switch Q1, the front slave switch Qsuf1, the front crossover switch Qcrf2, the front lower bridge switch QLf2, the rear slave switch Qsur1, the rear lower bridge switch QLr2, and the rear slave switch Qsur2 are switched to conducting according to the switching signals S1, Ssuf1, Scrf2, Slf2, Ssur1, Slr2, and Ssur2, respectively, so that the front capacitor Cf1 and the rear capacitor Cr1 are connected in series between the first power node N1 and the second power node N2. , and the series circuit of the front capacitor Cf1 and the rear capacitor Cr1 is further connected in series with the output capacitor Co between the first power node N1 and the ground potential, and the first power source charges the front capacitor Cf1 and the rear capacitor Cr1, and the front capacitor Cf2 and the rear capacitor Cr1 are connected in series between the second power node N2 and the ground potential, and the ground potential discharges the front capacitor Cf2 to the second power source through the rear capacitor Cr1, wherein the front capacitor Cf1 and the front capacitor Cf2 are connected in series between the first power node N1 and the ground potential to perform capacitive voltage division on the first power source, and the inductor L2 is coupled between the ground potential and the second power node N2, and the inductor L2 and the output capacitor Co are connected in parallel between the second power node N2 and the ground potential, so that the inductor current iL2 continues to flow toward the second power source.

As shown in FIG7N and FIG8C , in the fourteenth electrical connection state (ST14), the switch Q1, the front slave switch Qsuf1, the front jumper switch Qcrf2, the front lower bridge switch QLf2, the rear jumper switch Qcrr1, the rear jumper switch Qcrr2, and the rear lower bridge switch QLr2 are switched to non-conducting, and the switch Q2, the front lower bridge switch QLf1, the front jumper switch Qcrf1, the front slave switch Qsuf2, the rear lower bridge switch QLr1, the rear slave switch Qsur1, and the rear slave switch Qsur2 are switched to conducting according to the switching signals S2, Slf1, Scrf1, Ssuf2, Slr1, Ssur1, and Ssur2, respectively, so that the front capacitor Cf2 and the rear capacitor Cr2 are connected in series between the first power node N1 and the second power node N2. , and the series circuit of the front capacitor Cf2 and the rear capacitor Cr2 is further connected in series with the output capacitor Co between the first power node N1 and the ground potential, and the first power source charges the front capacitor Cf2 and the rear capacitor Cr2, and the front capacitor Cf1 and the rear capacitor Cr2 are connected in series between the second power node N2 and the ground potential, and the ground potential discharges the front capacitor Cf1 to the second power source through the rear capacitor Cr2, wherein the front capacitor Cf2 and the front capacitor Cf1 are connected in series between the first power node N1 and the ground potential to perform capacitive voltage division on the first power source, and the inductor L1 is coupled between the ground potential and the second power node N2, and the inductor L1 and the output capacitor Co are connected in parallel between the second power node N2 and the ground potential, so that the inductor current iL1 continues to flow toward the second power source.

As shown in FIG7O and FIG8C, in the fifteenth electrical connection state (ST15), the switches Q1, Q2, the front lower bridge switches QLf1, QLf2, the front slave switches Qsuf1, Qsuf2, the front crossover switches Qcrf1, Qcrf2, the rear slave switch Qsur1, and the rear crossover switch Qcrr2 are switched to non-conduction, and the rear lower bridge switch QLr1, the rear crossover switch Qcrr1, the rear lower bridge switch QLr2, and the rear slave switch Qsur2 are switched to conduction according to the switching signals Slr1, Scrr1, Slr2, and S sur2 is switched on, so that the post-capacitor Cr1 is electrically connected between the second power node N2 and the ground potential, and the series circuit of the post-capacitor Cr1 and the inductor L1 and the output capacitor Co are connected in parallel between the second power node N2 and the ground potential, and the ground potential discharges the post-capacitor Cr1 to the second power source, and the inductor L2 is coupled between the ground potential and the second power node N2, and the inductor L2 and the output capacitor Co are connected in parallel between the second power node N2 and the ground potential, so that the inductor current iL2 continues to flow toward the second power source.

As shown in FIG7P and FIG8C, in the sixteenth electrical connection state (ST16), the switches Q1, Q2, the front lower bridge switches QLf1, QLf2, the front slave switches Qsuf1, Qsuf2, the front crossover switches Qcrf1, Qcrf2, the rear slave switch Qsur2, and the rear crossover switch Qcrr1 are switched to non-conduction, and the rear lower bridge switch QLr2, the rear crossover switch Qcrr2, the rear lower bridge switch QLr1, and the rear slave switch Qsur1 are switched to conduction according to the switching signals Slr2, Scrr2, Slr1, and S sur1 is switched on, so that the post-capacitor Cr2 is electrically connected between the second power node N2 and the ground potential, and the series circuit of the post-capacitor Cr2 and the inductor L2 and the output capacitor Co are connected in parallel between the second power node N2 and the ground potential, and the ground potential discharges the post-capacitor Cr2 to the second power source, and the inductor L1 is coupled between the ground potential and the second power node N2, and the inductor L1 and the output capacitor Co are connected in parallel between the second power node N2 and the ground potential, so that the inductor current iL1 continues to flow toward the second power source.

Figure 9 is a schematic diagram showing signal waveforms of the multi-phase converter circuit of Figure 2A according to one embodiment of the present invention. Switching signals S1, S2, Slf1, Slf2, Slr1, Slr2, Scrf1, Scrf2, Scrr1, Scrr2, Ssuf1, Ssuf2, Ssur1, and Ssur2, currents I1 and I2, and output current Iout are shown in Figure 9. As shown in Figure 9, there is a dead time td between the falling edges of switching signals S1, Slf2, Slr2, Scrf2, Scrr2, Ssuf1, and Ssur1 and the rising edges of switching signals S2, Slf1, Slr1, Scrf1, Scrr1, Ssuf2, and Ssur2.

Figure 10 is a schematic diagram showing signal waveforms of the multi-phase conversion circuit of Figure 4 according to one embodiment of the present invention. Switching signals S1, S2, Slf1, Slf2, Slr1, Slr2, Scrf1, Scrf2, Scrr1, Scrr2, Ssuf1, Ssuf2, Ssur1, and Ssur2, inductor currents iL1 and iL2, output inductor current iLout, and zero-current detection signals ZCD1 and ZCD2 are shown in Figure 10 . As shown in Figure 10 , the sequence of the plurality of electrical connection states during a switching cycle Tsw in this embodiment is the fifth electrical connection state ST5 (from time t0 to time t1) and the sixth electrical connection state ST6 (from time t2 to time t3), followed by a repeating switching cycle Tsw. The fifth electrical connection state ST5 is shown in FIG7E , and the sixth electrical connection state ST6 is shown in FIG7F . In this embodiment, the switching frequency is related to the resonant frequency, so that the multi-phase conversion circuit 20 operates in the resonant mode to control the voltage ratio of the second voltage V2 to the first voltage V1 to be related to the voltage division ratio of the first voltage V1 to the first voltage V1 or the second voltage division, wherein the resonant frequency is related to the capacitance of the front capacitor Cf1 and/or the rear capacitor Cr1 and the inductance of the inductor L1, or the capacitance of the front capacitor Cf2 and/or the rear capacitor Cr2 and the inductance of the inductor L2. 10 , 2B or 2C , and 4 , the control circuit 202 generates a switching signal to switch the electrical connection state based on at least one of the following indications from the zero current detection signals ZCD1 and ZCD2: the inductor current iL1 flowing through the corresponding inductor L1 is zero current; or the inductor current iL2 flowing through the corresponding inductor L2 is zero current.

Figure 11 is a schematic diagram showing signal waveforms of the multi-phase converter circuit of Figure 4 according to another embodiment of the present invention. Figure 11 shows switching signals S1, S2, Slf1, Slf2, Slr1, Slr2, Scrf1, Scrf2, Scrr1, Scrr2, Ssuf1, Ssuf2, Ssur1, and Ssur2; switching node voltages VLX1 and VLX2; inductor currents iL1 and iL2; and output inductor current iLout. In this embodiment, the sequence of the plurality of electrical connection states during a switching cycle Tsw is the fifth electrical connection state ST5 (time t0 to time t1), the seventh electrical connection state ST7 (time t1 to time t2), the sixth electrical connection state ST6 (time t2 to time t3), and the seventh electrical connection state ST7 (time t3 to time t4). The switching cycle Tsw is then repeated in this order. The fifth electrical connection state ST5 is shown in FIG7E , the sixth electrical connection state ST6 is shown in FIG7F , and the seventh electrical connection state ST7 is shown in FIG7G . In this embodiment, the control circuit 202 adjusts the duty cycle of the plurality of switching signals according to the conversion ratio. In this embodiment, the switching frequency is much higher than the resonant frequency, causing the multi-phase converter circuit 20 to operate in a non-resonant mode, thereby adjusting the second voltage V2 to a preset level, or adjusting the first voltage V1 to a preset level, wherein the resonant frequency is related to the capacitance value of the front capacitor Cf1 and/or the rear capacitor Cr1 and the inductance value of the inductor L1, or the capacitance value of the front capacitor Cf2 and/or the rear capacitor Cr2 and the inductance value of the inductor L2.

FIG12 is a schematic diagram showing signal waveforms of the multi-phase converter circuit of FIG4 according to yet another embodiment of the present invention. FIG12 shows switching signals S1, S2, Slf1, Slf2, Slr1, Slr2, Scrf1, Scrf2, Scrr1, Scrr2, Ssuf1, Ssuf2, Ssur1, and Ssur2; switching node voltages VLX1 and VLX2; inductor currents iL1 and iL2; and output inductor current iLout. In this embodiment, the sequence of the plurality of electrical connection states during a switching cycle Tsw is the thirteenth electrical connection state ST13 (time t0 to time t1), the fourteenth electrical connection state ST14 (time t1 to time t2), the fifteenth electrical connection state ST15 (time t2 to time t3), and the sixteenth electrical connection state ST16 (time t3 to time t4). The switching cycle Tsw is then repeated in this order. The thirteenth electrical connection state ST13 is shown in FIG. 7M , the fourteenth electrical connection state ST14 is shown in FIG. 7N , the fifteenth electrical connection state ST15 is shown in FIG. 7O , and the sixteenth electrical connection state ST16 is shown in FIG. 7P .

13 to 16 are schematic diagrams showing signal waveforms of relevant signals of the multi-phase conversion circuit of FIG. 4 according to an embodiment of the present invention. Referring to both FIG13 and FIG4 , the control circuit 202 generates switching signals S1, S2, Slf1, Slf2, Slr1, Slr2, Scrf1, Scrf2, Scrr1, Scrr2, Ssuf1, Ssuf2, Ssur1, and Ssur2 based on the load level to switch the corresponding switches Q1, Q2, front lower bridge switches QLf1, QLf2, rear lower bridge switches QLr1, QLr2, front crossover switches Qcrf1, Qcrf2, rear crossover switches Qcrr1, Qcrr2, front slave switches Qsuf1, Qsuf2, and rear slave switches Qsur1, Qsur2, thereby switching the electrical connection states and causing the multiple sub-converter circuits 201a and 201b to operate in boundary conduction mode (BCM). As shown in Figure 13, the corresponding switches are switched at the zero-current point when the inductor current iL1 or iL2 is zero, thereby achieving zero-current switching (ZCS) soft switching.

Referring to FIG. 14 and FIG. 4 , the control circuit 202 generates switching signals S1, S2, Slf1, Slf2, Slr1, Slr2, Scrf1, Scrf2, Scrr1, Scrr2, Ssuf1, Ssuf2, Ssur1, and Ssur2 according to the load level to switch the corresponding switches Q1, Q2, front lower bridge switches QLf1, QLf2, rear lower bridge switches QLr1, QLr2, front crossover switches Qcrf1, Qcrf2, rear crossover switches Qcrr1, Qcrr2, front slave switches Qsuf1, Qsuf2, and rear slave switches Qsur1, Qsur2 to switch the electrical connection state and operate the multiple sub-converter circuits 201a and 201b in a discontinuous conduction mode. DCM). Referring to both FIG. 15 and FIG. 4 , the control circuit 202 generates switching signals S1, S2, Slf1, Slf2, Slr1, Slr2, Scrf1, Scrf2, Scrr1, Scrr2, Ssuf1, Ssuf2, Ssur1, and Ssur2 based on the load level to switch the corresponding switches Q1, Q2, front lower bridge switches QLf1, QLf2, rear lower bridge switches QLr1, QLr2, front crossover switches Qcrf1, Qcrf2, rear crossover switches Qcrr1, Qcrr2, front slave switches Qsuf1, Qsuf2, and rear slave switches Qsur1, Qsur2, thereby switching the electrical connection states and causing the multiple sub-converter circuits 201a and 201b to operate in continuous conduction mode (CCM).

FIG17 is a schematic circuit diagram and an operational diagram of a multi-phase converter circuit according to an embodiment of the present invention. Referring to both FIG16 and FIG17 , the switching signals Scrf1, Scrf2, Scrr1, and Scrr2 are activated after inductor L1 or L2 is demagnetized and the inductor current iL1 or iL2 flowing through inductor L1 or L2 reaches zero. After a stagnation time td, the corresponding front cross-connect switches Qcrf1 and Qcrf2 and rear cross-connect switches Qcrr1 and Qcrr2 are switched. As shown in FIG17 , the reverse inductor current iL2 on the inductor L2 flows along the path of the thick dashed line to the first voltage V1 or the second voltage V2, thereby utilizing the energy of the front jumper switch Qcrf1 and the rear jumper switch Qcrr2 and activating the body diodes of the front jumper switch Qcrf1 and the rear jumper switch Qcrr2, thereby achieving zero voltage switching (ZVS) soft switching. The reverse inductor current iL1 on the inductor L1 flows along the path of the thick dashed line to the first voltage V1 or the second voltage V2, thereby utilizing the energy of the front jumper switch Qcrf2 and the rear jumper switch Qcrr1 and activating the body diodes of the front jumper switch Qcrf2 and the rear jumper switch Qcrr1. diode) to achieve zero-voltage switching (ZVS) soft switching. As shown in FIG16 , the time point when the inductor current iL1 reaches zero current is the first zero-current time point, and the time point when the inductor current iL2 reaches zero current is the second zero-current time point. After the first zero-current time point and/or the second zero-current time point, the control circuit 202 waits for a corresponding first dead-time td and/or a second dead-time td before generating a switching signal to switch the electrical connection state.

In summary, the present invention can achieve low voltage stress, low component count, support for more voltage conversion ratios, support for resonant mode, regulation mode operation, and resonant operation with flexible switching to reduce power consumption.

The present invention has been described above with reference to preferred embodiments. However, the above description is intended only to facilitate understanding of the present invention by those skilled in the art and is not intended to limit the broadest scope of the present invention. Each of the described embodiments is not limited to individual application and can be combined for application. For example, two or more embodiments can be combined for application, and components of one embodiment can replace corresponding components of another embodiment. Furthermore, within the spirit of the present invention, those skilled in the art will be able to envision various equivalent variations and combinations. For example, the phrase "processing, calculating, or generating an output result based on a signal" as used herein is not limited to processing the signal itself but also includes, where necessary, performing voltage-to-current conversion, current-to-voltage conversion, and/or ratio conversion on the signal, and then processing or calculating the converted signal to generate an output result. It is clear that within the spirit of the present invention, those skilled in the art will be able to envision various equivalent variations and combinations, and the number of such combinations is too numerous to be fully detailed here. Therefore, the scope of the present invention shall encompass all of the above and other equivalent variations.

20: Multiphase conversion circuit 201a: First sub-conversion circuit 201b: Second sub-conversion circuit 2011a, 2011b: Front-switched capacitor-type conversion circuit 2012a, 2012b: Back-switched capacitor-type conversion circuit 202, 202': Control circuit 2021a, 2021b: Zero-current detection circuit 20211a, 20211b: Current flow detection circuit 20212a, 20212b: Comparator 2022: Phase control logic circuit 2023a-2023n: On-time control circuit C1, C4: Capacitors Cf1, Cf2: Front capacitors Co: Output capacitor Cr1, Cr2: Back capacitors I1, I2: Current iL, iL1, iL2: Inductor current iLout: Output inductor current Iout: Output current L, L1, L2: Inductor N1: First power node N2: Second power node Q1, Q2: Switches Qcrf1, Qcrf2: Front jumper switches Qcrr1, Qcrr2: Rear jumper switches QLf1, QLf2: Front lower bridge switches QLr1, QLr2: Rear lower bridge switches Qsuf1, Qsuf2: Front slave switches Qsur1, Qsur2: Rear slave switches S1, S2, Scrf1, Scrf2, Scrr1, Scrr2, SLf1, SLf2, SLr1, SLr2, Ssuf1, Ssuf2, Ssur1, Ssur2: Switching signals Spc1-Spc14: Phase control signal ST1: First electrical connection state ST2: Second electrical connection state ST3: Third electrical connection state ST4: Fourth electrical connection state ST5: Fifth electrical connection state ST6: Sixth electrical connection state ST7: Seventh electrical connection state ST8: Eighth electrical connection state ST9: Ninth electrical connection state ST10: Tenth electrical connection state ST11: Eleventh electrical connection state ST12: Twelfth electrical connection state ST13: Thirteenth electrical connection state ST14: Fourteenth electrical connection state ST15: Fifteenth electrical connection state ST16: Sixteenth electrical connection state t0-t4: Time points td: Dead time Tsw: Switching period V1: First voltage V2: Second voltage Vcf1, Vcf2, Vcr1, Vcr2: Cross-voltage VLX1, VLX2: Switching node voltage VM1: First switching node VM2: Second switching node Vout: Output voltage Vref1, Vref2: Reference signal ZCD1, ZCD2: Zero current detection signal

FIG1 is a schematic diagram showing a conventional two-phase conversion circuit.

FIG2A is a schematic circuit diagram showing a multi-phase conversion circuit according to an embodiment of the present invention.

FIG2B is a schematic circuit diagram showing a control circuit of a multi-phase converter circuit according to an embodiment of the present invention.

FIG2C is a schematic circuit diagram showing a control circuit of a multi-phase converter circuit according to another embodiment of the present invention.

FIG3 is a schematic circuit diagram showing a multi-phase conversion circuit according to another embodiment of the present invention.

FIG4 is a schematic circuit diagram showing a multi-phase conversion circuit according to yet another embodiment of the present invention.

FIG5 is a schematic circuit diagram showing a multi-phase conversion circuit according to another embodiment of the present invention.

FIG6 is a schematic circuit diagram showing a multi-phase conversion circuit according to yet another embodiment of the present invention.

7A to 7P are circuit diagrams and operation diagrams showing a multi-phase conversion circuit according to an embodiment of the present invention.

8A to 8C are lists showing different switching states of FIG. 7A to FIG. 7P according to an embodiment of the present invention.

FIG9 is a schematic diagram showing signal waveforms of relevant signals of the multi-phase conversion circuit of FIG2A according to one embodiment of the present invention.

FIG10 is a schematic diagram showing signal waveforms of relevant signals of the multi-phase conversion circuit of FIG4 according to one embodiment of the present invention.

FIG11 is a schematic diagram showing signal waveforms of related signals of the multi-phase conversion circuit of FIG4 according to another embodiment of the present invention.

FIG12 is a schematic diagram showing signal waveforms of relevant signals of the multi-phase conversion circuit of FIG4 according to yet another embodiment of the present invention.

13 to 16 are schematic diagrams showing signal waveforms of relevant signals of the multi-phase conversion circuit of FIG. 4 according to an embodiment of the present invention.

FIG17 is a circuit diagram and an operation diagram showing a multi-phase conversion circuit according to an embodiment of the present invention.

20: Multi-phase conversion circuit

201a: First sub-conversion circuit

201b: Second sub-conversion circuit

2011a, 2011b: Front-Switching Capacitive Converter Circuit

2012a, 2012b: Post-switching capacitive converter circuit

202: Control circuit

Cf1, Cf2: front capacitors

Co: output capacitance

Cr1, Cr2: post-capacitor

I1, I2: Current

Iout: output current

N1: First power node

N2: Second power node

Q1, Q2: Switch

Qcrf1, Qcrf2: Front jumper switch

Qcrr1, Qcrr2: rear jumper switch

QLf1, QLf2: Front lower bridge switch

QLr1, QLr2: Rear lower bridge switch

Qsuf1, Qsuf2: front slave switches

Qsur1, Qsur2: rear slave switches

S1, S2, Scrf1, Scrf2, Scrr1, Scrr2, SLf1, SLf2, SLr1, SLr2, Ssuf1, Ssuf2, Ssur1, Ssur2: Switching signal

V1: First voltage

V2: Second voltage

VM1: First switching node

VM2: Second switching node

Claims (30)

A multi-phase conversion circuit is provided for power conversion between a first power source at a first power node and a second power source at a second power node, wherein the first power source comprises a first voltage and the second power source comprises a second voltage. The multi-phase conversion circuit comprises: A first sub-conversion circuit comprising: A first switch coupled to the first power node; A first front-switching capacitive conversion circuit coupled between the first switch and the first switching node; and A first rear-switching capacitive conversion circuit coupled between the first switching node and the second power node; The first switch, the first front-switching capacitive conversion circuit, and the first rear-switching capacitive conversion circuit are sequentially connected in series between the first power node and the second power node; The first front-switched capacitive conversion circuit includes a first front crossover switch, a first front lower bridge switch, a first front slave switch, and a first front capacitor; The first rear-switched capacitive conversion circuit includes a first rear crossover switch, a first rear lower bridge switch, a first rear slave switch, and a first rear capacitor; A second sub-conversion circuit includes: A second switch coupled to the first power node; A second front-switched capacitive conversion circuit coupled between the second switch and a second switching node; and A second rear-switched capacitive conversion circuit coupled between the second switching node and the second power node; The second switch, the second front-switched capacitive conversion circuit, and the second rear-switched capacitive conversion circuit are sequentially connected in series between the first power node and the second power node; The second front-switched capacitive conversion circuit includes a second front crossover switch, a second front lower bridge switch, a second front slave switch, and a second front capacitor; The second rear-switched capacitive conversion circuit includes a second rear crossover switch, a second rear lower bridge switch, a second rear slave switch, and a second rear capacitor; and A control circuit for generating a plurality of switching signals; The first sub-conversion circuit and the second sub-conversion circuit are configured to periodically switch the electrical connection relationship of the first front capacitor, the first rear capacitor, the second front capacitor, and/or the second rear capacitor between a plurality of electrical connection states based on a switching frequency according to the plurality of switching signals; The plurality of switching signals, between the plurality of electrical connection states, operate the first front capacitor, the first rear capacitor, the second front capacitor, and/or the second rear capacitor to perform switching capacitive voltage division on the first voltage, thereby respectively switching the first switching node between a first divided voltage of the first voltage obtained by the switching capacitive voltage division and a first reference potential, and switching the second switching node between a second divided voltage of the first voltage obtained by the switching capacitive voltage division and a second reference potential, thereby performing power conversion between the first power node and the second power node; The first reference potential and the second reference potential are each related to the first voltage or a divided voltage thereof, a ground potential, a voltage across the first front capacitor, a voltage across the first rear capacitor, a voltage across the second front capacitor, and/or a voltage across the second rear capacitor; The first front slave switch is coupled between the first front capacitor and the first switching node to determine whether the first front capacitor and the first switching node are electrically connected based on the corresponding switching signal; The first rear slave switch is coupled between the first rear capacitor and the second power node to determine whether the first rear capacitor and the second power node are electrically connected based on the corresponding switching signal; The second front slave switch is coupled between the second front capacitor and the second switching node, and is configured to determine whether the second front capacitor and the second switching node are electrically connected based on the corresponding switching signal. The second rear slave switch is coupled between the second rear capacitor and the second power node, and is configured to determine whether the second rear capacitor and the second power node are electrically connected based on the corresponding switching signal. The multi-phase conversion circuit of claim 1, wherein the plurality of electrical connection states include: a first electrical connection state having: the first front capacitor and the first rear capacitor connected in series between the first power node and the second power node, and the first power source charging the first front capacitor and the first rear capacitor; the second front capacitor and the first rear capacitor connected in series between the second power node and the ground potential, and the ground potential discharges the second front capacitor to the second power source via the first rear capacitor; and the second rear capacitor connected between the second power source and the ground potential, and the ground potential discharges the second rear capacitor to the second power source; and a second electrical connection state having: The second front capacitor and the second back capacitor are connected in series between the first power node and the second power node, and the first power node charges the second front capacitor and the second back capacitor. The first front capacitor and the second back capacitor are connected in series between the second power node and the ground potential, and the ground potential discharges the first front capacitor to the second power node via the second back capacitor. The first back capacitor is electrically connected between the second power node and the ground potential, and the ground potential discharges the first back capacitor to the second power node. The plurality of switching signals operates the first sub-conversion circuit and the second sub-conversion circuit between the first electrical connection state and the second electrical connection state to perform capacitive voltage division on the first voltage, thereby switching the first switching node between the first divided voltage of the first voltage obtained by the switching capacitive voltage division and the first reference potential, and switching the second switching node between the second divided voltage of the first voltage obtained by the switching capacitive voltage division and the second reference potential, thereby converting the first power source into the second power source. The first reference potential and the second reference potential are the voltage across the first post-capacitor and the voltage across the second post-capacitor, respectively, and the first divided voltage and the second divided voltage are both half of the first voltage. A multi-phase conversion circuit as described in claim 2, wherein the duty cycle of the multiple switching signals is 50%, and the voltage across the first front capacitor and the voltage across the second front capacitor are both half of the first voltage, and the voltage across the first rear capacitor and the voltage across the second rear capacitor are both one-quarter of the first voltage. A multi-phase conversion circuit as described in claim 1, wherein the first sub-conversion circuit further includes a first inductor, and the second sub-conversion circuit further includes a second inductor, wherein the first inductor is coupled between the first post-capacitor and the second power node, and wherein the second inductor is coupled between the second post-capacitor and the second power node. The multi-phase conversion circuit as described in claim 4, wherein the plurality of electrical connection states include: a first electrical connection state having: the first pre-capacitor and the first post-capacitor are connected in series between the first power node and the second power node, and the first power source charges the first pre-capacitor and the first post-capacitor via the first inductor; the second pre-capacitor and the first pre-capacitor are connected in series between the first power node and the ground potential, and the ground potential discharges the second pre-capacitor to the second power source via the first inductor and the first post-capacitor; and the second post-capacitor and the second inductor are connected in series between the second power source and the ground potential, and the ground potential discharges the second post-capacitor to the second power source via the second inductor; and a second electrical connection state having: The second pre-capacitor and the second post-capacitor are connected in series between the first power node and the second power node, and the first power node charges the second pre-capacitor and the second post-capacitor via the second inductor. The first pre-capacitor and the second pre-capacitor are connected in series between the first power node and the ground potential, and the ground potential discharges the first pre-capacitor to the second power node via the second inductor and the second post-capacitor. The first post-capacitor and the first inductor are connected in series between the second power node and the ground potential, and the ground potential discharges the first post-capacitor to the second power node via the first inductor. The plurality of switching signals operates the first sub-conversion circuit and the second sub-conversion circuit between the first electrical connection state and the second electrical connection state to perform capacitive voltage division on the first voltage, thereby switching the first switching node between the first divided voltage of the first voltage obtained by the switching capacitive voltage division and the first reference potential, and switching the second switching node between the second divided voltage of the first voltage obtained by the switching capacitive voltage division and the second reference potential, thereby converting the first power source into the second power source. The first reference potential and the second reference potential are the voltage across the first post-capacitor and the voltage across the second post-capacitor, respectively, and the first divided voltage and the second divided voltage are both half of the first voltage. A multi-phase conversion circuit as described in claim 5, wherein the duty cycle of the multiple switching signals is 50%, and the voltage across the first front capacitor and the voltage across the second front capacitor are both half of the first voltage, and the voltage across the first rear capacitor and the voltage across the second rear capacitor are both one-quarter of the first voltage. The multi-phase converter circuit of claim 5, wherein the switching frequency includes a first resonant frequency associated with the resonance between the first inductor and the first post-capacitor, and a second resonant frequency associated with the resonance between the second inductor and the second post-capacitor. The multi-phase converter circuit of claim 5, wherein the control circuit further generates the switching signal to switch the electrical connection state based on a zero-current detection signal indicating at least one of the following: The current flowing through the corresponding first inductor is zero; or The current flowing through the corresponding second inductor is zero. A multi-phase conversion circuit as described in claim 8, wherein the time point when the first inductor current is zero current is a first zero current time point, and the time point when the second inductor current is zero current is a second zero current time point, and the control circuit waits for a corresponding first dead-time and/or a second dead-time after the first zero current time point and/or the second zero current time point, and then generates the switching signal to switch the electrical connection state. A multi-phase conversion circuit as described in claim 4, wherein the first inductor and the second inductor are electrically reversely electromagnetically coupled via a magnetic object. A multi-phase converter circuit as described in claim 4, wherein a single inductor serves as both the first inductor and the second inductor. A multi-phase conversion circuit as described in claim 4, wherein the control circuit adjusts the duty cycle of the plurality of switching signals respectively according to a conversion ratio. The multi-phase conversion circuit as described in claim 4, wherein the first pre-capacitor and the second pre-capacitor are alternately coupled between the first power source and the ground potential during a specific period to achieve charge balance. A multi-phase conversion circuit as described in claim 4, wherein the switching frequency is related to a resonant frequency, so that the multi-phase conversion circuit operates in a resonant mode to control a voltage ratio of the second voltage to the first voltage to be related to a voltage division ratio of the first voltage to the first voltage or the second voltage division of the first voltage, wherein the resonant frequency is related to the capacitance value of the first front capacitor and/or the first rear capacitor and the inductance value of the first inductor, or the capacitance value of the second front capacitor and/or the second rear capacitor and the inductance value of the second inductor. A multi-phase converter circuit as described in claim 4, wherein the switching frequency is much higher than a resonant frequency, so that the multi-phase converter circuit operates in a non-resonant mode, thereby adjusting the second voltage to a preset level, or adjusting the first voltage to a preset level, wherein the resonant frequency is related to the capacitance value of the first front capacitor and/or the first rear capacitor and the inductance value of the first inductor, or the capacitance value of the second front capacitor and/or the second rear capacitor and the inductance value of the second inductor. A multi-phase conversion circuit control method, comprising: generating a plurality of switching signals and periodically switching the electrical connection relationship of a first front capacitor and/or a first rear capacitor corresponding to a first sub-conversion circuit and a second front capacitor and/or a second rear capacitor of a second sub-conversion circuit in a multi-phase conversion circuit between a plurality of electrical connection states based on a switching frequency, so as to perform power conversion between a first voltage of a first power node and a second voltage of a second power node, wherein the first sub-conversion circuit includes a series connection of a A first switch, a first front-switching capacitive conversion circuit, and a first rear-switching capacitive conversion circuit, wherein the first switch is coupled to the first power node, the first front-switching capacitive conversion circuit is coupled between the first switch and a first switching node, and the first rear-switching capacitive conversion circuit is coupled between the first switching node and the second power node, wherein the first front-switching capacitive conversion circuit includes a first front cross-connect switch, a first front lower bridge switch, and a The first front slave switch and a first front capacitor, the first rear switching capacitive conversion circuit includes a first rear cross-connect switch, a first rear lower bridge switch, a first rear slave switch and a first rear capacitor, the second sub-conversion circuit includes a second switch, a second front switching capacitive conversion circuit and a second rear switching capacitive conversion circuit connected in series, wherein the second switch is coupled to the first power node, the second front switching capacitive conversion circuit is coupled to the second switch The second rear-switched capacitive conversion circuit is coupled between the second switching node and the second power node, wherein the second front-switched capacitive conversion circuit includes a second front cross-over switch, a second front lower bridge switch, a second front slave switch, and a second front capacitor; and the second rear-switched capacitive conversion circuit includes a second rear cross-over switch, a second rear lower bridge switch, a second rear slave switch, and a second rear capacitor; and The plurality of switching signals, between the plurality of electrical connection states, operate the first front capacitor, the first rear capacitor, the second front capacitor, and/or the second rear capacitor to perform switching capacitive voltage division on the first voltage, thereby respectively switching the first switching node between a first divided voltage of the first voltage obtained by the switching capacitive voltage division and a first reference potential, and switching the second switching node between a second divided voltage of the first voltage obtained by the switching capacitive voltage division and a second reference potential, thereby performing power conversion between the first power node and the second power node; The first reference potential and the second reference potential are each related to the first voltage or a divided voltage thereof, a ground potential, a voltage across the first front capacitor, a voltage across the first rear capacitor, a voltage across the second front capacitor, and/or a voltage across the second rear capacitor; The first front slave switch is coupled between the first front capacitor and the first switching node to determine whether the first front capacitor and the first switching node are electrically connected based on the corresponding switching signal; The first rear slave switch is coupled between the first rear capacitor and the second power node to determine whether the first rear capacitor and the second power node are electrically connected based on the corresponding switching signal; The second front slave switch is coupled between the second front capacitor and the second switching node, and is configured to determine whether the second front capacitor and the second switching node are electrically connected based on the corresponding switching signal. The second rear slave switch is coupled between the second rear capacitor and the second power node, and is configured to determine whether the second rear capacitor and the second power node are electrically connected based on the corresponding switching signal. The multi-phase conversion circuit control method as described in claim 16, wherein the plurality of electrical connection states include: a first electrical connection state having: the first front capacitor and the first rear capacitor connected in series between the first power node and the second power node, and the first power source charges the first front capacitor and the first rear capacitor; the second front capacitor and the first rear capacitor connected in series between the second power node and the ground potential, and the ground potential discharges the second front capacitor to the second power source via the first rear capacitor; and the second rear capacitor connected between the second power source and the ground potential, and the ground potential discharges the second rear capacitor to the second power source; and a second electrical connection state having: The second front capacitor and the second back capacitor are connected in series between the first power node and the second power node, and the first power node charges the second front capacitor and the second back capacitor. The first front capacitor and the second back capacitor are connected in series between the second power node and the ground potential, and the ground potential discharges the first front capacitor to the second power node via the second back capacitor. The first back capacitor is electrically connected between the second power node and the ground potential, and the ground potential discharges the first back capacitor to the second power node. The plurality of switching signals operates the first sub-conversion circuit and the second sub-conversion circuit between the first electrical connection state and the second electrical connection state to perform capacitive voltage division on the first voltage, thereby switching the first switching node between the first divided voltage of the first voltage obtained by the switching capacitive voltage division and the first reference potential, and switching the second switching node between the second divided voltage of the first voltage obtained by the switching capacitive voltage division and the second reference potential, thereby converting the first power source into the second power source. The first reference potential and the second reference potential are the voltage across the first post-capacitor and the voltage across the second post-capacitor, respectively, and the first divided voltage and the second divided voltage are both half of the first voltage. A multi-phase conversion circuit control method as described in claim 17, wherein the duty cycle of the multiple switching signals is 50%, and the voltage across the first front capacitor and the voltage across the second front capacitor are both half of the first voltage, and the voltage across the first rear capacitor and the voltage across the second rear capacitor are both one-quarter of the first voltage. A multi-phase conversion circuit control method as described in claim 16, wherein the first sub-conversion circuit further includes a first inductor, and the second sub-conversion circuit further includes a second inductor, wherein the first inductor is coupled between the first post-capacitor and the second power node, and wherein the second inductor is coupled between the second post-capacitor and the second power node. The multi-phase conversion circuit control method as described in claim 19, wherein the plurality of electrical connection states include: a first electrical connection state, comprising: the first front capacitor and the first rear capacitor are connected in series between the first power node and the second power node, and the first power source charges the first front capacitor and the first rear capacitor via the first inductor; the second front capacitor and the first front capacitor are connected in series between the first power node and the ground potential, and the ground potential is discharged from the second front capacitor to the second power source via the first inductor and the first rear capacitor; and the second rear capacitor and the second inductor are connected in series between the second power source and the ground potential, and the ground potential is discharged from the second rear capacitor to the second power source via the second inductor; and a second electrical connection state, comprising: The second pre-capacitor and the second post-capacitor are connected in series between the first power node and the second power node, and the first power node charges the second pre-capacitor and the second post-capacitor via the second inductor. The first pre-capacitor and the second pre-capacitor are connected in series between the first power node and the ground potential, and the ground potential discharges the first pre-capacitor to the second power node via the second inductor and the second post-capacitor. The first post-capacitor and the first inductor are connected in series between the second power node and the ground potential, and the ground potential discharges the first post-capacitor to the second power node via the first inductor. The plurality of switching signals operates the first sub-conversion circuit and the second sub-conversion circuit between the first electrical connection state and the second electrical connection state to perform capacitive voltage division on the first voltage, thereby switching the first switching node between the first divided voltage of the first voltage obtained by the switching capacitive voltage division and the first reference potential, and switching the second switching node between the second divided voltage of the first voltage obtained by the switching capacitive voltage division and the second reference potential, thereby converting the first power source into the second power source. The first reference potential and the second reference potential are the voltage across the first post-capacitor and the voltage across the second post-capacitor, respectively, and the first divided voltage and the second divided voltage are both half of the first voltage. A multi-phase conversion circuit control method as described in claim 20, wherein the duty cycle of the multiple switching signals is 50%, and the voltage across the first front capacitor and the voltage across the second front capacitor are both half of the first voltage, and the voltage across the first rear capacitor and the voltage across the second rear capacitor are both one-quarter of the first voltage. The multi-phase converter circuit control method of claim 20, wherein the switching frequency includes a first resonant frequency related to the resonance between the first inductor and the first post-capacitor, and a second resonant frequency related to the resonance between the second inductor and the second post-capacitor. The multi-phase conversion circuit control method of claim 20 further comprises: generating the switching signal to switch the electrical connection state based on a zero current detection signal indicating at least one of the following: A first inductor current flowing through the corresponding first inductor is zero current; or A second inductor current flowing through the corresponding second inductor is zero current. A multi-phase conversion circuit control method as described in claim 23, wherein the time point when the first inductor current is zero current is a first zero current time point, and the time point when the second inductor current is zero current is a second zero current time point. The multi-phase conversion circuit control method further includes: after the first zero current time point and/or the second zero current time point, waiting for a corresponding first dead-time and/or a second dead-time, generating the switching signal to switch the electrical connection state. A multi-phase conversion circuit control method as described in claim 19, wherein the first inductor and the second inductor are electrically reversely electromagnetically coupled via a magnetic object. A multi-phase converter circuit control method as described in claim 19, wherein a single inductor serves as both the first inductor and the second inductor. The multi-phase conversion circuit control method as described in claim 19 further includes: adjusting the duty cycle of the multiple switching signals respectively according to a conversion ratio. The multi-phase conversion circuit control method as described in claim 19 further includes: the first pre-capacitor and the second pre-capacitor are alternately coupled between the first power source and the ground potential during a specific period to achieve charge balance. A multi-phase conversion circuit control method as described in claim 19, wherein the switching frequency is related to a resonant frequency, so that the multi-phase conversion circuit operates in a resonant mode to control a voltage ratio of the second voltage to the first voltage that is related to a voltage division ratio of the first voltage to the first voltage or the second voltage division of the first voltage, wherein the resonant frequency is related to the capacitance value of the first front capacitor and/or the first rear capacitor and the inductance value of the first inductor, or the capacitance value of the second front capacitor and/or the second rear capacitor and the inductance value of the second inductor. A multi-phase conversion circuit control method as described in claim 19, wherein the switching frequency is much higher than a resonant frequency, so that the multi-phase conversion circuit operates in a non-resonant mode, thereby adjusting the second voltage to a preset level, or adjusting the first voltage to a preset level, wherein the resonant frequency is related to the capacitance value of the first front capacitor and/or the first rear capacitor and the inductance value of the first inductor, or the capacitance value of the second front capacitor and/or the second rear capacitor and the inductance value of the second inductor.