TWI900117B - Detection of an error condition on a serial data bus - Google Patents

Abstract

A controller is provided that includes a serial data (SDA) line interface to connect the controller to an SDA line of a two-wire, shared, serial data bus. The controller includes a circuitry to provide output data for transfer on to the SDA line via the output SDA pad buffer. The controller includes a logic circuit that is external to the circuitry, and that monitors data on the SDA line while the output data is transferred on to the SDA line. The logic circuit compares the monitored data on the SDA line and the output data to detect an error condition when the monitored data and the output data differ. The logic circuit disables an output SDA pad buffer of the SDA line interface for a current byte of the output data provided by the circuitry, and then causes a stop condition on the data bus.

Description

Detection of error conditions on the serial data bus

Cross-reference to related applications

This application claims priority to Indian provisional patent application No. 202341063537 filed on September 21, 2023, and entitled “Detection and Recovery from a Read-Write Data Conflict on a Serial Data Bus ,” which is incorporated herein by reference in its entirety.

This disclosure relates generally to serial communications, and more particularly to detecting an error condition on a serial data bus.

Serial communication plays a key role in facilitating inter-chip communication within electronic systems. It involves sequentially transferring data bit by bit over a communication link between devices. Compared to parallel communication, this method offers advantages such as simplicity, low pin count, and the ability to transmit data over long distances.

A common serial communication protocol is I2C (Inter-Integrated Circuit), which was developed by Philips Semiconductor (now NXP Semiconductors) in the early 1980s. I2C is a two-wire bus protocol that allows multiple devices to communicate with each other using a shared serial data (SDA) line and a serial clock (SCL) line. It supports a controller-target (master-slave) architecture, in which a controller device initiates and controls communication, and the target device responds to commands or requests from the controller. I2C is commonly used to connect various devices in embedded systems, consumer electronics, and computer peripherals.

As technology advances and demands for higher data rates, increased flexibility, and improved power efficiency arise, the MIPI Alliance developed the Improved Inter-Integrated Circuit (I3C). Launched in 2017, I3C builds on the strengths of I2C while offering enhancements and additional features. I3C is backward compatible with I2C, allowing I2C devices to coexist on the same data bus. It introduces higher data rates, increased flexibility for connecting multiple devices, multi-controller support, hot-join capabilities, dynamic address allocation, in-band interrupts, and other improvements. I3C has become popular in applications such as smartphones, tablets, Internet of Things (IoT) devices, and automotive systems.

Serial communication protocols such as I2C and I3C have become an integral part of inter-chip communication within electronic systems. They enable devices to efficiently and reliably exchange data, commands, and control signals. These protocols have been widely adopted and standardized, allowing interoperability between devices from different manufacturers and simplifying the integration of various components within electronic systems. The continuous evolution and development of serial communication protocols has contributed to the advancement of inter-chip communication and the seamless operation of modern electronic devices.

As serial communication protocols advance, it may happen that commercially available circuit systems (such as semiconductor intellectual property cores (IP blocks) that enable a controller to support serial communication over a serial data bus) may not support certain errors.

In I3C, a controller can initiate a transaction (e.g., a read transaction, a write transaction) with a target or receive an in-band interrupt (IBI); however, in some instances, an error type CE1 may occur. This error type CE1 occurs when the controller, in a write state, detects that the input data on the data bus is different from the data the controller intended to send as output data on the data bus. This can occur if the target misinterprets one or more pieces of information (indicating a read or write transaction, or an acknowledgment) during a transaction (including an in-band interrupt initiated by the target at approximately the same time as a private write transaction initiated by the controller). The target may behave as if it is responding to a read transaction when the controller actually intended to initiate a write transaction. When this happens, the write data on the data bus from the controller may conflict with the read data from the target. In I3C, when the controller detects a CE1 error condition, it should stop the transfer, then assert a stop condition on the data bus, and retry the transfer. However, existing devices and circuitry that provide output data for transmission on the SDA line do not properly support the CE1 error condition. The fact that such circuits can be implemented in a commercially available Intellectual Property block is undeniable.

Therefore, example embodiments of the present disclosure relate to externally detecting a CE1 error condition from a circuit system (e.g., a semiconductor intellectual property core (IP block)) that enables a controller to support serial communication over a serial data bus. This disclosure includes, but is not limited to, the following example embodiments.

Some example embodiments provide a controller comprising: a serial data (SDA) line interface for connecting the controller to an SDA line of a two-wire shared serial data bus, the SDA line interface comprising an output SDA pad buffer; a circuit system for providing output data for transmission to the SDA line via the output SDA pad buffer; and a logic circuit external to the circuit system, the logic circuit being configured to at least: The output data is transmitted onto the SDA line while monitoring the data on the SDA line; when the data monitored on the SDA line is different from the output data, comparing the data monitored on the SDA line with the output data to detect an error condition; and based on the detected error condition, disabling the output SDA pad buffer for a current byte of the output data provided by the circuit system, and subsequently causing a stall condition on the data bus.

Some example embodiments provide a method comprising: providing output data from a circuit system for transmission to a serial data (SDA) line of a two-wire shared serial data bus via an output SDA pad buffer; and monitoring data on the SDA line by a logic circuit external to the circuit system while transmitting the output data to the SDA line. data; comparing the data monitored on the SDA line with the output data to detect an error condition when the data monitored on the SDA line is different from the output data; and based on the detected error condition, disabling the output SDA pad buffer for a current byte of the output data provided by the circuit system, and subsequently causing a stall condition on the data bus.

These and other features, aspects, and advantages of the present disclosure will become apparent upon reading the following embodiments and referring to the accompanying drawings, which are briefly described below. The present disclosure includes any combination of two, three, four, or more features or elements described herein, regardless of whether such features or elements are explicitly combined in the specific example embodiments described herein or otherwise described. The present disclosure is intended to be read as a whole, such that any separable features or elements of the present disclosure in any of its aspects and example embodiments should be considered combinable unless the context of the present disclosure clearly indicates otherwise.

Therefore, it should be understood that this disclosure is provided only for the purpose of summarizing some exemplary embodiments in order to provide a basic understanding of some aspects of the present disclosure. Accordingly, it should be understood that the above exemplary embodiments are merely examples and should not be construed as narrowing the scope or spirit of the present disclosure in any way. Other exemplary embodiments, aspects, and advantages will become apparent from the following embodiments and with reference to the accompanying drawings, which illustrate by way of example the principles of some of the described exemplary embodiments.

Certain embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings, which show some, but not all, embodiments of the present disclosure. In fact, the various embodiments of the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these exemplary embodiments are provided so that this disclosure will be more thorough and complete and will fully convey the scope of the disclosure to those skilled in the art. Like reference numerals refer to like elements throughout.

Unless otherwise specified or clear from the context, references to first, second, or the like should not be construed as implying a particular order. A feature described as being above another feature (unless otherwise specified or clear from the context) may instead be located below, and vice versa; and similarly, a feature described as being to the left of another feature may instead be located to the right, and vice versa. Furthermore, although quantitative measurements, values, geometric relationships, or the like may be mentioned herein, any one or more (if not all) of these may be approximated, unless otherwise specified, to account for acceptable variations that may occur, such as due to engineering tolerances or the like.

As used herein, unless otherwise specified or clear from the context, an "or" of a set of operators is an "inclusive or," and thus is true only if and if one or more of the operators are true, as opposed to an "exclusive or," which is true only if all of the operators are true. Thus, for example, "[A] or [B]" is true if [A] is true, or if [B] is true, or if both [A] and [B] are true. Furthermore, the articles "a" and "an" mean "one or more," unless otherwise specified or clear from the context to be directed to the singular. Furthermore, it should be understood that the terms "data," "content," "digital content," "information," and similar terms are sometimes used interchangeably unless otherwise specified.

Furthermore, while reference may be made herein to terminology specific to a particular system or architecture, it should be understood that the disclosed embodiments are equally applicable to any of a number of systems and architectures. In this regard, some embodiments may be described in the context of serial communication standards for inter-chip communication, such as I3C and its predecessor, I2C. However, it should be understood that the embodiments are equally applicable to other serial communication standards.

Example embodiments of the present disclosure relate generally to serial communications, and more particularly to detecting and recovering from read and write data conflicts on a serial data bus.

FIG1 illustrates a controller 100 according to some example embodiments of the present disclosure. The controller can be an electronic device, such as an integrated circuit (IC). As explained in more detail below, the controller includes a circuit system 102 and a logic circuit 104 external to the circuit system 102. The controller can also include one or more interfaces to connect the controller to a data bus 104, through which the controller can communicate with other electronic devices. In the context of serial communication standards such as I2C and I3C, the data bus can be a two-wire shared serial data bus 104. In this regard, the data bus may include a serial data (SDA) line 104A for transmitting and receiving data between electronic devices connected to the data bus. The controller may include an SDA line interface 106 for connecting a target to the SDA line, and the SDA line interface may include an output SDA pad buffer 108 for driving output data 110 on the SDA line.

FIG2 illustrates a system 200 including a controller 100, according to some exemplary embodiments of the present disclosure. As shown, the system includes several electronic devices 202 (e.g., integrated circuits) connected to a data bus 104. In addition to an SDA line 104A, the data bus may also include an SCL line 204B, which provides a clock signal for synchronizing data transmission between electronic devices 202. Furthermore, in some embodiments, the controller 100 may also include an SCL line interface to connect the controller to the SCL line.

The system 200 can operate according to a controller-target architecture, wherein an electronic device 202 can act as a controller 100 to initiate and control communication (timing and data) on the data bus 104, and another electronic device can act as a target 208 to respond to commands or requests from the controller. In some embodiments, the system can support multiple controllers and targets.

FIG3 illustrates a system 300, which may correspond to the system 200 of FIG2, including multiple controllers and targets, according to some example embodiments. As shown, for example, the system 300 may include a primary controller 100A and one or more secondary controllers 100B, any of which may be the active controller currently controlling the data bus 104. The primary controller 100A may initialize the data bus and perform configuration of the target 208. The primary controller 100A may act as the authorizer of the data bus in its initial state and, once the data bus is configured, become the first active controller. The secondary controller 100B may initially act as a target, but the secondary controller 100B may accept the controller identity from the primary controller 100A and become the new active controller. In the context of I3C, a system may include an I3C master controller 100A and one or more I3C slave controllers 100B.

The system 300 may also include one or more targets 208. The system may also include one or more legacy targets 304, which are from older communication standards with which the system 300 is compatible. Similarly, in the context of I3C, the system may include one or more I3C targets 208, and the system may include one or more I2C targets 304.

Referring back to FIG. 2 , system 200 can support multiple data transfer modes, allowing electronic devices 202 to communicate at different speeds based on their capabilities. Modes can include a single data rate (SDR) mode and several high data rate (HDR) modes, each with increased data transfer rates and corresponding signal integrity requirements. SDR mode can be used, among other things, for performing private messaging from controller 100 to target 208 and entering other modes and states (e.g., HDR mode). In the context of I3C, SDR mode can be used to implement built-in I3C features such as common command code (CCC), in-band interrupt (IBI), and hot join. SDR mode can also be used to transition from I2C to I3C through dynamic address allocation, as well as perform traditional I2C transactions on the data bus 104.

The electronic device 202 can operate in various output modes to drive signals on the data bus 104. Examples of suitable modes include an open-drain mode and a push-pull mode, which define how the electronic device controls the voltage levels on the SDA line 104A and the SCL line 204B. In the open-drain mode, the electronic device can configure its output as an open drain or open collector. In open-drain mode, the electronic device can pull the signal line (SDA or SCL) to a low voltage level (logical 0) by actively sinking current. However, the electronic device 202 does not have an active component to pull the signal line to a high voltage level (logical 1). Instead, a pull-up resistor (which can be external) can be used to pull the line to a high voltage level (logical 1). In push-pull mode, the electronic device can be configured as a push-pull driver at its output. In push-pull mode, the electronic device can actively drive the signal line to a high (logical 1) and a low (logical 0) voltage level.

Figures 4A, 4B, and 4C are timing diagrams of signals on the SDA line 104A and the SCL line 204B for a read/write transaction on the data bus 104, according to some example embodiments. As shown in Figure 4A, a read/write transaction on the data bus can begin with a start condition, which can be asserted by the controller 100 and implemented as a high-to-low transition on the SDA line while the SCL line is held at a constant high by the controller 100. Similarly, a read/write transaction on the data bus can end with a stop condition asserted by the controller. A stop condition can be implemented as a low-to-high transition on the SDA line while a voltage level on the SCL line 204B is high. As an alternative to a stop condition, a restart condition allows multiple messages to be sent in the same frame without having to transmit a stop and start between messages. A restart condition may appear the same as a start condition on the data bus.

Following the start/restart condition, a read/write transaction on the data bus 104 may include an address header that may include a destination address, indicate a read or write transaction, and provide an acknowledgment. The address header may be transmitted on the SDA line 104A during the period when the SCL line 204B transitions from low to high (rising edge) or from high to low (falling edge). FIG4B is a timing diagram of the SDA line and the SCL line for an address header according to some example implementations. In the context of I2C and I3C, the address header may include seven address bits, a read/write (R/W) bit, and an acknowledge (ACK)/non-acknowledge (NACK) bit. In the context of I3C, the R/W bit may be referred to as In some examples, the controller 100 may transmit an address and a R/W bit. The controller 100 may use the address bits to address the target 208, and the controller may use the R/W bit to specify a write mode (the controller 100 writes data to the target 208) or a read mode (the controller 100 reads data from the target 208). In this regard, the controller 100 may transmit a low signal (R/W bit = 0) on the SDA line 104A to indicate write mode, or a high signal (R/W bit = 1) on the SDA line 104A to indicate read mode.

Once the controller 100 transmits the address and R/W bits of the address header on the data bus 104, the controller can wait for the target 208 to acknowledge (or not acknowledge) the request. This can be accomplished using the ACK/NACK bit in the address header. The target can pull the SDA line 104A low (ACK/NACK bit = 0) to respond with an acknowledgment (ACK), or release the SDA line high (ACK/NACK bit = 1) to respond with a negative acknowledgement (NACK).

As shown in FIG4C (in push/pull mode), one or more data words may follow the address header. Similar to the address header, the data words may be transmitted on the SDA line 104A during the period when the SCL line 204B transitions from low to high (rising edge) or from high to low (falling edge). In the context of I3C, a data word may be nine bits wide, consisting of eight bits of data and a ninth transition bit (T bit). When the controller 100 is writing data to the target 208, the T bit of each data word may be a parity bit calculated using odd parity, which helps detect errors caused by noise on the data bus. Conversely, when the controller 100 is reading data back from the target, the T bit of each data word can present an end-of-data bit. In this regard, the target 208 can use the T bit to control the number of data words returned by the target. The T bit also allows the controller 100 to terminate the read early. To end the message, the target 208 can return the T bit as "0". To continue the message, the target can return the T bit as "1" and monitor the SDA line. If the SDA line remains high on the next SCL falling edge, the target can continue to send the next data value. If the SDA line is low (restart) on the next SCL falling edge, the controller 100 has terminated the data transfer and the target 208 does not send the next data.

The electronic device 202 may implement one or more error detection and recovery methods to handle various error conditions during read/write transactions on the data bus 104. In this regard, in the context of I3C, if an error occurs in the R/W bit of the address header when the controller 100 is actually attempting to initiate a write transaction, the target 208 may interpret it as responding to a read transaction. When this occurs, the write data on the data bus from the controller may conflict with the read data from the target. In the MIPI ^I3C® specification published by the Mobile Industry Processor Interface (MIPI) Alliance, this error condition, when detected by a controller, is referred to as error type CE1. As specifically noted, when the controller 100 transmits a write transaction on the SDA line 104A of the data bus 104, the controller 100 should monitor the SDA line 104A of the data bus 104. This allows the controller to detect a CE1 error condition if the monitored data differs from the data the controller is attempting to transmit.

According to the MIPI ^I3C® specification, when the controller 100 detects a CE1 error condition during a private write transaction attempt with the target 208 (i.e., when the target 208 assumes it is responding to a private read transaction while the controller 100 has attempted to perform a private write transaction), the controller 100 may stop the transmission, then assert a stop condition on the SDA line 104A, and retry the transmission. Example embodiments of the present disclosure provide a logic circuit to detect such a CE1 error and take action to prevent conflicting data from being present on the data bus 104 for an extended period of time, thereby reducing power consumption and avoiding potential corruption.

According to some exemplary embodiments of the present disclosure, the controller 100 may operate in a write state to execute a write transaction to transfer output data 110 to the data bus 104. While in the write state, the controller may monitor data 112 on the SDA line 104A, compare the data 112 on the SDA line 104A with the output data 110, and detect an error condition if the data 112 on the SDA line 104A and the output data 110 are not simultaneously transmitted. Furthermore, based on the error condition, the controller may disable the internal output SDA buffer 108 (which drives the output data 110 on the SDA line 104A) until the transfer of the current byte of data 112 on the SDA line 104A is complete. The controller may then assert a stop condition on the SDA line 104A of the data bus 104 .

For example, as shown in FIG1 , circuitry 102 (which provides output data 110 for transmission onto SDA line 104A) transmits data 112 via output SDA pad buffer 108. Logic circuitry 104 may monitor data 112 on SDA line 104A while transmitting output data 110 onto SDA line 104A. When data 112 monitored on SDA line 104A differs from output data 110, logic circuitry 104 may compare data 112 monitored on SDA line 104A with output data 110 to detect an error condition (e.g., a CE1 error condition). Based on the detected error condition, logic circuit 104 may disable output SDA pad buffer 108 for a current byte of output data 110 provided by circuitry 102 and subsequently cause a stall condition on the data bus.

To further illustrate some exemplary embodiments of the present invention, FIG5 is a block diagram of a controller 100 according to some exemplary embodiments. As shown, the controller 100 includes a circuit system 102, such as a semiconductor intellectual property core (IP block), which enables the controller 100 to support serial communication on a data bus 104. In this regard, the circuit system 102 can provide output data 110 (SDA_OUT) for transmission to an SDA line 104A via an output SDA pad buffer 108 of an SDA line interface 106. In some examples, the output SDA pad buffer 108 may be a tri-state buffer, and the circuit system 102 may enable the output SDA pad buffer to drive the output data 110, such as when the controller 100 is in the write state. The circuit system 102 may not provide support for CE1 errors.

In some embodiments, the SDA line interface 106 also includes an input SDA pad buffer 502 to receive the data 112 (SDA_IN) monitored on the SDA line 104A. The input SDA pad buffer can filter noise from the data 112 monitored on the SDA line 104A to produce filtered data. More specifically, for example, the input SDA pad buffer 502 can include a surge filter (sometimes referred to as a spike filter) to filter unwanted noise from the monitored data 112 (e.g., by suppressing extreme changes in the voltage level on SDA). The monitored data can then be filtered data.

As further shown, the logic circuit 104 of the controller 100 may include a state machine 504 and a detector 506 to monitor the data 112 on the SDA line 104A. In this regard, the state machine 504 may receive an indication from the circuit system 102 that the address header on the SDA line 104A has been transmitted. This indication may be transmitted by the circuit system 102 or read from the circuit system 102 by the state machine 504 as part of a debug signal or port of the circuit system 102, and enable the detector 506 to monitor the data 112 on the SDA line 104A for one or more data words following the address header.

Detector 506 may include a logic gate, such as an XOR (exclusive OR) gate 508. The logic gate may perform a bit-by-bit comparison between one or more data words of data 112 monitored on SDA line 104A and one or more data words of output data 110 transmitted by circuitry 102 on line SDA_OUT. Detector 506 may also include one or more sequential logic elements, such as a multiplexer 510 and a D flip-flop 512. When the bit-by-bit comparison indicates that the one or more data words of data 112 monitored on the SDA line 104A are different from the one or more data words of the output data 110, the one or more sequence logic elements may set a flag to indicate that an error condition has been detected.

In some more specific examples, when one or more data words of the data 112 monitored on the SDA line 104A are different from one or more data words of the output data 110, the exclusive OR gate 508 can generate a high gate output (logical 1), and the high gate output of the exclusive OR gate 508 is fed to a first input of the multiplexer 510. Multiplexer 510 (in response to an asserted enable signal (EN) from state machine 504) can pass the output of XOR gate 508 to the D input of D flip-flop 512. D flip-flop 512 can be clocked by a signal (which can be the SCL clock, a synchronous SCL clock, or a faster clock), and D flip-flop can then latch the output of XOR gate 508.

If the one or more data words of data 112 monitored on SDA line 104A are not identical to the one or more data words of output data 110, D flip-flop 512 will therefore latch the high output as a flag (sometimes referred to as a CE1 error flag), which may be represented as a CE1_ERROR signal, to indicate to state machine 504 that a CE1 condition has been encountered. In response to the CE1 error flag being set (i.e., the active CE1_ERROR signal), state machine 504 may deassert the enable signal of multiplexer 510, thereby latching the CE1 error flag (which is fed back to a second input of multiplexer 510). In other embodiments, the multiplexer 510 and the D flip-flop 512 are not required, and the state machine 504 can respond to the CE1 error flag without latching the CE1 error flag. Similarly, when the detector 506 is not used or the controller exits the write state, the state machine 504 can clear the D flip-flop 512, thereby clearing the CE1 error flag.

In some examples, when the CE1 error flag is set, the logic circuit 104 may disable the output SDA pad buffer 108. In some examples where the output SDA pad buffer 108 is a tri-state buffer, the logic circuit 104 may disable the output SDA pad buffer 108 via an enable/disable input (ENB) of the tri-state buffer.

In some examples, the controller 100 includes a 2:1 multiplexer 514, and the logic circuit 104 includes a pad buffer control block 516. The 2:1 multiplexer 514 may include an output line coupled to the enable/disable input of the output SDA pad buffer 108 and a first input line coupled to a respective output of the circuitry 102 to allow the circuitry 102 to enable the output SDA pad buffer when the controller is in a write state or when the circuitry 102 is sending a command or address on the SDA line 104A.

The 2:1 multiplexer 514 may also include a second input line coupled to ground (logical 0) and a select line coupled to the pad buffer control block 516 to allow the pad buffer control block to select one of the first or second input lines of the 2:1 multiplexer 514. The pad buffer control block 516 may select the first input line to allow the circuitry 102 to control the output SDA pad buffer 108, such as to enable the SDA pad buffer 108 in a write state. However, when the state machine 504 detects the CE1 error flag, the state machine 504 can control the pad buffer control block to select the second input line of the 2:1 multiplexer and thereby connect the enable/disable input of the output SDA pad buffer to ground to disable the output SDA pad buffer. Thus, the state machine 504 and the detector 506 can detect the CE1 error condition outside the circuit system 102 and without interrupting the circuit system (e.g., the IP block) and perform operations based on the error condition.

Regardless of the exact manner in which the logic circuit 104 disables the output SDA pad buffer 108, in one example, the logic circuit 104 can subsequently cause a stall condition on the data bus 104, such as to cause a target 208 to terminate the transmission of data 112 monitored on the SDA line 104A. Specifically, the state machine 504 of the logic circuit 104 can cause a stall condition on the data bus to cause the target 208 to terminate the transmission of data 112 monitored on the SDA line 104A.

In some examples, the logic circuit 104 may include a counter block 516 that the state machine 504 may use to count the bit positions of a current data word of the data 112 monitored on the SDA line 104A. The state machine may thereby identify an ACK/NACK bit position of the current data word of the data 112 monitored on the SDA line 104A. Subsequently, upon identifying the ACK/NACK bit position of the current data word of the data 112 monitored on the SDA line 104A, the state machine may cause a stall condition on the data bus. In some examples, the state machine may cause a low-to-high transition in the voltage level on the SDA line 104A while a voltage level on the SCL line 204B is high.

Logic circuitry 104 may cause a stall condition on data bus 104 in any of several different ways. In some examples, logic circuitry 104 may instruct circuitry 102 to assert a stall condition on data bus 104. Specifically, for example, state machine 504 may use a test SCL and SDA test override to cause circuitry 102 to assert a stall condition.

In some examples, the logic circuitry can assert a stall condition on the data bus 104. In some of these examples, the controller 100 includes a second 2:1 multiplexer 518, and the second 2:1 multiplexer 518 can include an input line coupled to the SDA_OUT line of the circuitry 102 and an output line coupled to the output SDA pad buffer 108 to allow the circuitry 102 to provide output data 110 for transmission onto the SDA line 104A via the output SDA pad buffer 108.

The second 2:1 multiplexer 518 may also include a second input line (SDA_OVRD) and a select line (SDA_OVRD_EN) coupled to respective outputs of the pad buffer control block 516. The select line may allow the pad buffer control block 516 to select one of the first or second input lines of the second 2:1 multiplexer 518. The pad buffer control block 516 may select the first input line to allow the circuitry 102 to provide data to the output SDA pad buffer 108, such as driving the data to the SDA pad buffer 108 in a write state. When the CE1 error flag is detected, the state machine 504 may control the pad buffer control block 516 to select the second input line of the second 2:1 multiplexer 518, thereby connecting the second input line of the second 2:1 multiplexer to the output SDA pad buffer 108. The second 2:1 multiplexer 518 may provide an override signal on the second input line of the second 2:1 multiplexer to cause a low-to-high transition of the voltage level on the SDA line 104A while the voltage level on the SCL line 204B is high, thereby asserting a stop condition on the data bus 104.

After, simultaneously with, or immediately before causing the stall condition, the state machine 504 may assert an enable signal to the multiplexer 510, clear the D flip-flop 512, and signal the pad buffer control block 516 to reselect the first input of the 2:1 multiplexer 514 to again allow the circuit system 102 to enable the output SDA pad buffer 108.

6A through 6H are flow charts illustrating steps in a method 600 according to various exemplary embodiments. The method includes providing output data from a circuit system for transmission via an output SDA pad buffer onto a serial data (SDA) line of a two-wire shared serial data bus, as shown in block 602 of FIG. 6A . Subsequently, through a logic circuit external to the circuit system, the method includes monitoring data on the SDA line while transmitting the output data onto the SDA line, as shown in block 604. The method includes comparing the data monitored on the SDA line with the output data to detect an error condition when the data monitored on the SDA line is different from the output data, as shown in block 606. Based on the detected error condition, the method includes disabling the output SDA pad buffer for a current byte of output data provided by the circuitry and subsequently causing a stall condition on the data bus, as shown in blocks 608 and 610.

In some examples, method 600 includes filtering noise from the data on the SDA line to produce filtered data, as shown in block 612 of Figure 6B. In some of these examples, the monitored data is filtered data.

In some examples, in block 604, monitoring the SDA line for data includes receiving an indication that an address header has been transmitted on the SDA line, as shown in block 614 of FIG 6C . In some of these examples, monitoring the SDA line for data also includes monitoring the data on the SDA line for one or more data words following the address header, as shown in block 616.

In some examples, comparing the data monitored on the SDA line with the output data in block 606 includes performing a bit-by-bit comparison of the one or more data words of the data monitored on the SDA line with one or more data words of the output data (i.e., the one or more data words output by circuitry 102), as shown in block 618 of FIG6D . When the bit-by-bit comparison indicates that the one or more data words of the data monitored on the SDA line are different from the one or more data words of the output data, a flag is set to indicate that an error condition has been detected, as shown in block 620. In some of these examples, when the flag is set, the output SDA pad buffer is disabled in block 608 and subsequently a stall condition is caused in block 610.

In some examples, the output SDA pad buffer is a three-state buffer having an enable/disable input, and the output SDA pad buffer is disabled in block 608 via the enable/disable input.

In some examples, at block 610, a stall condition is caused on the data bus to cause a target to terminate the transmission of data monitored on the SDA line.

In some examples, causing the stall condition in block 610 includes counting bit positions of a current data word of data monitored on the SDA line to identify an acknowledge/not acknowledge (ACK/NACK) bit position of the current data word of data monitored on the SDA line, as shown in block 622 of FIG6E . In some of these examples, when the ACK/NACK bit position of the current data word of data monitored on the SDA line is identified, a stall condition on the data bus is caused, as shown in block 624.

In some examples, the data bus includes an SDA line and a serial clock (SCL) line. In some of these examples, in block 610, causing a stop condition on the data bus includes causing a low-to-high transition of a voltage level on the SDA line while a voltage level on the SCL line is high, as shown in block 626 of FIG6F .

In some examples, at block 610 , causing the stall condition on the data bus includes instructing the circuitry, via the logic circuit, to assert the stall condition on the data bus, as shown at block 628 of FIG. 6G .

In some examples, causing the stall condition on the data bus at block 610 includes asserting the stall condition on the data bus by logic circuitry, as shown at block 630 of FIG. 6H .

As stated above and reiterated below, the present disclosure includes, but is not limited to, the following example embodiments.

Item 1. A controller comprising: a serial data (SDA) line interface for connecting the controller to an SDA line of a two-wire shared serial data bus, the SDA line interface comprising an output SDA pad buffer; a circuit system for providing output data for transmission to the SDA line via the output SDA pad buffer; and a logic circuit external to the circuit system, the logic circuit being configured to at least: While output data is transmitted to the SDA line, data on the SDA line is monitored; when the data monitored on the SDA line is different from the output data, the data monitored on the SDA line is compared with the output data to detect an error condition; and based on the detected error condition, the output SDA pad buffer is disabled for a current byte of the output data provided by the circuit system, and a stall condition is subsequently caused on the data bus.

Item 2. The controller of Item 1, wherein the SDA line interface includes an input SDA pad buffer to receive the data monitored on the SDA line, the input SDA pad buffer being configured to filter noise from the data monitored on the SDA line to generate filtered data, and the monitored data being the filtered data.

Item 3. The controller of Item 1 or Item 2, wherein the logic circuit includes a state machine and a detector to monitor the data on the SDA line, the state machine being configured to at least: receive an indication that an address header on the SDA line has been transmitted; and enable the detector to monitor the data on the SDA line for one or more data words following the address header.

Item 4. The controller of any one of Items 1 to 3, wherein the logic circuit includes a detector to compare the data monitored on the SDA line with the output data, the detector comprising: a logic gate for performing a bit-by-bit comparison of one or more data words of the data monitored on the SDA line with one or more data words of the output data; and one or more sequence A sequence logic element is configured to set a flag to indicate that the error condition has been detected when the bit-by-bit comparison indicates that the one or more data words of the data monitored on the SDA line are different from the one or more data words of the output data, and wherein, when the flag is set, the logic circuit is configured to disable the output SDA pad buffer and subsequently cause the stall condition.

Item 5. The controller of any one of Items 1 to 4, wherein the output SDA pad buffer is a three-state buffer having an enable/disable input, and the logic circuit disables the output SDA pad buffer via the enable/disable input.

Clause 6. The controller of any one of clauses 1 to 5, wherein the logic circuit is configured to cause the stall condition on the data bus to cause a target to terminate the transmission of the data on the SDA line.

Clause 7. The controller of any one of Clauses 1 to 6, wherein the logic circuitry is configured to cause the stall condition to include the logic circuitry to: count bit positions of a current data word of the data monitored on the SDA line to identify an acknowledge/not acknowledge (ACK/NACK) bit position of the current data word of the data monitored on the SDA line; and cause the stall condition on the data bus when the ACK/NACK bit position of the current data word of the data monitored on the SDA line is identified.

Clause 8. The controller of any one of clauses 1 to 7, wherein the data bus includes the SDA line and a serial clock (SCL) line; and wherein the logic circuitry for causing the stop condition on the data bus comprises: the logic circuitry for causing a low-to-high transition of a voltage level on the SDA line while a voltage level on the SCL line is high.

Clause 9. The controller of any one of clauses 1 to 8, wherein the logic circuitry for causing the stall condition on the data bus comprises: the logic circuitry for instructing the circuitry to assert the stall condition on the data bus.

Clause 10. The controller of any one of Clauses 1 to 9, wherein the logic circuitry for causing the stall condition on the data bus comprises: the logic circuitry for asserting the stall condition on the data bus.

Item 11. A method comprising: providing output data from a circuit system for transmission to a serial data (SDA) line of a two-wire shared serial data bus via an output SDA pad buffer; and monitoring data on the SDA line by a logic circuit external to the circuit system while transmitting the output data to the SDA line; When the data monitored on the SDA line is different from the output data, the data monitored on the SDA line is compared with the output data to detect an error condition; and based on the detected error condition, the output SDA pad buffer is disabled for a current byte of the output data provided by the circuit system, and a stall condition is subsequently caused on the data bus.

Clause 12. The method of clause 11, comprising filtering noise from the data on the SDA line to produce filtered data, and wherein the monitored data is the filtered data.

Clause 13. The method of clause 11 or clause 12, wherein monitoring the data on the SDA line comprises: receiving an indication that an address header on the SDA line has been transmitted; and monitoring the data on the SDA line for one or more data words following the address header.

Clause 14. The method of any one of Clauses 11 to 13, wherein comparing the data monitored on the SDA line with the output data comprises: performing a bit-by-bit comparison of one or more data words of the data monitored on the SDA line with one or more data words of the output data; and setting a flag to indicate that the error condition has been detected when the bit-by-bit comparison indicates that the one or more data words of the data monitored on the SDA line are different from the one or more data words of the output data, and wherein when the flag is set, disabling the output SDA pad buffer and subsequently causing the stall condition.

Clause 15. The method of any one of Clauses 11 to 14, wherein the output SDA pad buffer is a three-state buffer having an enable/disable input, the output SDA pad buffer being disabled via the enable/disable input.

Clause 16. The method of any one of clauses 11 to 15, wherein causing the stall condition on the data bus is used to cause a target to terminate transmission of the data monitored on the SDA line.

Clause 17. The method of any one of Clauses 11 to 16, wherein causing the stall condition comprises: counting bit positions of a current data word of the data monitored on the SDA line to identify an acknowledgement/non-acknowledgement (ACK/NACK) bit position of the current data word of the data monitored on the SDA line; and causing the stall condition on the data bus when the ACK/NACK bit position of the current data word of the data monitored on the SDA line is identified.

Clause 18. The method of any one of Clauses 11 to 17, wherein the data bus includes the SDA line and a serial clock (SCL) line, and wherein causing the stop condition on the data bus comprises: causing a low-to-high transition of a voltage level on the SDA line while a voltage level on the SCL line is high.

Clause 19. The method of any one of Clauses 11 to 18, wherein causing the stall condition on the data bus comprises: instructing the circuit system, by the logic circuit, to establish the stall condition on the data bus.

Clause 20. The method of any one of Clauses 11 to 19, wherein causing the stall condition on the data bus comprises: establishing the stall condition on the data bus by the logic circuit.

Numerous modifications and other embodiments of the present disclosure set forth herein will come to mind to one skilled in the art having the benefit of the teachings presented in the foregoing description and the associated drawings. It should be understood, therefore, that the present disclosure is not limited to the specific embodiments disclosed, and that modifications and other embodiments are intended to be included within the scope of the appended claims. Furthermore, while the foregoing description and the associated drawings describe example embodiments in the context of certain example combinations of elements and/or functions, it should be understood that different combinations of elements and/or functions may be provided through alternative embodiments without departing from the scope of the present invention. In this regard, for example, combinations of elements and/or functions other than those explicitly described above are also contemplated, as may be set forth in some of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

100: Controller 100A: Primary Controller 100B: Secondary Controller 102: Circuit System 104: Data Bus; Logic Circuit 104A: Serial Data (SDA) Line 106: SDA Line Interface 108: Output SDA Pad Buffer 110: Output Data 112: Data 200: System 202: Electronic Device 204B: SCL Line 208: Target 300: System 304: Traditional Target; I2C Target 502: Input SDA Pad Buffer 504: State Machine 506: Detector 508: Exclusive OR Gate; XOR Gate 510: Multiplexer 512: D-type flip-flop 514: Multiplexer 516: Pad buffer control block 518: Multiplexer 600: Method 602: Block 604: Block 606: Block 608: Block 610: Block 612: Block 614: Block 616: Block 618: Block 620: Block 622: Block 624: Block 626: Block 628: Block 630: Block

Having thus generally described example embodiments of the present disclosure, reference is now made to the accompanying drawings, which are not necessarily drawn to scale, and in which: [FIG. 1] illustrates a controller according to some example embodiments of the present disclosure; [FIG. 2] illustrates a system including the controller of FIG. 1 according to some example embodiments; [FIG. 3] illustrates a system, which may correspond to the system of FIG. 2 , including multiple controllers and targets according to some example embodiments; [FIG. 4A], [FIG. 4B], and [FIG. 4C] are timing diagrams of signals on lines of a data bus of the system of FIG. 2 or FIG. 3 according to some example embodiments, for a transaction on the data bus, including specifying start, stop, and restart conditions (FIG. 4A), an address header (FIG. 4B), and a data word (FIG. 4C); FIG5 is a functional block diagram of a controller of FIG1 according to some example embodiments; and FIG6A, FIG6B, FIG6C, FIG6D, FIG6E, FIG6F, FIG6G, and FIG6H are flow charts illustrating steps in a method according to various example embodiments.

100: Controller

102: Circuit System

104: Data bus; logic circuit

104A: Serial data (SDA) line

106: SDA line interface

108: Output SDA pad buffer

110: Output data

112: Data

Claims (20)

A controller includes: a serial data (SDA) line interface for connecting the controller to an SDA line of a two-line shared serial data bus, the SDA line interface including an output SDA pad buffer; a circuit system for providing output data for transmission to the SDA line via the output SDA pad buffer; and a logic circuit located outside the circuit system, the logic circuit being configured to at least: transmit the output data to the SDA line; line, monitoring data on the SDA line; when the data monitored on the SDA line is different from the output data, comparing the data monitored on the SDA line with the output data to detect an error condition; and based on the detected error condition, disabling the output SDA pad buffer for a current byte of the output data provided by the circuit system, and subsequently causing a stall condition on the data bus. A controller as claimed in claim 1, wherein the SDA line interface includes an input SDA pad buffer to receive the data monitored on the SDA line, the input SDA pad buffer is used to filter noise in the data monitored on the SDA line to generate filtered data, and the monitored data is the filtered data. A controller as in claim 1, wherein the logic circuit includes a state machine and a detector to monitor the data on the SDA line, the state machine being configured to at least: receive an indication that an address header on the SDA line has been transmitted; and enable the detector to monitor the data on the SDA line for one or more data words following the address header. The controller of claim 1, wherein the logic circuit includes a detector to compare the data monitored on the SDA line with the output data, the detector including: a logic gate for performing a bit-by-bit comparison of one or more data words of the data monitored on the SDA line with one or more data words of the output data; and one or more sequence logic elements A device is provided for setting a flag to indicate that the error condition has been detected when the bit-by-bit comparison indicates that the one or more data words of the data monitored on the SDA line are different from the one or more data words of the output data, and wherein, when the flag is set, the logic circuit is configured to disable the output SDA pad buffer and subsequently cause the stall condition. The controller of claim 1, wherein the output SDA pad buffer is a tri-state buffer having an enable/disable input, and the logic circuit disables the output SDA pad buffer via the enable/disable input. The controller of claim 1, wherein the logic circuit is configured to cause the stall condition on the data bus to cause a target to terminate the transmission of the data on the SDA line. The controller of claim 1, wherein the logic circuit is configured to cause the stall condition to include the logic circuitry to: count bit positions of a current data word of the data monitored on the SDA line to identify an acknowledge/non-acknowledge (ACK/NACK) bit position of the current data word of the data monitored on the SDA line; and cause the stall condition on the data bus when the ACK/NACK bit position of the current data word of the data monitored on the SDA line is identified. The controller of claim 1, wherein the data bus includes the SDA line and a serial clock (SCL) line; and wherein the logic circuit for causing the stop condition on the data bus comprises: the logic circuit for causing a low-to-high transition of a voltage level on the SDA line while a voltage level on the SCL line is high. The controller of claim 1, wherein the logic circuit is configured to cause the stall condition on the data bus, comprising: the logic circuit is configured to instruct the circuit system to establish the stall condition on the data bus. The controller of claim 1, wherein the logic circuit is configured to cause the stall condition on the data bus, comprising: the logic circuit is configured to establish the stall condition on the data bus. A method for detecting an error condition on a serial data bus includes: providing output data from a circuit system for transmission to a serial data (SDA) line of a two-wire shared serial data bus through an output SDA pad buffer; and monitoring the SDA line while transmitting the output data to the SDA line by a logic circuit external to the circuit system. data on the SDA line; comparing the data monitored on the SDA line with the output data to detect an error condition when the data monitored on the SDA line is different from the output data; and based on the detected error condition, disabling the output SDA pad buffer for a current byte of the output data provided by the circuit system, and subsequently causing a stall condition on the data bus. The method of claim 11, comprising filtering noise from the data on the SDA line to produce filtered data, and wherein the monitored data is the filtered data. The method of claim 11, wherein monitoring the data on the SDA line comprises: receiving an indication that an address header has been transmitted on the SDA line; and monitoring the data on the SDA line for one or more data words following the address header. The method of claim 11, wherein comparing the data monitored on the SDA line with the output data comprises: performing a bit-by-bit comparison of one or more data words of the data monitored on the SDA line with one or more data words of the output data; and setting a flag to indicate that the error condition has been detected when the bit-by-bit comparison indicates that the one or more data words of the data monitored on the SDA line are different from the one or more data words of the output data, and wherein when the flag is set, disabling the output SDA pad buffer and subsequently causing the stop condition. The method of claim 11, wherein the output SDA pad buffer is a tri-state buffer having an enable/disable input, the output SDA pad buffer being disabled via the enable/disable input. The method of claim 11, wherein causing the stall condition on the data bus is used to cause a target to terminate transmission of the data monitored on the SDA line. The method of claim 11, wherein causing the stall condition comprises: counting the bit positions of a current data word of the data monitored on the SDA line to identify an acknowledgement/non-acknowledgement (ACK/NACK) bit position of the current data word of the data monitored on the SDA line; and causing the stall condition on the data bus when the ACK/NACK bit position of the current data word of the data monitored on the SDA line is identified. The method of claim 11, wherein the data bus includes the SDA line and a serial clock (SCL) line, and wherein causing the stop condition on the data bus comprises: causing a low-to-high transition of a voltage level on the SDA line while a voltage level on the SCL line is high. The method of claim 11, wherein causing the stall condition on the data bus comprises: instructing the circuit system to establish the stall condition on the data bus via the logic circuit. The method of claim 11, wherein causing the stall condition on the data bus comprises: establishing the stall condition on the data bus by the logic circuit.