TWI839966B - Probe card - Google Patents

Abstract

A probe card includes a substrate and a membrane circuit structure. The substrate has rigidity. The membrane circuit structure is at least partially connected to the substrate surface. The membrane circuit structure includes a membrane circuit portion and a first conductive bump. The membrane circuit portion includes a dielectric layer and a pad structure. The pad structure is at least partially within the dielectric layer. The first conductive bump is located on the pad structure. An orthographic projection of the first conductive bump on the dielectric layer overlaps a orthographic projection of the pad structure on the dielectric layer.

Description

Probe Card

The present invention relates to a probe card.

Generally speaking, the reliability of a probe card is often closely related to the thin-film circuit structure. Furthermore, when the probe gripping force in the thin-film circuit structure is low, problems such as probe loosening or breaking are likely to occur, which will reduce the reliability of the probe card. Therefore, how to effectively improve the probe gripping force is a challenge.

The present invention provides a probe card that can effectively improve the probe's grip and enhance its reliability.

A probe card of the present invention includes a substrate and a thin film circuit structure. The substrate has rigidity. The thin film circuit structure is at least partially connected to the surface of the substrate. The thin film circuit structure includes a thin film circuit portion and a first conductive bump. The thin film circuit portion includes a dielectric layer and a pad structure. The pad structure is at least partially located in the dielectric layer. The first conductive bump is located on the pad structure. The orthographic projection of the first conductive bump on the dielectric layer overlaps with the orthographic projection of the pad structure on the dielectric layer.

In one embodiment of the present invention, the above-mentioned substrate is a substrate having a first circuit wiring, and the first circuit wiring is located in the substrate dielectric layer.

In one embodiment of the present invention, the thin film circuit portion includes a base layer located between the pad structure and the substrate, the base layer has a base dielectric layer and a second circuit wiring located in the base dielectric layer, the first circuit wiring is in direct contact with the second circuit wiring, and the substrate dielectric layer is in direct contact with the base dielectric layer.

In one embodiment of the present invention, the above-mentioned substrate is a substrate that does not have conductive properties.

In one embodiment of the present invention, the size of the thin film circuit portion is equal to the size of the substrate.

In one embodiment of the present invention, the size of the thin film circuit portion is larger than the size of the substrate.

In one embodiment of the present invention, the thin film circuit portion includes a central region overlapping with the substrate in the orthographic projection direction and edge regions on both sides of the central region, and the first conductive bump is disposed in the central region, and the thin film circuit structure further includes a second conductive bump disposed in the edge region.

In one embodiment of the present invention, the size of the thin film circuit portion is smaller than the size of the substrate.

In one embodiment of the present invention, the above-mentioned thin film circuit structure further includes a second conductive bump, and the second conductive bump is arranged on the substrate on both sides of the thin film circuit part.

In one embodiment of the present invention, the probe card further includes a third conductive bump disposed on the second surface of the substrate.

Based on the above, the probe card of the present invention can stabilize the probe, increase the firmness and maintain the probe bearing capacity by designing a pad structure that is disposed in the dielectric layer and overlaps with the conductive bump (probe) in the top view direction, so as to reduce the loosening or breakage of the probe. In this way, the probe gripping force can be effectively improved, thereby enhancing its reliability.

In order to make the above features and advantages of the present invention more clearly understood, the following is a detailed description of the embodiments with the accompanying drawings.

10, 10A, 10B, 10C, 10D, 10E, 20, 20A, 20B, 20C, 20D, 20E, 30, 30A, 30B, 30C, 30D, 30E: Thin film circuit structure

100, 100A, 100B, 100C, 100D, 100E, 200, 200A, 200B, 200C, 200D, 200E, 300, 300A, 300B, 300C, 300D, 300E, MP, MP1, MP2: Probe Card

110: Substrate

110d: substrate dielectric layer

110e, 120e: Circuit wiring

111: First surface

112: Second surface

120: Basal layer

120d: Base dielectric layer

130, 130C, 230, 230C, 330, 330C: Gasket structure

130w, 131w, 132w, 160w, 232w, 332w: Width

131, 132, 133, 134, 232, 234, 332, 333: Conductive part

140, 140D, 240, 240D, 340, 340D: Multi-layer dielectric structure

141, 142, 143, 241, 242, 243, 341, 342, 343: Dielectric layer

141a, 341a, 342a: Opening

151, 152, 251, 252, 351, 352: Seed layer

160, 260, 360: Conductive bumps

170, 270: Conductive layer

160t, 170t: Top surface

160s, 170s: Sidewall

B: Marginal area

C: Central area

MC, MC1, MC2: Thin film circuit part

PR1, PR2, PR3, PR4: patterned photoresist

Figures 1A to 1E are partial cross-sectional schematic diagrams of a partial manufacturing method of a probe card according to some embodiments of the present invention.

FIG1F is a partial cross-sectional schematic diagram of the thin film circuit structure separated from FIG1E.

Figures 2A and 2B are partial cross-sectional schematic diagrams of a partial manufacturing method of a probe card according to some embodiments of the present invention.

FIG2C is a partial cross-sectional schematic diagram of the thin film circuit structure separated from FIG2B.

FIG3A is a partial cross-sectional schematic diagram of a probe card according to some embodiments of the present invention.

FIG3B is a partial cross-sectional schematic diagram of the thin film circuit structure separated from FIG3A.

Figures 4A to 4C are partial cross-sectional schematic diagrams of a partial manufacturing method of a probe card according to some embodiments of the present invention.

FIG4D is a partial cross-sectional schematic diagram of the thin film circuit structure separated from FIG4C.

FIG. 4E is a schematic cross-sectional view of FIG. 4C in some embodiments.

Figure 4F and Figure 4G are cross-sectional schematic diagrams in some alternative embodiments.

FIG5A is a partial cross-sectional schematic diagram of a probe card according to some embodiments of the present invention.

FIG5B is a partial cross-sectional schematic diagram of the thin film circuit structure separated from FIG5A.

FIG6A is a partial cross-sectional schematic diagram of a probe card according to some embodiments of the present invention.

FIG6B is a partial cross-sectional schematic diagram of the thin film circuit structure separated from FIG6A.

Figures 7A to 7E are partial cross-sectional schematic diagrams of a partial manufacturing method of a probe card according to some embodiments of the present invention.

Figure 7F is a partial cross-sectional schematic diagram of the thin film circuit structure separated from Figure 7E.

FIG8A is a partial cross-sectional schematic diagram of a probe card according to some embodiments of the present invention.

FIG8B is a partial cross-sectional schematic diagram of the thin film circuit structure separated from FIG8A.

FIG9A is a partial cross-sectional schematic diagram of a probe card according to some embodiments of the present invention.

FIG9B is a partial cross-sectional schematic diagram of the thin film circuit structure separated from FIG9A.

Figures 10A to 10C are partial cross-sectional schematic diagrams of a partial manufacturing method of a probe card according to some embodiments of the present invention.

FIG10D is a partial cross-sectional schematic diagram of the thin film circuit structure separated from FIG10C.

FIG. 11A is a partial cross-sectional schematic diagram of a probe card according to some embodiments of the present invention.

FIG11B is a partial cross-sectional schematic diagram of the thin film circuit structure separated from FIG11A.

FIG. 12A is a partial cross-sectional schematic diagram of a probe card according to some embodiments of the present invention.

FIG12B is a partial cross-sectional schematic diagram of the thin film circuit structure separated from FIG12A.

Figures 13A to 13E are partial cross-sectional schematic diagrams of a partial manufacturing method of a probe card according to some embodiments of the present invention.

FIG13F is a partial cross-sectional schematic diagram of the thin film circuit structure separated from FIG13E.

FIG. 14A is a partial cross-sectional schematic diagram of a probe card according to some embodiments of the present invention.

FIG14B is a partial cross-sectional schematic diagram of the thin film circuit structure separated from FIG14A.

FIG. 15A is a partial cross-sectional schematic diagram of a probe card according to some embodiments of the present invention.

FIG15B is a partial cross-sectional schematic diagram of the thin film circuit structure separated from FIG15A.

Figures 16A to 16C are partial cross-sectional schematic diagrams of a partial manufacturing method of a probe card according to some embodiments of the present invention.

FIG16D is a partial cross-sectional schematic diagram of the thin film circuit structure separated from FIG16C.

FIG. 17A is a partial cross-sectional schematic diagram of a probe card according to some embodiments of the present invention.

FIG17B is a partial cross-sectional schematic diagram of the thin film circuit structure separated from FIG17A.

FIG. 18A is a partial cross-sectional schematic diagram of a probe card according to some embodiments of the present invention.

FIG18B is a partial cross-sectional schematic diagram of the thin film circuit structure separated from FIG18A.

Figures 19A to 19B are schematic diagrams of the corresponding configuration of the thin film circuit structure and the substrate of the probe card according to some embodiments of the present invention.

Figures 20A and 20B are schematic diagrams of the corresponding configuration of the thin film circuit structure and the substrate of the probe card according to some embodiments of the present invention.

Figures 21A to 21D are schematic diagrams of the corresponding configuration of the thin film circuit structure and the substrate of the probe card according to some embodiments of the present invention.

Directional terms used herein (e.g., up, down, right, left, front, back, top, bottom) are used only as a reference to the drawings and are not intended to imply an absolute orientation. Unless otherwise expressly stated, any method described herein is in no way intended to be interpreted as requiring its steps to be performed in a particular order. The present invention is more fully described with reference to the drawings of the present embodiment. However, the present invention may also be embodied in a variety of different forms and should not be limited to the embodiments described herein. The thickness, size or size of layers or regions in the drawings are exaggerated for clarity. The same or similar reference numbers represent the same or similar elements, and the following paragraphs will not be repeated one by one.

Figures 1A to 1E are partial cross-sectional schematic diagrams of a partial manufacturing method of a probe card according to some embodiments of the present invention. Figure 1F is a partial cross-sectional schematic diagram of a thin film circuit structure separated from Figure 1E.

Please refer to FIG. 1A. In this embodiment, the manufacturing process of the probe card may include the following steps. First, a substrate 110 having a first surface 111 and a second surface 112 relative to each other is provided, and a base layer 120 is formed on the first surface 111. In some embodiments, the substrate 110 may have a supporting function, and may be, for example, a glass substrate, a sapphire substrate, a ceramic substrate, a silicon carbide substrate, a silicon substrate that does not have conductive properties, or, for example, a multilayer ceramic (MLC) substrate with circuit wiring, wherein the aforementioned substrate 110 may also have excellent properties such as flatness, rigidity, and thermal conductivity at the same time, but the present invention is not limited thereto. In addition, the base layer 120 may be formed by a conductive line and a dielectric material, wherein the conductive line and the dielectric layer may be suitable conductive and dielectric materials selected according to actual design requirements.

Next, a conductive portion 131 may be formed on the base layer 120, wherein the material of the conductive portion 131 is, for example, metal (such as copper, aluminum, nickel, gold, silver, tin) or other suitable conductive materials. Then, a dielectric layer 141 may be formed on the first surface 111 of the substrate 110, wherein the dielectric layer 141 may surround the conductive portion 131 and may cover the top surface 131t of the conductive portion 131 for preparing subsequent components, but the present invention is not limited thereto. In addition, in the present embodiment, the material of the dielectric layer 141 may be a thermosetting material, such as polyimide (PI), benzocyclobutene (BCB) or other suitable thermosetting materials.

Referring to FIG. 1B , an opening 141a is formed in the dielectric layer 141 to expose a portion of the conductive portion 131 below. In some embodiments, the opening 141a can be formed by a laser drill process, and in cross-sectional view, the opening 141a can be trapezoidal, that is, the size of the opening 141a (e.g., the diameter of the hole) gradually decreases toward the base layer 120, but the present invention is not limited thereto, and the opening 141a can also use other suitable removal processes and form other shapes. Then, a patterned photoresist PR1 with an opening can be formed on the dielectric layer 141, wherein the patterning process is, for example, a litho process. Here, the photoresist can be a positive photoresist or a negative photoresist.

Referring to FIG. 1C , a metal evaporation process is performed to form a conductive portion 132 in the opening of the patterned photoresist PR1, wherein the material of the conductive portion 132 is, for example, metal (such as copper, aluminum, nickel, gold, silver, tin) or other suitable conductive materials. Then, the patterned photoresist PR1 can be removed by a suitable method, and a seed layer 151 can be formed on the substrate 110 in an all-round manner. Here, the all-round formation, for example, the seed layer 151 can be conformally formed on the substrate 110.

Furthermore, the conductive portion 131 and the conductive portion 132 can be regarded as the pad structure 130, so the pad structure 130 can include the conductive portion 131 and the conductive portion 132 stacked on each other, and the conductive portion 131 and the conductive portion 132 are stacked from the inside to the outside of the dielectric layer 141, that is, the pad structure 130 can be at least partially buried in the dielectric layer 141.

In this embodiment, the number of the conductive portion 131 and the number of the conductive portion 132 are both one, the conductive portion 131 is a column (circular column or square column), and the conductive portion 132 is a disc. In addition, the maximum width 132w of the conductive portion 132 may be different from the maximum width 131w of the conductive portion 131. As shown in FIG. 1C, the maximum width 132w of the conductive portion 132 may be greater than the maximum width 131w of the conductive portion 131, but the present invention is not limited thereto. In other embodiments, the number, shape, and width of the conductive portion may be adjusted according to actual design requirements.

Referring to FIG. 1D , another patterned photoresist (not shown) is formed on the substrate 110, and a metal plating process is performed on the patterned photoresist to form a conductive bump 160 (which can be regarded as a probe). Then, the patterned photoresist and the portion of the seed layer 151 not covered by the conductive bump 160 are removed, so that another portion of the seed layer 151 that is not removed is disposed under the conductive bump 160.

Referring to FIG. 1E , an electroless plating process is performed on the conductive bump 160 to form a conductive layer 170 covering the conductive bump 160 , wherein the material of the conductive layer 170 is, for example, nickel, cobalt, palladium, platinum, gold, tungsten, rhodium, ruthenium or an alloy thereof. After the above-mentioned manufacturing, the probe card 100 of FIG. 1E has been substantially completed. Here, the structure on the first surface 111 of the substrate 110 can be regarded as a thin film circuit structure 10.

Optionally, for actual commercial needs, the thin film circuit structure 10 can be further separated from the substrate 110 by an appropriate method (such as peeling) so that the thin film circuit structure 10 can form a terminal product, as shown in FIG. 1F, wherein the thin film circuit structure 10 may include a base layer 120, a pad structure 130, a dielectric layer 141, a seed layer 151, a conductive bump 160, and a conductive layer 170.

It should be noted that in this embodiment, the dielectric layer is a single-layer structure (dielectric layer 141), but the present invention is not limited thereto. In other embodiments, the dielectric layer may be a multi-layer structure.

In this embodiment, the thin film circuit structure 10 includes a dielectric layer 141, a pad structure 130, and a conductive bump 160, wherein the pad structure 130 is at least partially located in the first dielectric layer 141, the conductive bump 160 is located on the pad structure 130, and the orthographic projection of the conductive bump 160 on the dielectric layer 141 overlaps with the orthographic projection of the pad structure 130 on the dielectric layer 141. , accordingly, the thin film circuit structure 10 of this embodiment can stabilize the probe, increase the firmness and maintain the probe bearing capacity by designing the pad structure 130 disposed in the dielectric layer 141 and overlapping with the conductive bump 160 (probe) in the top view direction, so as to reduce the loosening or breaking of the probe, thereby effectively improving the probe gripping force and thus improving the reliability of the probe card 100.

In some embodiments, as the semiconductor process continues to shrink, the probes in the thin film circuit structure will inevitably tend to be miniaturized. Therefore, when the probe diameter is miniaturized, the effect of improving the probe gripping force through the design of the pad structure 130 will be more significant, so it will be more competitive in the market of miniaturized probe cards, but the present invention is not limited to this.

In some embodiments, as shown in FIG. 1D , the top width 130w of the pad structure 130 is greater than the maximum width 160w of the probe 160 , so that the pad structure 130 can be ensured to fully support the conductive bump 160 , so as to achieve a better effect of enhancing the probe gripping force , but the present invention is not limited thereto.

It must be noted here that the following embodiments use the component numbers and some contents of the above embodiments, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same or similar technical contents is omitted. For the description of the omitted parts, please refer to the above embodiments, and the following embodiments will not be repeated.

Figures 2A and 2B are partial cross-sectional schematic diagrams of a partial manufacturing method of a probe card according to some embodiments of the present invention. Figure 2C is a partial cross-sectional schematic diagram of a thin film circuit structure separated from Figure 2B.

Please refer to FIG. 2A , and then to FIG. 1E , a dielectric layer 142 is formed on the entire structure of FIG. 1E , wherein the dielectric layer 142 can cover the top surface 170t and the sidewall 170s of the conductive layer 170 .

Please refer to FIG. 2B , then, the dielectric layer 142 is etched to shrink the dielectric layer 142 toward the dielectric layer 141, so that the shrunken dielectric layer 142 exposes the top surface 170t of the conductive layer 170 and covers part of the side wall 170s of the conductive layer 170, so as to complete the probe card 100A of FIG. 2B . Here, the structure on the first surface 111 of the substrate 110 can be regarded as a thin film circuit structure 10A, and the dielectric layer 141 and the dielectric layer 142 can constitute a multi-layer dielectric structure 140.

Optionally, for actual commercial needs, the thin film circuit structure 10A can be further separated from the substrate 110 by an appropriate method (such as peeling) so that the thin film circuit structure 10A can form a terminal product, as shown in FIG. 2C , wherein the thin film circuit structure 10A can include a base layer 120, a pad structure 130, a multi-layer dielectric structure 140, a seed layer 151, a conductive bump 160, and a conductive layer 170.

FIG3A is a partial cross-sectional schematic diagram of a probe card according to some embodiments of the present invention. FIG3B is a partial cross-sectional schematic diagram of a thin film circuit structure separated from FIG3A.

Please refer to FIG. 3A, and continue with FIG. 1D. Similar to the process from FIG. 2A to FIG. 2B, a dielectric layer 142 is formed on the structure of FIG. 1D, and then an etching process is performed on the dielectric layer 142. Then, a conductive layer 270 is formed on the top surface 160t and the side wall 160s of the exposed conductive bump 160, so that the conductive layer 270 can cover the top surface 160t and the side wall 160s of the conductive bump 160 to complete the probe card 100B of FIG. 3A. Here, the structure on the first surface 111 of the substrate 110 can be regarded as a thin film circuit structure 10B, and the dielectric layer 141 and the dielectric layer 142 can constitute a multi-layer dielectric structure 140.

Optionally, for actual commercial needs, the thin film circuit structure 10B can be further separated from the substrate 110 by an appropriate method (such as peeling) so that the thin film circuit structure 10B can form a terminal product, as shown in FIG. 3B , wherein the thin film circuit structure 10B can include a base layer 120, a pad structure 130, a multi-layer dielectric structure 140, a seed layer 151, a conductive bump 160, and a conductive layer 270.

Figures 4A to 4C are partial cross-sectional schematic diagrams of a partial manufacturing method of a probe card according to some embodiments of the present invention. Figure 4D is a partial cross-sectional schematic diagram of a thin film circuit structure separated from Figure 4C. Figure 4E is a cross-sectional schematic diagram of Figure 4C in some embodiments. Figures 4F and 4G are cross-sectional schematic diagrams in some alternative embodiments.

Referring to FIG. 4A , following FIG. 1C , a patterned photoresist (not shown) is formed on the structure of FIG. 1C , and a metal plating process is performed on the patterned photoresist to form a conductive portion 133 . Then, the patterned photoresist and the portion of the seed layer 151 not covered by the conductive portion 133 are removed, so that another portion of the seed layer 151 that is not removed is disposed below the conductive portion 133 .

Referring to FIG. 4B , similar to the process of FIG. 1A to FIG. 1E , a dielectric layer 142 is formed on the substrate 110 in its entirety, and then an opening is formed in the dielectric layer 142 to expose a portion of the conductive portion 133 below, and then a metal evaporation process is performed using a patterned photoresist (not shown) to form a conductive portion 134. Next, a seed layer 152 is formed on the substrate 110 in its entirety, and then a metal electroplating process is performed using a patterned photoresist having an opening to form a conductive bump 160 (which can be regarded as a probe). Then, the patterned photoresist and the portion of the seed layer 152 not covered by the conductive bump 160 are removed, so that another portion of the seed layer 152 that is not removed is disposed below the conductive bump 160.

Referring to FIG. 4C , an electroless plating process is performed on the conductive bump 160 to form a conductive layer 170 covering the conductive bump 160 to complete the probe card 100C of FIG. 4C . Here, the structure on the first surface 111 of the substrate 110 can be regarded as a thin film circuit structure 10C, the conductive portion 131, the conductive portion 132, the conductive portion 133, and the conductive portion 134 constitute a pad structure 130C, and the dielectric layer 141 and the dielectric layer 142 can constitute a multi-layer dielectric structure 140.

Optionally, for actual commercial needs, the thin film circuit structure 10C can be further separated from the substrate 110 by an appropriate method (such as peeling) so that the thin film circuit structure 10C can form a terminal product, as shown in FIG. 4D , wherein the thin film circuit structure 10C can include a base layer 120, a pad structure 130C, a multi-layer dielectric structure 140, a seed layer 151, a seed layer 152, a conductive bump 160, and a conductive layer 170.

In some embodiments, as shown in FIG. 4E , the substrate 110 is a substrate having a circuit wiring 110e, and the circuit wiring 110e is located in the substrate dielectric layer 110d. In addition, the base layer 120 located between the pad structure 130C and the substrate 110 has a base dielectric layer 120d and a circuit wiring 120e located in the base dielectric layer 120d, wherein the circuit wiring 110e is in direct contact with the circuit wiring 120e (forming a conductive area for electrical connection, wherein the circuit wiring 110e and the circuit wiring 120e can be bonded by direct high temperature bonding or solder ball reflow), and the substrate dielectric layer 110d is in direct contact with the base dielectric layer 120d (forming a non-conductive area without electrical connection).

Furthermore, in the embodiment of Figure 4E, since the size of the substrate 110 is equal to the size of the base layer 120, the direct contact pattern between the substrate dielectric layer 110d and the base dielectric layer 120d is full direct contact, but the present invention is not limited to this. In other alternative embodiments, as shown in Figure 4F, the size of the substrate 110 is smaller than the size of the base layer 120, and therefore the direct contact pattern between the substrate dielectric layer 110d and the base dielectric layer 120d is partial direct contact. In addition, in some alternative embodiments, as shown in FIG. 4G , the circuit wiring 120e of the base layer 120 may extend beyond the edge of the underlying substrate 110, that is, the edge portion of the circuit wiring 120e of the base layer 120 does not overlap with the substrate 110 in the top view direction, but the present invention is not limited thereto.

It should be noted that the connection method between the substrate and the base layer described in FIG. 4E and FIG. 4F can be applied to any embodiment described in the present invention, such as FIG. 1E or other similar embodiments.

FIG5A is a partial cross-sectional schematic diagram of a probe card according to some embodiments of the present invention. FIG5B is a partial cross-sectional schematic diagram of a thin film circuit structure separated from FIG5A.

Please refer to FIG. 5A, and then FIG. 4C, similar to the process from FIG. 2A to FIG. 2B, a dielectric layer 143 is formed on the structure of FIG. 4C, and then the dielectric layer 143 is etched so that the reduced dielectric layer 143 exposes the top surface 170t of the conductive layer 170 and covers part of the side wall 170s of the conductive layer 170, so as to complete the probe card 100D of FIG. 5A. Here, the structure on the first surface 111 of the substrate 110 can be regarded as a thin film circuit structure 10D, and the dielectric layer 141, the dielectric layer 142, and the dielectric layer 143 can constitute a multi-layer dielectric structure 140D.

Optionally, for actual commercial needs, the thin film circuit structure 10D can be further separated from the substrate 110 by an appropriate method (such as peeling) so that the thin film circuit structure 10D can form a terminal product, as shown in FIG. 5B , wherein the thin film circuit structure 10D can include a base layer 120, a pad structure 130C, a multi-layer dielectric structure 140D, a seed layer 151, a seed layer 152, a conductive bump 160, and a conductive layer 170.

FIG6A is a partial cross-sectional schematic diagram of a probe card according to some embodiments of the present invention. FIG6B is a partial cross-sectional schematic diagram of a thin film circuit structure separated from FIG6A.

Please refer to FIG. 6A , and continue with FIG. 4B . Similar to the process of FIG. 3A , a dielectric layer 143 is formed on the structure of FIG. 4B , and then an etching process is performed on the dielectric layer 143 . Then, a conductive layer 270 is formed on the top surface 160t and the side wall 160s of the exposed conductive bump 160 , so that the conductive layer 270 can cover the top surface 160t and the side wall 160s of the conductive bump 160 , so as to complete the probe card 100E of FIG. 6A . Here, the structure on the first surface 111 of the substrate 110 can be regarded as a thin film circuit structure 10E, and the dielectric layer 141 , the dielectric layer 142 , and the dielectric layer 143 can constitute a multi-layer dielectric structure 140D.

Optionally, for actual commercial needs, the thin film circuit structure 10E can be further separated from the substrate 110 by an appropriate method (such as peeling) so that the thin film circuit structure 10E can form a terminal product, as shown in FIG6B , wherein the thin film circuit structure 10E can include a base layer 120, a pad structure 130C, a multi-layer dielectric structure 140D, a seed layer 151, a seed layer 152, a conductive bump 160, and a conductive layer 270. It should be noted that the dielectric layer 141, the dielectric layer 142, and the dielectric layer 143 can all use thermosetting materials.

Figures 7A to 7E are partial cross-sectional schematic diagrams of a partial manufacturing method of a probe card according to some embodiments of the present invention. Figure 7F is a partial cross-sectional schematic diagram of a thin film circuit structure separated from Figure 7E.

Referring to FIG. 7A , in this embodiment, the manufacturing process of the probe card may include the following steps. First, similar to FIG. 1A , a base layer 120 and a conductive portion 131 are formed on the first surface 111 of the substrate 110 . Then, a dielectric layer 241 is formed on the first surface 111 of the substrate 110 , surrounding the conductive portion 131 and covering the top surface 131t of the conductive portion 131 . In addition, in this embodiment, the material of the dielectric layer 241 may include a thermoplastic material, such as tetrafluoroethylene/perfluoroalkoxy vinyl ether copolymer (PFA), cycloolefin polymer (COP), polyarylate (PAR) or a suitable thermoplastic material thereof.

Referring to FIG. 7B , the dielectric layer 241 is etched to shrink the dielectric layer 241 toward the base layer 120 . Then, a seed layer 251 is formed on the substrate 110 . In an embodiment not shown, the top surface of the shrunk dielectric layer 241 is lower than the top surface of the conductive portion 131 .

Referring to FIG. 7C , a patterned photoresist (not shown) is formed on the substrate 110 , and a metal plating process is performed on the patterned photoresist to form a conductive portion 232 . Here, the shape of the conductive portion 232 may be different from that of the conductive portion 132 , and the shape of the conductive portion 232 may be rectangular (the conductive portion 132 is a disk as shown in FIG. 1C ), and the size of the conductive portion 232 may be different from that of the conductive portion 131 , and as shown in FIG. 7C , the width 232w of the conductive portion 232 may be greater than the width 131w of the conductive portion 131 . Then, after the conductive portion 232 is formed, another patterned photoresist PR2 having an opening is formed on the substrate 110 .

Referring to FIG. 7D , a metal plating process is performed to form a conductive bump 160 in the opening of the patterned photoresist PR2. Then, the patterned photoresist PR2 and the portion of the seed layer 251 not covered by the conductive portion 232 are removed, so that another portion of the seed layer 251 that is not removed is disposed below the conductive portion 232.

Referring to FIG. 7E , an electroless plating process is performed on the conductive bump 160 to form a conductive layer 170 covering the conductive bump 160 to complete the probe card 200 of FIG. 7E . Here, the structure on the first surface 111 of the substrate 110 can be regarded as a thin film circuit structure 20 , and the conductive portion 131 and the conductive portion 232 constitute a pad structure 230 .

Optionally, for actual commercial needs, the thin film circuit structure 20 can be further separated from the substrate 110 by an appropriate method (such as peeling) so that the thin film circuit structure 20 can form a terminal product, as shown in FIG. 7F , wherein the thin film circuit structure 20 may include a base layer 120, a pad structure 230, a dielectric layer 241, a seed layer 251, a conductive bump 160, and a conductive layer 170.

FIG8A is a partial cross-sectional schematic diagram of a probe card according to some embodiments of the present invention. FIG8B is a partial cross-sectional schematic diagram of a thin film circuit structure separated from FIG8A.

Please refer to FIG8A, and continue with FIG7E. Similar to the process from FIG2A to FIG2B, a dielectric layer 242 is formed on the structure of FIG7E. Then, the dielectric layer 242 is etched so that the reduced dielectric layer 242 exposes the top surface 170t of the conductive layer 170 and covers part of the side wall 170s of the conductive layer 170 to complete the probe card 200A of FIG8A. Here, the structure on the first surface 111 of the substrate 110 can be regarded as a thin film circuit structure 20A, and the dielectric layer 241 and the dielectric layer 242 can constitute a multi-layer dielectric structure 240.

Optionally, for actual commercial needs, the thin film circuit structure 20A can be further separated from the substrate 110 by an appropriate method (such as peeling) so that the thin film circuit structure 20A can form a terminal product, as shown in FIG. 8B , wherein the thin film circuit structure 20A can include a base layer 120, a pad structure 230, a multi-layer dielectric structure 240, a seed layer 251, a conductive bump 160, and a conductive layer 170.

FIG9A is a partial cross-sectional schematic diagram of a probe card according to some embodiments of the present invention. FIG9B is a partial cross-sectional schematic diagram of a thin film circuit structure separated from FIG9A.

Please refer to FIG. 9A, and continue with FIG. 7D. Similar to the process from FIG. 2A to FIG. 2B, a dielectric layer 242 is formed on the structure of FIG. 7D, and then an etching process is performed on the dielectric layer 242. Then, a conductive layer 270 is formed on the top surface 160t and the side wall 160s of the exposed conductive bump 160, so that the conductive layer 270 can cover the top surface 160t and the side wall 160s of the conductive bump 160 to complete the probe card 200B of FIG. 9A. Here, the structure on the first surface 111 of the substrate 110 can be regarded as a thin film circuit structure 20B, and the dielectric layer 241 and the dielectric layer 242 can constitute a multi-layer dielectric structure 240.

Optionally, for actual commercial needs, the thin film circuit structure 20B can be further separated from the substrate 110 by an appropriate method (such as peeling) so that the thin film circuit structure 20B can form a terminal product, as shown in FIG. 9B , wherein the thin film circuit structure 20B can include a base layer 120, a pad structure 230, a multi-layer dielectric structure 240, a seed layer 251, a conductive bump 160, and a conductive layer 270.

Figures 10A to 10C are partial cross-sectional schematic diagrams of a partial manufacturing method of a probe card according to some embodiments of the present invention. Figure 10D is a partial cross-sectional schematic diagram of a thin film circuit structure separated from Figure 10C.

Referring to FIG. 10A , following FIG. 7C (but excluding the patterned photoresist PR2), another patterned photoresist (not shown) is formed on the structure of FIG. 7C (but excluding the patterned photoresist PR2), and a metal plating process is performed on the patterned photoresist to form a conductive portion 133. Then, the patterned photoresist is removed.

Referring to FIG. 10B , a dielectric layer 242 is formed on the substrate 110 in its entirety. Then, an etching process is performed on the dielectric layer 242 and a seed layer 252 is formed on the substrate 110 in its entirety. Then, a conductive portion 234 is formed by a patterned photoresist (not shown) and a conductive bump 160 is formed by another patterned photoresist (not shown). Then, the patterned photoresist and the portion of the seed layer 252 not covered by the conductive portion 234 are removed, so that another portion of the seed layer 252 that is not removed is disposed below the conductive portion 234.

Referring to FIG. 10C , an electroless plating process is performed on the conductive bump 160 to form a conductive layer 170 covering the conductive bump 160 to complete the probe card 200C of FIG. 10C . Here, the structure on the first surface 111 of the substrate 110 can be regarded as a thin film circuit structure 20C, the conductive portion 131, the conductive portion 232, the conductive portion 133, and the conductive portion 234 constitute a pad structure 230C, and the dielectric layer 241 and the dielectric layer 242 can constitute a multi-layer dielectric structure 240.

Optionally, for actual commercial needs, the thin film circuit structure 20C can be further separated from the substrate 110 by an appropriate method (such as peeling) so that the thin film circuit structure 20C can form a terminal product, as shown in FIG. 10D , wherein the thin film circuit structure 20C can include a base layer 120, a pad structure 230C, a multi-layer dielectric structure 240, a seed layer 251, a seed layer 252, a conductive bump 160, and a conductive layer 170.

FIG. 11A is a partial cross-sectional schematic diagram of a probe card according to some embodiments of the present invention. FIG. 11B is a partial cross-sectional schematic diagram of a thin film circuit structure separated from FIG. 11A .

Please refer to FIG. 11A, and continue with FIG. 10C. Similar to the process from FIG. 2A to FIG. 2B, a dielectric layer 243 is formed on the structure of FIG. 10C. Then, the dielectric layer 243 is etched so that the reduced dielectric layer 243 exposes the top surface 170t of the conductive layer 170 and covers part of the side wall 170s of the conductive layer 170, thereby completing the probe card 200D of FIG. 11A. Here, the structure on the first surface 111 of the substrate 110 can be regarded as a thin film circuit structure 20D, and the dielectric layer 241, the dielectric layer 242, and the dielectric layer 243 can constitute a multi-layer dielectric structure 240D.

Optionally, for actual commercial needs, the thin film circuit structure 20D can be further separated from the substrate 110 by an appropriate method (such as peeling) so that the thin film circuit structure 20D can form a terminal product, as shown in FIG. 11B , wherein the thin film circuit structure 20D can include a base layer 120, a pad structure 230C, a multi-layer dielectric structure 240D, a seed layer 251, a seed layer 252, a conductive bump 160, and a conductive layer 170.

FIG12A is a partial cross-sectional schematic diagram of a probe card according to some embodiments of the present invention. FIG12B is a partial cross-sectional schematic diagram of a thin film circuit structure separated from FIG12A.

Please refer to FIG. 12A , and then FIG. 10B , similar to the method of FIG. 3A , a dielectric layer 243 is formed on the structure of FIG. 10B , and then the dielectric layer 243 is etched. Then, a conductive layer 270 is formed on the top surface 160t and the side wall 160s of the exposed conductive bump 160 , so that the conductive layer 270 can cover the top surface 160t and the side wall 160s of the conductive bump 160 to complete the probe card 200E of FIG. 12A . Here, the structure on the first surface 111 of the substrate 110 can be regarded as a thin film circuit structure 20E, and the dielectric layer 241, the dielectric layer 242, and the dielectric layer 243 can constitute a multi-layer dielectric structure 240D.

Optionally, for actual commercial needs, the thin film circuit structure 20E can be further separated from the substrate 110 by an appropriate method (such as peeling) so that the thin film circuit structure 20E can form a terminal product, as shown in FIG12B , wherein the thin film circuit structure 20E can include a base layer 120, a pad structure 230C, a multi-layer dielectric structure 240D, a seed layer 251, a seed layer 252, a conductive bump 160, and a conductive layer 270. It should be noted that the dielectric layer 241, the dielectric layer 242, and the dielectric layer 243 can all use thermoplastic materials.

Figures 13A to 13E are partial cross-sectional schematic diagrams of a partial manufacturing method of a probe card according to some embodiments of the present invention. Figure 13F is a partial cross-sectional schematic diagram of a thin film circuit structure separated from Figure 13E.

Referring to FIG. 13A , in this embodiment, the manufacturing process of the probe card may include the following steps. First, similar to FIG. 1A , a base layer 120 and a conductive portion 131 are formed on the first surface 111 of the substrate 110 . Then, a dielectric layer 341 is formed on the first surface 111 of the substrate 110 to surround the conductive portion 131 and cover the top surface (not shown) of the conductive portion 131 . In addition, in this embodiment, the material of the dielectric layer 341 may include a photosensitive material, such as photosensitive polyimide (PSPI), photosensitive benzocyclobutene (BCB) or a suitable photosensitive material thereof. Next, an opening 341a is formed in the dielectric layer 341 (for example, by lithography and thermal curing processes) to expose a portion of the conductive portion 131 below. Then, a seed layer 351 may be formed completely on the substrate 110.

Referring to FIG. 13B , a patterned photoresist PR3 having an opening is formed on the dielectric layer 341. Then, a conductive portion 332 is formed by the patterned photoresist PR3. Here, the shape of the conductive portion 332 may be different from the conductive portion 132 and the conductive portion 232. The shape of the conductive portion 332 may be a trapezoid (the conductive portion 132 is a disk as shown in FIG. 1C , and the conductive portion 232 is a rectangle as shown in FIG. 7C ), and the size of the conductive portion 332 may be different from the size of the conductive portion 131. As shown in FIG. 13B , the width 332w of the conductive portion 332 may be greater than the width 131w of the conductive portion 131.

Referring to FIG. 13C and FIG. 13D , the patterned photoresist PR3 is removed. Another patterned photoresist PR4 is formed on the substrate 110, and a metal plating process is performed on the patterned photoresist PR4 to form the probe 160. Then, the patterned photoresist PR4 and the portion of the seed layer 351 not covered by the conductive portion 332 are removed.

Referring to FIG. 13E , an electroless plating process is performed on the conductive bump 160 to form a conductive layer 170 covering the conductive bump 160 to complete the probe card 300 of FIG. 13E . Here, the structure on the first surface 111 of the substrate 110 can be regarded as a thin film circuit structure 30, and the conductive portion 131 and the conductive portion 332 constitute a pad structure 330.

Optionally, for actual commercial needs, the thin film circuit structure 30 can be further separated from the substrate 110 by an appropriate method (such as peeling) so that the thin film circuit structure 30 can form a terminal product, as shown in FIG. 13F , wherein the thin film circuit structure 30 may include a base layer 120, a pad structure 330, a dielectric layer 341, a seed layer 351, a conductive bump 160, and a conductive layer 170.

FIG14A is a partial cross-sectional schematic diagram of a probe card according to some embodiments of the present invention. FIG14B is a partial cross-sectional schematic diagram of a thin film circuit structure separated from FIG14A.

Please refer to FIG. 14A, and continue with FIG. 13E. Similar to the process from FIG. 2A to FIG. 2B, a dielectric layer 342 is formed on the structure of FIG. 13E. Then, the dielectric layer 342 is etched so that the reduced dielectric layer 342 exposes the top surface 170t of the conductive layer 170 and covers part of the side wall 170s of the conductive layer 170, thereby completing the probe card 300A of FIG. 14A. Here, the structure on the first surface 111 of the substrate 110 can be regarded as a thin film circuit structure 30A, and the dielectric layer 341 and the dielectric layer 342 can constitute a multi-layer dielectric structure 340.

Optionally, for actual commercial needs, the thin film circuit structure 30A can be further separated from the substrate 110 by an appropriate method (such as peeling) so that the thin film circuit structure 30A can form a terminal product, as shown in FIG. 14B , wherein the thin film circuit structure 30A can include a base layer 120, a pad structure 330, a multi-layer dielectric structure 340, a seed layer 351, a conductive bump 160, and a conductive layer 170.

FIG. 15A is a partial cross-sectional schematic diagram of a probe card according to some embodiments of the present invention. FIG. 15B is a partial cross-sectional schematic diagram of a thin film circuit structure separated from FIG. 15A.

Please refer to FIG. 15A, and continue with FIG. 13D. Similar to the process from FIG. 2A to FIG. 2B, a dielectric layer 342 is formed on the structure of FIG. 13D, and then an etching process is performed on the dielectric layer 342. Then, a conductive layer 270 is formed on the top surface 160t and the side wall 160s of the exposed conductive bump 160, so that the conductive layer 270 can cover the top surface 160t and the side wall 160s of the conductive bump 160 to complete the probe card 300B of FIG. 15A. Here, the structure on the first surface 111 of the substrate 110 can be regarded as a thin film circuit structure 30B, and the dielectric layer 341 and the dielectric layer 342 can constitute a multi-layer dielectric structure 340.

Optionally, for actual commercial needs, the thin film circuit structure 30B can be further separated from the substrate 110 by an appropriate method (such as peeling) so that the thin film circuit structure 30B can form a terminal product, as shown in FIG. 15B , wherein the thin film circuit structure 30B can include a base layer 120, a pad structure 330, a multi-layer dielectric structure 340, a seed layer 351, a conductive bump 160, and a conductive layer 270.

Figures 16A to 16C are partial cross-sectional schematic diagrams of a partial manufacturing method of a probe card according to some embodiments of the present invention. Figure 16D is a partial cross-sectional schematic diagram of a thin film circuit structure separated from Figure 16C.

Please refer to FIG. 16A , and continue with FIG. 13B , the patterned photoresist PR3 and the portion of the seed layer 351 not covered by the conductive portion 332 are removed, so that another portion of the seed layer 351 that is not removed is disposed under the conductive portion 332 . Then, a dielectric layer 342 is formed on the entire substrate 110 .

Referring to FIG. 16B , an opening 342a is formed in the dielectric layer 342 to expose a portion of the conductive portion 332 below. Next, a seed layer 352 is formed on the substrate 110. Then, a patterned photoresist (not shown) is formed on the dielectric layer 342, and a metal plating process is performed through the patterned photoresist to form the conductive portion 333 and then the patterned photoresist is removed. Next, a conductive bump 160 is formed through another patterned photoresist (not shown), and then the patterned photoresist and the portion of the seed layer 352 not covered by the conductive portion 333 are removed.

Referring to FIG. 16C , an electroless plating process is performed on the conductive bump 160 to form a conductive layer 170 covering the conductive bump 160 to complete the probe card 300C of FIG. 16C . Here, the structure on the first surface 111 of the substrate 110 can be regarded as a thin film circuit structure 30C, the conductive portion 131, the conductive portion 332, and the conductive portion 333 constitute a pad structure 330C, and the dielectric layer 341 and the dielectric layer 342 can constitute a multi-layer dielectric structure 340.

Optionally, for actual commercial needs, the thin film circuit structure 30C can be further separated from the substrate 110 by an appropriate method (such as peeling) so that the thin film circuit structure 30C can form a terminal product, as shown in FIG. 16D , wherein the thin film circuit structure 30C can include a base layer 120, a pad structure 330C, a multi-layer dielectric structure 340, a seed layer 351, a seed layer 352, a conductive bump 160, and a conductive layer 170.

FIG17A is a partial cross-sectional schematic diagram of a probe card according to some embodiments of the present invention. FIG17B is a partial cross-sectional schematic diagram of a thin film circuit structure separated from FIG17A.

Please refer to FIG. 17A, and continue with FIG. 16C. Similar to the process from FIG. 2A to FIG. 2B, a dielectric layer 343 is formed on the structure of FIG. 16C. Then, the dielectric layer 343 is etched to expose the top surface 170t of the conductive layer 170 and cover part of the side wall 170s of the conductive layer 170. Thus, the probe card 300D of FIG. 17A is completed. Here, the structure on the first surface 111 of the substrate 110 can be regarded as a thin film circuit structure 30D, and the dielectric layer 341, the dielectric layer 342, and the dielectric layer 343 can constitute a multi-layer dielectric structure 340D.

Optionally, for actual commercial needs, the thin film circuit structure 30D can be further separated from the substrate 110 by an appropriate method (such as peeling) so that the thin film circuit structure 30D can form a terminal product, as shown in FIG. 17B , wherein the thin film circuit structure 30D can include a base layer 120, a pad structure 330C, a multi-layer dielectric structure 340D, a seed layer 351, a seed layer 352, a conductive bump 160, and a conductive layer 170.

FIG18A is a partial cross-sectional schematic diagram of a probe card according to some embodiments of the present invention. FIG18B is a partial cross-sectional schematic diagram of a thin film circuit structure separated from FIG18A.

Please refer to FIG. 18A , and then FIG. 16B , similar to the method of FIG. 3A , a dielectric layer 343 is formed on the structure of FIG. 16B , and then the dielectric layer 343 is etched. Then, a conductive layer 270 is formed on the top surface 160t and the side wall 160s of the exposed conductive bump 160 , so that the conductive layer 270 can cover the top surface 160t and the side wall 160s of the conductive bump 160 to complete the probe card 300E of FIG. 18A . Here, the structure on the first surface 111 of the substrate 110 can be regarded as a thin film circuit structure 30E, and the dielectric layer 341, the dielectric layer 342, and the dielectric layer 343 can constitute a multi-layer dielectric structure 340D.

Optionally, for actual commercial needs, the thin film circuit structure 30E can be further separated from the substrate 110 by an appropriate method (such as peeling) so that the thin film circuit structure 30E can form a terminal product, as shown in FIG. 18B , wherein the thin film circuit structure 30E can include a base layer 120, a pad structure 330C, a multi-layer dielectric structure 340D, a seed layer 351, a seed layer 352, a conductive bump 160, and a conductive layer 270. It should be noted that the dielectric layer 341, the dielectric layer 342, and the dielectric layer 343 can all use photosensitive materials.

FIG. 19A to FIG. 19B are schematic diagrams of the corresponding configuration of the thin film circuit structure and the substrate of the probe card according to some embodiments of the present invention. Please refer to FIG. 19A and FIG. 19B. In this embodiment, the probe card MP includes a substrate 110 and a thin film circuit structure, wherein the thin film circuit structure includes a thin film circuit portion MC and a conductive bump 160. Here, the thin film circuit portion MC can be the various embodiments of the above-mentioned combination of the base layer, the pad structure, the dielectric layer, and the seed layer, which will not be repeated here.

In addition, the thin film circuit part MC includes any of the above-mentioned dielectric layers, any of the above-mentioned pad structures, and the conductive bump 160, wherein any of the above-mentioned pad structures is at least partially located in any of the above-mentioned dielectric layers, the conductive bump 160 is located on any of the above-mentioned pad structures, and the orthographic projection of the conductive bump 160 on any of the above-mentioned dielectric layers overlaps with the orthographic projection of any of the above-mentioned pad structures on any of the above-mentioned dielectric layers. Accordingly, the probe card MP of this embodiment can stabilize the probe, increase the firmness, and maintain the probe bearing capacity by designing the pad structure that is disposed in the dielectric layer and overlaps with the conductive bump 160 (probe) in the top view direction, so as to reduce the loosening or breaking of the probe, thereby effectively improving the probe gripping force and thereby enhancing its reliability.

In this embodiment, the size of the thin film circuit part MC is equal to the size of the substrate 110, and the conductive bumps 160 on the substrate 110 can have an arrangement as shown in FIG. 19B , corresponding to the measurement position, spacing and size requirements of the object to be measured, but the present invention is not limited thereto. In other embodiments, the size of the thin film circuit part MC and the size of the substrate 110 can have different corresponding relationships, and the conductive bumps 160 can also have different arrangement patterns.

The probe card MP further includes a conductive bump 260 disposed on the second surface 112 of the substrate 110, which can be vertically bonded with other components to reduce the integration space.

FIG. 20A to FIG. 20B are schematic diagrams of the corresponding configuration of the thin film circuit structure and the substrate of the probe card according to some embodiments of the present invention. Referring to FIG. 20A and FIG. 20B, the main difference between the probe card MP1 of this embodiment and the probe card MP of FIG. 19A and FIG. 19B is that the size of the thin film circuit part MC1 of this embodiment is larger than the size of the substrate 110. In addition, the thin film circuit part MC1 may include a central area C overlapping with the substrate 110 in the orthographic projection direction and edge areas B on both sides of the central area C, and the conductive bump 160 is disposed in the central area C. In this embodiment, the size of the thin film circuit portion MC further includes a conductive bump 360 disposed in the edge region B, and the conductive bump 160 and the conductive bump 360 can have an arrangement pattern as shown in FIG. 20B on the substrate 110. Since the edge region B of the thin film circuit is not fixed to the rigid substrate, its flexible film can be bent according to space requirements, and the conductive bump 360 can be bonded to other components, but the present invention is not limited thereto.

FIG. 21A to FIG. 21D are schematic diagrams of the corresponding configuration of the thin film circuit structure and the substrate of the probe card according to some embodiments of the present invention. Referring to FIG. 21A to FIG. 21D, the main difference between the probe card MP2 of this embodiment and the probe card MP of FIG. 19A and FIG. 19B is that the size of the thin film circuit part MC2 of this embodiment is smaller than the size of the substrate 110. In addition, the size of the thin film circuit part MC2 further includes the conductive bumps 360 disposed on the substrate 110 on both sides of the thin film circuit part MC2, and the conductive bumps 160 and the conductive bumps 360 on the substrate 110 can have the arrangement of FIG. 21B to FIG. 21D, which can contact or bond with the object to be tested and other components, expand from the horizontal to the three-dimensional space, shorten the signal transmission distance and improve the space utilization rate, but the present invention is not limited to this.

In some embodiments, when the substrate is a substrate without conductive properties, the thin film circuit part and substrate with different size combinations can be formed by adhesive bonding, for example, the thin film circuit part and substrate of the required size can be pre-formed, and then the thin film circuit part and the substrate are bonded by a bonding layer (not shown) with dielectric properties, so that there will be a bonding layer between the thin film circuit part and the substrate, wherein the size of the bonding layer can be the same as the size of the thin film circuit part, that is, the bonding layer can be first formed on the thin film circuit part and then bonded to the substrate, but the present invention is not limited to this. Here, the bonding layer can be any suitable adhesive material, and the present invention is not limited to this.

In some embodiments, when the substrate is a substrate without conductive properties, the thin film circuit part and substrate with different size combinations can be formed by, for example, a thin film circuit part with the same size as the substrate can be formed first, and then cut according to actual design requirements. For example, if the thin film circuit part and the substrate need to have the same size, the thin film circuit part and the substrate can be cut and peeled at the same time, so that the thin film circuit part and the substrate have aligned edges. When the size of the thin film circuit part needs to be larger than the size of the substrate, only the substrate is cut and peeled, so that parts on both sides of the substrate are removed and shrunk below the thin film circuit part. When the size of the thin film circuit part needs to be smaller than the size of the substrate, only the thin film circuit part is cut and peeled, so that parts on both sides of the thin film circuit part are removed and shrunk above the substrate, but the present invention is not limited to this.

In some embodiments, when the substrate is a substrate with circuit wiring, the thin film circuit part and the substrate with different size combinations can be formed by an integrated molding method. For example, a substrate with circuit wiring (such as an MLC substrate) can be provided, and then a thin film circuit part with the same size or smaller than the required size can be directly formed on the substrate. When the size of the thin film circuit part is required to be larger than the size of the substrate, the substrate can be further cut and peeled off so that the parts on both sides of the substrate are removed and retracted under the thin film circuit part, but the present invention is not limited to this.

In some embodiments, when the substrate is a substrate with circuit wiring, the thin film circuit part and substrate with different size combinations can be formed by surface mount technology (SMT). For example, the thin film circuit part and substrate of the required size can be pre-formed, and then the thin film circuit part and substrate are connected by a connecting element (not shown) with conductive properties, wherein the connecting element can be a solder ball. In addition, a primer can be further formed to fill the gaps between the solder balls, but the present invention is not limited to this.

In some embodiments, when the substrate is a substrate with circuit wiring, the thin film circuit part and substrate with different size combinations can be formed by, for example, heterogeneous bonding. For example, the thin film circuit part and substrate of the required size can be formed in advance, and then the thin film circuit part and substrate can be bonded by direct bonding techniques such as hybrid bonding or the like. In addition, when the size of the thin film circuit part is required to be larger than the size of the substrate, the substrate can be further cut and peeled off so that the parts on both sides of the substrate are removed and retracted under the thin film circuit part, but the present invention is not limited to this.

The dielectric layer materials described in the above embodiments are only examples, and in addition to the above-mentioned thermosetting materials, thermoplastic materials, and photosensitive materials, the dielectric layer materials can also be organic-inorganic composite materials. Therefore, as long as the dielectric layer materials include thermosetting materials, thermoplastic materials, photosensitive materials, organic-inorganic composite materials or their combinations, they all belong to the protection scope of the present invention. In addition, the above-mentioned multi-layer dielectric layers can be different materials, so the multi-layer dielectric layers can form interfaces in the diagram, but the present invention is not limited to this. The multi-layer dielectric layers can also be the same material, so there may be no interface between the multi-layer dielectric layers. On the other hand, when the substrates of Figures 19A, 20A, and 21A are substrates with conductive properties, the internal circuits can be arranged according to the actual design requirements, and the present invention does not limit them.

In summary, the probe card of the present invention can stabilize the probe, increase its firmness and maintain its bearing capacity by designing a pad structure that is arranged in the dielectric layer and overlaps with the conductive bump (probe) in the top view, so as to reduce the loosening or breakage of the probe. In this way, the probe gripping force can be effectively improved, thereby enhancing its reliability. In addition, the size of the space where the thin film circuit part is placed on the rigid substrate and the bumps are distributed on the thin film circuit structure or the rigid substrate. The different arrangement patterns make the probe card have higher scalability and space utilization.

Although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the attached patent application.

10: Thin film circuit structure

100:Probe card

110: Substrate

111: First surface

120: Basal layer

130: Gasket structure

131, 132: Conductive part

141: Dielectric layer

151: Seed layer

160: Conductive bump

170: Conductive layer

Claims (11)

A probe card includes: a substrate, wherein the substrate has rigidity; and a thin film circuit structure, at least partially connected to the surface of the substrate, wherein the thin film circuit structure includes: a thin film circuit portion, including a dielectric layer and a pad structure, wherein the pad structure is at least partially located in the dielectric layer; a first conductive bump, located on the pad structure, wherein the orthographic projection of the first conductive bump on the dielectric layer overlaps the orthographic projection of the pad structure on the dielectric layer; a conductive layer, covering the side wall of the first conductive bump; and another dielectric layer, covering the side wall of the conductive layer. A probe card as described in claim 1, wherein the substrate is a substrate having a first circuit wiring, and the first circuit wiring is located in a substrate dielectric layer. A probe card as described in claim 2, wherein the thin film circuit portion includes a base layer located between the pad structure and the substrate, the base layer having a base dielectric layer and a second circuit wiring located in the base dielectric layer, the first circuit wiring is in direct contact with the second circuit wiring, and the substrate dielectric layer is in direct contact with the base dielectric layer. A probe card as described in claim 2, wherein the substrate is a multilayer ceramic substrate. A probe card as described in claim 1, wherein the substrate is a substrate that does not have conductive properties. A probe card as described in claim 1, wherein the size of the thin film circuit portion is equal to the size of the substrate. A probe card as described in claim 1, wherein the size of the thin film circuit portion is larger than the size of the substrate. The probe card as described in claim 7, wherein the thin film circuit portion includes a central area overlapping with the substrate in the orthographic projection direction and edge areas on both sides of the central area, and the first conductive bump is disposed in the central area, and the thin film circuit structure further includes a second conductive bump disposed in the edge area. A probe card as described in claim 1, wherein the size of the thin film circuit portion is smaller than the size of the substrate. A probe card as described in claim 9, wherein the thin film circuit structure further includes a second conductive bump, and the second conductive bump is disposed on the substrate on both sides of the thin film circuit portion. The probe card as described in claim 1 further includes a third conductive bump disposed on the surface of the substrate opposite to the thin film circuit structure.

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