TWI838629B - Vcsel with tunnel junction - Google Patents

Abstract

Provided is a vertical cavity surface emitting laser diode (VCSEL). A tunnel junction with a high doping concentration is provided in the VCSEL. An n-type semiconductor layer of the tunnel junction has stress relative to the substrate, and is doped with at least one element such that the tunnel junction not only has a high doping concentration, but also the epitaxial layer can be oxidized and the oxidation rate is relatively stable during the oxidation process. Alternatively, the n-type semiconductor layer is doped with at least two elements. As a result, the oxidation process of the VCSEL can be stably performed, and the resistance of the tunnel junction with a high doping concentration is low. The tunnel junction is suitable to be arranged between two active layers of the VCSEL or between the p-type semiconductor and the n-type semiconductor layer of the VCSEL.

Description

Vertical Cavity Surface Emitting Laser Diode (VCSEL) with Tunneling Junction Layer

A VCSEL, in particular a VCSEL with a tunneling junction layer.

The tunnel junction layer is generally composed of a P-type semiconductor layer and an N-type semiconductor layer. In principle, the higher the doping concentration of the P-type semiconductor layer and the N-type semiconductor layer, the higher the tunneling probability of the carriers in the tunnel junction layer, and the lower the resistance of the tunnel junction layer. A common material for the tunnel junction layer is GaAs. P-type GaAs is usually doped with Carbon (C) elements to increase its doping concentration; while N-type GaAs is usually doped with Tellurium (Te) elements or Selenium (Se) elements to increase its doping concentration.

In addition, when the doping concentration of the ohmic contact layer is higher and the energy gap is smaller, the ohmic contact layer and the metal material can form ohmic contact more easily. One of the commonly used materials for the ohmic contact layer is also GaAs. Therefore, the doping concentration of the ohmic contact layer can also be increased by doping Te or Se in N-type GaAs.

When the oxide layer material, aluminum content and oxidation process conditions remain unchanged, the doping concentration of N-type GaAs doped with Te or Se is significantly higher than that of N-type GaAs not doped with Te or Se, but it actually affects the VCSEL oxidation process. Specifically, the oxidation rate of the oxide layer will be slowed down, or it will be difficult to carry out a stable oxidation process or the oxidation process will become difficult to control due to the unstable oxidation rate; although the oxidation rate may be increased by increasing the aluminum content of the oxide layer, if the aluminum content of the oxide layer is too high, the reliability of the VCSEL may decrease.

If the Te or Se doping concentration of GaAs is higher, the oxide layer may be more difficult to oxidize even if the aluminum content of the oxide layer is increased.

In order to solve the shortcomings of the prior art, a first tunnel junction layer or a second tunnel junction layer with high doping concentration and low resistance is provided in the VCSEL. When the VCSEL undergoes an oxidation process, the oxide layer of the VCSEL can be smoothly oxidized.

In one embodiment, a VCSEL includes a GaAs substrate and an epitaxial structure; the epitaxial structure is formed on the GaAs substrate, the epitaxial structure includes at least one oxide layer and a first tunneling junction layer; the first tunneling junction layer includes an N-type first semiconductor layer; the N-type first semiconductor layer is disposed above or below the oxide layer, the N-type first semiconductor layer is at least doped with Te and/or Se and provides stress to the GaAs substrate.

In one embodiment, a VCSEL includes a GaAs substrate and an epitaxial structure; the epitaxial structure is formed on the GaAs substrate, the epitaxial structure includes at least one oxide layer and a second tunneling junction layer; the second tunneling junction layer includes an N-type second semiconductor layer, the N-type second semiconductor layer is disposed above or below the oxide layer, the N-type second semiconductor layer includes an N-type GaAs layer, the N-type GaAs layer is doped with at least one doping material selected from the group consisting of Te and Se and at least one doping material selected from the group consisting of Si and C.

On the other hand, the above-mentioned N-type first semiconductor layer and N-type second semiconductor layer can also be used as ohmic contact layers alone. In one embodiment, a VCSEL includes a GaAs substrate and an epitaxial structure; the epitaxial structure is formed on the GaAs substrate, and the epitaxial structure includes at least one oxide layer and an ohmic contact layer. The ohmic contact layer is located above or below the oxide layer; the ohmic contact layer includes an N-type first semiconductor layer or an N-type second semiconductor layer. The N-type first semiconductor layer is doped with at least Te and/or Se and provides stress to the GaAs substrate; the N-type second semiconductor layer includes an N-type GaAs layer, which is doped with at least one doping material selected from the group consisting of Te and Se and at least one doping material selected from the group consisting of Si and C.

The following is a more detailed description of the implementation of the present invention with the help of diagrams and component symbols, so that those who are familiar with the technology can implement it accordingly after reading this manual.

The following describes specific examples of components and their arrangement to simplify the present invention. Of course, these are only examples and should not be used to limit the scope of the present invention. For example, when a layer is mentioned in the description as being on top of another layer, it may include embodiments in which the layer is in direct contact with the other layer, and it may also include embodiments in which there are other components or epitaxial layers formed between the two layers without direct contact. In addition, repeated numbers and/or symbols may be used in different embodiments. These repetitions are only for the purpose of simply and clearly describing some embodiments, and do not represent a specific relationship between the different embodiments and/or structures discussed.

In addition, spatially relative terms such as "below", "below", "lower", "above", "higher" and similar terms may be used to facilitate the description of the relationship between one (or some) elements or features and another (or some) elements or features in the drawings. These spatially relative terms include different orientations of the device in use or operation, as well as the orientations described in the drawings.

This specification provides different embodiments to illustrate the technical features of different embodiments. For example, "some embodiments" referred to in the entire specification means that the specific features, structures, or characteristics described in the embodiments are included in at least one embodiment. Therefore, the phrase "in some embodiments" appearing in different places in the entire specification does not necessarily refer to the same embodiment.

In addition, specific features, structures, or characteristics may be combined in one or more embodiments by any suitable method. Further, for the terms "including", "having", "having", "wherein" or variations thereof used herein, these terms are similar to the term "comprising" to include the corresponding features.

In addition, a "layer" may be a single layer or may include multiple layers; and a "part" of an epitaxial layer may be a single layer of the epitaxial layer or multiple layers adjacent to each other.

In the prior art, a laser diode can be selectively provided with a buffer layer according to actual needs, and in some examples, the buffer layer can be made of the same material as the substrate. Whether or not a buffer layer is provided has no substantial relevance to the technical features and effects to be provided in the following embodiments. Therefore, for the sake of brief illustration, the following embodiments only use a laser diode with a buffer layer as an example for illustration, and do not further describe a laser diode without a buffer layer. That is, the following embodiments can be applied even if a laser diode without a buffer layer is replaced.

The VCSEL in the following embodiments is manufactured by epitaxially growing a multi-layer epitaxial structure on a GaAs substrate 10 by metal organic chemical vapor deposition (MOCVD). However, the epitaxial growth method is not limited to MOCVD, and molecular beam epitaxy (MBE) or other epitaxial growth methods may also be used to form a multi-layer epitaxial structure.

[Example 1-1]

Referring to FIG. 1 , an N-type buffer layer 12, an N-type lower DBR layer 20, an N-type first lower spacer layer 30, an active layer 32, a P-type first upper spacer layer 34, a P-type oxide layer 36 (to be oxidized), a P-type upper DBR layer 401, and a P-type first semiconductor layer 601 are sequentially epitaxially grown on an N-type GaAs substrate 10; then, an N-type first semiconductor layer 603, an N-type upper DBR layer 403, and an N-type ohmic contact layer 50 are sequentially formed on the P-type first semiconductor layer 601; thereby, the structure of VCSEL 100 is formed. After the oxidation process of VCSEL 100, an optical aperture (OA) is formed in the oxide layer 36, which is not shown.

The above-mentioned P-type first semiconductor layer 601 and N-type first semiconductor layer 603 constitute a first tunnel junction layer 60; as shown in FIG. 1 , the upper DBR layer 40 includes the first tunnel junction layer 60.

[Example 1-2]

If a P-type second semiconductor layer, an N-type second semiconductor layer, an N-type upper DBR layer 403, and an N-type ohmic contact layer 50 are sequentially epitaxially grown on the P-type upper DBR layer 401 of FIG. 1 , the upper DBR layer 40 includes a second tunneling junction layer (not shown). The above-mentioned P-type second semiconductor layer and N-type second semiconductor layer constitute the second tunneling junction layer.

For the convenience of the following description, the epitaxial region between the substrate and the active region will be referred to as the lower epitaxial region; the lower epitaxial region must be provided with the lower DBR layer 20. In addition, the lower epitaxial region further includes but is not limited to the buffer layer 12 and the first lower spacer layer 30. According to the purpose or characteristics of the VCSEL, the lower epitaxial region may further include an oxide layer and other appropriate epitaxial layers. The epitaxial region above the active region is referred to as the upper epitaxial region.

[Example 2-1]

Referring to FIG. 2 , an N-type lower epitaxial region (not shown, see FIG. 1 ), an active layer 32, a P-type first upper spacer layer 341, and a P-type first semiconductor layer 601 are sequentially epitaxially grown on a GaAs substrate 10; then, an N-type first semiconductor layer 603, an N-type first upper spacer layer 343, an N-type oxide layer 36, an N-type upper DBR layer 40, and an N-type ohmic contact layer 50 are formed on the P-type first semiconductor layer 601; thereby, the production of VCSEL 100 is preliminarily completed. After the oxidation process of VCSEL 100 in FIG. 2 , an optical aperture (OA) is formed in the oxide layer 36, and the current limiting aperture is not shown. The aforementioned P-type first semiconductor layer 601 and the N-type first semiconductor layer 603 constitute a first tunnel junction layer 60. As shown in FIG. 2 , the first spacer layer 34 includes the first tunnel junction layer 60.

[Example 2-2]

If a P-type second semiconductor layer (not shown), an N-type second semiconductor layer (not shown), an N-type first upper spacer layer 343, an N-type oxide layer 36, an N-type DBR layer 40, and an N-type ohmic contact layer 50 are sequentially epitaxially grown on the P-type first upper spacer layer 341 of FIG. 2 , the second tunneling junction layer (not shown) will be included in the first spacer layer 34. The above-mentioned P-type second semiconductor layer and the N-type second semiconductor layer constitute the second tunneling junction layer.

[Example 3-1]

Referring to FIG3 , an N-type lower epitaxial region (not shown, see FIG1 ), an active layer 32, a P-type first lower spacer layer 34, a P-type oxide layer 36, a P-type second upper spacer layer 381, and a P-type first semiconductor layer 601 are sequentially epitaxially grown on a GaAs substrate 10; then, an N-type first semiconductor layer 603 and an N-type second upper spacer layer 383, an N-type upper DBR layer 40, and an N-type ohmic contact layer 50 are formed on the P-type first semiconductor layer 601. Thus, the first tunneling junction layer 60 is disposed in the second spacer layer 38. The above-mentioned P-type first semiconductor layer 601 and the N-type first semiconductor layer 603 constitute the first tunneling junction layer 60.

[Example 3-2]

If a P-type second semiconductor layer and an N-type second semiconductor layer, an N-type second upper spacer layer 383, an N-type DBR layer 40 and an N-type ohmic contact layer 50 are sequentially formed on the P-type second upper spacer layer 381 of FIG. 3 , in other words, the first tunneling junction layer 60 of FIG. 3 is replaced by the second tunneling junction layer; thus, the second tunneling junction layer will be included in the second spacer layer 38.

The first tunnel junction layer or the second tunnel junction layer can also be formed in the lower epitaxial region.

[Example 4-1]

As shown in FIG. 4 , an N-type buffer layer 12, an N-type lower DBR layer 203, and an N-type first semiconductor layer 603 are formed on the GaAs substrate 10; then, a P-type first semiconductor layer 601, a P-type lower DBR layer 201, a P-type oxide layer 36, and a P-type first lower spacer layer 30 are formed on the N-type first semiconductor layer 603, and an active layer 32 and an N-type upper epitaxial region are formed on the P-type first lower spacer layer 30. Thus, the first tunneling junction layer 60 can be formed in the lower DBR layer 20.

[Implementation Example 4-2].

If the N-type lower DBR layer 203 of FIG. 4 is formed with an N-type second semiconductor layer and a P-type second semiconductor layer, a P-type lower DBR layer 201, a P-type oxide layer 36 and a P-type first lower spacer layer 30 in sequence, in other words, the first tunneling junction layer 60 of FIG. 4 is replaced with the second tunneling junction layer; thereby, the second tunneling junction layer can be included in the lower DBR layer 20.

FIG5 and FIG6 respectively show that the first (second) tunnel junction layer is disposed in the first lower spacer layer 30 and the second lower spacer layer 39 of the lower epitaxial region. The method of making the first (second) tunnel junction layer is described in the above embodiment and will not be described in detail here.

The above-mentioned N-type first semiconductor layer is doped with Te and/or Se and "has stress relative to the GaAs substrate". Compared with the N-type semiconductor layer of the known tunnel junction layer (under the same oxidation process conditions and the same material and composition of the oxide layer), the first tunnel junction layer can not only have a higher doping concentration, but also the oxide layer can be smoothly oxidized, that is, the oxidation rate of the oxide layer is faster or the oxidation rate is more stable, or the oxidation process is easier to control.

In one embodiment, the N-type first semiconductor layer doped with Te and/or Se is further doped with silicon (Si) and/or carbon (C).

The above-mentioned "having stress relative to the GaAs substrate" means that: the lattice constant of the material of the N-type first semiconductor layer is different from the lattice constant of the GaAs substrate; wherein the preferred material of the N-type first semiconductor layer "having stress relative to the GaAs substrate" includes at least one material selected from the group consisting of InGaAs, InGaP, GaAsP, GaAsSb, GaAsPSb, AlGaAs, AlGaAsSb, AlGaAsP, InAlGaAs, InAlGaP, InGaAsSb, InGaAsP and GaPSb; wherein, the lattice constant of InGaP and InAlGaP is greater than that of the GaAs substrate.

The N-type second semiconductor layer comprises an N-type GaAs layer, which is doped with at least one material selected from the group consisting of Te and Se and at least one material selected from the group consisting of Si and C. Compared with the N-type GaAs layer of the conventional tunnel junction layer, under the same oxidation process conditions and the same material and composition of the oxide layer, the oxide layer of the VCSEL having the second tunnel junction layer can be smoothly oxidized, that is, the oxidation rate of the oxide layer is faster or more stable, or the oxidation process is easily controlled.

The above-mentioned P-type first semiconductor layer or P-type second semiconductor layer is doped with carbon, wherein the carbon doping concentration is greater than 1x10 ¹⁹ /cm ³ , for example, the carbon doping concentration can be greater than 1x10 ¹⁹ /cm ³ , greater than 3x10 ¹⁹ /cm ³ , greater than 5x10 ¹⁹ /cm ³ , greater than 8x10 ¹⁹ /cm ³ , greater than 1x10 ²⁰ /cm ³ , greater than 1.3x10 ²⁰ /cm ³ , greater than 1.6x10 ²⁰ /cm ³ , greater than 2.0x10 ²⁰ /cm ³ , greater than 2.5x10 ²⁰ /cm ³ or greater than 3.0x10 ²⁰ /cm ³ .

The above carbon doping concentrations were measured by secondary ion mass spectrometry (SIMS).

The above-mentioned P-type first semiconductor layer or the above-mentioned P-type second semiconductor layer includes at least one material of the group consisting of GaAs, InGaAs, GaAsP, GaAsPSb, GaAsSb, AlGaAs, AlGaAsSb, AlGaAsP, InAlGaAs, InAlGaP, InGaAsSb, GaPSb and InGaAsP.

In some embodiments, when only one oxide layer is provided in the VCSEL and the oxide layer is provided in the upper epitaxial region, the first (second) tunneling junction layer may be provided in the upper epitaxial region, the active region or the lower epitaxial region.

In some embodiments, when only one oxide layer is provided in the VCSEL and the oxide layer is provided in the lower epitaxial region, the first (second) tunneling junction may be provided in the lower epitaxial region, the active region or the upper epitaxial region.

The formation position of the oxide layer in the upper epitaxial region or the lower epitaxial region is not limited to the above embodiment. According to the VCSEL with different structures, the formation position and the number of the oxide layer can be appropriately changed.

The above-mentioned embodiment arranges the first (second) tunnel junction layer in the first upper (lower) spacer layer or the second upper (lower) spacer layer, which is only used to illustrate that the first (second) tunnel junction layer can be arranged in the epitaxial layer other than the upper DBR layer, and does not mean that the first upper (lower) spacer layer and/or the second (lower) upper spacer layer must be arranged in the upper (lower) epitaxial region. Because the upper epitaxial region or the lower epitaxial region may not form a spacer layer according to different purposes or characteristics of VCSEL. Alternatively, in addition to forming a spacer layer, the upper (lower) epitaxial region may also form other epitaxial layers, so the arrangement position and number of the first (second) tunnel junction layer can be appropriately changed according to various structures of VCSEL.

The first tunnel junction layer or the second tunnel junction layer of the above embodiment can also be disposed alone or further in the active region A including multiple active layers, and the preferred material, doping material and other conditions mentioned above of the first tunnel junction layer or the second tunnel junction layer are the same as those of the above embodiment.

[Example 5-1]

Referring to FIG. 7 , an active layer 32 is epitaxially grown on the lower epitaxial region (not shown). An oxide layer 36 is formed on the active layer 32; then, a P-type first semiconductor layer 601 and an N-type first semiconductor layer 603 are sequentially formed on the oxide layer 36; an active layer 33 and an upper epitaxial region are continuously formed on the N-type first semiconductor layer 603; the upper epitaxial region includes a first upper spacer layer 34, an oxide layer 37, an upper DBR layer 40 and an ohmic contact layer 50. Thus, a first tunneling junction layer 60 is provided in the active region A.

[Example 5-2]

If a P-type second semiconductor layer and an N-type second semiconductor layer (or an N-type second semiconductor layer and a P-type second semiconductor layer) are sequentially formed on the oxide layer 36 of FIG. 7 ; an active layer 33 and an upper epitaxial region are sequentially formed on the P-type second semiconductor layer (N-type second semiconductor layer), then the second tunneling junction layer is disposed in the active region.

[Example 6]

The number of active layers can be three or more than four, and every two adjacent active layers do not need to be connected in series through the first tunneling junction layer and/or the second tunneling junction layer. For example, when there are three active layers, the three active layers can be connected in series through the first tunneling junction layer (or the second tunneling junction layer) and the existing tunneling junction layer. In this case, the upper epitaxial region or the lower epitaxial region can also be provided with the existing tunneling junction layer. An active layer can include one or more quantum well layers.

The first (second) tunnel junction layer with high doping concentration has a lower resistance when the appropriate material is selected. Therefore, by connecting two or more active layers in series through the first (second) tunnel junction, the power loss in the active region is reduced, and the light output power or photoelectric characteristics of the VCSEL are improved. The two active layers may also include but are not limited to a spacer layer and/or an oxide layer. In some embodiments, the first tunnel junction layer or the second tunnel junction layer may be disposed in the spacer layer in the active region.

[Example 7]

When the VCSEL includes multiple oxide layers, the number of the first (second) tunnel junction layers can be one or more; for example, when the lower epitaxial region, the active region with multiple active layers, and the upper epitaxial region each include at least one oxide layer, the number of the first (second) tunnel junction layers may be only one layer to facilitate the oxidation process, such as arranging the first (second) tunnel junction layer between the active region and the upper (lower) epitaxial region. According to different epitaxial structures of the VCSEL, the number and arrangement method of the first (second) tunnel junctions can be further increased and changed.

[Example 8-1]

When the N-type first semiconductor layer 603 of the above embodiment is formed on the upper DBR layer 40 of FIG. 1 , the N-type first semiconductor layer 603 can form a good ohmic contact with the metal material due to its high doping concentration, small energy gap and small resistance. Therefore, the N-type first semiconductor layer can be used as an ohmic contact layer.

[Example 8-2]

The N-type second semiconductor layer of the above embodiment is formed on the upper DBR layer 40 of FIG1 . Since the N-type second semiconductor layer has high doping concentration, small energy gap and small resistance, the N-type second semiconductor layer can easily form a good ohmic contact with the metal material, and therefore, the N-type second semiconductor layer can be used as an ohmic contact layer.

[Example 8-3]

Referring to FIG. 8 , the VCSEL in FIG. 8 may be a back-emitting type or a front-emitting type VCSEL. As shown in FIG. 8 , the VCSEL 100 includes two ohmic contact layers 50 and 51. The ohmic contact layer 51 is formed in the N-type lower DBR layer 20 , and the ohmic contact layer 51 may also include an N-type first semiconductor layer 601 .

[Example 8-4]

As shown in FIG9 , the N-type first semiconductor layer 603 in the upper DBR layer 40 is not only a part of the first tunnel junction layer 60, but also can be used as an ohmic contact layer.

[Example 9]

As shown in FIG. 10 , the VCSEL includes two first tunneling junction layers 60 and an N-type first semiconductor layer 603. The N-type first semiconductor layer 603 on the upper DBR layer 40 can be used as an ohmic contact layer; the two first tunneling junction layers 60 are respectively disposed in the active region A and the upper DBR layer 40. The two first tunneling junction layers 60 can also be replaced by two second tunneling junction layers or a first tunneling junction layer and a second tunneling junction layer.

The preferred material of the N-type first semiconductor layer as the ohmic contact layer includes at least one material selected from the group consisting of InGaAs, GaAsSb, GaAsPSb, AlGaAs, AlGaAsSb, AlGaAsP, InAlGaAs, InGaAsSb, InGaAsP and GaPSb. In principle, the smaller the energy gap of the N-type first semiconductor layer as the ohmic contact layer, the easier it is to form an ohmic contact with a metal material.

Refer to FIG. 11 . The five oxidation rates shown in FIG. 11 correspond to five VCSELs. The main structures of these five VCSELs are the same as those in FIG. 7 . Three of the VCSELs have the first tunneling junction layer in the active region, while the other VCSEL has the existing tunneling junction layer in the active region. In addition, a VCSEL with "GaAs without Te doping" in the active region is used as a control group. In the five VCSELs, the material of the oxide layer in the active region and the upper epitaxial region is AlGaAs and the aluminum content is about 98%, and the P-type (first) semiconductor layer in the (first) tunneling junction layer is GaAs with a carbon doping concentration of 1.0x10 ²⁰ /cm ³ .

The VCSEL used as the control group has a "GaAs layer not doped with Te" between the P-type semiconductor layer 601 and the active layer 33. The N-type semiconductor layer of the existing tunnel junction layer is "GaAs doped with Te". The three N-type first semiconductor layers are "InGaAs doped with Te", "GaAsSb doped with Te" and "GaAsP doped with Te", and the Te doping concentration of the above-mentioned layers is 2.5x10 ¹⁹ /cm ³ .

It is worth reiterating that the three N-type first semiconductor layers have stress relative to the GaAs substrate, but the N-type semiconductor layer in the existing tunneling junction layer does not.

Refer to Figure 11, which shows the oxidation rate of the oxide layer in the active region of the five VCSELs after the oxidation process under the same oxidation process conditions. As shown in Figure 11, the VCSEL in the control group has the fastest oxidation rate of the oxide layer; in Figure 11, the oxidation rate of "GaAs without Te doping" is set to 100%, and the oxidation rate of "GaAs without Te doping" is used as the comparison benchmark with the other four VCSELs.

However, when the N-type semiconductor layer of the existing tunnel junction layer is "GaAs doped with Te" (relative to the GaAs substrate, which has no stress), the oxidation rate of the oxide layer 36 in the active region is significantly reduced; if the Te doping concentration is higher, the oxidation rate of the oxide layer may further decrease.

Compared with the "GaAs doped with Te" without stress (relative to the GaAs substrate), the three N-type first semiconductor layers with stress (relative to the GaAs substrate) all increase the oxidation rate of the oxide layer to a certain extent, among which the "GaAsSb doped with Te" is very close to the oxidation rate of GaAs without Te.

Refer to FIG. 12 . The four oxidation rates shown in FIG. 12 correspond to four VCSELs. The main structures of these four VCSELs are the same as FIG. 7 . Two of the VCSELs have a second tunneling junction layer in the active region, while the other VCSEL has an existing tunneling junction layer in the active region. In addition, a VCSEL with "GaAs without Te doping" in the active region is used as a control group. In the four VCSELs, the material of the oxide layer set in the active region and the upper epitaxial region is AlGaAs and the aluminum content is about 98%, and the P-type (second) semiconductor layer in the (second) tunneling junction layer is GaAs with a carbon doping concentration of 8x10 ¹⁹ /cm ³ .

The VCSEL used as the control group has a "GaAs layer not doped with Te" between the P-type semiconductor layer 601 and the active layer 33. The N-type semiconductor layer of the existing tunnel junction layer is "GaAs doped with Te". The two types of second tunnel junction layers are "GaAs doped with Te and C" and "GaAs doped with Te and Si", and the Te doping concentrations are both 2.5x10 ¹⁹ /cm ³ , the carbon doping concentration is 3x10 ¹⁸ /cm ³ , and the silicon doping concentration is 2x10 ¹⁸ /cm ³ .

Refer to Figure 12, which shows the oxidation rate of the oxide layer in the active region of the four VCSELs when the four VCSELs are oxidized under the same oxidation process conditions. As shown in Figure 12, the VCSEL in the control group has the fastest oxidation rate of the oxide layer; in Figure 12, the oxidation rate of "GaAs without Te doping" is set to 100%, and the oxidation rate of "GaAs without Te doping" is used as the comparison benchmark with the other three VCSELs.

Different from the existing N-type semiconductor layer, the N-type second semiconductor layer doped with the above two elements can increase the oxidation rate of the oxide layer to a certain extent (without the need for stress relative to the GaAs substrate).

The above is only used to explain the preferred embodiments of the present invention, and is not intended to limit the present invention in any form. Therefore, any modification or change of the present invention made under the same spirit of the invention should still be included in the scope of protection intended by the present invention.

100: VCSEL 10: GaAs substrate 12: Buffer layer 20: Lower DBR layer 201: P-type upper DBR layer 203: N-type upper DBR layer 30: First lower spacer layer 301: P-type first lower spacer layer 303: N-type first lower spacer layer A: Active region 32, 33: Active layer 34: First upper spacer layer 341: P-type first upper spacer layer 343: N-type first upper spacer layer 36 , 37: oxide layer 38: second upper spacer layer 381: P-type second upper spacer layer 383: N-type second upper spacer layer 39: second lower spacer layer 391: P-type second lower spacer layer 393: N-type second lower spacer layer 40: upper DBR layer 401: P-type upper DBR layer 403: N-type upper DBR layer 50: ohmic contact layer 60: first tunneling junction layer 601: P-type first semiconductor layer 603: N-type first semiconductor layer

FIG. 1 is a schematic diagram of a first tunneling junction layer disposed on an upper DBR layer according to an embodiment described. FIG. 2 is a schematic diagram of a first tunneling junction layer disposed on a first upper spacer layer according to an embodiment described. FIG. 3 is a schematic diagram of a first tunneling junction layer disposed on a second upper spacer layer according to an embodiment described. FIG. 4 is a schematic diagram of a first tunneling junction layer disposed on a lower DBR layer according to an embodiment described. FIG. 5 is a schematic diagram of a first tunneling junction layer disposed on a first lower spacer layer according to an embodiment described. FIG. 6 is a schematic diagram of a first tunneling junction layer disposed on a second lower spacer layer according to an embodiment described. FIG. 7 is a schematic diagram of a first tunnel junction layer disposed between two active layers according to an embodiment described, and an oxide layer is respectively provided in the active region and the upper epitaxial region. FIG. 8 is a schematic diagram of a first N-type semiconductor layer disposed on a lower DBR layer as an ohmic contact layer according to an embodiment described. FIG. 9 is a schematic diagram of a first N-type semiconductor layer disposed on an upper DBR layer as an ohmic contact layer according to an embodiment described. FIG. 10 is a schematic diagram of a VCSEL having two first tunnel junction layers and a first semiconductor layer according to an embodiment described. FIG11 is a schematic diagram showing the oxidation rate of the oxide layer in the active region when three embodiments of the N-type first semiconductor layer and the existing N-type semiconductor layer and the N-type GaAS layer are respectively formed between the two active layers of the VCSEL. FIG12 is a schematic diagram showing the oxidation rate of the oxide layer in the active region when two embodiments of the N-type second semiconductor layer and the existing N-type semiconductor layer and the N-type GaAS layer are respectively formed between the two active layers of the VCSEL.

100:VCSEL

10:GaAs substrate

12: Buffer layer

20: Lower DBR layer

30: First lower compartment layer

32: Active layer

34: First upper compartment layer

36: Oxide layer

40: Upper DBR layer

401: P-type upper DBR layer

403: N-type upper DBR layer

50: Ohm contact layer

60: First tunneling junction layer

601: P-type first semiconductor layer

603: N-type first semiconductor layer

A: Active zone

Claims (21)

A vertical resonant cavity surface emitting laser diode comprises: a GaAs substrate; and an epitaxial structure formed on the GaAs substrate, the epitaxial structure comprising: at least one oxide layer; and a first tunneling junction layer comprising an N-type first semiconductor layer, the N-type first semiconductor layer being disposed above or below the oxide layer, the N-type first semiconductor layer being doped with at least Te and/or Se, and the lattice constant of the material of the N-type first semiconductor layer being different from the lattice constant of the GaAs substrate, so that the N-type first semiconductor layer has stress relative to the GaAs substrate; wherein the at least one oxide layer is formed into a current limiting through hole after an oxidation process. A vertical cavity surface emitting laser diode as described in claim 1, wherein the first tunnel junction layer further comprises a P-type first semiconductor layer, the P-type first semiconductor layer is doped with carbon, and the carbon doping concentration of the P-type first semiconductor layer is greater than 1x10 ¹⁹ /cm ³ . A vertical resonant cavity surface emitting laser diode as described in claim 1, wherein the first tunneling junction layer further comprises a P-type first semiconductor layer, and the P-type first semiconductor layer comprises at least one material selected from the group consisting of GaAs, InGaAs, GaAsP, GaAsPSb, GaAsSb, AlGaAs, AlGaAsSb, AlGaAsP, InAlGaAs, InAlGaP, InGaAsSb, GaPSb and InGaAsP. A vertical resonant cavity surface emitting laser diode as described in claim 1, wherein the epitaxial structure further comprises an upper DBR layer and a lower DBR layer, and the first tunneling junction layer is included in the upper DBR layer or the lower DBR layer. A vertical resonant cavity surface emitting laser diode as described in claim 1, wherein the epitaxial structure further comprises an active region, the active region comprises a plurality of active layers, wherein the first tunneling junction layer is between two active layers. A vertical resonant cavity surface emitting laser diode as described in claim 1, wherein the epitaxial structure further comprises an active region and at least one spacer layer, the at least one spacer layer is located above or below the active region, and the first tunneling junction layer is included in the at least one spacer layer. A vertical resonant cavity surface emitting laser diode as described in claim 1, wherein the epitaxial structure further comprises an active region, the active region comprises a plurality of active layers and at least one spacer layer, the at least one spacer layer is between two active layers, and the first tunneling junction layer is formed in the at least one spacer layer. A vertical resonant cavity surface emitting laser diode as described in claim 5, wherein the epitaxial structure further comprises another oxide layer, and the other oxide layer is between the two active layers. A vertical cavity surface emitting laser diode as described in any one of claims 1 to 8, wherein the N-type first semiconductor layer comprises at least one material selected from the group consisting of InGaAs, InGaP, GaAsP, GaAsSb, GaAsPSb, AlGaAs, AlGaAsSb, AlGaAsP, InAlGaAs, InAlGaP, InGaAsSb, InGaAsP and GaPSb. A vertical cavity surface emitting laser diode as described in claim 9, wherein the lattice constant of InGaP and InAlGaP is greater than the lattice constant of the GaAs substrate. A vertical resonant cavity surface emitting laser diode as described in any one of claims 1 to 8, wherein the N-type first semiconductor layer is further doped with Si and/or C. A vertical cavity surface emitting laser diode as described in claim 11, wherein the N-type first semiconductor layer is at least one material selected from the group consisting of InGaAs, InGaP, GaAsP, GaAsSb, GaAsPSb, AlGaAs, AlGaAsSb, AlGaAsP, InAlGaAs, InAlGaP, InGaAsSb, InGaAsP and GaPSb. A vertical cavity surface emitting laser diode as described in claim 12, wherein the lattice constants of InGaP and InAlGaP are greater than the lattice constant of the GaAs substrate. A vertical resonant cavity surface emitting laser diode comprises: a GaAs substrate; and an epitaxial structure formed on the GaAs substrate, the epitaxial structure comprising: at least one oxide layer; and a second tunneling junction layer comprising an N-type second semiconductor layer, the N-type second semiconductor layer being disposed above or below the oxide layer, the N-type second semiconductor layer comprising an N-type GaAs layer, the N-type GaAs layer being doped with at least one doping material selected from the group consisting of Te and Se and at least one doping material selected from the group consisting of Si and C; wherein the at least one oxide layer is formed into a current limiting through hole after an oxidation process. A vertical cavity surface emitting laser diode as described in claim 14, wherein the second tunnel junction layer further comprises a P-type second semiconductor layer, the P-type second semiconductor layer is doped with carbon, and the carbon doping concentration of the P-type second semiconductor layer is greater than 1x10 ¹⁹ /cm ³ . A vertical resonant cavity surface emitting laser diode as described in claim 14, wherein the second tunneling junction layer further comprises a P-type second semiconductor layer, and the P-type second semiconductor layer comprises at least one material selected from the group consisting of GaAs, InGaAs, GaAsP, GaAsPSb, GaAsSb, AlGaAs, AlGaAsSb, AlGaAsP, InAlGaAs, InAlGaP, InGaAsSb, GaPSb and InGaAsP. A vertical resonant cavity surface emitting laser diode as described in claim 14, wherein the epitaxial structure further comprises an upper DBR layer and a lower DBR layer, and the second tunneling junction layer is included in the upper DBR layer or the lower DBR layer. A vertical resonant cavity surface emitting laser diode as described in claim 14, wherein the epitaxial structure further comprises an active region, the active region comprises a plurality of active layers, wherein the second tunneling junction layer is between two active layers. A vertical resonant cavity surface emitting laser diode as described in claim 14, wherein the epitaxial structure further comprises an active region and at least one spacer layer, the at least one spacer layer is located above or below the active region, and the second tunneling junction layer is included in the at least one spacer layer. A vertical resonant cavity surface emitting laser diode as described in claim 14, wherein the epitaxial structure further comprises an active region, the active region comprises a plurality of active layers and at least one spacer layer, the at least one spacer layer is between two active layers, and the second tunneling junction layer is formed in the at least one spacer layer. A vertical resonant cavity surface emitting laser diode as described in claim 18, wherein the epitaxial structure further comprises another oxide layer, and the other oxide layer is between the two active layers.