TWI838125B - Semiconductor package and manufacturing method thereof - Google Patents

Abstract

A semiconductor package includes a lead frame, a plurality of conductive pillars, a chip and a molding compound. The lead frame includes a die pad and a plurality of leads. The plurality of conductive pillars are disposed on the plurality of leads and electrically connected to the plurality of leads. The chip is disposed on the die pad and electrically connected to the plurality of leads. The molding compound encapsulates the chip, the lead frame and the plurality of conductive pillars. The molding compound exposes bottom surfaces of the plurality of leads and top surfaces of the plurality of conductive pillars.

Description

Semiconductor package and manufacturing method thereof

The present disclosure relates to a semiconductor package and a manufacturing method thereof.

As electronic products become smaller, the market for handheld products continues to expand. Driven primarily by the mobile phone and digital assistant markets, manufacturers of these devices are facing the challenge of product size compression and the need for more personal computer functions. The additional functions can only be achieved through high-performance logic integrated circuits combined with increased memory capacity. In response to this challenge, smaller printed circuit boards will put pressure on surface mount component manufacturers to design products.

In today's handheld product market, many widely used components are beginning to transition from pinned to pinless forms. This has led to electronic components being designed to save printed circuit board space. The extra space saved can be used to configure components required for additional device functions.

Most of the widely used leadless package structures such as Quad Flat No Leads (QFN) or Dual Flat No-Lead (DFN) have electrical connection pads on one side as terminals for external connections. Therefore, they can only perform planar (2D) package mounting operations, but cannot perform three-dimensional (3D) stacking settings, making it difficult to further expand the functions and performance of this package structure.

The present disclosure provides a semiconductor package and a manufacturing method thereof, which can achieve the purpose of three-dimensional stacking of the original lead frame semiconductor package and can also improve the function and performance of the semiconductor package.

A semiconductor package disclosed herein includes a lead frame, a plurality of conductive pillars, and a chip. The lead frame includes a chip seat and a plurality of pins. The plurality of conductive pillars are disposed on the plurality of pins and electrically connected to the plurality of pins. The chip is disposed on the chip seat and electrically connected to the plurality of pins. A packaging colloid covers the chip, the lead frame, and the plurality of conductive pillars, wherein the packaging colloid exposes the lower surfaces of the plurality of pins and the top surfaces of the plurality of conductive pillars.

The present invention discloses a method for manufacturing a semiconductor package, comprising the following steps: providing a lead frame, wherein the lead frame comprises a chip base and a plurality of pins; providing a plurality of conductive posts on the plurality of pins and electrically connecting the plurality of conductive posts to the plurality of pins; placing a chip on the chip base and electrically connecting the chip to the plurality of pins; and forming a packaging colloid to cover the chip, the lead frame and the plurality of conductive posts.

Based on the above, the conductive pillars in the semiconductor package disclosed in the present invention can be arranged on at least part of the pins of the lead frame as needed, and the chip is arranged on the chip seat of the lead frame, and the packaging colloid exposes the lower surface of the pins and the top surface of the conductive pillars. In this configuration, the lower surface of the pins and the top surface of the conductive pillars exposed by the packaging colloid can be electrically connected to other components respectively, so that the semiconductor package can be stacked on the upper and lower sides of the packaging colloid respectively. Other substrates or packaging components can be stacked to achieve the purpose of three-dimensional stacking, and the function and performance of the semiconductor package can be improved.

The above-mentioned and other technical contents, features and effects of the present disclosure will be clearly presented in the detailed description of each embodiment with reference to the drawings below. The directional terms mentioned in the following embodiments, such as "up", "down", "front", "back", "left", "right", etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used for explanation, not for limiting the present disclosure. In addition, in the following embodiments, the same or similar components will adopt the same or similar labels.

Figures 1 to 7 are schematic cross-sectional views of a process of manufacturing a semiconductor package according to an embodiment of the present disclosure. In some embodiments, the method for manufacturing a semiconductor package may include the following steps. First, referring to Figure 1, a lead frame 110 is provided, wherein the lead frame 110 includes a chip base 112 and a plurality of pins 114. In this embodiment, the pins 114 may surround the chip base 112 and be disposed at the periphery of the chip base 112. In one embodiment, the lead frame 110 may be formed into a patterned lead frame by performing an etching process on a metal layer.

Next, please refer to Figure 2, provide a plurality of conductive posts 120 on a plurality of pins 114, and electrically connect the conductive posts 120 to the corresponding pins 114. The conductive posts 120 may be formed of a conductive material, such as copper, gold, silver, titanium, tungsten, aluminum and/or the like. In the present embodiment, the conductive posts 120 may be a preformed structure, and the conductive posts 120 are attached to the corresponding pins 114 via a solder layer 130. In the present embodiment, the conductive posts 120 may be copper posts or metal posts formed of other possible conductive materials mentioned above. In one embodiment, the conductive posts 120 may be selectively disposed on the corresponding pins 114 or all of the pins 114, for example, by a pick and place mechanism.

Specifically, the step of disposing the conductive pillar 120 on the plurality of pins 114 may include the following steps. First, a solder layer 130 is provided between the conductive pillar 120 and the corresponding pin 114. In one embodiment, the solder layer 130 may be first disposed on the corresponding pin 114, and then the conductive pillar 120 is placed on the solder layer 130. Of course, in other embodiments, the solder layer 130 may also be first disposed on the bottom surface of the conductive pillar 120, and then the conductive pillar 120 provided with the solder layer 130 may be disposed on the corresponding pin 114. The present disclosure is not limited to this. In some embodiments, the solder layer 130 may be disposed between the conductive pillar 120 and the corresponding pin 114 using, for example, electroplating or chemical plating, screen printing, coating, or the like. Then, a reflow process may be performed to join the conductive pillar 120 and the corresponding pin 114 via the solder layer 130. In this embodiment, the solder layer 130 may be any conductive material that can accept reflow, such as lead-free solder, solder paste, etc. In one embodiment, before providing the solder layer 130, a flux may be applied between the conductive pillar 120 and the corresponding pin 114. The flux can form a thin film on the surface of the solder layer 130 in the subsequent reflow process to isolate the air and prevent the solder layer 130 from being easily oxidized. Of course, this embodiment is only used for illustration, and the present disclosure does not limit the formation method of the conductive pillar 120 and the solder layer 130.

Next, referring to FIG. 3 , a chip 140 is placed on the chip base 112, and the chip 140 is electrically connected to the corresponding pins 114. In one embodiment, the chip 140 may include a plurality of contacts 142, which may be formed on the active surface S1 of the chip 140. In this embodiment, the chip 140 may include a display driver circuit integrated circuit (IC), an image sensor integrated circuit, a memory integrated circuit, a logic integrated circuit, an analog integrated circuit, an ultra-high frequency (UHF) integrated circuit, or a radio frequency (RF) integrated circuit, but the present disclosure is not limited thereto. In the present embodiment, the chip 140 may be disposed on the lead frame 110 and electrically connected to the corresponding pins 114 by, for example, wire bonding. Specifically, the semiconductor package may further include a plurality of wires 150, wherein the chip 140 includes an active surface S1 having a plurality of contacts 142 and a back surface S2 opposite to the active surface S1, and the chip 140 is disposed on the chip base 112 with the back surface S2, and the wires 150 are connected between the contacts 142 of the chip 140 and the pins 114 of the lead frame 110 to electrically connect the chip 140 and the lead frame 110. In the present embodiment, the chip 140 may be attached to the chip base 112 via a die attach film (DAF). Of course, the present disclosure does not limit the method of placing the chip 140 on the chip base 112 and electrically connecting the chip 140 to the corresponding pins 114 .

It is worth noting that in the aforementioned embodiments, the conductive pillars 120 in the present disclosure are first set on the corresponding pins 114 and then the chip 140 and the wire bonding process are performed, but the present disclosure is not limited to this. In other feasible embodiments, the process sequence of the chip 140, the conductive pillars 120 and the wire bonding process can be adjusted as needed. For example, the present disclosure can first place the chip 140 on the chip seat 112, and then set the conductive pillars 120 on the corresponding pins 114, and then perform wire bonding to electrically connect the chip 140 to the pins 114. Alternatively, the chip 140 can be placed on the chip seat 112 first and then wire bonding can be performed, and then the conductive pillars 120 can be placed on the corresponding pins 114. This also falls within the scope of application of the present disclosure.

Next, referring to FIG. 4 , a packaging body 160 is formed to cover the chip 140, the lead frame 110, and the conductive pillar 120. The packaging body 160 may be formed, for example, by a molding process. In the present embodiment, the wire 150 is also encapsulated in the packaging body 160. For example, the packaging body 160 may include an epoxy resin. In the present embodiment, the packaging body 160 may fully cover the chip 140, the wire 150, and the conductive pillar 120 at this stage, and the packaging body 160 exposes the lower surface of the chip base 112 and the lead 114.

Next, referring to FIG. 5 , the packaging colloid 160 is subjected to a thinning process so that the packaging colloid 160 exposes the top surface of the conductive pillar 120. In the present embodiment, the packaging colloid 160 can be subjected to a thinning process such as chemical mechanical polishing, laser thinning and/or grinding using a thinning jig 50 until the top surface of the conductive pillar 120 is exposed. In other words, the present embodiment can utilize a thinning process such as chemical mechanical polishing, laser thinning and/or grinding to remove the packaging colloid 160 above the top surface of the conductive pillar 120 so that the top surface of the conductive pillar 120 is substantially coplanar with the top surface of the packaging colloid 160. In this way, the packaging gel 160 can expose at least the lower surface of the lead 114 and the top surface of the conductive pillar 120. At this point, the manufacturing method of the package 100 can be substantially completed.

Please continue to refer to Figures 5 and 6. In some embodiments, since the packaging body 160 of the package 100 shown in Figure 5 exposes at least the lower surface of the pin 114 and the top surface of the conductive column 120, the package 100 can be electrically connected to other components on its upper and lower sides. For example, in the embodiment of Figure 6, the substrate 200 can be placed on the bottom surface of the packaging body 160 of the package 100 and form an electrical connection with the pin 114. In one embodiment, the substrate 200 includes a plurality of electrical contacts 232, which are respectively connected to the lower surface of the pin 114 exposed by the packaging body 160. In the present embodiment, the substrate 200 may further include a plurality of electrical vias 234 and a plurality of electrical contacts 236, wherein the electrical contacts 232 and the electrical contacts 236 may be respectively disposed on two opposite surfaces of the substrate 200, and the electrical vias 234 may extend through the substrate 200 to electrically connect the electrical contacts 232 and the electrical contacts 236. Thus, the electrical contacts 232, the electrical vias 234, the electrical contacts 236 and other conductive elements may together form an electrical conductive path 230 to electrically connect two opposite surfaces of the substrate 200. In the present embodiment, the substrate 200 may include electronic elements such as a circuit board, an interposer, and a wafer that may be electrically connected to the package 100.

In one embodiment, the substrate 200 may further selectively include an upper heat sink 222, a lower heat sink 226 and a heat dissipation hole 224, wherein the upper heat sink 222 and the lower heat sink 226 may be respectively disposed on two opposite surfaces (upper and lower surfaces) of the substrate 200, and the heat dissipation hole 224 may extend through the substrate 200 to connect between the upper heat sink 222 and the lower heat sink 226, so as to form a thermal coupling between the upper heat sink 222 and the lower heat sink 226. In one embodiment, the upper heat sink 222 can be in contact with the chip base 112 to form a thermal coupling, so that the heat energy generated by the chip 140 can be transferred downward to the chip base 112, and then transferred to the lower surface of the substrate 200 through the heat conduction path 220 formed by the upper heat sink 222, the heat dissipation through hole 224 and the lower heat sink 226 to help the chip 140 to dissipate heat. In this embodiment, the upper heat sink 222, the lower heat sink 226 and the heat dissipation through hole 224 can be electrically insulated from other electrical components of the substrate 200 (such as electrical contacts 232, 236 and electrical conductive holes 234, etc.). In another feasible embodiment, the upper heat sink 222, the heat sink holes 224 and the lower heat sink 226 can also be used as other non-electrically connected circuits, such as grounding or anti-static circuits, etc., rather than being limited to heat dissipation purposes.

Next, please refer to FIG. 7. In this embodiment, an upper package 100a is disposed on the top surface of the packaging colloid 160, and the upper package 100a includes a plurality of electrical contacts 170, which are respectively connected to the top surfaces of the conductive posts 120 exposed by the packaging colloid 160. In this embodiment, the upper package 100a may be substantially similar to the structure of the package 100 (also including components such as a lead frame, a chip, a wire, and a packaging colloid). However, in other embodiments, the upper package 100a may also be a package that is completely different in structure from the package 100, as long as its electrical contacts 170 can be electrically connected to the conductive posts 120 of the package 100. At this point, the method for manufacturing the semiconductor package 10 can be substantially completed.

FIG8 is a cross-sectional schematic diagram of a semiconductor package according to an embodiment of the present disclosure. It should be noted that the semiconductor package 10a of the present embodiment is similar to the semiconductor package 10 of the aforementioned embodiment. The differences between the semiconductor package 10a of the present embodiment and the semiconductor package 10 of the aforementioned embodiment will be described below.

In this embodiment, the upper package 300 of the semiconductor package 10a may be a package having a structure completely different from that of the package 100. The upper package 300 may include components such as an upper substrate 310, an upper chip 320, an upper bump 330, and an upper package colloid 340. Specifically, the upper chip 320 is disposed on the upper substrate 310 and may be electrically connected to the upper substrate 310 through the upper bump 330, for example, by flip chip bonding. The upper package colloid 340 is disposed on the upper substrate 310 and encapsulates the upper chip 320 and the upper bump 330 therein.

In one embodiment, the package 300 stacked on the package 100 may include a semiconductor device such as a memory device, which may be used to provide stored data to the chip 140 in the package 100. In such an embodiment, the chip 140 may include a memory control module, which may provide control functions for the memory device of the package 300. However, this embodiment is only used for illustration, and the present disclosure does not limit the types and functions of the packages stacked on the package 100.

Fig. 9 is a top view of some components of a semiconductor package according to an embodiment of the present disclosure. The differences between the package 100 of this embodiment and the package of the aforementioned embodiment will be described below.

Please refer to FIG. 9 . In this embodiment, the pins 114 include a plurality of first pins 1141 and at least one second pin 1142, wherein a plurality of conductive pillars 120 are respectively disposed on the plurality of first pins 1141. In one embodiment, the conductive pillar 120 is not disposed on the second pin 1142. In other words, the conductive pillar 120 is not disposed on all the pins 114, but is selectively disposed on a portion of the pins 114 according to actual electrical requirements, and has an adjustable flexibility in circuit design. In addition, in the present embodiment, the contacts 142 of the chip 140 may be disposed along two opposite sides of the chip 140, and the pins 114 and the corresponding conductive pillars 120 may also be disposed correspondingly on two opposite sides of the chip 140, so that they may be connected to the corresponding contacts 142 via the wires 150. However, in other embodiments, the contacts 142 of the chip 140 may also be disposed around all edges of the chip 140, for example, along four sides of the chip 140. In this way, the pins 114 and the corresponding conductive pillars 120 may also be disposed correspondingly around the four sides of the chip 140, so that they may be connected to the corresponding contacts 142 via the wires 150. The present disclosure is not limited thereto.

10 is a schematic diagram of a conductive pillar of a semiconductor package according to an embodiment of the present disclosure. The difference between the conductive pillar 120a of this embodiment and the conductive pillar 120 of the above-mentioned embodiment will be described below.

Please refer to Figures 2 and 10. In the present embodiment, the conductive column 120a may include a copper column core 122 and a solder layer 124. Specifically, the method of providing the conductive column 120a may include the following steps. First, a solder layer 124 is formed on the copper column core 122 of the conductive column 120a, so that the solder layer 124 at least covers the side surface of the copper column core 122. In the present embodiment, the solder layer 124 may be a tin layer, which may be formed, for example, by electroplating to cover the side surface of the copper column core 122. In the present embodiment, the thickness of the solder layer 124 formed by electroplating is approximately between 10 micrometers (μm) and 20 micrometers, for example, about 15 micrometers. In one embodiment, after forming the solder layer 124, a flux can be applied on the conductive pillar 120a or the corresponding lead 114, which can form a thin film on the surface of the solder layer 124 to isolate the air in the subsequent reflow process, so that the solder layer 124 is not easily oxidized. Then, the reflow process is performed to join the conductive pillar 120a and the corresponding lead 114 through the solder layer 124. Of course, the present disclosure does not limit the method for forming the conductive pillar. In other embodiments, the conductive pillar can also be formed directly on the lead of the lead frame by electroplating by providing a patterned photoresist layer and a seed layer directly on the lead frame.

11 to 13 are schematic cross-sectional views of a process of manufacturing a semiconductor package according to an embodiment of the present disclosure. The differences between the semiconductor package manufacturing method of this embodiment and the semiconductor package manufacturing method of the aforementioned embodiment will be described below.

Please refer to FIG. 11 . In the present embodiment, the chip 140 is disposed on the chip seat 112a by means of flip chip bonding. Specifically, the chip seat 112a is composed of a plurality of extension portions 112a extending from a plurality of pins 114a to a central region of the lead frame 110a, and a plurality of contacts of the chip 140 are respectively connected to the plurality of extension portions 112a. In other words, the lead frame 110a includes a plurality of pins 114a disposed around a center point of the lead frame 110a, and each pin 114a includes an extension portion 112a extending in a direction toward the center point. These extension portions 112a surrounding the center point together constitute a chip seat 112a on which the chip 140 is disposed. In this way, the chip 140 can be disposed on the chip seat 112 by means of flip chip bonding via a plurality of bumps 180.

Next, as described in the aforementioned embodiment, a plurality of conductive posts 120 are provided on a plurality of pins 114a, and the conductive posts 120 are electrically connected to the corresponding pins 114a. In the present embodiment, the conductive posts 120 may be a preformed structure, and the conductive posts 120 are attached to the corresponding pins 114 via a solder layer 130. In the present embodiment, the conductive posts 120 may be copper posts or metal posts formed of the above-mentioned other possible materials. In the present embodiment, the solder layer 130 may be disposed between the conductive posts 120 and the corresponding pins 114a. In some embodiments, the solder layer 130 may be disposed between the conductive pillar 120 and the corresponding pin 114a using, for example, electroplating or chemical plating, screen printing, coating, or the like. Then, a reflow process may be performed to join the conductive pillar 120 and the corresponding pin 114a via the solder layer 130. In this embodiment, the solder layer 130 may be any conductive material that can accept reflow, such as lead-free solder, solder paste, etc. In one embodiment, before providing the solder layer 130, a flux may be applied between the conductive pillar 120 and the corresponding pin 114a.

Next, the chip 140 is placed on the chip seat 112a, and the chip 140 is electrically connected to the corresponding pins 114a. As described in the aforementioned embodiment, the chip 140 may be flip-chip placed on the chip seat 112a earlier than the conductive pillars 120 are placed on the lead frame 110a. In other words, the chip 140 may be first placed on the chip seat 112a by flip-chip bonding, and then the conductive pillars 120 may be placed on the plurality of pins 114a of the lead frame 110a. The present disclosure does not limit the order in which the chip 140 and the conductive pillars 120 are placed. In the present embodiment, the chip 140 is, for example, placed on the chip seat 112a of the lead frame 110a by flip-chip bonding, and is electrically connected to the corresponding pins 114a. In this embodiment, the chip 140 is bonded to the chip base 112a (multiple extensions of the multiple leads 114a) via multiple bumps 180. Of course, the present disclosure does not limit the method of disposing the chip 140 on the chip base 112a.

Next, referring to FIG. 12 , a packaging resin 160 is formed to cover the chip 140, the lead frame 110a, and the conductive pillar 120. For example, the packaging resin 160 may include epoxy resin. In this embodiment, the packaging resin 160 may fully cover the chip 140 and the conductive pillar 120 at this stage, and the packaging resin 160 covers at least a portion of the lead frame 110a and exposes the lower surface of the lead frame 110a.

Next, referring to FIG. 13 , the packaging colloid 160 is subjected to a thinning process so that the packaging colloid 160 exposes the top surface of the conductive pillar 120. In this embodiment, the packaging colloid 160 may be subjected to a thinning process such as chemical mechanical polishing, laser thinning, and/or grinding until the top surface of the conductive pillar 120 is exposed. In this way, the packaging colloid 160 may expose at least the bottom surface of the lead frame 110a and the top surface of the conductive pillar 120.

Please refer to FIG. 14, which is a cross-sectional schematic diagram of a semiconductor package according to an embodiment of the present disclosure. The difference between the semiconductor package and the semiconductor package of the aforementioned embodiment is that a patterned circuit layer 190 is formed on the top surface of the packaging gel 160, and the patterned circuit layer 190 is electrically connected to the conductive pillar 120. In this way, the manufacturing method of the package 100a can be substantially completed, and the package 100a can be electrically connected to different components through the exposed lower surface of the lead frame 110a and the patterned circuit layer 190 connected to the conductive pillar 120.

Please refer to Figure 15, which is a cross-sectional schematic diagram of a semiconductor package according to an embodiment of the present disclosure. In this embodiment, the chip disposed on the lead frame 110a may include a plurality of chips 140a, 140b stacked on each other. Moreover, the chips 140a, 140b are stacked on each other and disposed on the chip seat 112a of the lead frame 110a, for example, by flip-chip bonding. In this embodiment, the chip 140a is bonded to the chip seat 112a (multiple extensions of the plurality of pins 114a) via a plurality of bumps 180, and the chip 140b is bonded to the chip 140a via a plurality of bumps 180. Of course, the present disclosure does not limit the method of disposing the chips 140a, 140b on the chip seat 112a.

Fig. 16 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure. The difference between the semiconductor package of this embodiment and the semiconductor package of the aforementioned embodiment will be described below.

Please refer to FIG. 16 . In this embodiment, after the package 100b is formed, another upper package 100c may be disposed on the package 100b, and the upper package 100c includes a plurality of electrical contacts 170, which are respectively connected to the top surface of the conductive pillar 120 exposed by the encapsulation colloid 160. In this embodiment, the upper package 100c may be substantially similar to the structure of the package 100b (also including a lead frame, a plurality of chips stacked on each other, bumps, encapsulation colloid and other components). However, in other embodiments, the upper package 100c may also be a package completely different in structure from the package 100b, as long as its electrical contacts 170 can be electrically connected to the conductive pillar 120 of the package 100b.

In summary, the semiconductor package disclosed in the present invention has the characteristics of selectivity and adjustability according to the needs of electrical connection, and is arranged on the pins of the lead frame as needed, and the chip is arranged on the chip seat of the lead frame, and the packaging colloid exposes the lower surface of the pins and the top surface of the conductive pillars. In this configuration, the lower surface of the pins and the top surface of the conductive pillars exposed by the packaging colloid can be electrically connected to other components respectively, so that the semiconductor package can be stacked on the upper and lower sides of the packaging colloid respectively. Other substrates or packaging components are stacked to achieve the purpose of three-dimensional stacking, and the function and performance of the semiconductor package can be improved.

10, 10a: semiconductor package 50: thinning jig 100, 100a, 100b: package 100a, 100c, 300: upper package 110, 110a: lead frame 112, 112a: chip seat 112a: extension 114, 114a: lead 1141: first lead 1142: second lead 120, 120a: conductive column 122: copper column core 124, 130: solder layer 140, 140a, 140b: chip 142: contact 150: wire 160: package glue 180: bump 190: patterned circuit layer 200: substrate 222: upper heat sink 224: heat sink via 226: lower heat sink 232, 236, 170: electrical contacts 234: electrical vias 310: upper substrate 320: upper chip 330: upper bump 340: upper packaging gel S1: active surface S2: back surface

Figures 1 to 7 are schematic cross-sectional diagrams of a process of manufacturing a semiconductor package according to an embodiment of the present disclosure. Figure 8 is a schematic cross-sectional diagram of a semiconductor package according to an embodiment of the present disclosure. Figure 9 is a schematic top view of a portion of components of a semiconductor package according to an embodiment of the present disclosure. Figure 10 is a schematic diagram of a conductive column of a semiconductor package according to an embodiment of the present disclosure. Figures 11 to 14 are schematic cross-sectional diagrams of a process of manufacturing a semiconductor package according to an embodiment of the present disclosure. Figure 15 is a schematic cross-sectional diagram of a semiconductor package according to an embodiment of the present disclosure. Figure 16 is a schematic cross-sectional diagram of a semiconductor package according to an embodiment of the present disclosure.

100:Packaging parts

110: Conductor frame

112: Wafer holder

114: Pins

120: Conductive column

130: Solder layer

140: Chip

150: Conductor wire

160: Packaging colloid

50:Thinning fixture

Claims (18)

A semiconductor package includes: a lead frame including a chip seat and a plurality of leads; a plurality of conductive pillars disposed on and electrically connected to the plurality of leads; a chip disposed on the chip seat and electrically connected to the plurality of leads; and a packaging colloid covering the chip, the lead frame and the plurality of conductive pillars, wherein the packaging colloid exposes the lower surface of the plurality of leads and the top surface of the plurality of conductive pillars, wherein each of the plurality of conductive pillars includes a copper pillar core and a solder layer covering the outside of the copper pillar core. The semiconductor package as described in claim 1 further includes a plurality of wires, wherein the chip includes an active surface having a plurality of contacts and a back surface opposite to the active surface, and the chip is disposed on the chip seat with the back surface, and the plurality of wires are respectively connected between the plurality of contacts and the plurality of pins of the chip. A semiconductor package as described in claim 1, wherein the chip base is composed of a plurality of extensions extending from the plurality of pins toward the central area of the lead frame, and the plurality of contacts of the chip are respectively connected to the plurality of extensions. A semiconductor package as described in claim 1, wherein the chip includes multiple chips stacked on top of each other. The semiconductor package as described in claim 1 further includes: a substrate disposed on the bottom surface of the packaging body, and the substrate includes a plurality of first electrical contacts, which are respectively connected to the bottom surface of the plurality of pins exposed by the packaging body, and a packaging component is disposed on the top surface of the packaging body, and the packaging component includes a plurality of second electrical contacts, which are respectively connected to the top surface of the plurality of conductive pillars exposed by the packaging body. A semiconductor package includes: a lead frame including a chip seat and a plurality of leads; a plurality of conductive pillars disposed on the plurality of leads and electrically connected to the plurality of leads; a chip disposed on the chip seat and electrically connected to the plurality of leads; and a packaging colloid covering the chip, the lead frame and the plurality of conductive pillars, wherein the packaging colloid exposes the lower surface of the plurality of leads and the top surface of the plurality of conductive pillars, wherein the plurality of leads include a plurality of first leads and at least one second lead, wherein the plurality of conductive pillars are respectively disposed on the plurality of first leads. A semiconductor package as described in claim 6, wherein the plurality of conductive pillars are copper pillars. A semiconductor package as described in claim 6, wherein the plurality of conductive pillars include a copper pillar core and a tin layer covering the copper pillar core. A method for manufacturing a semiconductor package includes: providing a lead frame, wherein the lead frame includes a chip seat and a plurality of pins; providing a plurality of conductive posts on the plurality of pins and electrically connecting the plurality of conductive posts to the plurality of pins; placing a chip on the chip seat and electrically connecting the chip to the plurality of pins; and forming a packaging colloid to cover the chip, the lead frame and the plurality of conductive posts, wherein the plurality of pins include a plurality of first pins and at least one second pin, wherein the plurality of conductive posts are respectively arranged on the plurality of first pins. The method for manufacturing a semiconductor package as described in claim 9 further includes: providing a solder layer between the plurality of conductive pillars and the corresponding plurality of pins; and performing a reflow process to join the plurality of conductive pillars and the corresponding plurality of pins through the solder layer. The method for manufacturing a semiconductor package as described in claim 9 further includes: forming a solder layer on the plurality of conductive pillars so that the solder layer at least covers the side surfaces of the plurality of conductive pillars; and performing a reflow process so that the plurality of conductive pillars are joined to the corresponding plurality of pins through the solder layer. The method for manufacturing a semiconductor package as described in claim 9 further includes: performing a thinning process on the packaging colloid so that the packaging colloid exposes the top surface of the plurality of conductive pillars. A method for manufacturing a semiconductor package as described in claim 9, wherein the plurality of conductive pillars are copper pillars. A method for manufacturing a semiconductor package includes: providing a lead frame, wherein the lead frame includes a chip seat and a plurality of pins; providing a plurality of conductive posts on the plurality of pins and electrically connecting the plurality of conductive posts to the plurality of pins; placing a chip on the chip seat and electrically connecting the chip to the plurality of pins; and forming a packaging colloid to cover the chip, the lead frame and the plurality of conductive posts, wherein the plurality of conductive posts include a copper post core and a solder layer covering the copper post core. A method for manufacturing a semiconductor package as described in claim 14, wherein the plurality of conductive pillars are placed on corresponding pins by a pick and place mechanism. The method for manufacturing a semiconductor package as described in claim 14 further includes: performing a thinning process on the packaging colloid so that the packaging colloid exposes the top surface of the plurality of conductive pillars, wherein the thinning process on the packaging colloid includes laser thinning and grinding processes. The method for manufacturing a semiconductor package as described in claim 14 further includes: setting a substrate on the bottom surface of the packaging body, and the substrate includes a plurality of first electrical contacts, which are respectively connected to the bottom surfaces of the plurality of pins exposed by the packaging body, and setting a packaging component on the top surface of the packaging body, and the packaging component includes a plurality of second electrical contacts, which are respectively connected to the top surfaces of the plurality of conductive posts exposed by the packaging body. A method for manufacturing a semiconductor package as described in claim 14, wherein the chip is placed on the chip holder by wire bonding or flip chip bonding.

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