TWI836871B - Bus system - Google Patents

Abstract

A bus system is provided. A plurality of slave devices are electrically connected to a master device via a bus. The alert handshake pins of the slave devices are electrically connected together via an alert handshake control line. When a first slave device communicates with the master device via the bus, in a first phase of each assignment period corresponding to the first slave device, the first slave device is configured to control the alert handshake control line to a first voltage level via the alert handshake pin. When the first slave device communicates with the master device via the bus, a second slave device is configured to control the alert handshake control line to a second voltage level via the alert handshake pin during a level enhancement time period after the first phase of each of the assignment periods.

Description

Bus System

The present invention relates to a bus system, and more particularly to a bus system having a plurality of slave components.

In the past, in computer systems, chipsets such as south bridge chips used low pin count (LPC) interfaces to communicate with other circuit modules, such as system-on-a-chip (System-on-chip) with different functions. on-a-chip, SoC) are electrically connected to each other. These external circuit modules connected through the low-pin-count interface can be assigned to different independent addresses, so the Southbridge chip can communicate with the external circuit modules in a one-to-many manner. However, in recent years, some newly proposed bus architectures, such as the Enhanced Serial Peripheral Interface (eSPI) bus, only allow one-to-one communication between the chipset and external circuit modules.

Therefore, a mechanism that can schedule buses of multiple circuit modules is needed.

An embodiment of the present invention provides a bus system. The bus system includes a master control component, a bus and a plurality of slave components. The slave components are electrically connected to the master control component via the bus. Each of the slave components has an alarm handshake pin, and the alarm handshake pins of the slave components are electrically connected together via an alarm handshake control line. When a first slave component of the slave components communicates with the master control component via the bus, in a first phase corresponding to the first slave component in the plurality of phases of each distribution cycle, the first slave component controls the alarm handshake control line to a first voltage level via the alarm handshake pin. When the first slave device communicates with the master device via the bus, a second slave device of the slave devices controls the alert handshake control line to a second voltage level via the alert handshake pin during a level-enhanced time period after the first phase of each distribution cycle.

Furthermore, an embodiment of the present invention provides a bus system. The bus system includes a master control component, a bus and a plurality of slave components. The slave components are electrically connected to the master control component via the bus. Each of the slave components has an alarm handshake pin, and the alarm handshake pins of the slave components are electrically connected together via an alarm handshake control line. When a first slave element among the slave elements detects that a second slave element among the slave elements controls the warning handshake control line to a first voltage level within a first time period after power is turned on or reset, the first slave element controls the warning handshake control line to a second voltage level via the warning handshake pin within a second time period corresponding to a first phase of the second slave element in a plurality of phases of each distribution phase of a distribution phase.

In order to make the above and other objects, features, and advantages of the present invention more clearly understood, preferred embodiments are listed below and described in detail with reference to the accompanying drawings:

FIG. 1 shows a bus system 1 according to some embodiments of the present invention. The bus system 1 includes a master component 10, a bus 12, and a plurality of slave components 14A-14D. In some embodiments, the master component 10 is a south bridge chip. In some embodiments, the master component 10 can be electrically connected to a processing module 20 of a computer system (not shown) so as to access data through the bus 12 and the slave components 14A-14D in response to instructions from the processing module 20. In some embodiments, the processing module 20 can be electrically connected to a memory 22 of the computer system so as to access the memory 22 according to the requirements of different applications. In some embodiments, the bus 12 is an Enhanced Serial Peripheral Interface (eSPI) bus. The master component 10 is electrically connected to the slave components 14A-14D via the bus 12. In addition, the master component 10 communicates with the slave components 14A-14D in a one-to-one mechanism, and the slave components 14A-14D communicate with the master component 10 according to an arbitration mechanism. It is worth noting that the number of the slave components 14A-14D is only an example and is not intended to limit the present invention.

Figure 2 is a connection configuration diagram of the bus system 1 in Figure 1 according to some embodiments of the present invention. In this embodiment, the bus 12 includes a reset signal line eSPI_RST, a chip select signal line eSPI_CS, a clock signal eSPI_CLK, and an input/output signal line eSPI_IO. The master control device 10 communicates with the slave devices 14A-14D in a one-to-one mechanism through the chip selection signal line eSPI_CS. In addition, through the arbitration mechanism, the slave components 14A-14D can communicate (such as transmitting data and instructions) with the master control component 10 through the input and output signal lines eSPI_IO. When the master device 10 communicates with the slave devices 14A-14D via the bus 12, the clock signal eSPI_CLK can be used as a reference clock.

Generally speaking, according to the operation mechanism of the chip select signal line eSPI_CS, the master control component 10 can only select a single component for communication. However, by using the arbitration mechanism, only one of the slave components 14A-14D responds to the master control component 10 at a time in the bus system 1. Therefore, when the master control component 10 still operates in a one-to-one communication mechanism, the bus 12 can correspond to one chip select signal line eSPI_CS and connect the slave components 14A-14D for communication, thereby improving the scalability of the bus system 1.

In FIG. 2, the slave devices 14A-14D include address segment selection pins 18A-18D, address entry selection pins 16A-16D, and alert handshake pins Alert_1-Alert_4. The address corresponding to the slave device 14A-14D can be configured by a combination of the voltage levels received by the address segment selection pins 18A-18D and the address entry selection pins 16A-16D, so that the slave device 14A -14D has mutually different address segments. For example, the address segment selection pins 18A and 18C of the slave devices 14A and 14C are coupled to the ground terminal GND to correspond to the first address segment. The address entry selection pins 16A and 16C of the slave devices 14A and 14C are respectively coupled to the ground terminal GND and the power supply VDD to respectively correspond to different address entry codes, such as corresponding to the first bit of the first address section. address and the second address. In addition, the address segment selection pins 18B and 18D of the slave devices 14B and 14D are coupled to the power supply VDD to correspond to the second address segment. The address entry selection pins 16B and 16D of the slave devices 14B and 14D are respectively coupled to the ground terminal GND and the power supply VDD to respectively correspond to different address entry codes, such as corresponding to the first bit of the second address section. address and the second address. It is worth noting that the configuration of the address section selection pins 18A-18D and the address entry selection pins 16A-16D is only an example and is not intended to limit the present invention. In other embodiments, any suitable settings may be used to set the address segments corresponding to the slave elements 14A-14D.

The alert handshake pins Alert_1 - Alert_4 of the slave components 14A-14D are electrically connected to the alert handshake control line ALERT_HAND. In this embodiment, the alert handshake control line ALERT_HAND is electrically connected to the power source VDD via a pull-up resistor R, so that the alert handshake control line ALERT_HAND is a high voltage level (e.g., a high logic signal "H"). In addition, the schedule controller in the slave components 14A-14D can drive the alert handshake control line ALERT_HAND by controlling the corresponding alert handshake pins Alert_1-Alert_4 to a low voltage level (e.g., a low logic signal "L"), so that the alert handshake control line ALERT_HAND is a low voltage level. Therefore, each slave component 14A-14D can obtain the right to actively communicate with the master component 10 by controlling the voltage level of the alert handshake control line ALERT_HAND. The alert handshake pins Alert_1-Alert_4 are bidirectional input/output pins and are open drain in output mode. In some embodiments, the alert handshake control line ALERT_HAND is electrically connected to the ground terminal GND via a pull-down resistor so that the alert handshake control line ALERT_HAND is a low voltage level (e.g., a low logic signal "L").

In FIG. 2, each slave component 14A-14D includes its own schedule controller. For example, slave components 14A, 14C, and 14D include a schedule controller 110, and slave component 14B includes a level enhancement schedule controller 120. Each schedule controller 110 and level enhancement schedule controller 120 are used to control the alert handshake control line ALERT_HAND for communication sequencing. In addition, the priority of the slave components 14A-14D controlling the alert handshake control line ALERT_HAND is determined by the address segment selection pins 18A-18D and the address entry selection pins 16A-16D of FIG. 2. In other embodiments, other hardware or software settings may be used to determine the priority of the slave components 14A-14D controlling the alert handshake control line ALERT_HAND. It is worth noting that in the bus system 1, only one slave device (e.g., slave device 14B) has a schedule controller (e.g., level-enhanced schedule controller 120) capable of performing level-enhanced on the alert handshake control line ALERT_HAND. The operations of the level-enhanced schedule controller 120 and the schedule controller 110 will be described below.

In this embodiment, pull-up resistors R are impedance elements provided externally to slave elements 14A-14D. Therefore, the pull-up resistor R is coupled to the alert handover pins Alert_1-Alert_4 of the slave devices 14A-14D via the alert handshake control line ALERT_HAND. In some embodiments, the pull-up resistor R is implemented (disposed) within the slave device 14B with the level-enhanced schedule controller 120 . Therefore, the pull-up resistor R is coupled to the alert handover control line ALERT_HAND via the alert handover pin Alert_2 of the slave device 14B.

FIG. 3 is a flow chart showing a scheduling control method of the bus system 1 according to some embodiments of the present invention. The scheduling control method of FIG. 3 is executed by the level-enhanced scheduling controller 120 of the slave component 14B in the bus system 1. In addition, the process S350 in the scheduling control method of FIG. 3 can also be executed by the scheduling controller 110 of the slave components 14A, 14C and 14D in the bus system 1. FIG. 4 is a diagram showing exemplary signal waveforms of the clock signals clk1-clk4 of the slave components 14A-14D and the alert handshake control line ALERT_HAND, which are used to illustrate the operations of the synchronization stage ST_Sync, the synchronization end stage ST_SyncEnd and the distribution stage ST_Ass of the scheduling control method of FIG. 3. In addition, the waveforms of the clock signals clk1-clk4 and the alert handshake control line ALERT_HAND shown in FIG. 4 are merely examples and are not intended to limit the present invention.

Referring to FIG. 3 and FIG. 4 simultaneously, the slave components 14A-14D use the same frequency clock signals clk1-clk4 as the counting basis for the schedule controller 110 and the level-enhanced schedule controller 120. In some embodiments, the clock signals clk1-clk4 have the same phase. In some embodiments, the clock signals clk1-clk4 have different phases. In some embodiments, the clock signals clk1-clk4 have the same frequency, so the clock signals clk1-clk4 have the same time period, that is, TP1=TP2=TP3=TP4. In some embodiments, the slave components 14A, 14B, 14C or 14D count according to the rising edge of the corresponding clock signal. In some embodiments, 14A, 14B, 14C or 14D counts according to the falling edge of the corresponding clock signal. In addition, in the signal waveform diagram, the dotted line of the alert handshake control line ALERT_HAND indicates that the alert handshake control line ALERT_HAND is not driven by any slave component, and the alert handshake control line ALERT_HAND is driven by the pull-up resistor R. As described previously, the pull-up resistor R can be set outside the slave components 14A-14D or inside the slave component 14B.

First, when the slave device 14B is powered on or reset (step S302), the level enhancement schedule controller 120 monitors (or detects) the alert handover control through the corresponding alert handover pin Alert_2. The voltage level of the line ALERT_HAND is determined to determine whether the alert handover control line ALERT_HAND is driven and the number of driven clock cycles does not exceed a specific value (step S304).

In some embodiments, the schedule controller 110 and the level-enhanced schedule controller 120 detect whether the alert handshake control line ALERT_HAND is driven by any slave component 14A-14D (e.g., detect that the alert handshake control line ALERT_HAND changes from a high voltage level to a low voltage level) within 2×n clock cycles, where n is the number of slave components 14A-14D in the bus system 1. For example, in FIG. 4 , the level-enhanced schedule controller 120 detects whether the alert handshake control line ALERT_HAND is driven by other slave components 14A, 14C, or 14D. When the ALERT_HAND control line is driven, the slave device 14B further determines whether the number of clock cycles during which the ALERT_HAND control line is driven does not exceed 2×4 clock cycles (step S304). It should be noted that the number of clock cycles is only an example and is not intended to limit the present invention.

When it is detected that the alarm handover control line ALERT_HAND is driven and does not exceed 2×4 clock cycles, the level enhancement schedule controller 120 will determine that other slave devices have been activated when the slave device 14B is powered on or reset. The driver alert hands over the control line ALERT_HAND to communicate with the main control component 10 . Therefore, the level enhancement schedule controller 120 controls the slave component 14B to enter a hot join mode. The operation of the hot add mode will be described later.

When it is detected that the alert handshake control line ALERT_HAND is not driven or is driven for more than 2×4 clock cycles, the level-enhanced scheduling controller 120 controls the slave component 14B to enter the idle wait stage ST_IdleWait (step S306). In the idle wait stage ST_IdleWait, the level-enhanced scheduling controller 120 of the slave component 14B controls the corresponding alert handshake pin Alert_2 to be in input mode, so as to monitor whether the alert handshake control line ALERT_HAND is driven by other slave components 14A, 14C or 14D (step S308), for example, the alert handshake control line ALERT_HAND changes from a high voltage level to a low voltage level. If the alert handshake control line ALERT_HAND is not driven by other slave components 14A, 14C or 14D, the level-enhanced scheduling controller 120 of the slave component 14B will further determine whether it needs to communicate with the master component 10 (step S310). If the slave component 14B does not need to communicate with the master component 10, the process returns to step S306. If the slave component 14B needs to communicate with the master component 10, the level-enhanced scheduling controller 120 will drive the alert handshake control line ALERT_HAND (i.e., control the alert handshake control line ALERT_HAND to a low voltage level). When the ALERT_HAND control line is detected to be driven, each schedule controller 110 and the level-enhanced schedule controller 120 will control the corresponding slave components 14A-14D to enter the synchronization phase ST_Sync (step S312). Therefore, the slave components 14A-14D of the bus system 1 will enter the synchronization phase ST_Sync at the same time.

In Figure 4, corresponding to the interrupt request REQ1, the level enhancement schedule controller 120 of the slave device 14B2 controls the alert handover pin Alert_2 to the output mode and outputs a low voltage level to drive the alert handover control line ALERT_HAND. Exceeding a certain number of clock cycles (for example, driving more than 3 clock cycles), so that other slave components of the bus system 1 can recognize that the bus system 1 enters the synchronization phase ST_Sync instead of other phases (such as the distribution phase ST_Ass). When the alert handshake control line ALERT_HAND is driven for more than 3 clock cycles, the level enhancement schedule controller 120 will stop driving the alert handshake control line ALERT_HAND, and control the alert handshake pin Alert_2 to the input mode to monitor Alert handover control line ALERT_HAND. At the same time, other slave components of the bus system 1 will also detect that the alarm handover control line ALERT_HAND returns to a high voltage level (for example, driven by the pull-up resistor R), so all slave components enter the synchronization end stage ST_SyncEnd at the same time. (Step S314).

In the synchronization end phase ST_SyncEnd, each schedule controller waits for at least one clock cycle to ensure that each slave device 14A-14D of the bus system 1 completes the synchronization phase ST_Sync, and then the schedule controller 110 and the level The enhanced schedule controller 120 will respectively control the corresponding slave components 14A-14D to enter the distribution stage ST_Ass from the synchronization end stage ST_SyncEnd (step S316). In the assignment phase ST_Ass, each slave element 14A-14D monitors the status of the alert handshake control line ALERT_HAND via the alert handshake pins Alert_1-Alert_4 in each assignment period AP.

In Figure 4, each slave element 14A-14D has a distribution period AP1-AP4 of the same time period. In this embodiment, each distribution period AP1-AP4 has 2×4 clock periods CY1-CY8. In addition, each distribution cycle AP1-AP4 can be divided into 4 phases PH1-PH4, and each phase includes 2 clock cycles. For example, phase PH1 includes clock cycles CY1 and CY2, phase PH2 includes clock cycles CY3 and CY4, phase PH3 includes clock cycles CY5 and CY6, and phase PH4 includes clock cycles CY7 and CY8.

In the distribution phase ST_Ass of FIG. 4, each slave component 14A-14D performs corresponding operations according to phases PH1-PH4. In this embodiment, slave component 14A corresponds to phase PH1, slave component 14B corresponds to phase PH2, slave component 14C corresponds to phase PH3, and slave component 14D corresponds to phase PH4. In some embodiments, the correspondence between slave components 14A-14D and phases PH1-PH4 is determined by address segment selection pins 18A-18D and address entry selection pins 16A-16D of FIG. 2. In other embodiments, other hardware or software settings may be used to determine the correspondence between the slave components 14A-14D and the phases PH1-PH4.

In FIG. 4 , the slave components 14A-14D count the clock cycles CY1-CY8 in the distribution cycles AP1-AP4 according to the rising edges of the internal clock signals clk1-clk4. In the distribution phase ST_Ass, if the slave component 14A communicates with the master component 10, the slave component 14A can only have the power to drive the alert handshake control line ALERT_HAND (i.e., control the alert handshake control line ALERT_HAND to a low voltage level) in the phase PH1 of the distribution cycle AP1. Similarly, if the slave component 14B communicates with the master component 10, the slave component 14B can only have the power to drive the alert handshake control line ALERT_HAND in the phase PH2 of the distribution cycle AP2. Specifically, when the slave device 14B communicates with the master device 10, the level-enhanced scheduling controller 120 of the slave device 14B controls the alert handshake pin Alert_2 to be in output mode and outputs a low voltage level in phase PH2 to drive the alert handshake control line ALERT_HAND, that is, controls the alert handshake control line ALERT_HAND to be at a low voltage level. If the slave device 14B does not need to communicate with the master device 10, the level-enhanced scheduling controller 120 of the slave device 14B controls the alert handshake pin Alert_1 to be in input mode or tri-state mode in phase PH2, that is, does not drive the alert handshake control line ALERT_HAND.

In FIG. 4 , in response to the interruption request REQ1, the slave component 14B needs to communicate with the master component 10. Before the slave component 14B wants to communicate with the master component 10, it will first monitor the voltage level of the alert handshake control line ALERT_HAND to determine that the alert handshake control line ALERT_HAND is not driven by the slave components 14A, 14C, and 14D. Then, at time point t1, the slave component 14B controls the alert handshake pin Alert_2 to be in output mode and outputs a low voltage level within 3 clock cycles of the clock signal clk2 to drive the alert handshake control line ALERT_HAND, so as to notify the slave components 14A, 14C, and 14D to enter the synchronization stage ST_Sync. Then, at time point t2, after completing the synchronization phase ST_Sync, the slave component 14B controls the alert handshake pin Alert_2 to the input mode or tri-state mode to stop driving the alert handshake control line ALERT_HAND. Then, each slave component 14A-14D of the bus system 1 enters the synchronization end phase ST_SyncEnd. In some embodiments, in the synchronization end phase ST_SyncEnd, each slave component 14A-14D waits for at least one clock cycle, and then the slave component 14A-14D enters the distribution phase ST_Ass from the synchronization end phase ST_SyncEnd.

In the distribution phase ST_Ass of Figure 4, the slave component 14B obtains control of the alert handshake control line ALERT_HAND in order to communicate with the master component 10. Therefore, at time point t3, the alert handshake control line ALERT_HAND becomes a low voltage level in phase PH2 of the distribution cycle AP2 of the slave component 14B. Therefore, the slave component 14B can obtain the right to communicate. Then, the slave component 14A detects that the alert handshake control line ALERT_HAND is at a low voltage level in phase PH2 of the distribution cycle AP1 (as shown by arrow 402). Therefore, the slave component 14A can know that the slave component 14B corresponding to phase PH2 wants to communicate (for example, to handle an interrupt request). At the same time, the slave component 14D also detects that the alert handshake control line ALERT_HAND is at a low voltage level in phase PH2 of the distribution cycle AP4 (as shown by arrow 404). Therefore, the slave component 14D can know that the slave component 14B corresponding to phase PH1 is communicating (e.g., processing an interrupt request). Then, the slave component 14C detects that the alert handshake control line ALERT_HAND is at a low voltage level in phase PH2 of the distribution cycle AP3 (as shown by arrow 406). Therefore, the slave component 14C can know that the slave component 14B corresponding to phase PH2 is communicating (e.g., processing an interrupt request).

In some embodiments, when the slave device 14B is communicating with the master device 10, the slave device 14B provides the event alert signal ALERT to the input and output signal line eSPI_IO of the bus 12 via its input and output signal line eSPI_IO2 in order to transmit the event. The warning signal ALERT is sent to the main control component 10 . The event alert signal ALERT is a request signal indicating that the slave component 14B requests communication from the master control component 10 . Corresponding to the event alert signal ALERT, the master control component 10 transmits the status retrieval signal GET_STATUS via the input and output signal line eSPI_IO to query the status of the slave components 14A-14D. At this time, the slave component 14B will receive the status acquisition signal GET_STATUS via the input and output signal line eSPI_IO and respond to notify the master control component 10 that there is information to be transmitted. At this time, the other slave components 14A, 14C and 14D will not receive the status retrieval signal GET_STATUS and will not respond. Then, the master control component 10 will transmit the event capture signal GET_VWIRE via the input and output signal line eSPI_IO to capture the event information of the slave component 14B. Then, the slave component 14B will receive the event capture signal GET_VWIRE and respond to transmit the event message to the master control component 10 . The slave components 14A, 14C and 14D will not receive the event capture signal GET_VWIRE and will not respond.

When the slave device 14B is detected to drive the alert handshake control line ALERT_HAND, if the other slave devices 14A, 14C and 14D want to communicate with the master device 10, they will store the event information and communicate with the master device 10 when they obtain the control right of the alert handshake control line ALERT_HAND later. When the slave device 14B communicates with the master device 10, the slave device 14B drives the alert handshake control line ALERT_HAND in the phase PH2 of each distribution cycle AP2 until the communication with the master device 10 is terminated. Similarly, when other slave devices communicate with the master device 10, the slave device drives the alert handshake control line ALERT_HAND in the corresponding phase of each distribution cycle until the communication is terminated.

When the alert handshake control line ALERT_HAND is driven at the corresponding phase (step S318), the level enhancement schedule controller 120 of the slave device 14B performs level enhancement on the alert handshake control line ALERT_HAND more than the schedule controllers 110 of the slave devices 14A, 14C, and 14D (step S322). As previously described, the level enhancement schedule controller 120 of the slave device 14B drives the alert handshake control line ALERT_HAND to a low voltage level at phase PH2 in the distribution cycle AP2. Then, the level enhancement scheduling controller 120 of the slave device 14B controls the alert handshake control line ALERT_HAND to a high voltage level in the level enhancement time period Level_EH (i.e., the clock periods CY5-CY8 in the distribution period AP2), thereby avoiding the function failure caused by the unstable transition time of the alert handshake control line ALERT_HAND by the pull-up resistor R. In other words, in the level enhancement time period Level_EH, the slave devices 14A, 14C and 14D will not detect that the alert handshake control line ALERT_HAND has a low voltage level caused by the unstable transition time. After the level enhancement time period Level_EH ends, the level enhancement scheduling controller 120 stops controlling the alert handshake control line ALERT_HAND (ie, the slave device 14B controls the alert handshake pin Alert_2 to be in input mode or tri-state mode). Therefore, the level of the alert handshake control line ALERT_HAND is maintained at a high voltage level through the pull-up resistor R. Therefore, compared with the unstable transition time of pulling the alert handshake control line ALERT_HAND to a high voltage level through a pull-up resistor R in a conventional bus system, the level enhancement scheduling controller 120 performs level enhancement on the alert handshake control line ALERT_HAND during the level enhancement time period Level_EH, thereby preventing the slave components 14A-14D in the bus system 1 from misjudging the unstable transition voltage as the alert handshake control line ALERT_HAND being driven by a certain slave component. Therefore, the bus system 1 will not have a functional failure problem. In addition, by performing the level enhancement function through the level enhancement scheduling controller 120, the adjustment time cost of selecting an appropriate pull-up resistor R can be saved. In some embodiments, when the pull-up resistor R is built into the slave device having the level-enhanced scheduling controller 120, the cost of configuring an external pull-up resistor R can be saved.

In FIG. 4 , the level enhancement scheduling controller 120 controls the level enhancement time period Level_EH to be 4 clock cycles. In some embodiments, the level enhancement scheduling controller 120 can control the level enhancement time period Level_EH to be 1 to (2n-2) clock cycles, where n is the number of slave components. Then, after performing level enhancement on the alert handshake control line ALERT_HAND (step S322), the level enhancement scheduling controller 120 controls the process back to step S316.

After ending the communication (step S316), the slave component 14B will not drive the alarm handover control line ALERT_HAND in the phase PH2 of the distribution cycle AP2 (step S318), so the slave components 14A-14D will enter the standby waiting stage ST_IdleWait (step S306). As described previously, in the standby waiting phase ST_IdleWait, each slave component 14A-14D controls the corresponding alert handover pins Alert_1-Alert_4 to the input mode in order to monitor whether the alert handover control line ALERT_HAND is controlled by any slave. Driven by elements 14A-14D.

FIG. 5 is an exemplary waveform diagram showing the alarm handover control line ALERT_HAND to illustrate the operation of the slave components 14A-14D to drive the alarm handover control line ALERT_HAND according to the schedule control method in FIG. 3. Referring to Figures 3 and 5 at the same time, corresponding to the interrupt request REQ2, the slave component 14A needs to communicate with the master control component 10. When the slave device 14A wants to communicate with the master device 10, it will first monitor the voltage level of the alarm handshake control line ALERT_HAND to determine that the alarm handshake control line ALERT_HAND is not driven by the slave devices 14B-14D. Then, at time point t11, the slave component 14A controls the alert handover pin Alert_1 to be in the output mode and outputs a low voltage level within 3 clock cycles of the clock signal clk1 to drive the alert handover control line ALERT_HAND, so that The slave elements 14B-14D are notified to enter the synchronization phase ST_Sync. Since the bus system 1 is operating in the synchronization phase ST_Sync, although the slave component 14B has an interrupt request REQ3 generated at this time, the slave component 14B will not drive the alarm handover control line ALERT_HAND. After completing the synchronization phase ST_Sync, the slave component 14A controls the alert handshake pin Alert_1 to the input mode to stop driving the alert handshake control line ALERT_HAND. Therefore, at time point t12, each slave element 14A-14D of the bus system 1 will enter the synchronization end phase ST_SyncEnd. As described previously, in the synchronization end phase ST_SyncEnd, the slave elements 14A-14D will wait for at least one clock cycle, and then the slave elements 14A-14D will enter the distribution phase ST_Ass from the synchronization end phase ST_SyncEnd.

In the distribution phase ST_Ass, the slave component 14A will obtain control of the alert handover control line ALERT_HAND in order to communicate with the master control component 10 . Therefore, at time point t13, the alert handover control line ALERT_HAND changes to a low voltage level during the phase PH1 in the distribution cycle AP1 of the slave device 14A. Therefore, the slave component 14A can obtain the right to communicate with the master control component 10 . Then, the slave devices 14B-14D will detect that the alarm handover control line ALERT_HAND is a low voltage level during the phase PH1 in the respective distribution cycles AP2-AP4. Therefore, the slave components 14B-14D can know that the slave component 14A corresponding to the stage PH1 is communicating with the master control component 10 (for example, processing an interrupt request).

When the slave component 14A is communicating with the master control component 10, the slave component 14A will provide the event alert signal ALERT to the input and output signal line eSPI_IO of the bus 12 via its input and output signal line eSPI_IO1, so as to transmit the event alert signal ALERT to the master control Element 10. The event alert signal ALERT is a request signal indicating that the slave component 14A requests communication from the master control component 10 . When it is detected that the slave component 14A drives the alarm handover control line ALERT_HAND, if other slave components 14B-14D want to communicate with the master control component 10, the event message will be stored to obtain the alarm handover control line later. Then communicate with the main control component 10 when the control right of ALERT_HAND is obtained.

Corresponding to the event alert signal ALERT, the master control component 10 transmits the status retrieval signal GET_STATUS via the input and output signal line eSPI_IO to query the status of the slave components 14A-14D. At this time, the slave component 14A will receive the status retrieval signal GET_STATUS via the input and output signal line eSPI_IO and respond to notify the master control component 10 that there is information to be transmitted. At this time, other slave components 14B-14D will not receive the status retrieval signal GET_STATUS and will not respond. Then, the master control component 10 transmits the event capture signal GET_VWIRE via the input and output signal line eSPI_IO to capture the event information of the slave component 14A. Then, the slave component 14A will receive the event retrieval signal GET_VWIRE and respond to transmit the event message to the master control component 10 . The slave components 14B-14D will not receive the event capture signal GET_VWIRE and will not respond. When the slave component 14A communicates with the master control component 10, the slave component 14A drives the alarm handover control line ALERT_HAND in the phase PH1 of each distribution cycle AP1 until the communication with the master control component 10 is completed.

As previously described, when the level-enhanced scheduling controller 120 of the slave component 14B detects that the alert handshake control line ALERT_HAND is driven by the slave component 14A (step S308), the level-enhanced scheduling controller 120 controls the slave component 14B to sequentially enter the synchronization end stage ST_SyncEnd (step S314) and the distribution stage ST_Ass (step S316). Next, when the level enhancement scheduling controller 120 detects that the alert handshake control line ALERT_HAND is driven by the slave component 14A at the phase PH1 corresponding to the slave component 14A (step S318), the level enhancement scheduling controller 120 controls the slave component 14B to enter the level enhancement time period Level_EH after the phase PH1 of the distribution period AP2 to perform level enhancement on the alert handshake control line ALERT_HAND (step S322).

In FIG. 5 , although the clock signals clk1-clk4 have different phases, the level enhancement performed by the slave component 14B during the level enhancement time period Level_EH ensures that the other slave components detect the alert handshake control line ALERT_HAND as a high voltage level during the phase PH2 of the corresponding distribution cycle. For example, the slave component 14A detects the alert handshake control line ALERT_HAND as a high voltage level during the phase PH2 of the distribution cycle AP1 (as shown by arrow 502). The slave component 14C detects the alert handshake control line ALERT_HAND as a high voltage level during the phase PH2 of the distribution cycle AP3 (as shown by arrow 504). The slave device 14D detects that the alert handshake control line ALERT_HAND is at a high voltage level during phase PH2 (as indicated by arrow 506) of the distribution cycle AP4.

In FIG. 5 , the level enhancement scheduling controller 120 controls the level enhancement time period Level_EH to be 4 clock cycles (i.e., phases PH2 and PH3 of the distribution cycle AP2). In some embodiments, the level enhancement scheduling controller 120 can control the level enhancement time period Level_EH to be 1 to (2n-2) clock cycles, where n is the number of slave components. Then, after executing the level enhancement (step S322), the level enhancement scheduling controller 120 controls the process back to step S316.

In FIG. 5 , the level enhancement scheduling controller 120 of the slave device 14B controls the alert handshake control line ALERT_HAND to a high voltage level in phases PH2 and PH3 (i.e., the level enhancement time period Level_EH) in the distribution cycle AP2, thereby avoiding the functional failure caused by the unstable transition time of the alert handshake control line ALERT_HAND caused by the pull-up resistor R. In other words, in the level enhancement time period Level_EH, the slave devices 14A, 14C, and 14D will not detect that the alert handshake control line ALERT_HAND has a low voltage level caused by the unstable transition time. After the level enhancement time period Level_EH ends, the level enhancement scheduling controller 120 stops controlling the alert handshake control line ALERT_HAND (ie, the slave device 14B controls the alert handshake pin Alert_2 to be in input mode or tri-state mode). Therefore, the level of the alert handshake control line ALERT_HAND is maintained at a high voltage level through the pull-up resistor R. Therefore, compared to the unstable transition time of pulling the alert handshake control line ALERT_HAND to a high voltage level through a pull-up resistor R in a conventional bus system, the level enhancement scheduling controller 120 performs level enhancement on the alert handshake control line ALERT_HAND during the level enhancement time period Level_EH, thereby preventing the slave components 14A-14D in the bus system 1 from misjudging the unstable transition voltage as the alert handshake control line ALERT_HAND being driven by a certain slave component. Therefore, the bus system 1 will not have a functional failure problem. In addition, by performing the level enhancement function through the level enhancement scheduling controller 120, the adjustment time cost of selecting an appropriate pull-up resistor R and the cost of configuring an external pull-up resistor R can be saved.

FIG. 6 is an exemplary waveform diagram showing the alert handshake control line ALERT_HAND, which is used to illustrate the operation of the slave components 14A-14D driving the alert handshake control line ALERT_HAND according to the scheduling control method of FIG. 3, wherein the slave component 14B is operated in the hot join mode. Referring to FIG. 3 and FIG. 6 at the same time, in this embodiment, the slave component 14B is operated in the power on or reset (step S302) before the time point t24, and therefore cannot monitor (or detect) the voltage level of the alert handshake control line ALERT_HAND.

Corresponding to the interrupt request REQ4, the slave component 14C needs to communicate with the master control component 10 . When the slave component 14C wants to communicate with the master control component 10, it will first monitor the voltage level of the alert handshake control line ALERT_HAND to ensure that the alert handshake control line ALERT_HAND is not driven by other slave components. Then, at time point t21, the slave component 14C controls the alert handover pin Alert_3 to be in the output mode and outputs a low voltage level within 3 clock cycles of the clock signal clk3 to drive the alert handover control line ALERT_HAND, so that The other slave elements (ie slave elements 14A and 14D) are notified to enter the synchronization phase ST_Sync. After completing the synchronization phase ST_Sync, the slave component 14C controls the alert handshake pin Alert_3 to the input mode to stop driving the alert handshake control line ALERT_HAND. Therefore, at time point t22, the slave components 14A and 14D of the bus system 1 will enter the synchronization end phase ST_SyncEnd. As described previously, in the synchronization end phase ST_SyncEnd, the slave elements 14A, 14C and 14D will wait for at least one clock cycle, and then the slave elements 14A, 14C and 14D will enter the distribution phase ST_Ass from the synchronization end phase ST_SyncEnd.

In the distribution phase ST_Ass, the slave component 14C obtains control of the alert handshake control line ALERT_HAND in order to communicate with the master component 10. Therefore, at time point t23, the alert handshake control line ALERT_HAND becomes a low voltage level in phase PH3 of the distribution cycle AP3 of the slave component 14C. Therefore, the slave component 14C can obtain the right to communicate with the master component 10. Then, the other slave components will detect that the alert handshake control line ALERT_HAND is at a low voltage level in phase PH3 of their respective distribution cycles. Therefore, the slave components 14A and 14D can know that the slave component 14C corresponding to phase PH3 is communicating with the master component 10 (for example, processing an interrupt request).

After the power is turned on or reset, the slave element 14B will start to monitor the voltage level of the alarm handover control line ALERT_HAND at the rising edge of each clock signal clk2 at time point t24. Therefore, when the slave device 14C drives the alert handover control line ALERT_HAND to a low voltage level in the phase PH3 of the distribution cycle AP3, the level enhancement schedule controller 120 will execute step S320 and detect whether the alert handover control line ALERT_HAND driven for more than 2 clock cycles. If the alert handshake control line ALERT_HAND is driven for more than 2 clock cycles (eg, driven for 3 clock cycles), the level enhancement schedule controller 120 will determine that the slave device of the bus system 1 enters the synchronization end phase ST_SyncEnd (Step S314). At time point t25, if the alert handover control line ALERT_HAND has not been driven for more than 2 clock cycles (as shown by arrows 602 and 604), the level enhancement schedule controller 120 will control the slave element 14B to enter the distribution phase ST_Ass ( Step S316). Next, when the level enhancement schedule controller 120 detects that the alert handover control line ALERT_HAND is driven by the slave device 14C in the phase PH3 corresponding to the slave device 14C (step S318), the level enhancement schedule controller 120 controls The slave element 14B performs level strengthening on the alert handover control line ALERT_HAND in the level strengthening time period Level_EH (step S322).

In FIG. 6 , the level-enhanced scheduling controller 120 controls the slave device 14B to enter the distribution phase ST_Ass at time t25. Since the level-enhanced scheduling controller 120 monitors the alert handshake control line ALERT_HAND being driven for the first time, the level-enhanced scheduling controller 120 directly regards the alert handshake control line ALERT_HAND as being driven by the slave device 14A to avoid identifying the wrong slave device and causing the counting to the wrong clock cycle (e.g., CY1-CY8) or phase (e.g., PH1-PH4). Therefore, the level-enhanced scheduling controller 120 will treat the slave device 14C as the slave device 14A and start counting from the clock cycle CY3 after entering the distribution phase ST_Ass.

In FIG. 6 , the level enhancement schedule controller 120 controls the level enhancement time period Level_EH to be 4 clock cycles. In some embodiments, the level enhancement schedule controller 120 may control the level enhancement time period Level_EH to be 1 to (2n-2) clock cycles, where n is the number of slave elements. Next, after performing the level enhancement (step S322), the level enhancement schedule controller 120 returns the control process to step S316.

In the bus system 1, the clock signals of each slave component (eg, the clock signals clk1-clk4) may generate clock deviation after long-term operation. In order to avoid that the accumulated clock pulse will cause different slave devices to count to different clock cycles (such as clock cycles CY1-CY8) and cause scheduling errors or conflicts, each slave device of the bus system 1 will When any interrupt is required, the synchronization phase ST_Sync will be re-entered to reset the deviation of the clock signal to zero. Therefore, different slave components will not count different clock cycles in the corresponding distribution phases, causing scheduling errors or conflicts. In other words, the slave device (such as the slave device 14B) with the level enhanced schedule controller 120 will not control the alert handover control line ALERT_HAND to a high voltage level in the wrong clock cycle, thus avoiding functional failure.

In the embodiment of the present invention, by using the level enhancement schedule controller 120 to perform level enhancement on the alert handover control line ALERT_HAND, the problem caused by the pull-up resistor R on the alert handover control line ALERT_HAND in the traditional bus system can be solved. The unstable transition time or other factors may lead to misjudgment and functional failure, thus making the bus system 1 more robust (robus) in operation. In addition, for the bus system 1 , using the level enhancement schedule controller 120 does not require extra time to select a suitable pull-up resistor R or configure an external pull-up resistor R, thus reducing manufacturing costs.

Although the present invention has been described above with preferred embodiments, they are not intended to limit the present invention. Any person skilled in the art, including those with common knowledge, may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of the attached patent application.

1:Bus system 10: Main control component 12:Bus 14A-14D: Slave components 16A-16D: Address entry selection pin 18A-18D: Address segment selection pin 20: Processing module 22:Memory 110:Scheduling controller 120: Level enhanced schedule controller Alert_1-Alert_4: Alert handshake pin ALERT_HAND: Alert handover control line AP1-AP4: distribution cycle clk1-clk4: clock signal CY1-CY8: clock cycle eSPI_CLK: Clock signal eSPI_CS: Chip select signal line eSPI_IO, eSPI_IO1-eSPI_IO3: input and output signal lines eSPI_RST: reset signal line GND: ground terminal Level_EH: Level enhancement time period PH1-PH4: Stage R: pull-up resistor REQ1-REQ4: Interrupt requirements S302-S322: Steps S350:Process ST_IdleWait: standby waiting phase ST_Sync: synchronization phase ST_SyncEnd: synchronization end phase ST_Ass: Distribution stage TP1-TP4: time period VDD: power supply ALERT: event warning signal

FIG. 1 shows a bus system according to some embodiments of the present invention. FIG. 2 shows a connection configuration diagram of the bus system in FIG. 1 according to some embodiments of the present invention. FIG. 3 shows a flow chart of a scheduling control method for a bus system according to some embodiments of the present invention. FIG. 4 shows a sample signal waveform diagram of a clock signal of a slave component and a warning handshake control line, which is used to illustrate the operation of the synchronization phase, the synchronization end phase, and the distribution phase of the scheduling control method of FIG. 3. FIG. 5 shows a sample waveform diagram of a warning handshake control line, which is used to illustrate the operation of a slave component driving the warning handshake control line according to the scheduling control method of FIG. 3. Figure 6 is a sample waveform diagram showing the warning handshake control line, which is used to illustrate the operation of the slave component driving the warning handshake control line according to the scheduling control method of Figure 3.

1:Bus system

10: Main control components

12:Bus

14A-14D: Slave components

20: Processing module

22: Memory

Claims (20)

A bus system, comprising: a master control element; a bus; and a plurality of slave elements electrically connected to the master control element via the bus; wherein each of the slave elements has an alarm handshake pin, and the alarm handshake pins of the slave elements are electrically connected together via an alarm handshake control line; wherein when a first slave element of the slave elements communicates with the master control element via the bus, in a first phase corresponding to the first slave element in a plurality of phases of each distribution cycle, the first slave element controls the alarm handshake control line to a first voltage level via the alarm handshake pin; When the first slave component communicates with the master component via the bus, during a standard enhancement time period after the first phase of each distribution cycle, a second slave component of the slave components controls the warning handshake control line to a second voltage level via the warning handshake pin. The bus system of claim 1, wherein when the second slave component communicates with the master control component via the bus, a first slave component corresponding to the second slave component in the stages of each distribution cycle In the second phase, the second slave component controls the alert handover control line to the first voltage level through the alert handover pin, and the level strengthening time after the second phase of each distribution cycle During the cycle, the second slave component controls the alert handover control line to the second voltage level via the alert handover pin. A bus system as claimed in claim 1, wherein each of the phases includes a fixed number of clock cycles, and the level enhancement time period includes at least one time cycle. Such as the bus system of claim 1, wherein each distribution cycle includes n such stages, and each such stage includes 2 clock cycles, wherein the above-mentioned level enhancement time period includes 1 to (2n-2) time period. For example, the bus system of claim 1, wherein in each distribution cycle, the number of the stages is equal to the number of the slave components. The bus system of claim 1, wherein when the first slave component communicates with the master component via the bus, the second slave component only communicates via the level enhancement time period of each distribution cycle. The warning handover pin controls the warning handover control line to the second voltage level. A bus system as claimed in claim 1, wherein when the first slave component communicates with the master component via the bus, the first slave component controls the alert handshake control line to the first voltage level via the alert handshake pin only in the first phase of each of the distribution cycles. For example, the bus system of request item 1 further includes: An impedance element coupled between the alarm handover control line and a power supply having the second voltage level; Wherein, after the level strengthening time period, the second slave component stops controlling the warning handover control line, and the warning handover control line is pulled to the second voltage level through the impedance component. A bus system as claimed in claim 8, wherein the impedance element is disposed outside the slave elements, and the impedance element is coupled to the warning handshake pin of each of the slave elements via the warning handshake control line. A bus system as claimed in claim 8, wherein the impedance element is implemented in the second slave element, and the impedance element is coupled to the alert handshake control line via the alert handshake pin of the second slave element. A bus system including: a main control component; a bus; and A plurality of slave components are electrically connected to the master control component via the busbar; Each of the slave components has an alert handshake pin, and the alert handshake pins of the slave components are electrically connected together through an alert handshake control line; When one of the slave components detects one of the slave components and the second slave component controls the alarm handover control line within a first time period after the power is turned on or reset, the alarm handover control line is a first When the voltage level is correct, the first slave element is controlled through the alert handshake pin in a second time period after a first phase corresponding to the second slave element in a plurality of phases of each distribution cycle of a distribution phase. The warning control line is a second voltage level. The bus system of claim 11, wherein when the first time period and the first phase have the same number of clock cycles, the first slave element is powered on when the slave elements operate in the distribution phase. or reset. The bus system of claim 11, wherein when the first time period has a greater number of clock cycles than the first phase, the first slave element is a time period before the slave elements operate in the distribution phase. Powered on or reset during the synchronization phase. The bus system of claim 11, wherein each phase includes a fixed number of clock cycles, and the second time period includes at least one time period. A bus system as claimed in claim 11, wherein each of the distribution cycles includes n such phases, and each of the phases includes 2 clock cycles, wherein the second time cycle includes 1 to (2n-2) time cycles. A bus system as claimed in claim 11, wherein in each of the distribution cycles, the number of the phases is equal to the number of the slave components. A bus system as claimed in claim 11, wherein when the second slave component communicates with the master component via the bus, the first slave component controls the alert handshake control line to the second voltage level via the alert handshake pin only during the second time period of each distribution cycle. The bus system of claim 11, wherein when the second slave component communicates with the master control component via the bus, the second slave component only passes the alert in the first phase of each distribution cycle. The handover pin controls the alarm handover control line to be the first voltage level. For example, the bus system in request item 11 further includes: An impedance element coupled between the alarm handover control line and a power supply having the second voltage level; Wherein after the second time period, the first slave component stops controlling the warning handover control line, and the warning handover control line is pulled to the second voltage level through the impedance component; The impedance element is disposed outside the slave components, and the impedance element is coupled to the alert handshake pin of each slave component via the alert handshake control line. For example, the bus system in request item 11 further includes: An impedance element coupled between the alarm handover control line and a power supply having the second voltage level; Wherein after the second time period, the first slave element stops controlling the warning handover control line, and the warning handover control line is pulled to the second voltage level through the impedance element; The impedance element is implemented in the first slave element, and the impedance element is coupled to the alarm handshake control line through the alarm handshake pin of the first slave element.

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