TWI835599B - Liquid crystal display panel - Google Patents

Abstract

A liquid crystal display (LCD) panel includes a first substrate, a plurality of pixel electrodes, a pixel circuit array, a transparent conductive layer, a second substrate, and a liquid crystal layer disposed between the first substrate and the second substrate. Each of the pixel electrodes includes at least one first electrode stem, a second electrode stem, and a plurality of electrode branches. The pixel circuit array is disposed on the first substrate and the pixel electrodes are disposed on the pixel circuit array. The pixel circuit array includes a plurality of data lines electrically connected to pixel electrodes. One of the two adjacent data lines is electrically connected to the pixel electrodes in odd columns, and the other of the two adjacent data lines is electrically connected to the pixel electrodes in even columns. The transparent conductive layer is disposed between the pixel circuit array and the pixel electrodes.

Description

LCD panel

The present disclosure relates to a liquid crystal display panel, and in particular to a liquid crystal display panel with a HG2D (half-gate and two-data line) architecture.

Today, LCD panels have been widely used in many displays, such as computer screens, televisions, and mobile phone screens. In LCD panel technology, resolution and refresh frequency (frame rate) will affect the image quality of the LCD display. The charging time of each pixel in the LCD panel = 1/(resolution Í refresh frequency), so when the resolution or refresh frequency is higher, the charging time of each pixel is shorter.

In each row of pixels of the HG2D architecture LCD panel, the two adjacent pixels above and below are electrically connected to different data lines, and the two columns of pixels are charged at the same scanning time. Therefore, compared with 1D1G ( One-data line and one-gate line) architecture LCD panel, HG2D architecture LCD panel has twice the charging time, thereby improving the image quality of the LCD display. However, HG2D structured LCD panels usually have shielding metal, so such LCD panels often have a problem of low aperture ratio.

The data lines of the liquid crystal display panel of the present disclosure are arranged at the junction of the sub-pixel areas of two adjacent rows. In addition, the liquid crystal display panel of the present disclosure can increase the aperture ratio of the liquid crystal display panel.

A liquid crystal display panel provided by at least one embodiment of the present invention includes a first substrate, a plurality of pixel electrodes, a pixel circuit array, a transparent conductive layer, a second substrate, and a liquid crystal layer. A plurality of pixel electrodes are disposed on the first substrate and are arranged in an array. The pixel electrodes are arranged in multiple rows along the first direction and in multiple columns along the second direction. The first direction and the second direction are arranged in an array. The direction is vertical. Each pixel electrode includes at least a first electrode trunk, a second electrode trunk and a plurality of electrode branches. The second electrode trunk is perpendicular to at least one first electrode trunk, wherein at least one first electrode trunk extends along the first direction, and the second electrode trunk extends along the second direction. A plurality of electrode branches are connected to at least a first electrode trunk and a second electrode trunk, and extend from at least a first electrode trunk and a second electrode trunk. The pixel circuit array is disposed on the first substrate, and the pixel electrodes are disposed on the pixel circuit array. The pixel circuit array includes a plurality of data lines electrically connected to the pixel electrodes, wherein each of the data lines extends along the first direction, and the data lines are arranged along the second direction, wherein two adjacent ones One of the data lines is electrically connected to the plurality of pixel electrodes in the odd-numbered columns, and the other of the two adjacent data lines is electrically connected to the plurality of pixel electrodes in the even-numbered columns. In one of the plurality of pixel electrodes, the first data line and the third data line among the three data lines arranged in sequence are located on opposite sides of the pixel electrode, and the second data line among the three data lines The data lines overlap with at least one first electrode trunk of the pixel electrode. The transparent conductive layer is disposed between the pixel circuit array and the plurality of pixel electrodes. The liquid crystal layer is disposed between the first substrate and the second substrate.

In at least one embodiment of the present invention, each of the m-th data line and the (m+2)-th data line is located below the intersection of a plurality of pixel electrodes in two adjacent rows, and the (m+1)-th data line Each data line overlaps with at least one first electrode backbone of multiple pixel electrodes in the same row, where m is a natural number greater than zero.

In at least one embodiment of the present invention, the width of the m-th data line, the width of the (m+1)-th data line, and the width of the (m+2)-th data line are the same as each other.

In at least one embodiment of the present invention, the width of the (m+1)th data line is greater than the width of at least one first electrode trunk.

In at least one embodiment of the present invention, in one of the plurality of pixel electrodes in odd-numbered columns, the m-th data line overlaps with at least one first electrode trunk of the pixel electrode. In one of the plurality of pixel electrodes in the even-numbered column, the m-th data line is located below the intersection of two adjacent plurality of pixel electrodes, where m is a natural number greater than zero.

In at least one embodiment of the present invention, the width of the m-th data line in a pixel electrode of an odd-numbered column is smaller than the width of the m-th data line in a pixel electrode of an even-numbered column.

In at least one embodiment of the present invention, the liquid crystal display panel further includes a color filter layer, wherein the color filter layer is disposed on the pixel circuit array to form a color filter film transistor array.

In at least one embodiment of the present invention, the liquid crystal display panel further includes a liquid crystal layer, wherein the liquid crystal layer is disposed between the second substrate and the transparent conductive layer, and the liquid crystal layer is a vertically aligned liquid crystal layer.

In at least one embodiment of the present invention, the liquid crystal display panel further includes a common electrode layer and a liquid crystal layer. The common electrode layer is disposed on the second substrate. The liquid crystal layer is disposed between the common electrode layer and the transparent conductive layer.

In at least one embodiment of the present invention, the plurality of electrode branches extend along a third direction and a fourth direction, the third direction is different from the fourth direction, the third direction and the fourth direction are not parallel and not perpendicular to the first direction and the fourth direction. Two directions.

In the following text, in order to clearly present the technical features of the present application, the dimensions (such as length, width, thickness and depth) of the elements (such as layers, films, substrates, regions, etc.) in the drawings will be exaggerated at varying proportions. . Therefore, the description and explanation of the embodiments below are not limited to the sizes and shapes of the components in the drawings, but should cover the size, shape, and deviations in both caused by actual manufacturing processes and/or tolerances. For example, flat surfaces shown in the drawings may have rough and/or non-linear features, while acute angles shown in the drawings may be rounded. Therefore, the components shown in the drawings of this case are mainly for illustration and are not intended to accurately depict the actual shapes of the components, nor are they intended to limit the patent scope of this case.

Secondly, the words "about", "approximately" or "substantially" appearing in the content of this case not only cover the clearly stated numerical values and numerical ranges, but also cover what can be understood by a person with ordinary knowledge in the technical field to which the invention belongs. The allowable deviation range, where the deviation range can be determined by the error generated during measurement, and this error is caused, for example, by limitations of the measurement system or process conditions. For example, two objects (such as the plane or traces of a substrate) are "substantially parallel" or "substantially perpendicular", where "substantially parallel" and "substantially perpendicular" respectively represent the parallelism and perpendicularity between the two objects. It can include non-parallelism and non-perpendicularity caused by the allowable deviation range.

In addition, "about" may mean within one or more standard deviations of the above numerical value, such as within ±30%, ±20%, ±10%, or ±5%. Words such as "approximately", "approximately" or "substantially" appearing in this text can be used to select acceptable deviation ranges or standard deviations based on optical properties, etching properties, mechanical properties or other properties, and are not solely based on one The standard deviation applies to all the above optical properties, etching properties, mechanical properties and other properties.

It will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element, without departing from the scope of the embodiments. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

In a liquid crystal display panel with a HG2D structure with shield metal, the shield metal can be distributed at the intersection between two adjacent filter layers, where the aforementioned filters are, for example, blue light, green light and red light filters. light layer. Due to the uneven surface at the junction between two adjacent filter layers, the liquid crystal is tilted or deflected at an unexpected angle, resulting in grayscale distortion of some pixels and uneven images (mura).

Shielding metal can eliminate the above-mentioned uneven images, or reduce the adverse effects of uneven images on image quality. It can also increase the storage capacitance (Cst) between the shielding metal and pixel electrodes, and simultaneously suppress the data lines and pixel electrodes. parasitic capacitance (Cpd) between. However, the opacity of the shielding metal will create dark areas, and the data lines made of metal will also block light. As a result, the aperture ratio of the LCD panel will be significantly lower due to the blocking of light by the shielding metal and data lines. . It should be noted that the "aperture ratio" in this case is defined as the ratio of the display area (also called the light-transmitting area) to the sub-pixel area.

Various embodiments of the present invention provide liquid crystal display panels without the above-mentioned shielding metal. The liquid crystal display panel of the present invention uses the wiring structure (layout) of data lines to shield the junctions between different filter layers to eliminate the above-mentioned uneven images, or reduce the adverse effects of uneven images on image quality, and at the same time improve the liquid crystal display panel opening rate. In addition, the liquid crystal display panel of the present invention includes a transparent conductive layer disposed between the filter layer and the pixel electrode to shield the parasitic capacitance (Cpd) generated between the data line (located under the filter layer) and the pixel electrode. .

1A and 1B are schematic top views of the liquid crystal display panel 100 according to at least one embodiment of the present invention. Referring to FIG. 1A , the liquid crystal display panel 100 has a plurality of sub-pixel areas SP (ie, SP11, SP12, SP21, SP22, SP31, SP32), where these sub-pixel areas SP can be arranged in a regular manner, such as in an array. It should be noted that FIG. 1A depicts six sub-pixel areas SP arranged in a 3×2 array as an example. In actual situations, the liquid crystal display panel 100 may have more than six sub-pixel areas SP, for example, thousands or tens of thousands of sub-pixel areas SP. Therefore, FIG. 1A is only for illustration and does not limit the features of the liquid crystal display panel 100. The number of sub-pixel areas SP.

The liquid crystal display panel 100 includes a first substrate 111 and a pixel circuit array 120, where the pixel circuit array 120 is disposed on the first substrate 111. The first substrate 111 may be a transparent substrate, such as a glass plate, a sapphire substrate or a transparent plastic plate. The pixel circuit array 120 includes a plurality of first data lines 121d1, a plurality of second data lines 121d2 and a plurality of scan lines 121s. The first data lines 121d1 and the second data lines 121d2 both extend along the first direction D1 and are arranged along the second direction D2. These scan lines 121s all extend along the second direction D2 and are arranged along the first direction D1.

In FIGS. 1A and 1B , the first direction D1 may be a vertical direction, and the second direction D2 may be a horizontal direction, so the first direction D1 and the second direction D2 are substantially perpendicular to each other, and the scan line 121s may Extend along the horizontal direction, and the first data line 121d1 and the second data line 121d2 may extend along the vertical direction (eg, the first direction D1). Therefore, the scan lines 121s can intersect the first data lines 121d1 and the second data lines 121d2.

The pixel circuit array 120 of the liquid crystal display panel 100 also includes a plurality of control elements 123 . The first data lines 121d1, the second data lines 121d2 and the scan lines 121s are electrically connected to the control elements 123. It should be emphasized that since FIG. 1A is a partial top view of the liquid crystal display panel 100 , FIG. 1A only shows a part of the pixel circuit array 120 . In other words, FIG. 1A does not limit the number of the first data lines 121d1, the second data lines 121d2, the scan lines 121s and the control elements 123. In addition, the first data line 121d1, the second data line 121d2 and the scanning line 121s are all made of metal and therefore do not transmit light.

In the embodiments of FIGS. 1A and 1B , the control element 123 may be a transistor, and may be a thin film transistor (TFT) formed by stacking multiple film layers, or may be a field effect transistor (TFT). Field-Effect Transistor; FET). Specifically, each control element 123 may include a gate, a channel layer, a source and a drain (not labeled).

See Figure 1A. In the sub-pixel areas SP of each column, the first data lines 121d1 and the second data lines 121d2 are arranged alternately. The first data lines 121d1 are located at the junction of two adjacent sub-pixel areas SP, and these The second data line 121d2 is located between two adjacent first data lines 121d1.

Specifically, at the junction of the sub-pixel area SP11 and the sub-pixel area SP12, the junction of the sub-pixel area SP21 and the sub-pixel area SP22, and the junction of the sub-pixel area SP31 and the sub-pixel area SP32 There is the first data line 121d1. There is a second data line 121d2 inside the sub-pixel area SP11, the sub-pixel area SP21, and the sub-pixel area SP31. Similarly, there is a second data line 121d2 inside the sub-pixel area SP12, the sub-pixel area SP22, and the sub-pixel area SP32. The pattern shapes of the first data line 121d1 and the second data line 121d2 are different, but are substantially parallel to each other, as shown in FIG. 1A .

In this embodiment, a first data line 121d1 is electrically connected to the control elements 123 in odd-numbered columns, and a second data line 121d2 is electrically connected to the control elements 123 in even-numbered columns, as shown in FIG. 1A . In other words, taking FIG. 1A as an example, in the sub-pixel areas SP in the same row (for example, the sub-pixel areas SP11, SP21, SP31 arranged in the same row), the first data line 121d1 is electrically connected to the sub-pixels at the same time. The control element 123 in the area SP11 and the control element 123 in the sub-pixel area SP31, and the second data line 121d2 is electrically connected to the control element 123 in the sub-pixel area SP21.

Referring to FIG. 1B , the liquid crystal display panel 100 further includes a transparent conductive layer 130 . In FIG. 1A and FIG. 1B , the transparent conductive layer 130 is omitted and the liquid crystal display panel 100 is shown. The transparent conductive layer 130 is disposed above the pixel circuit array 120 and has a plurality of openings 132h corresponding to the control elements 123 of the pixel circuit array 120. That is to say, the control elements 123 are respectively located in the openings 132h.

The transparent conductive layer 130 in FIG. 1B is shown as dots and covers the pixel circuit array 120. The transparent conductive layer 130 spans the conductive layers of multiple sub-pixel regions SP and is a patterned film layer. In detail, the transparent conductive layer 130 has a plurality of openings 132h, and each opening 132h is a closed opening, so these openings 132h are not connected to each other, and each sub-pixel area SP is provided with an opening 132h. The transparent conductive layer 130 may be made of metal oxide, where the metal oxide is, for example, Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO).

FIG. 1C is a partial top view of the liquid crystal display panel 100 of FIG. 1A , wherein FIG. 1C depicts a partial top view of the liquid crystal display panel 100 in a single sub-pixel area. Please refer to FIG. 1C . The liquid crystal display panel 100 also includes a plurality of pixel electrodes 140 . The pixel electrodes 140 are respectively located in the sub-pixel areas SP11 , SP12 , SP21 , SP22 , SP31 and SP32 . In FIG. 1C , The pixel area SP11 is taken as an example. In addition, FIGS. 1A and 1B illustrate the liquid crystal display panel 100 with the pixel electrode 140 omitted.

It should be noted that the transparent conductive layer 130 is omitted in FIG. 1C (please refer to FIG. 1B ). The transparent conductive layer 130 is actually disposed between the pixel circuit array 120 and the pixel electrode 140 . The relative position between the transparent conductive layer 130 and other film layers is The location is detailed in Figures 2A and 2B.

Referring to FIG. 1C , the pixel electrode 140 is disposed on the pixel circuit array 120 and is electrically connected to the pixel circuit array 120 . The control element 123 is electrically connected to the pixel electrode 140 to control the input of the pixel voltage to the pixel electrode 140 . The pixel electrode 140 includes at least a first electrode trunk 141 and a second electrode trunk 142 perpendicular to the first electrode trunk 141, wherein the first electrode trunk 141 extends along the first direction D1, and the second electrode trunk 142 extends along the second direction D2. extend. The two first electrode trunks 141 are both connected to the second electrode trunk 142, and the second electrode trunk 142 is located between the two first electrode trunks 141, where the two first electrode trunks 141 can extend along the same straight line, that is, this The two first electrode backbones 141 may be coaxial.

Since the first direction D1 and the second direction D2 are substantially perpendicular to each other, the first electrode trunk 141 and the second electrode trunk 142 are also perpendicular to each other. In addition, in the embodiment shown in FIG. 1C , the patterns are crossed to form a cross.

The pixel electrode 140 also includes a vertical electrode strip V11, a vertical electrode strip V12, a horizontal electrode strip H21 and a horizontal electrode strip H22. The extending directions of the vertical electrode strips V11 and V12 are substantially parallel to the extending direction of the first electrode trunk 141 , and the extending directions of the horizontal electrode strips H21 and H22 are substantially parallel to the extending direction of the second electrode trunk 142 . The second electrode trunk 142 connects the vertical electrode strips V11 and V12, and the first electrode trunk 141 connects the horizontal electrode strips H21 and H22.

The pixel electrode 140 also includes a plurality of electrode branches 143. These electrode branches 143 connect the first electrode trunk 141 and the second electrode trunk 142 and extend from the first electrode trunk 141 and the second electrode trunk 142 . The pixel electrode 140 can be divided into four regions based on the first electrode trunk 141 and the second electrode trunk 142, wherein the electrode branches 143 are distributed in these four regions, and the electrode branches 143 in these regions are along at least two different directions. extend. Taking FIG. 1C as an example, these electrode branches 143 extend along the third direction D3 and the fourth direction D4 to form a plurality of slits (slits, not labeled) extending in the third direction D3 and the fourth direction D4, where the third direction D3 is different from the fourth direction D4, and the third direction D3 and the fourth direction D4 are not parallel and not perpendicular to the first direction D1 and the second direction D2.

These electrode branches 143 and these slits can generate multiple fields (multi-domain), so that the image displayed on the liquid crystal display panel 100 is not easily changed significantly by the change of viewing angle, so that the image of the liquid crystal display panel 100 is not easy to be viewed. It is affected by changes in the user's viewing angle, thereby maintaining or improving the image quality of the liquid crystal display panel 100 . It should be noted that in any of these sub-pixel areas SP11, SP12, SP21, SP22, SP31 and SP32, the number of electrode branches 143 is not limited to that of FIG. 1C.

In the embodiment of FIG. 1C , the first data line 121d1 on the left, the second data line 121d2 in the middle, and the first data line 121d1 on the right are arranged in sequence, where the first data line 121d1 on the left and the first data line 121d1 on the right are The lines 121d1 are respectively located on opposite sides of the pixel electrode 140, and the second data line 121d2 is located in the middle of the pixel electrode 140. Specifically, the first data line 121d1 on the left overlaps the vertical electrode strip V11, the first data line 121d1 on the right overlaps the vertical electrode strip V12, and the second data line 121d2 overlaps the first electrode backbones 141.

It can be understood that, although the pixel electrode 140 is not shown in FIGS. 1A and 1B in order to clearly present the pixel circuit array 120, each sub-pixel area SP in FIG. 1A may include a The pixel electrodes 140 shown in FIG. 1C are arranged on the first substrate 111 and arranged in an array. The pixel electrodes 140 are arranged in multiple rows along the first direction D1 and in multiple columns along the second direction D2. In each sub-pixel area SP, the control element 123 is electrically connected to the pixel electrodes 140 to control the pixel electrodes 140 .

In other words, please refer to FIG. 1A and FIG. 1C, the m-th data line (for example, the first data line 121d1 on the left in the sub-pixel areas SP11, SP21, SP31) and the (m+2)-th data line (for example, the sub-pixel area SP11, SP21, SP31) Each of the right first data lines 121d1) in the pixel areas SP11, SP21, and SP31 is located below the intersection of the pixel electrodes 140 (not shown in FIG. 1A) of two adjacent rows. The (m+1)th data line (for example, the second data line 121d2 in the sub-pixel areas SP11, SP21, SP31) and the first data line of the pixel electrodes 140 (not shown in FIG. 1A) arranged in one row The electrode backbones 141 overlap, where m is a natural number greater than zero.

In the embodiment of FIG. 1C , the width W1 of the first data line 121d1 is approximately equal to the width W2 of the second data line 121d2 , and the width W2 of the second data line 121d2 is greater than the width W3 of the first electrode backbone 141 . In other words, in FIG. 1C , the width W1 of the first data line 121d1 on the left, the width W2 of the second data line 121d2 in the middle, and the width W1 of the first data line 121d1 on the right are the same as each other. However, in other embodiments, the width W2 of the second data line 121d2 may be approximately equal to the width W3 of the first electrode trunk 141.

In some embodiments, since the wiring structures of the first data line 121d1 and the second data line 121d2 are different, for example, the first data line 121d1 and the second data line 121d2 have different path lengths, the width of the first data line 121d1 W1 may be different from the width W2 of the second data line 121d2 to balance the resistance and capacitance of the first data line 121d1 and the second data line 121d2.

For example, the width W1 of the first data line 121d1 may range from 10 microns to 12.5 microns, the width W2 of the second data line 121d2 may range from 10 microns to 12.5 microns, and the width of the first electrode backbone 141 W3 is between 4 microns and 6 microns. In some embodiments, the width W3 of the first electrode trunk 141 is approximately equal to the width W4 of the second electrode trunk 142, but is not limited thereto.

In the same pixel electrode 140, the first electrode backbone 141, the second electrode backbone 142, and these electrode branches 143 can be formed by lithography and etching of the same transparent conductive layer, so that there are multiple electrode branches in each area. The connection between 143 and the first electrode trunk 141 and the second electrode trunk 142 has no identifiable boundary such as a seam. Therefore, in the same pixel electrode 140, the first electrode backbone 141, the second electrode backbone 142, and the electrode branches 143 may be integrally formed into one. The pixel electrode 140 may be a transparent conductive layer, which may be made of a metal oxide, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

In the embodiment of FIG. 1C , the first data line 121d1 in the sub-pixel area SP11 is electrically connected to the pixel electrode 140 through the control element 123 . Although FIG. 1A and FIG. 1B omit the pixel electrodes 140 in each sub-pixel area SP, it can be understood that in each of the sub-pixel areas SP21 and SP22, the second data line 121d2 also passes through the control element 123. The pixel electrode 140 is electrically connected therein.

2A is a schematic cross-sectional view drawn along line A-A’ in FIG. 1C , where line A-A’ passes through the second electrode trunk 142 of the pixel electrode 140. Referring to FIG. 2A , the pixel circuit array 120 provided on the first substrate 111 may also include an insulating layer 125 and an insulating layer 126 . The insulating layer 125 may also be called a gate insulating layer. The insulating layer 125 completely covers the upper surface of the first substrate 111 , and the insulating layer 125 further covers the scanning lines 121 s (please refer to FIG. 1A ) and the gates of the control elements 123 (please refer to FIG. 1A ). The insulating layer 126 is formed on the insulating layer 125 and surrounds the first data line 121d1 and the second data line 121d2.

Referring to FIG. 2A , the liquid crystal display panel 100 further includes a second substrate 112 and a plurality of color filter layers 160 . These color filter layers 160 are disposed between the first substrate 111 and the second substrate 112 and are disposed on the pixel circuit array 120, and the transparent conductive layer 130 is disposed on the color filter layer 160, wherein the transparent conductive layer 130 and There may be an insulating layer 152 between the color filter layers 160. It can be understood that the color filter layer 160 shown in FIG. 2A is disposed on the pixel circuit array 120. Therefore, the liquid crystal display panel 100 can be called a color-filter on array (hereinafter referred to as COA). ) structure. It should be noted that the present invention is not limited to COA.

Referring to FIG. 2A , the liquid crystal display panel 100 also includes a liquid crystal layer 170 and a common electrode layer 180 . The liquid crystal layer 170 and the common electrode layer 180 are both disposed between the first substrate 111 and the second substrate 112 . The pixel electrode 140 and the liquid crystal layer 170 are both disposed on the transparent conductive layer 130, and there may be an insulating layer 153 between the pixel electrode 140 and the transparent conductive layer 130. In other words, the transparent conductive layer 130 is disposed between the pixel circuit array 120 and the pixel electrode 140 .

The common electrode layer 180 is disposed on the second substrate 112 and on the liquid crystal layer 170 . The liquid crystal layer 170 is disposed between the common electrode layer 180 and the transparent conductive layer 130 , and is also disposed between the common electrode layer 180 and the pixel electrode 140 . The liquid crystal layer 170 of the present invention is a vertical alignment liquid crystal layer, in which the liquid crystal molecules in the liquid crystal layer 170 can be deflected by the vertical electric field formed between the common electrode layer 180 and the pixel electrode 140 . It should be noted that some components, such as the second substrate 112, the liquid crystal layer 170 and the common electrode layer 180, are omitted in FIGS. 1A to 1C to present the wiring structure of the pixel circuit array 120.

Similar to the first substrate 111, the second substrate 112 can also be a transparent substrate, such as a glass plate, a sapphire substrate or a transparent plastic plate. Similar to the transparent conductive layer 130 and the pixel electrode 140, the common electrode layer 180 can also be a transparent conductive layer, which can be made of the above-mentioned metal oxide, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

Please refer to FIG. 1C, FIG. 2A and FIG. 2B. In the liquid crystal layer 170, affected by the arrangement of the liquid crystal on the first electrode backbone 141 and the second electrode backbone 142, the liquid crystal on the first electrode backbone 141 and the second electrode backbone 142 Block out light. Therefore, please refer to FIG. 1C . When the second data lines 121d2 are disposed directly below the plurality of first electrode trunks 141 , the aperture ratio of the liquid crystal display panel 100 will not be affected.

In addition, the opaque first data line 121d1 is disposed at the junction of the sub-pixel areas SP, so there is no need to provide a shielding metal to shield the junction of the sub-pixel areas SP. Therefore, compared with a liquid crystal display panel with shielding metal, the liquid crystal display panel 100 of the present invention can increase the aperture ratio, thereby improving image quality. In some embodiments, the aperture ratio of the liquid crystal display panel 100 is above 35% to 50%, such as 45.56%.

Referring to FIG. 2A , the liquid crystal display panel 100 further includes a light-transmitting layer 192 and a black matrix 194 disposed between the second substrate 112 and the common electrode layer 180 . The black matrix 194 may be in a mesh shape and have a plurality of grids (not labeled), and the light-transmitting layers 192 are arranged within the grids of the black matrix 194 so that the light-transmitting layers 192 may be arranged in an array.

The color filter layers 160 in the liquid crystal display panel 100 can filter light to generate multiple colors of light, such as blue light, green light and red light, so the color filter layers 160 can be blue light, green light and red light filter layers. The color filter layer 160 can be aligned with the pixel electrode 140 located in the sub-pixel area SP, so that the light passing through the color filter layer 160 can be incident on the pixel electrode 140 . Therefore, multiple colors of light, such as blue light, green light, and red light, can penetrate the liquid crystal layer 170 and be emitted from these light-transmitting layers 192 respectively.

2B is a schematic cross-sectional view drawn along line BB' in FIG. 1C, where line BB' passes through the vertical electrode strip V11 of the pixel electrode 140, the plurality of electrode branches 143, the first electrode trunk 141 and the vertical electrode strip. V12.

Referring to FIGS. 2A and 2B , the transparent conductive layer 130 is disposed between the color filter layer 160 and the pixel electrode 140 so that a storage capacitor (Cst) can be formed between the transparent conductive layer 130 and the pixel electrode 140 and is transparent. The conductive layer 130 can also shield the parasitic capacitance (Cpd) generated between the first data line 121d1, the second data line 121d2 (located under the color filter layer 160) and the pixel electrode 140, thereby improving the image quality of the liquid crystal display.

Please refer to FIG. 1A again. The color filter layer 160 is omitted in FIGS. 1A to 1C. Specifically, each sub-pixel area SP may include a color filter layer 160 . In some embodiments, the sub-pixel areas SP11, SP21 and SP31 are provided with filter layers of the same color, and the sub-pixel areas SP12, SP22 and SP32 are provided with another filter layer of the same color. However, the present invention Not limited to this.

3A and 3B are schematic top views of a liquid crystal display panel 300 according to another embodiment of the present invention. Please refer to FIG. 3A and FIG. 3B. The liquid crystal display panel 300 has a plurality of sub-pixel areas SP (ie, SP11, SP12, SP21, SP22, SP31, SP32). FIG. 3A depicts six sub-pixel areas arranged in a 3×2 array. The prime area SP is used as an example. The liquid crystal display panel 300 is similar to the aforementioned liquid crystal display panel 100. The following mainly describes the differences between the liquid crystal display panel 300 and the liquid crystal display panel 100. Basically, the same features of the liquid crystal display panel 300 and the liquid crystal display panel 100 will not be repeated again.

Referring to FIG. 3A , the liquid crystal display panel 300 includes a pixel circuit array 320 , wherein the pixel circuit array 320 is disposed on the first substrate 111 . The pixel circuit array 320 includes a plurality of first data lines 321d1, a plurality of second data lines 321d2, a plurality of scan lines 321s and a plurality of control elements 323. The first data lines 321d1 and the second data lines 321d2 both extend along the first direction D1 and are arranged along the second direction D2. These scan lines 321s all extend along the second direction D2 and are arranged along the first direction D1. These scan lines 321s intersect the first data lines 321d1 and the second data lines 321d2. The scan lines 321s, the first data lines 321d1 and the second data lines 321d2 are electrically connected to the control elements 323.

See Figure 3A. In the sub-pixel areas SP of each column, the first data lines 321d1 and the second data lines 321d2 are alternately arranged. Taking the first column in FIG. 3A as an example, that is, the sub-pixel areas SP11 and SP12, these first data lines 321d1 are located at the junction of two adjacent sub-pixel areas SP, and these second data lines 321d2 are located at the adjacent Between the two first data lines 321d1. In the sub-pixel areas SP of each row, the first data lines 321d1 and the second data lines 321d2 have bending portions around the control element 123.

Different from the liquid crystal display panel 100 of FIG. 1A , in the embodiment of the liquid crystal display panel 300 of FIG. 3A , the pattern shapes of the first data lines 321d1 and the second data lines 321d2 are the same, for example, they have substantially the same path length. , and all have S-shaped structures. Please refer to FIG. 3A. The first data line 321d1 at the intersection of the sub-pixel areas SP11 and SP12 first extends along the first direction D1, and has a bend around the control element 323 in the sub-pixel area SP11, and then this The first data line 321d1 extends along the first direction D1 to the sub-pixel area SP21, and has a bend around the control element 323 in the sub-pixel area SP21. Afterwards, the first data line 321d1 extends to the junction of the sub-pixel areas SP31 and SP32, and has a bend around the control element 323 in the sub-pixel area SP31.

Similar to the structure of the first data line 321d1, the second data line 321d2 in the sub-pixel area SP12 first extends along the first direction D1, and has a bend around the control element 323 in the sub-pixel area SP12, and then The second data line 321d2 extends along the first direction D1 to the intersection of the sub-pixel areas SP21 and SP22, and has a bend around the control element 323 in the sub-pixel area SP22. Afterwards, the second data line 321d2 extends along the first direction D1 to the sub-pixel area SP32, and has a bend around the control element 323 in the sub-pixel area SP32.

In other words, each of the first data line 321d1 and the second data line 321d2 is located at the junction of two adjacent rows of sub-pixel areas and passes through another sub-pixel area to have an S-shaped structure, and the first The pattern shapes of the data line 321d1 and the second data line 321d2 are substantially the same as each other.

Please refer to FIG. 3B . The liquid crystal display panel 300 further includes a transparent conductive layer 330 . In other words, FIG. 3A is the liquid crystal display panel 300 shown in FIG. 3B with the transparent conductive layer 330 omitted. The transparent conductive layer 330 is disposed above the pixel circuit array 320 and has a plurality of openings 332h corresponding to the control elements 323 of the pixel circuit array 320. In other words, the control elements 323 are respectively located in the openings 332h.

FIG. 3C is a partial top view of the liquid crystal display panel 300 of FIG. 3A . FIG. 3C depicts a partial top view of the liquid crystal display panel 300 in a single sub-pixel area SP11. Referring to FIG. 3C , the liquid crystal display panel 300 also includes a plurality of pixel electrodes 340 . In other words, FIG. 3A and FIG. 3B illustrate the liquid crystal display panel 100 with the pixel electrode 340 omitted. In addition, FIG. 3C also omits the transparent conductive layer 330 (please refer to FIG. 3B ), where the transparent conductive layer 330 is actually disposed between the pixel circuit array 320 and the pixel electrode 340 .

The pixel electrode 340 of FIG. 3C has similar features to the pixel electrode 140 of FIG. 1C , and the difference lies in the wiring structure of the pixel electrodes 140 and 340 connecting the control elements 123 and 323 . The pixel electrodes 140 and 340 can be adjusted according to the wiring structure of the pixel circuit arrays 120 and 320.

Referring to FIG. 3C , the pixel electrode 340 is disposed on the pixel circuit array 320 and is electrically connected to the pixel circuit array 320 . The control element 323 is electrically connected to the pixel electrode 340 to control the input of the pixel voltage to the pixel electrode 340 . The pixel electrode 340 includes at least a first electrode trunk 341 and a second electrode trunk 342 perpendicular to the first electrode trunk 341, wherein the first electrode trunk 341 extends along the first direction D1, and the second electrode trunk 342 extends along the second direction D2. extend. The two first electrode trunks 341 are both connected to the second electrode trunk 342 , and the second electrode trunk 342 is located between the two first electrode trunks 341 .

Since the first direction D1 and the second direction D2 are substantially perpendicular to each other, the first electrode trunk 341 and the second electrode trunk 342 are also perpendicular to each other. In addition, in the embodiment shown in FIG. 3C , the patterns are crossed to form a cross.

The pixel electrode 340 also includes a plurality of electrode branches 343. These electrode branches 343 connect the first electrode trunk 341 and the second electrode trunk 342 and extend from the first electrode trunk 341 and the second electrode trunk 342 .

The pixel electrode 340 also includes a vertical electrode strip V11, a vertical electrode strip V12, a horizontal electrode strip H21 and a horizontal electrode strip H22. The extending directions of the vertical electrode strips V11 and V12 are substantially parallel to the extending direction of the first electrode trunk 341 , and the extending directions of the horizontal electrode strips H21 and H22 are substantially parallel to the extending direction of the second electrode trunk 342 . The second electrode trunk 342 connects the vertical electrode strips V11 and V12, and the first electrode trunk 341 connects the horizontal electrode strips H21 and H22.

In the embodiment of FIG. 3C , the first data line 321d1 on the left, the second data line 321d2 in the middle, and the first data line 321d1 on the right are arranged in sequence, where the first data line 321d1 on the left and the first data line 321d1 on the right are The lines 321d1 are respectively located on opposite sides of the pixel electrode 340, and the second data line 321d2 is located in the middle of the pixel electrode 340. Specifically, the first data line 321d1 on the left overlaps the vertical electrode strip V11, the first data line 321d1 on the right overlaps the vertical electrode strip V12, and the second data line 321d2 overlaps the first electrode backbones 341.

It can be understood that although the pixel electrode 340 is not shown in FIG. 3A, each sub-pixel area SP in FIG. 3A may include the pixel electrode 340 as shown in FIG. 3C, so that these multiple pixels The electrodes 340 are disposed on the first substrate 111 and arranged in an array. The pixel electrodes 340 are arranged in multiple rows along the first direction D1 and in multiple columns along the second direction D2. In each sub-pixel area SP, the control element 323 is electrically connected to the pixel electrodes 340 to control the pixel voltage input to these pixel electrodes 340.

In other words, please refer to FIG. 3A and FIG. 3C , in one of the pixel electrodes 340 in the odd-numbered columns (such as the pixel electrodes 340 in the sub-pixel areas SP11, SP12, SP31 and SP32), the m-th The data line (for example, the second data line 321d2) overlaps the first electrode trunk 341 of the pixel electrode 340. In one of the pixel electrodes 340 in the even columns (such as the pixel electrodes 3402 in the sub-pixel areas SP21 and SP2), the m-th data line (such as the second data line 321d2) is located between two adjacent ones. Below the junction of the pixel electrodes 340, where m is a natural number greater than zero.

In the embodiment of FIG. 3C , the width W5 of the first data line 321d1 is greater than the width W6 of the second data line 321d2 , and the width W6 of the second data line 321d2 is approximately equal to the width W7 of the first electrode backbone 341 . In other words, in FIG. 3C , the width W5 of the first data line 321d1 on the left is the same as the width W5 of the first data line 321d1 on the right. The width of the first data line 321d and the second data line 321d2 at the bend may be smaller than the width of the first data line 321d and the second data line 321d2 at the intersection of the sub-pixel area SP. For example, the width W5 of the first data line 321d1 may range from 10 microns to 12.5 microns, the width W6 of the second data line 321d2 may range from 4 microns to 6 microns, and the width of the first electrode backbone 341 W7 is between 4 microns and 6 microns.

That is to say, please refer to FIG. 3A and FIG. 3C. The m-th data line (for example, the second data line 321d2) is in a pixel electrode 340 in an odd column (for example, the pixel electrode 340 in the sub-pixel area SP11 or SP12). The width in is smaller than the width of the m-th data line (eg, the second data line 321d2) in one pixel electrode 340 of the even column (eg, the pixel electrode 340 in the sub-pixel area SP21 or SP22).

It can be understood that, please refer to FIG. 3A , whether it is the first data line 321d1 or the second data line 321d2, the relationship between the first data line 321d1 and the second data line 321d2 at the junction of two adjacent sub-pixel areas SP The widths are larger than the widths of the first data line 321d1 and the second data line 321d2 in the middle of the sub-pixel area SP.

The cross-sectional structures of the liquid crystal display panel 300 of FIG. 3C and the liquid crystal display panel 100 of FIG. 1C are substantially the same. That is, the liquid crystal display panel 300 has substantially the same cross-sectional structure as shown in FIG. 2A and FIG. 2B , so it is not shown again. in the diagram. The difference between the liquid crystal display panels 100 and 300 lies in the second data lines 121d2 and 321d2. For example, please refer to FIG. 1A and FIG. 3A. In the sub-pixel area SP11, the width of the second data line 121d2 of the liquid crystal display panel 100 is larger than the width of the second data line 121d2 of the liquid crystal display panel 300.

In the liquid crystal layer (not shown), affected by the arrangement of the liquid crystals on the first electrode backbone 341 and the second electrode backbone 342, the liquid crystals on the first electrode backbone 341 and the second electrode backbone 342 block light. Therefore, please refer to FIG. 3C , when the second data line 321d2 is disposed directly below the plurality of first electrode trunks 341, it will not affect the aperture ratio of the liquid crystal display panel 300.

In addition, the first data line 321d1 of the liquid crystal display panel 300 is disposed at the junction of the sub-pixel areas SP, so there is no need to provide a shielding metal to shield the junction of the sub-pixel areas SP. Therefore, compared with a liquid crystal display panel with shielding metal, the liquid crystal display panel 300 of the present invention can increase the aperture ratio, thereby improving image quality. In some embodiments, the aperture ratio of the liquid crystal display panel 300 is above 35% to 50%, such as 48.8% or 49.8%.

In summary, the liquid crystal display panel of the present invention includes a transparent conductive layer disposed between the color filter layer and the pixel electrode. Therefore, it can shield the data line (located under the color filter layer) and the pixel electrode. generated parasitic capacitance. In addition, the data lines of the liquid crystal display panel of the present invention are arranged at the junction of the sub-pixel areas of two adjacent rows to increase the aperture ratio, thereby improving image quality.

The above summary of features of various embodiments allows those skilled in the art to better understand aspects of the present disclosure. Those skilled in the art should appreciate that the present disclosure may be readily used as a basis for designing or modifying other processes and structures that carry out the same purposes and/or achieve the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and various changes, substitutions and modifications may be made herein without departing from the spirit and scope of the disclosure. .

100, 300: LCD panel 111: First substrate 112:Second substrate 120, 320: Pixel circuit array 121d1, 321d1: first data line 121d2, 321d2: Second data line 121s, 321s: scan line 123, 323:Control components 125, 126: Insulation layer 130, 330:Transparent conductive layer 132h, 332h: Opening 140, 340: Pixel electrode 141, 341: first electrode trunk 142, 342: Second electrode trunk 143, 343:Electrode branch 152, 153: Insulation layer 160: Color filter layer 170:Liquid crystal layer 180: Common electrode layer 192: Translucent layer 194:Black Matrix V11, V12: vertical electrode strips H21, H22: Horizontal electrode strip SP, SP11, SP12, SP21, SP22, SP31, SP32: sub-pixel area D1: first direction D2: second direction D3: Third direction D4: The fourth direction W1, W2, W3, W4, W5, W6, W7: Width A-A’, B-B’: line

Various aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be understood that, in accordance with standard practice in the industry, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily increased or reduced for clarity. 1A and 1B are schematic top views of a liquid crystal display panel according to at least one embodiment of the present invention. FIG. 1C is a partial top view of the liquid crystal display panel of FIG. 1A . Figure 2A is a schematic cross-sectional view drawn along line A-A' in Figure 1C. Figure 2B is a schematic cross-sectional view drawn along line B-B' in Figure 1C. 3A and 3B are schematic top views of a liquid crystal display panel according to another embodiment of the present invention. FIG. 3C is a partial top view of the liquid crystal display panel of FIG. 3A.

Domestic storage information (please note in order of storage institution, date and number) without Overseas storage information (please note in order of storage country, institution, date, and number) without

100:LCD display panel

111: First substrate

120: Pixel circuit array

121d1: The first data line

121d2: Second data line

121s: scan line

123:Control components

SP, SP11, SP12, SP21, SP22, SP31, SP32: sub-pixel area

D1: first direction

D2: second direction

Claims (10)

A liquid crystal display panel including: a first substrate; A plurality of pixel electrodes are disposed on the first substrate and arranged in an array, wherein the pixel electrodes are arranged in multiple rows along a first direction and in multiple columns along a second direction, wherein the The first direction is perpendicular to the second direction, and each pixel electrode includes: At least one first electrode trunk and a second electrode trunk perpendicular to the at least one first electrode trunk, wherein the at least one first electrode trunk extends along the first direction, and the second electrode trunk extends along the second direction; as well as A plurality of electrode branches connect the at least one first electrode trunk and the second electrode trunk, and extend from the at least one first electrode trunk and the second electrode trunk; A pixel circuit array is provided on the first substrate, wherein the pixel electrodes are provided on the pixel circuit array, and the pixel circuit array includes: A plurality of data lines are electrically connected to the pixel electrodes, each of the data lines extends along the first direction, and the data lines are arranged along the second direction, wherein two adjacent data lines One of the lines is electrically connected to the pixel electrodes in the odd-numbered columns, and the other of the two adjacent data lines is electrically connected to the pixel electrodes in the even-numbered columns; In one of the pixel electrodes, the first data line and the third data line among the three data lines arranged in sequence are respectively located on opposite sides of the pixel electrode, and the three data lines among the three data lines The second data line overlaps the at least one first electrode trunk of the pixel electrode; A transparent conductive layer is disposed between the pixel circuit array and the pixel electrodes; a second substrate; and A liquid crystal layer is provided between the first substrate and the second substrate. The liquid crystal display panel as described in claim 1, wherein each of the m-th data line and the (m+2)-th data line is located below a junction of the pixel electrodes of two adjacent rows, and the (m-th) data line m+1) data lines overlap with the at least one first electrode backbone of the pixel electrodes in the same row, where m is a natural number greater than zero. The liquid crystal display panel as described in claim 2, wherein a width of the m-th data line, a width of the (m+1)-th data line, and a width of the (m+2)-th data line identical to each other. The liquid crystal display panel of claim 2, wherein a width of the (m+1)th data line is greater than a width of the at least one first electrode trunk. The liquid crystal display panel of claim 1, wherein in one of the pixel electrodes in the odd-numbered column, the m-th data line overlaps with the at least one first electrode backbone of the pixel electrode, and In one of the pixel electrodes in the even-numbered column, the m-th data line is located below a junction of two adjacent pixel electrodes, where m is a natural number greater than zero. The liquid crystal display panel of claim 5, wherein a width of the m-th data line in a pixel electrode of the odd-numbered column is smaller than a width of the m-th data line in a pixel electrode of the even-numbered column. Width. The liquid crystal display panel as described in claim 1 further includes: A color filter layer is disposed on the pixel circuit array to form a color filter film transistor array. The liquid crystal display panel as described in claim 1 further includes: A liquid crystal layer is disposed between the second substrate and the transparent conductive layer, wherein the liquid crystal layer is a vertical alignment liquid crystal layer. The liquid crystal display panel as described in claim 1 further includes: A common electrode layer is provided on the second substrate; and A liquid crystal layer is disposed between the common electrode layer and the transparent conductive layer. The liquid crystal display panel of claim 1, wherein the electrode branches extend along a third direction and a fourth direction, the third direction is different from the fourth direction, and the third direction is not parallel to the fourth direction. and not perpendicular to the first direction and the second direction.

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