TWI830212B - Communication terminals and communication systems - Google Patents

Abstract

The communication terminal 30 of the present invention receives a voltage signal in which the signal voltage is superimposed on a specific reference voltage through the signal line 60, and is provided with: a signal receiving part 310 having a receiving terminal B for receiving the voltage signal; and a voltage clamp circuit 320 , which clamps the receiving end B when the voltage at the receiving end B exceeds the voltage within a specific range from the reference voltage V10, that is, the first specific voltage V1. The voltage clamp circuit 320 has: a reference voltage holding part 321, which holds the first specific voltage V1; and a voltage detection part 322, which maintains the receiving end B and the reference voltage when the voltage of the receiving end B exceeds the first specific voltage V1. Part 321 is turned on.

Description

Communication terminals and communication systems

The present disclosure relates to a communication terminal and a communication system.

Previously, communication systems for load control using 2-wire signal lines have become popular. This communication system is composed of a transmitting terminal, which is the mother machine of the central control device, and communication terminals such as switches, which are connected to each other with a 2-wire signal line. This communication system has the characteristic of freely connecting or branching 2-wire signal lines and arranging communication terminals (called free topology), and is a flexible system structure. According to this communication system, a communication system can be implemented in a large-scale building with less wiring. Patent Document 1 discloses an example of a communication system.

[Prior technical literature] [Patent Document]

[Patent Document 1] Japanese Patent Application Publication No. 2019-204638

In communication systems, there is an increase in the number of communication terminals or a requirement for high-speed and large-capacity communication. In response to this, it is considered to increase the frequency of signals sent from the sending terminal. However, if you believe As the signal frequency increases, due to the impedance mismatch between signal lines, transmitting terminals or communication terminals, the influence of reflected waves cannot be ignored. Due to the influence of reflected waves, communication terminals may misread signals.

In order to suppress the reflected waves of high-frequency signals, impedance matching is usually adopted. However, since the communication system is a free topology, the characteristic impedance of the signal line changes due to changes in the configuration of the signal line or communication terminal, making impedance matching more difficult. As the frequency of transmission signals in this communication system increases, signal misreading caused by reflected waves becomes a problem.

The purpose of this disclosure is to provide a communication terminal and communication system that are not easily affected by reflected waves and are not prone to signal misreading.

The communication terminal of the present disclosure receives a voltage signal in which the signal voltage is superimposed on a specific reference voltage through a signal line, and is provided with: a signal receiving part having a receiving end to receive the voltage signal; and a voltage clamping circuit at the receiving end. When the voltage exceeds the voltage within a specific range from the reference voltage, that is, the first specific voltage, the receiving end is clamped. The voltage clamp circuit is characterized by having: a reference voltage holding part that holds a first specific voltage; and a voltage detection part that conducts the receiving end and the reference voltage holding part when the voltage at the receiving end exceeds the first specific voltage.

According to the present disclosure, communication terminals and communication systems that are not easily affected by reflected waves and are not prone to signal misreading can be realized.

10:Communication system

20: Sending terminal

30: Communication terminal

31: switch

31a:Operation Department

31b: Operation Department

31c:Operation Department

31d:Operation Department

32:Terminal unit

40a:Relay

40b:Relay

40c:Relay

40d:Relay

50a:Lighting fixtures

50b:Lighting fixtures

50c:Lighting fixtures

50d: lighting fixtures

60:Signal line

310: Signal receiving department

320: Voltage clamp circuit

321: Reference voltage holding part

322: Voltage detection department

330:Bypass circuit

340: Trigger circuit

B: receiving end

C1: Capacitor

C2: Capacitor

C3: Capacitor

C4: Capacitor

CP: Comparator

D1: Diode

D2: Diode

OP: operational amplifier

Q1: Transistor

Q2: Transistor

R1: Resistor

R2: Resistor

R3: Resistor

R4: Resistor

R5: Resistor

R6: Resistor

R7: Resistor

R8: Resistor

R9: Resistor

R10: Resistor

R11: Resistor

R12: Resistor

R13: Resistor

Td: signal delay time

V10: reference voltage

Vi: voltage signal

Vo: receiving end voltage

Vo_: receiving end voltage

V(t):voltage

V(t-Td): voltage

Z _A :Output impedance

Z _AB :Characteristic impedance

Z _B : input impedance

ρ _A :reflection coefficient

ρ _B :reflection coefficient

Fig. 1 is a structural diagram of the communication system of the embodiment.

Figure 2 is an equivalent circuit diagram of one form of the communication system.

Figure 3 is a diagram illustrating the principle of reflected waves in a transmission line.

Figure 4 is a waveform diagram showing the transmitted signal and its reflected wave in the transmission line.

FIG. 5 is a structural diagram of a communication system including a communication terminal according to the embodiment.

FIG. 6 is a waveform diagram illustrating reflection wave suppression of the communication terminal according to the embodiment.

Figures 7 (a) and (b) are circuit diagrams of the communication terminal according to the embodiment.

FIG. 8 is a circuit diagram of a communication terminal according to another embodiment.

FIG. 9 is a circuit diagram of a communication terminal according to another embodiment.

FIG. 10 is a circuit diagram of a communication terminal according to another embodiment.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following description, specific shapes, materials, directions, numerical values, etc. are examples used to facilitate understanding of the present disclosure, and can be appropriately changed according to the use, purpose, specifications, etc. In addition, the case of selectively combining the constituent elements of the embodiments and modifications described below has been conceived from the beginning.

First, the overall structure and general operation of a communication system using the communication terminal of the present disclosure will be described.

[Communication system]

FIG. 1 is a structural diagram of the communication system 10. The communication system 10 includes a sending terminal 20 as a communication The switch 31 and the terminal unit 32 of the terminal 30, the relays 40a~40d and the lighting fixtures 50a~50d. The lighting fixtures 50a to 50d are control objects in the communication system 10 . In addition, in addition to these machines, the communication system 10 can be connected to other switches, other terminal units, other control objects, etc., but illustration is omitted. The communication system 10 is a system centered on the transmitting terminal 20 and capable of controlling the lighting fixtures 50a to 50d, etc., which are the control objects in the communication system 10. The control of lighting equipment means on-off control, dimming control, scene control, monitoring control, etc. of lighting equipment. Scene control means dimming and coloring control of lighting equipment according to the lighting equipment’s settings in Japanese-style rooms, Western-style rooms, bedrooms, studies, etc., and the conditions of use of lighting equipment in the morning, day, night, eating time, reunion time, etc. . Monitoring control means monitoring the control status of lighting fixtures. In addition, these controls can be performed by operating the switch 31 .

The communication system 10 adopts, for example, a time-sharing multiplex transmission method, and the signal line 60 is composed of a two-wire wire. In the signal line 60, signals (information) are transmitted by pulse signals caused by the potential difference between the two lines. Furthermore, in the communication system 10 , for example, a cyclic transmission method is used, and the signal transmitted from the transmitting terminal 20 passes through all the devices connected to the signal line 60 . Each machine confirms the content of the signal and causes the machine that needs the signal to receive the signal based on the content. For example, each machine receives the signal when the signal contains its own address information, and ignores the signal when it does not contain its own address information. In this way, the device connected to the signal line 60 can also confirm the content of the signal sent from the sending terminal 20 with a destination address other than its own.

The sending terminal 20 is a parent controller that operates as a center in the communication system 10 . The transmission terminal 20 transmits the signal from the switch 31 connected to the signal line 60 to the terminal unit 32 . The switch 31 and the terminal unit 32 in Figure 1 are the communication terminal 30 of the present disclosure.

The switch 31 is a wall switch set by the user to control (on, off, dimming, etc.) the lighting fixtures 50a to 50d. For example, the switch 31 has four operating parts 31a to 31d as shown in FIG. 1 . Each operating part has, for example, two states: an on state and an off state, and the lighting fixture corresponding to each operating part can be turned on and off by the user's operation.

For example, address information is assigned to each operation part, and a correspondence between the address information and the lighting fixture is established in a one-to-one manner.

The terminal unit 32 is a device that transmits signals transmitted from the transmission terminal 20 to the relays 40a to 40d. The terminal unit 32 has a plurality of terminals, and relays 40a to 40d are connected to the plurality of terminals.

The relays 40a to 40d are switches that switch on and off the supply of electric power to the respective connected lighting fixtures 50a to 50d. For example, when each relay receives an instruction to turn on the power supply from the terminal unit 32, it turns on the power supply to the lighting fixture connected to itself, and when it receives an instruction to turn off the power supply, it turns off the power supply to the lighting fixture connected to itself. Electricity supply for lighting fixtures. In addition, the terminal unit 32 and the relays 40a to 40d may be integrally formed.

The lighting fixtures 50a to 50d are, for example, installed on the ceiling of the floor of the facility. Each lighting fixture can be switched on and off and the dimming rate (brightness) can be changed by a signal from the transmitting terminal 20, for example. Light sources of lighting fixtures include LEDs (Light Emitting Diodes), fluorescent lamps, etc., but are not particularly limited.

According to this communication system 10, wiring for connecting the control object and the switch 31 one-to-one is unnecessary. In the communication system 10, only the signal line 60 including two lines is sufficient. Thereby, for example, the wiring of the communication system 10 in a large-scale building can be reduced.

The above describes an example in which the control object is applied to the lighting fixture in the communication system 10, but the control object is not limited to the lighting fixture. The communication system 10 can also be configured to control other machines such as air conditioning equipment.

In the communication system 10, when the number of connected terminals is increased or the signal information between terminals is increased, corresponding measures are taken to increase the frequency of the signal in order to maintain the response of the system. If the frequency of the control signal transmitted through the signal line is increased, the influence of the reflected wave becomes significant. The communication terminal of the present disclosure has a structure that is not affected by reflected waves and suppresses misreading of signals.

The communication system 10 of the present disclosure is topologically free, so impedance matching is not required. When impedance matching is not performed, reflected waves are generated. The principle of generating reflected waves is explained below.

[The generation principle of reflected waves]

Referring to Figures 2 to 4, the principle of generating reflected waves will be explained.

FIG. 2 is an equivalent circuit diagram of the smallest unit of the communication system 10 of the present disclosure, which is composed of a transmitting terminal 20, a signal line 60, and a communication terminal 30.

Vi is the voltage signal sent from the sending terminal 20. Point A is the sending end of the sending terminal 20. Z _A is the output impedance of the sending terminal 20. The signal line 60 is connected between point A and point B, and Z _AB is the characteristic impedance of the signal line 60 . Point B is the receiving end of the communication terminal 30 . Z _B is the input impedance of the communication terminal 30 .

ρ _A represents the reflection coefficient of the transmitting end A, and ρ _B represents the reflection coefficient of the receiving end B, respectively defined by the following formulas.

ρ _A =(Z _A -Z _AB )/(Z _A +Z _AB ) (Formula 1)

ρ _B =(Z _B -Z _AB )/(Z _B +Z _AB ) (Formula 2)

Let the signal delay time of the signal line 60 (the time required to propagate a signal from point A to point B) be Td.

The output impedance Z _A of the transmitting terminal 20 is set to a low impedance, Z _A < Z _AB , for the purpose of suppressing a voltage drop caused by the output current. Therefore, the numerator sign of Equation 1 is negative, and the reflection coefficient ρ _A at the transmitting end is negative. The input impedance Z _B of the communication terminal 30 is set to high impedance in order to maintain the amplitude of the voltage signal at the receiving end, and is Z _B >Z _AB . Therefore, the numerator sign of Equation 2 is positive, and the reflection coefficient ρ _B at the receiving end is positive. In the communication system 10 of the present disclosure, unless otherwise specified, the communication system 10 will be described as being under this condition.

Figure 3 is a conceptual diagram showing the reflected wave generated between the transmitter A and the receiver B. FIG. 4 shows the voltage Vi of the transmitting terminal 20 and the receiving end voltage Vo of the receiving end B. As shown in FIG. The transmitting terminal 20 of the present disclosure outputs a voltage signal in which a negative voltage is superimposed on a specific DC (Direct current) voltage (reference voltage V10) as a voltage signal. Voltage Vi in Figure 4 represents a single transmission from the transmitting terminal 20 The voltage of the voltage signal. The receiving end voltage Vo in Figure 4 is the voltage observed at the receiving end B and represents the waveform affected by the reflected wave.

[Reflected wave at the receiving end at time Td]

The voltage Vi sent from the transmitting terminal 20 at time 0 is reduced by the output impedance Z _A. The voltage V(t) propagates on the signal line 60 and reaches the receiving end B after the delay time Td. The receiving end voltage received by receiving end B is delayed by time Td from V(t), expressed as V(t-Td). Since impedance matching is not performed at the receiving end B, a reflected wave corresponding to the arriving voltage V(t-Td) is generated and propagates in the signal line 60 toward the transmitting end.

In the receiving end B, the reflected wave generated is ρ B V(t-Td) of the arriving voltage V(t-Td) multiplied by the reflection coefficient _{ρ B.} Since the reflection coefficient ρ _B of the receiving end B is positive, the reflected wave ρ _B V(t-Td) is a voltage in the same phase as the voltage V(t). The reflected wave ρ _B V (t-Td) propagates toward the transmitting end after time Td. In the receiving end B, the composite voltage of the arriving voltage V(t-Td) and the reflected wave ρ _B V(t-Td) is observed. This voltage appears as a voltage that fluctuates significantly in the negative direction after time Td in FIG. 4 . In this disclosure, the signal that initially changes on the negative side at the receiving end B is called the main wave (wave 1).

The voltage generated at the receiving end B since time Td is expressed by the following formula.

V(t-Td)+ ρ _B V(t-Td)=(1+ ρ _B )V(t-Td) (Equation 3)

[Reflected wave at the sending end at time 2Td]

The reflected wave ρ _B V (t-Td) at the receiving end B reaches the transmitting end at time 2Td (the elapsed time of 2 times the delay time). Since the sending end is delayed by time Td, the arriving reflected wave is ρ _B V (t-2Td). Since the transmitting end A does not perform impedance matching, a reflected wave is generated. The reflected wave at the transmitting end A opposite to ρ _B V (t-2Td) is ρ _A ρ _B V (t-2Td). Since the reflection coefficient of the transmitting end A is negative, the reflected wave ρ _A ρ _B V (t-2Td) is a voltage that is inverse phase with the arriving voltage ρ _B V (t-2Td). The voltage ρ _A ρ _B V (t-2Td) propagates in the signal line and reaches the receiving end B at time 3Td.

[Reflected wave at the receiving end after time 3Td]

If the reflected wave ρ _A ρ _B V (t-2Td) from the transmitting end A reaches the receiving end B at time 3Td, due to the delay of time Td, the arriving voltage is ρ _A ρ _B V (t-3Td). A reflected wave corresponding to the arrival voltage is generated. The reflected wave relative to the arriving voltage ρ _A ρ _B V (t-3Td) is ρ _A ρ _B ² V (t-3Td). The reflected wave ρ _A ρ _B ² V(t-3Td) propagates from the receiving end B to the transmitting side. The combined voltage of the voltage arriving at time 3Td and its reflected wave is expressed by the following formula.

ρ _A ρ _B V(t-3Td)+ ρ _A ρ _B ² V(t-3Td)= ρ _A ρ _B (1+ ρ _B )V(t-3Td) (Equation 4)

On the other hand, in the receiving end B, the voltage generated at time Td, that is, the voltage of equation 3, still exists. Therefore, what is observed at the receiving end B is the combined voltage of the voltages expressed by Equation 3 and Equation 4.

The voltage component represented by Equation 4 has the opposite sign than the voltage component of Equation 3. The voltage component represented by Equation 4 is shown in FIG. 4 as a voltage that changes on the positive side. In this disclosure, the signal that initially changes on the positive side is called the second wave.

From now on, similarly at time 5Td, the combined voltage of the voltage reaching the receiving end B and its reflected wave is expressed by the following formula. is: ρ _A ² ρ _B ² V(t-5Td)+ ρ _A ² ρ _B ³ V(t-5Td)= ρ _A ² ρ _B ² (1+ ρ _B )V(t-5Td) (Equation 5)

The voltage component represented by Equation 5 has the same positive sign as the voltage component of Equation 3. This voltage component is shown in Figure 4 as the voltage that changes on the negative side for the second time. In this disclosure, this signal is referred to as wave 3.

Afterwards, reflections are also repeated at the receiving end B and the transmitting end A every time Td. At the receiving end B, every delay time 2Td, a reflected wave will arrive, generating the Mth wave (M is an integer).

[Influence of reflected waves in communication systems]

The 3rd wave, 5th wave, and Nth wave (N is an odd number) in Figure 4 are voltages whose amplitude direction is the same as the main wave and overlaps in the negative direction. As a signal transmission method, when the reference voltage V10 is used as the base state and a negative voltage is superimposed as a data signal transmission method, there is a risk of misreading the Nth wave such as the 3rd wave and the 5th wave as a data signal. Wave 3, which has less attenuation, is particularly problematic.

Thereafter, the details of the reflected wave suppression of the communication terminal of the present disclosure are explained.

[Mechanism of reflected wave suppression]

FIG. 5 is a block diagram showing the structure of the communication terminal 30 connected to the communication system 10 . The communication terminal 30 is connected to the signal line 60 at the receiving end B. At the receiving end B, a voltage clamp circuit 320, a bypass circuit 330, and a trigger circuit 340 are connected. Z _B is the input impedance of the communication terminal 30 including the signal receiving part 310 .

The signal receiving unit 310 reads the signal from the receiving end voltage Vo_ and interprets the information contained in the signal sent from the sending terminal 20 . The communication terminal 30 performs various actions based on this signal, but details are omitted. section.

The voltage clamp circuit 320 inputs the receiving end voltage Vo_ received by the receiving end B. The voltage clamp circuit 320 receives the receiving end voltage Vo_ and maintains the first specific voltage V1 (hereinafter also referred to as the holding voltage V1). The voltage clamp circuit 320 clamps the receiving end voltage Vo_ to the first specific voltage V1 when the receiving end voltage Vo_ is a voltage higher than the first specific voltage V1. The first specific voltage V1 is set to a voltage within a specific range from the reference voltage V10 of the communication system 10 for transmitting signals, for example, within the range of 0.3V~1.4V.

The bypass circuit 330 is connected to the receiving end B, and when the receiving end voltage Vo_ exceeds the first specific voltage V1, the receiving end B is bypassed with a low impedance to suppress the rise of the receiving end voltage Vo_. The bypass circuit 330 operates when the trigger circuit 340 receives the trigger signal.

The trigger circuit 340 generates a trigger signal for activating the bypass circuit 330 . When the receiving end voltage Vo_ exceeds the first specific voltage V1, the trigger circuit 340 is configured to generate a trigger signal.

In the communication terminal 30 of this embodiment, since the voltage clamp circuit 320 is provided at the receiving end B, the second wave of the reflected wave shown in FIG. 4 is generated, and the receiving end voltage Vo_ is clamped to the first specific voltage. V1. Specifically, the voltage above the voltage V1 of the second wave in FIG. 4 is cut off. Since the second wave disappears, the subsequent reflected waves after the third wave also disappear. Thereby, reflected waves that cause signal misreading by the communication terminal 30 are suppressed.

In this embodiment, when the reception signal transmitted from the transmission terminal 20 first arrives, the reception The reflected wave generated at terminal B (the main wave in Figure 4) is not suppressed. The reason is that since the polarity of the received signal at the receiving end B is the same as that of the corresponding reflected wave, only the amplitude increases and there is no signal misreading.

FIG. 6 shows the receiving end voltage Vo_, the transmitting end transmitting voltage Vi, and the receiving end voltage Vo when the reflected wave is not suppressed of the communication terminal 30 of this embodiment.

As described above, the voltage clamp circuit 320 has the function of cutting off the portion of the receiving terminal voltage Vo exceeding the first specific voltage V1 (shown with a hatched line in the figure) when the reflected wave is not suppressed. In fact, the voltage clamping circuit 320 clamps the first positive polarity change voltage (the second wave) of the receiving end voltage Vo to the first specific voltage V1. Thereby, reflection from the receiving end B to the transmitting end A is substantially suppressed. Thereby, the reflection from the transmitting end A also disappears, and the higher-order reflected waves disappear. It can be seen that the receiving end voltage Vo_ of the communication terminal 30 of this embodiment is cut off to a voltage higher than the first specific voltage V1. By cutting off the second wave of the receiving end voltage Vo_, the subsequent reflected waves after the third wave are suppressed. Through the above actions, reflected waves are suppressed and the risk of signal misreading is eliminated.

Next, specific embodiments will be described.

[First Embodiment]

FIG. 7(a) shows a circuit diagram of the first embodiment of the communication terminal 30. The signal receiving unit 310 is not shown in the figure. In the first embodiment, the voltage clamp circuit 320 and the bypass circuit 330 are connected in parallel to the receiving end B.

The voltage clamp circuit 320 consists of a series circuit of diode D1, resistor R3 and capacitor C1, and Resistor R1 is connected in parallel with capacitor C1. The bypass circuit 330 and the emitter-collector of the PNP transistor Q1 are formed by a series circuit of the resistor R2. The diode D1, the resistors R3, R4, and the emitter-base of the transistor Q1 form a trigger circuit 340.

The capacitor C1 and the resistor R1 of the voltage clamp circuit 320 constitute the reference voltage holding part 321. The capacitor C1 works by receiving the receiving end voltage Vo_ received by the receiving end B and maintaining the first specific voltage V1. The capacitor C1 is set to a sufficiently large capacity in order to maintain the voltage at a substantially specific level with respect to the frequency of the signal included in the receiving end voltage Vo_ (that is, the frequency included in the transmission signal). The resistor R1 is a discharge resistor of the capacitor C1 and prevents the holding voltage of the capacitor C1 from excessively rising from the first specific voltage V1. Resistor R1 is set to a higher resistance. Diode D1 constitutes voltage detection section 322 . The diode D1 is turned on when the receiving end voltage Vo_ is higher than the sum of the holding voltage of the capacitor C1 and the forward voltage of the diode D1, and current flows through the resistor R3 to the capacitor C1. Since the capacitance of the capacitor C1 is set to a sufficiently large capacity as described above, the voltage hardly changes due to the current flowing through the resistor R3. Resistor R3 is selected to have a smaller resistance value compared with resistor R1. The holding voltage V1 of the capacitor C1 is maintained as the voltage obtained by subtracting the forward voltage of the diode D1 (about 0.3~0.7V) from the reference voltage.

Through the function of the above voltage clamping circuit 320, the receiving end voltage Vo_ received by the receiving end B can be restrained from rising above the first specific voltage V1. This suppresses reflected waves and eliminates the risk of signal misreading.

In this embodiment, the bypass circuit 330 is connected in parallel to the voltage clamp circuit 320 . The bypass circuit 330 connects the resistor R2 to the receiving end B via the transistor Q1 to bypass the current and assist The voltage holding function of the voltage clamp circuit 320 operates.

The bypass circuit 330 is a PNP transistor Q1 whose emitter is connected to the receiving terminal B, and whose collector is connected to one end of the resistor R2. The other end of resistor R2 is connected to circuit ground. Resistor R2 is preferably selected to have low resistance. The base of transistor Q1 is connected to the connection point of resistor R3 and capacitor C1 via resistor R4.

When the receiving end voltage Vo_ exceeds the holding voltage of capacitor C1 and rises, as shown above, diode D1 is turned on, and current flows through the path of diode D1, resistor R3, and capacitor C1. At this time, due to the forward voltage of diode D1 and the voltage drop of resistor R3, the base potential becomes low relative to the emitter potential of transistor Q1, and current flows from the emitter of transistor Q1 to the base. Thereby, the emitter-collector of the transistor Q1 is conductive, forming a path that bypasses the receiving end B and the emitter-collector of the transistor Q1 with the resistor R2. The resistor R2 has a low resistance. When the transistor Q1 is turned on and the receiving end voltage Vo_ is to be increased, the current can also be bypassed to suppress the increase in the receiving end voltage Vo_. The bypass circuit 330 can suppress the sudden rise of the voltage at the receiving end.

As shown above, between the diode D1, the resistors R3 and R4, and the emitter-base of the transistor Q1, the trigger circuit 340 of the bypass circuit 330 functions. In addition, the diode D1 is turned on when the receiving end voltage Vo_ is equal to or higher than the first specific voltage V1 of the capacitor C1, and functions as the voltage detection unit 322 that operates the trigger circuit 340.

When the receiving end voltage Vo_ is less than the sum of the holding voltage V1 of the capacitor C1 and the forward voltage of the diode D1 (the second specific voltage), the diode D1 is disconnected, and the emitter potential of the transistor Q1 is less than the base voltage of Q1. potential, and transistor Q1 is turned off, bypass circuit 330 is stopped.

That is, in this embodiment, when the receiving end voltage Vo_ exceeds the first specific voltage, the bypass circuit that bypasses the receiving end B operates, and thereafter, when the receiving end voltage Vo_ is lower than the first specific voltage or more That is, at the second specific voltage, the operation of the bypass circuit is stopped. In addition, the relationship between the first specific voltage and the second specific voltage is not limited to this embodiment. The second specific voltage may be set to be the same as the first specific voltage.

As mentioned above, through the operation described in the first embodiment, the receiving terminal voltage Vo_ can be prevented from generating a voltage higher than the holding voltage V1 of the capacitor C1, and the influence of the reflected wave can be suppressed. Therefore, misreading of signals can be prevented.

Fig. 7(b) shows a modified example of the first embodiment. The configurations of the voltage clamp circuit 320 and the trigger circuit 340 are the same as those of the first embodiment in FIG. 7(a) , except that the connection position of the bypass circuit 330 is changed from the receiving end B to the cathode of the diode D1.

When the receiving end voltage Vo_ rises beyond the holding voltage of the capacitor C1 and the diode D1 is turned on, the voltage drops due to the current flowing through the resistor R3, causing the base potential to be at a low potential relative to the emitter potential of the transistor Q1, and Current flows from the emitter to the base. Compared with the embodiment of FIG. 7(a) , only the forward voltage part of the diode D1, which involves the voltage between the emitter and the base of the transistor Q1, becomes lower, and the operation of the bypass circuit 330 is the same. The holding voltage V1 of the capacitor C1 is maintained as the voltage obtained from the reference voltage minus the sum of the forward voltage of the diode D1 and the emitter-base voltage of the transistor Q1 (approximately 1.4V).

When the signal voltage is received at the receiving end B, that is, when the main wave arrives in Figure 6, the voltage at the receiving end B is a lower voltage than the reference voltage V10. Since the capacitor C1 of the voltage clamp circuit 320 maintains the holding voltage V1, a voltage V3 is generated from the non-ground side terminal of the capacitor C1 toward the receiving end B. In the structure of FIG. 7(a) , voltage V3 is applied from the cathode toward the anode of diode D1 and at the same time, it is applied from the base of transistor Q1 toward the emitter. When the amplitude of the signal voltage is large, that is, when the voltage V3 is large, a component with a large withstand voltage between the terminals of the transistor Q1 must be selected.

In the structure of Figure 7(b), since the voltage V3 is only generated from the cathode toward the anode of the diode D1, there is an advantage that a component with a smaller withstand voltage between the terminals of the transistor Q1 can be selected. The action of suppressing reflected waves has the same effect as in Figure 7(a).

[Second Embodiment]

FIG. 8 shows a circuit diagram of the second embodiment of the communication terminal 30. In this embodiment, the voltage clamp circuit 320 is connected in parallel to the receiving end B and does not have a bypass circuit and a trigger circuit.

The voltage clamp circuit 320 is composed of a series circuit of a diode D1 and a capacitor C1, and a resistor R1 connected in parallel with the capacitor C1. Capacitor C1 is a capacitor used to maintain the reference voltage, and resistor R1 is the discharge resistance of capacitor C1. The diode D1 conducts when the receiving end voltage Vo_ exceeds the holding voltage V1 of the capacitor C1 and charges the capacitor C1. The capacitance of the capacitor C1 is appropriately set so that the voltage hardly changes due to the charging current. Therefore, the receiving terminal voltage Vo_ is clamped to the holding voltage V1 of the capacitor C1.

In the second embodiment, there is no bypass circuit. When only the discharge resistor R1 is connected in parallel with the capacitor C1, the voltage of the reflected wave may rise, gradually causing the voltage of the capacitor C1 to rise. Specifically, when the signal voltage is repeatedly transmitted from the transmitting terminal 20 and a reflected wave in a direction more positive than the reference voltage V10 is continuously generated, the capacitor C1 may not be fully discharged due to the resistance value of the resistor R1. When the holding voltage of the capacitor C1 rises, the clamp voltage rises and the reflected wave may not be sufficiently suppressed. In the second embodiment, as a countermeasure, a discharge circuit of the capacitor C1 including the PNP transistor Q2 and the resistors R5 and R6 is provided.

The discharge circuit of capacitor C1 is that when the holding voltage V1 of capacitor C1 is higher than the receiving end voltage Vo_, the emitter potential of transistor Q2 is higher than the base potential, so transistor Q2 can be turned on, and capacitor C1 can be turned on through resistor R5. The charge discharges. Resistor R5 is set to a smaller resistance value than resistor R1, and causes the charge of capacitor C1 to be rapidly discharged. The discharge circuit of the capacitor C1 is not limited to this structure. As long as it monitors the voltage of the capacitor C1 and connects a discharge resistor when it is above a specific voltage.

The operation of the voltage clamp circuit 320 is the same as that of the above-mentioned embodiment, so the effect of suppressing reflected waves and preventing signal misreading is the same as that of the above-mentioned embodiment.

[Third Embodiment]

FIG. 9 shows a circuit diagram of the third embodiment of the communication terminal 30. Components having the same function as those in the first embodiment are assigned the same circuit symbols. In the third embodiment, a voltage clamp circuit 320 and a bypass circuit 330 are also connected in parallel to the receiving end B.

In the third embodiment, the voltage clamp circuit 320 is composed of a series circuit of a diode D1, a resistor R8, a capacitor C1, and a resistor R7 connected to both ends of the series circuit of the resistor R8 and the capacitor C1. The bypass circuit 330 is composed of a series circuit between the collector and the emitter of the NPN transistor Q1 and the resistor R2. The flip-flop circuit 340 is composed of the comparator CP.

The capacitor C1 of the voltage clamp circuit 320 receives the receiving terminal voltage Vo_ received by the receiving terminal B and maintains the first specific voltage V1, similar to the first embodiment. The capacitance of the capacitor C1 is set to a sufficiently large capacity so that the voltage can be maintained almost constant with respect to the frequency of the voltage signal. In the third embodiment, the capacitor C1 is discharged through the resistors R8 and R7. Resistor R7 is set to a higher resistance. Resistor R8 is set to a smaller resistance than resistor R7. Like the first embodiment, the diode D1 is turned on when the receiving terminal voltage Vo_ is higher than the sum of the holding voltage of the capacitor C1 and the forward voltage of the diode D1, and current flows through the resistor R8 to the capacitor C1. Since the capacitance of the capacitor C1 is set to a sufficiently large capacity as described above, the voltage hardly changes due to the current flowing through the resistor R8.

The bypass circuit 330 is composed of a series circuit of a transistor Q1 and a resistor R2, similar to the first embodiment. The difference from the first embodiment is that the transistor Q1 is changed to an NPN transistor. By flowing current through the base of the transistor Q1, the transistor Q1 is turned on, and the resistor R2 is connected to the receiving end B. The bypass circuit 330 of this embodiment also connects the resistor R2 to the receiving end B to bypass the current and perform the voltage holding function of the auxiliary voltage clamping circuit 320.

The trigger circuit 340 of the third embodiment is composed of a comparator CP. The + input terminal of the comparator CP is connected to the connection point between the diode D1 and the resistor R8. The - input terminal of comparator CP is connected to the resistor The connection point between R8 and capacitor C1. The output terminal of comparator CP is connected to the base of transistor Q1. The output terminal of the comparator CP is configured as an open collector, for example, and a pull-up resistor (not shown) is connected to the control power supply.

When the receiving end voltage Vo_ exceeds the holding voltage V1 of the capacitor C1 and rises, the diode D1 is turned on, and current flows in the path of the diode D1, the resistor R8, and the capacitor C1. At this time, according to the voltage drop of the resistor R8, the resistor R8 generates a voltage in the upward direction of Figure 9. Therefore, since the voltage of the + input terminal of the comparator CP is higher than the voltage of the - input terminal, the output terminal of the comparator CP outputs a Hi level voltage. When the output terminal of the comparator CP reaches the Hi level, current flows through the base of the transistor Q1, causing the transistor Q1 to turn on. Thereby, a path is formed that bypasses the receiving terminal B and the collector-emitter of the transistor Q1 with the resistor R2. The resistor R2 has a low resistance, turns on the transistor Q1, and when the voltage of the receiving end voltage Vo_ is to be increased, it also bypasses the current and suppresses the increase of the receiving end voltage Vo_. The bypass circuit 330 can suppress the sudden rise of the receiving end voltage Vo_.

In the third embodiment, the comparator CP functions as the trigger circuit 340 of the bypass circuit 330 . The diode D1 is turned on when the receiving end voltage Vo_ is greater than the holding voltage V1 of the capacitor C1, and functions as the voltage detection unit 322 for operating the trigger circuit 340, which is the same as the first embodiment.

When the receiving end voltage Vo_ is less than the holding voltage V1 of the capacitor C1, the diode D1 is disconnected and the current flowing from the diode D1 to the resistor R8 stops. Thereafter, the capacitor C1 is gradually discharged through the resistors R8 and R7. By this discharge current, resistor R8 is bypassed in the opposite direction from before, and comparator CP The voltage of the - input terminal is higher than the voltage of the + input terminal, and the output terminal of the comparator CP becomes Low level. Thereby, the base current of the transistor Q1 no longer flows, the transistor Q1 is turned off, and the bypass circuit stops operating.

Through the above operation, the receiving end voltage Vo_ can be prevented from becoming a higher voltage than the holding voltage V1 of the capacitor C1, and the influence of the reflected wave can be suppressed. Therefore, misreading of signals can be prevented.

[Fourth Embodiment]

In the fourth embodiment, the comparator CP of the flip-flop circuit 340 of the third embodiment is replaced with an operational amplifier OP as shown in FIG. 10 . The receiving end B is connected to a power circuit having a series circuit of diode D2 and capacitor C2. The voltage of capacitor C2 is used as the operating power supply of the operational amplifier OP.

Since the structure of the voltage clamp circuit 320 and the bypass circuit 330 is the same as that of the third embodiment, and the operation of the trigger circuit 340 is also the same as that of the third embodiment, detailed description is omitted.

Through the fourth embodiment, it is also possible to prevent the receiving end voltage Vo_ from generating a voltage higher than the holding voltage V1 of the capacitor C1, and to suppress the influence of reflected waves. Therefore, misreading of signals can be prevented.

[Other variations]

The circuit structure used to suppress the reflected waves of the communication terminal 30 is not limited to the above embodiment. For example, the trigger circuit 340 can be implemented even using a microcontroller with analog input terminals. The voltage clamp circuit 320 has the same structure as in FIG. 8 , for example. At the receiving end B, connect the transistor in parallel with A series circuit of resistors forms a bypass circuit. Its structure is to input the receiving end voltage Vo_ into the analog input terminal of the microcontroller, monitor the receiving end voltage Vo_, and turn on the transistor when the voltage of the analog input terminal exceeds a specific value (the holding voltage V1 of the capacitor C1). And bypass the receiving end B with a resistor. By installing a microcontroller with a program for performing the above actions and the above-mentioned trigger circuit, the generation of reflected waves in a direction more positive than the reference voltage can be cut off, thereby preventing misreading of signals caused by reflected waves.

In the communication system 10 of the present disclosure, in addition to the situation where the sending terminal 20 sends a signal and is received by the communication terminal 30 , the communication system 10 can also send a signal for the communication terminal 30 and be received by the sending terminal 20 . Therefore, it is preferable that the transmitting terminal 20 of the communication system 10 also has a structure for suppressing the above-mentioned reflected waves. Furthermore, it can also be configured to communicate among a plurality of communication terminals 30 .

In addition, in the above embodiment, the explanation is based on the premise that neither the transmitting end nor the receiving end performs impedance matching. An impedance matching unit for performing impedance matching may also be provided in either the transmitting terminal or the communication terminal. Specifically, the output impedance of the transmitting terminal 20 is made equal to the characteristic impedance of the signal line 60 , or the input impedance of the communication terminal 30 is made equal to the characteristic impedance of the signal line 60 . In a communication system, if impedance matching is performed, the influence of reflected waves can be basically eliminated. However, by having the composition of the communication terminal of the present disclosure, the influence of unexpected reflection or noise can be suppressed.

In addition, the present invention is not limited to the above-mentioned embodiments and modifications thereof, and it goes without saying that various changes or improvements can be made within the scope of the matters described in the patentable scope of this application.

10:Communication system

20: Sending terminal

30: Communication terminal

60:Signal line

320: Voltage clamp circuit

330:Bypass circuit

340: Trigger circuit

Vi: voltage signal

Vo_: receiving end voltage

Z _A :Output impedance

Z _B : input impedance

Claims (8)

A communication terminal that receives a voltage signal in which a signal voltage is superimposed on a specific reference voltage via a signal line, and is provided with: a signal receiving unit having a receiving end to receive the voltage signal; and a voltage clamp circuit having the above voltage When the voltage at the receiving end exceeds the voltage within a specific range from the above-mentioned reference voltage, that is, the first specific voltage, the above-mentioned receiving end is clamped; and the above-mentioned voltage clamp circuit has: a reference voltage holding part that maintains the above-mentioned first specific voltage; and voltage detection part, which conducts the receiving end and the reference voltage holding part when the voltage of the receiving end exceeds the first specific voltage. The communication terminal of claim 1 further includes: a bypass circuit that bypasses the receiving end; and a trigger circuit that when the voltage detection unit detects that the voltage of the receiving end exceeds the first specific voltage, Triggers the bypass circuit described above. If the communication terminal of claim 1 or 2 is used connected to a communication system, the communication system has a transmission terminal that transmits the voltage signal, and the signal line that transmits the voltage signal; and the reflection of the transmission end of the transmission terminal The sign of the coefficient is different from the sign of the reflection coefficient of the receiving end of the communication terminal. For example, in the communication terminal of claim 3, the reflection coefficient of the above-mentioned sending end is negative, and the reflection coefficient of the above-mentioned receiving end is positive. For example, in the communication terminal of claim 1 or 2, after the voltage at the receiving end exceeds the above-mentioned first specific voltage, the operation of the above-mentioned bypass circuit is stopped when it is lower than the second specific voltage. Such as the communication terminal of claim 5, wherein the above-mentioned second specific voltage is above the above-mentioned first specific voltage. The communication terminal of claim 2, wherein the reference voltage holding part has a series circuit of a diode and a capacitor; the voltage detection part detects that the voltage at the receiving end exceeds the first specific voltage based on the conduction and disconnection of the diode. The above-mentioned bypass circuit has a series circuit of a switch and a resistor triggered by the above-mentioned voltage detection part. A communication system, which is provided with: a communication terminal as in any one of claims 1 to 7; a sending terminal that sends the above voltage signal; and a signal line that transmits the above voltage signal.