TWI830079B - Integrated circuit (ic) structure with high impedance semiconductor material between substrate and transistor - Google Patents

Abstract

Embodiments of the disclosure provide an integrated circuit (IC) structure with a high impedance semiconductor material between a substrate and transistor. The IC structure may include: a substrate, a high impedance semiconductor material on a portion of the substrate, and a transistor on a top surface of the high impedance semiconductor material. The transistor includes a semiconductor channel region horizontally between a first source/drain (S/D) region and a second S/D region. The high impedance semiconductor material is vertically between the transistor and the substrate; a first insulator region is on the substrate and horizontally adjacent the first S/D region; and a first doped well is on the substrate and horizontally adjacent the first insulator region. The first insulator region is horizontally between the first doped well and the transistor.

Description

Integrated circuit (IC) structure with high resistance semiconductor material between substrate and transistor

Embodiments of the invention generally relate to integrated circuit (IC) structures. In more detail, various embodiments of the present invention provide an IC structure with a high resistance semiconductor material between a substrate and a transistor.

In the microelectronics industry, as well as other industries involving the construction and purchase of microstructures, there is an ongoing desire to reduce the size of structural features and microelectronic components and/or to provide a greater number of circuits for a specific die size. Miniaturization often results in improved performance (more processing per clock cycle, less heat generation) at lower power levels and lower cost. Current technology is atomically shrinking certain microdevices such as logic gates, FETs, and capacitors. Circuit wafers with hundreds of millions of these components are common.

The circuit industry is currently seeking to reduce the two-dimensional area occupied by component components, for example, to reduce two-dimensional area and power consumption. One problem with radio frequency (RF) component miniaturization is reducing the resistance of the body connection (e.g., backgate terminal) to the transistor, which can reduce the voltage gain and/or the expected input-output voltage function in a circuit component linearity. In traditional circuits, a transistor can offset lower resistance by applying a larger voltage bias to the body to reduce capacitance. However, this may not be feasible in many components or technical settings.

Many aspects of the present invention provide an integrated circuit (IC) structure including: a substrate; a high-resistance semiconductor material on a portion of the substrate; and a transistor on a top surface of the high-resistance semiconductor material, The transistor includes a semiconductor channel region located horizontally between a first source/drain (S/D) region and a second S/D region, wherein the high-resistance semiconductor material is located vertically between the transistor and the substrate between; a first insulating region on the substrate and horizontally adjacent to the first S/D region; and a first doping well on the substrate and horizontally adjacent to the first insulating region, wherein the first The insulating region is located horizontally between the first doping well and the transistor.

Many other aspects of the present invention provide an integrated circuit (IC) structure including: a substrate having a top surface; and a high-impedance semiconductor material within the substrate, wherein a top surface of the high-impedance semiconductor material is in contact with the The top surface of the substrate is coplanar; a transistor, on the top surface of the high-resistance semiconductor material, the transistor includes a first source/drain (S/D) region and a second S/ a semiconductor channel area between the D areas, wherein the high-resistance semiconductor material is vertically located between the transistor and the substrate; a first insulating area on the top surface of the substrate and horizontally adjacent to the first S/ D region; a first doping well in the substrate and horizontally adjacent to the first insulating region, wherein the first insulating region is horizontally located between the first doping well and the first S/D region of the transistor between; a first base terminal on the first doping well; a second insulating region on the top surface of the substrate and horizontally adjacent to the second S/D region; a second doping well, within the substrate and horizontally adjacent to the second insulating region, wherein the second insulating region is horizontally located between the second doping well and the second S/D region of the transistor; and a second body terminal, on the second doped well.

Another aspect of the present invention provides an integrated circuit (IC) structure, including: a substrate having a top surface; a high-resistance semiconductor material in the substrate, wherein a top surface of the high-resistance semiconductor material is in contact with the substrate The top surface is coplanar; a transistor, on the top surface of the high-resistance semiconductor material, the transistor includes a first source/drain (S/D) region and a second S/D located horizontally a semiconductor channel region between regions, wherein the high-resistance semiconductor material is vertically located between the transistor and the substrate; a first insulating region between the top surface of the substrate and the top surface of the high-resistance semiconductor material, and horizontally adjacent to the first S/D region; a second insulating region on the top surface of the substrate and the top surface of the high-resistance semiconductor material, and horizontally adjacent to the second S/D region; a first doped A miscellaneous well, on the top surface of the substrate and horizontally adjacent to the first insulating region and the substrate, wherein the first insulating region is horizontally located between the first doping well and the transistor; a first base terminal , in the first doping well; a second doping well, on the top surface of the substrate and horizontally adjacent to the first insulating region and the substrate, wherein the second insulating region is horizontally located on the second doping well. between the impurity well and the transistor; and a second base terminal in the second doping well.

In the following description, reference will be made to the accompanying drawings, which form a part hereof and which are shown by way of illustration of specific exemplary embodiments of the practice of the invention. These specific embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other specific embodiments may be utilized and changes may be made without departing from the scope of the invention. Therefore, the following description is an example only.

Specific embodiments of the present invention provide an integrated circuit (IC) structure having a high resistance semiconductor material between a substrate and a transistor. IC structures may be formed on a substrate, such as a bulk area of semiconductor material. The structure may also include a layer of high resistance semiconductor material on a portion of the substrate, which may be embedded within the semiconductor material. The IC structure may include a transistor on top of a high-resistance semiconductor material. The transistor includes a semiconductor channel region located horizontally between a first source/drain (S/D) region and a second S/D region. In this configuration, a high-impedance semiconductor material electrically insulates the active region of the transistor from the underlying substrate at radio frequency frequencies while allowing a direct current (DC) bias voltage to be applied to the substrate from other contacts. One or more insulating regions may be on the substrate and horizontally adjacent the first or second S/D region. One or more doped wells on the substrate may be horizontally adjacent to a corresponding insulating region. An insulating region horizontally separates the transistor from the doping well. By being located near the transistor, the doped wells can electrically bias the substrate beneath the high-resistance semiconductor material.

Please refer to FIG. 1 , which shows a cross-sectional view of an integrated circuit (IC) structure 100 according to an embodiment of the present invention. IC structure 100 may be formed from a substrate 102 including, for example, one or more semiconductor materials. Substrate 102 may include any currently known or later _developed semiconductor material, which may include, but is not limited to, silicon, _germanium , silicon _carbide , and substantially include a semiconductor material having _the chemical formula _Al Multiple III-V compound semiconductors, where X1, X2, X3, Y1, Y2, Y3, Y4 represent relative proportions, each of which is greater than or equal to 0, and 1 (1 is the total relative molar amount). Other suitable substrates include II-VI compound semiconductors having a set of Zn _A1CdA2 Se _B1 Te _B2 , where A1, A2, B1 and B2 are relative proportions, each of which is greater than or equal to 0, and A1+A2+B1+ B2=1 (1 is the total molar amount). The entire substrate 102 or a portion thereof may be deformed. The substrate 102 may include a bulk silicon layer, but in other embodiments may take the form of a Semiconductor on Insulator (SOI) substrate, a semiconductor fin, and/or other types of substrates.

To provide a biasing element to the transistor, the substrate 102 may include one or more doped regions in the form of a first doped well 104a having a first doping type. The substrate 102 may also include a second doping well 104b, also having the same (ie, first) doping type. Each of the first doped well 104a and the second doped well 104b may be at a different location in the substrate 102 and horizontally distant from each other. According to an example, the first doping type may be P-type doping. When it comes to dopants, P-type dopants are elements introduced into semiconductor materials that create free holes by "accepting" electrons from a semiconductor atom and thereby "releasing" the holes. The acceptor atom must have one less valence electron than the host semiconductor. P-type dopants suitable for the substrate 102 may include, but are not limited to, boron (B), indium (In), and gallium (Ga). Boron (B) is the most common acceptor in silicon technology. Other alternative elements include In and Ga. Ga has high diffusivity in silicon dioxide ( _SiO2 ), so the oxide cannot be used as a mask during Ga diffusion.

The undoped portion of the substrate 102 may separate the first doped well 104a and the second doped well 104b. The first doping well 104a and the second doping well 104b may be formed in the substrate 102, such as by vertical ion implantation. In some cases, substrate 102 may also include dopants. In such cases, the doping wells 104a, 104b may have the same doping type as the substrate 102, but have a higher dopant concentration of the first doping type (eg, P-type doping) than the substrate 102. Thus, even if the doping wells 104a, 104b have the same doping type as the substrate 102, they may be distinguished from the substrate 102 based at least in part on their doping concentration, dopant material, etc. The substrate 102 may include other doped wells with the same or different doping types, and for clarity, such wells are omitted in FIG. 1 .

IC structure 100 may include a high-resistance semiconductor material 106 on a portion of substrate 102 . High-resistance semiconductor material 106 may be formed of silicon (Si) and/or any other semiconductor material capable of exhibiting a high-resistance form, ie, having an electrical impedance that is significantly higher than substrate 102 . The term "high impedance" as used herein may refer to materials having an impedance of at least about ten million ohms (MΩ). To form high-resistance semiconductor material 106, crystalline semiconductor material may be formed on or converted from other portions of substrate 102. Crystalline semiconductor materials can be converted into polycrystalline silicon (poly-Si) to form high-resistance materials through any process currently known or later developed, such as through implantation, annealing, and/or other operations to deliberately destroy the crystalline semiconductor materials. Polycrystalline semiconductor material refers to any polycrystalline thin film semiconductor without long-range crystalline order. The polycrystalline semiconductor material may be converted from amorphous silicon (α-Si), and in this case, some portion of the amorphous material may remain in or near the high-resistance semiconductor material 106 . Due to the variety of components included in the resulting material, high-impedance semiconductor material 106 may generally include any semiconductor material or combination of semiconductor-based materials with an impedance of at least approximately ten MΩ (e.g., polycrystalline silicon, one or more crystalline films of semiconductor materials, etc. ), as described in this article. Polycrystalline semiconductor materials specifically provide electrical insulation compared to single crystals (eg, the material within substrate 102 and doping wells 104a, 104b).

The high resistance semiconductor material 106 may be formed on a portion of the substrate 102 that is between and physically separated from the doping wells 104a, 104b. In this position, the high-resistance semiconductor material 106 may electrically isolate the substrate 102 from other materials and/or structures formed thereon. A top surface J of the high-resistance semiconductor material 106 may be substantially coplanar with an adjacent top surface of the substrate 102 .

IC structure 100 may include a transistor 110 on top surface J of high-resistance semiconductor material 106 . Transistor 110 may include a channel region 112 (eg, a crystalline semiconductor having the same doping type as doping wells 104a, 104b), and thus may be referred to as a "shallow well" in some cases. The channel region 112 may be horizontally located between a first source/drain (S/D) region 114a and a second S/D region 114b. The S/D regions 114a, 114b may have a second doping type (eg, N-type doping) that is opposite to the doping type of the first doping well 104a and the second doping well 104b. The S/D regions 114a, 114b may be formed by introducing N-type dopants into the substrate 102 and/or the precursor semiconductor material by any currently known or later developed technology, such as ion implantation. N-type dopants are elements that are introduced into semiconductor materials to generate free electrons, for example, by "donating" an electron to the semiconductor. N-type dopants must have one more valence electron than the semiconductor. Common N-type donors in silicon (Si) include, for example, phosphorus (P), arsenic (As) and/or antimony (Sb).

Transistor 110 may include a gate dielectric layer 116 over channel region 112 . Gate dielectric layer 116 may include a high-k dielectric such as, but not limited to, metal oxide tantalum oxide (Ta ₂ O ₅ ), barium titanium oxide (BaTiO ₃ ), hafnium dioxide (HfO ₂ ), oxide Zirconium (ZrO ₂ ), aluminum oxide (Al ₂ O ₃ ), or metal silicates, such as hafnium silicate oxide (Hf _A1 Si _A2 O _A3 ) or hafnium silicate oxynitride (Hf _A1 Si _A2 O _A3 N _A4 ), where A1, A2, A3 and A4 represent relative proportions, each of which is greater than or equal to 0, and A1+A2+A3+A4=1 (1 is the total relative molar amount). Gate dielectric layer 116 may include any imaginable insulating material, such as, but not limited to: silicon nitride (Si ₃ N ₄ ), silicon oxide (SiO ₂ ), fluorinated silicon oxide (FSG), hydrogenated silicon oxide (SiCOH), porous SiCOH, borophosphosilicate glass (BPSG), sesquioxane, carbon (C) doped containing silicon (Si), carbon (C), oxygen (O) and/or hydrogen (H) atoms Heterooxides (aka organosilicates), thermoset polyarylene ethers, SiLK (polyarylene ethers available from The Dow Chemical Company), spin-on silicone-containing polymers available from JSR Materials, hydrogenated silicon oxide (SiCOH), porous SiCOH, porous methyl sesquioxane (MSQ), porous hydrogen sesquioxane (HSQ), octamethane available from Air Liquide, etc. cyclotetrasiloxane (OMCTS) [(CH ₃ ) ₂ SiO] ₄ 2.7, etc., or other low dielectric constant (k<3.9) materials, or their combinations. Gate dielectric layer 116 may also include a high-k dielectric material such as, but not limited to, hafnium silicate (HfSiO), zirconium silicate (ZrSiO _x ), silicon oxynitride (SiON), or any combination of these materials.

Transistor 110 may include a gate structure 118 located above gate dielectric layer 116 and between S/D regions 114a, 114b. During operation, gate structure 118 may be used to apply a voltage across gate dielectric layer 116 to channel region 114 to place transistor 110 in an operating state, e.g., allowing charge carriers to flow from first S/D region 114a to Second S/D area 114b and vice versa. Those skilled in the art will understand that gate structure 118 may include one or more layers, possibly forming a gate stack. According to an example, the gate structure 118 may be formed of doped or undoped poly-Si. In additional examples, gate structure 118 may include multiple materials, such as, but not limited to, aluminum (Al), zinc (Zn), indium (In), copper (Cu), copper indium (InCu), tin (Sn) ), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), titanium (Ti), titanium nitride (TiN), titanium carbide (TiC), tungsten (W), tungsten nitride (WN), Tungsten carbide (WC) and/or combinations thereof. Various insulating materials (eg, spacers) may be included within and/or formed on the sidewalls of gate structure 118, but these materials are omitted from FIG. 1 for clarity of illustration.

A set of insulating regions (identified respectively as a first insulating region 120a and a second insulating region 120b) separates the transistor 110 from the first doping well 104a and the second doping well 104b, respectively. The insulating regions 120a, 120b may be identified and referred to as "trench isolation" and thus may be provided in the form of shallow or deep trench isolation. In this case, the insulating regions 120a, 120b may be provided by forming a trench in a selected portion of the substrate 102 and filling the trench with an insulating material such as an oxide to connect one area of the substrate to an adjacent area of the substrate. Regional isolation. In the case where two insulation regions 120a and 120b are provided, the high-resistance semiconductor material 106 may continuously extend from a first end E1 below the first insulation region 120a to a second end E2 below the second insulation region 120b. A separation distance L between the first doping well 104a or the second doping well 104b and the high-resistance semiconductor material 106 may be less than the horizontal width of the overlying insulating regions 120a, 120b. In this configuration, the high-resistance semiconductor material 106, along with the insulating regions 120a, 120b, physically isolates the substrate 102 from the transistor 110. Transistor 110 and/or other suitable components may be disposed in a region separated by insulating region(s) 120a, 120b. Each insulating region 120a, 120b may be formed of any currently known or later developed substance for providing electrical _insulation , and may include, for example: silicon nitride ( _Si3N4 ), silicon oxide ( _SiO2 ), fluorinated oxide Silicon (FSG), hydrogenated silicon oxide (SiCOH), porous SiCOH, borophosphorus silica glass (BPSG), sesquioxane, containing silicon (Si), carbon (C), oxygen (O) and/or hydrogen ( H) atomic carbon (C) doped oxide (i.e., organosilicate), thermosetting polyarylene ether, a spin-coated silicon-containing carbon polymer material, near frictionless carbon (NFC) or its layers.

Transistor 110 may be capable of operating under predetermined conditions, such as by causing a voltage to be applied through gate structure 118 to control the flow of current between S/D regions 114a, 114b. Various embodiments of IC structure 100 may include additional components for electrically biasing transistor 110 itself (eg, via a bulk voltage). In addition, a bias voltage applied to the substrate 102 may affect the flow of current between the S/D regions 114a, 114b and/or the flow of current between the S/D regions 114a, 114b during the application of such a voltage. The voltage of the gate structure 118 required for the current flow. Conventional transistors may include a body contact region for electrically biasing a substrate material underlying the transistor. Such transistors may include one or more insulating layers and/or alternately doped materials to physically and electrically separate the biased substrate material from the active regions of the device. However, various embodiments of the present invention avoid the use of additional insulating material by including the high-resistance semiconductor material 106 discussed herein.

The IC structure 100 may include a plurality of body terminals in the form of, for example, a first body contact region 122a on the first doped well 104a, and/or a second body contact region 122b on the second doped well 104b. Body contact regions 122a, 122b may be formed from a doped semiconductor material, and may initially form part of the substrate 102 prior to doping. However, body contact regions 122a and 122b are provided to be of a first dopant type (eg, P+ doped). According to an example, the base contact region(s) 122a, 122b may be directly horizontally adjacent to an upper portion of the insulating region 120a, 122b, and may be directly located on the doping wells 104a, 104b. The vertical interface between each pair of doped wells 104a, 104b and base contact regions 122a, 122b can bisect one side wall of the insulating region 120a, 120b, as shown in FIG. 1 .

The IC structure 100 may include an inter-level dielectric (ILD) 130, formed in the base contact regions 122a, 122b, the insulating region 120a, 120b and above the transistor 110. ILD 130 may include the same insulating material as insulating region(s) 120a, 120b, or may include a different electrically insulating material. The ILD 130 and the insulating region(s) 120a, 120b still constitute distinct components, for example, because the insulating region(s) 120a, 120b are formed from portions of the substrate 102 rather than being formed on it. Additional metallization layers (not shown) may be formed on ILD 130 during mid-end and/or back-end processing. To electrically couple portions of IC structure 100 to such metallization layers, a set of S/D contact regions 132a, 132b may be formed on S/D regions 114a, 114b and within ILD 130. Likewise, a gate contact region 134 may be formed within the gate structure 118 and within the ILD 130 . Additionally, one or more body contact regions 134a, 134b may be formed on the body terminals 122a, 122b and within the ILD 130.

By controlled amounts of vertical etching, one or more of contact regions 130a, 130b, 132, 134a, 134b covering circuit elements may be formed within predetermined portions of ILD 130 to form openings to one or more contact locations. , and then fill the openings with a conductor. Each contact region 130a, 130b, 132, 134a, 134b may include any currently known or later developed conductive material configured for electrical contact regions, such as copper (Cu), aluminum (Al), gold (Au) wait. Contact regions 132a, 132b, 134, 136a, 136b may additionally include refractory metal liners (not shown) alongside ILD 130 to prevent electromigration degradation, shorting to other components, etc. Additionally, selected portions of S/D regions 114a, 114b, gate structure 118, and/or body terminals 122a, 122b may include silicide regions (ie, semiconductor portions that are annealed in the presence of an overlying conductor to Increase the conductivity of the semiconductor region) to increase the conductivity of the contact regions 132a, 132b, 134, 136a, 136b.

During operation of a device, applying a voltage to the base contact region(s) 122a, 122b can electrically bias the doping wells 104a, 104b below them and adjacent portions of the substrate 102. However, the high resistance semiconductor material 106 will prevent this bias voltage from forming a low resistance electrical path from the body contact region(s) 122a, 122b to the channel region 112 of the transistor 110. The formation of high-impedance semiconductor material 106 prevents any noise from coupling from the substrate or adjacent components (which may be another MOSFET, diode, BJT, etc.). Applying a bias voltage to the body contact region(s) 122a, 122b can affect, for example, the threshold voltage required by the gate structure 118 to form a conductive path through the channel region 112 of the transistor 110 and through the high resistance semiconductor material 106. . The electrical bias of the substrate 102 can be provided simultaneously through each of the plurality of base terminals 122a, 122b, or can be provided individually through one base terminal 122a, 122b. In this configuration, the portions of the substrate 102 underlying the amorphous semiconductor material 106 may not require additional doping as long as those portions are in close proximity to the doping wells 104a, 104b (eg, about five microns (um)). The minimum distance for a specific application may vary and is typically governed by rules defined in a technology-specific Design Rule Check (DRC). To provide and/or enhance these electrical properties, substrate 102, doping wells 104a, 104b, transistor 110, and/or other elements of IC structure 100 may be free of amorphous semiconductor materials.

Referring now to FIG. 2 , in addition to the high resistance semiconductor material 106 and the insulating region(s) 120 a , 120 b , various embodiments of the IC structure 100 may allow the transistor 110 to be formed without the need to form additional insulating material in the substrate 102 . electrical bias. FIG. 2 depicts an implementation of an IC structure 100 in which substrate 102 spans an indeterminate horizontal length from a transistor 110 to an active component 140 that is also formed on or within substrate 102 . Active component 140 may include any conceivable electrically active component that is formed within substrate 102 and operates differently than transistor 110 . Active component 140 is illustrated as a doped region within substrate 102 (eg, a portion of a diode junction extending into or beyond the plane of the page), but in other examples active component 140 may include transistors, capacitors, One or more resistors and/or other electrical components formed on or within substrate 102 .

The portion of the substrate 102 located between the transistor 110 and the active device 140 may define a separation region D of the substrate 102 . The portion of the separation area D is shown with a dashed line to represent an indeterminate length. According to one example, the separation region D may have a horizontal width of at least about thirty microns (um), and in various implementations may be fifty microns, one hundred microns, five hundred microns, etc. However, in practice, the separation region D may be defined to include all portions of the substrate 102 between the substrate 102 and the active device 140 that are free of other electrically active devices and/or insulating materials formed on or within the substrate 102 . Additionally, the size of the separation region D prevents any current within the active element 140 from electrically biasing the substrate 102 below the channel region 112 despite the absence of additional insulating material within the separation region D. The presence of body contact regions 122a, 122b provides strong local control such that the electrical behavior of transistor 110 is not affected by any other active or passive components on IC 100.

Referring now to FIG. 3 , further embodiments of IC structure 100 may include further configurations of components adjacent transistor 110 . Similar to other configurations discussed herein, IC structure 100 may include a substrate 102 , a high-resistance semiconductor material 106 formed on a portion of the substrate 102 , and a transistor 110 positioned on the high-resistance semiconductor material 106 . The high-resistance semiconductor material 106 vertically separates the substrate 102 from the channel region 112 of the transistor 110 above it. The transistor 110 may be horizontally located between the first and second insulating regions 120a, 120b. However, in the configuration of FIG. 3 , the top surface J of the high-resistance semiconductor material 106 may be coplanar with a top surface K of the substrate 102 . Here, the substrate 102 may be free of doped well regions, and the high resistance semiconductor material 106 defines the only distinct material regions within the substrate 102 . The first doped well 104a and/or the second doped well 104b may remain present in the IC structure 100 by being formed on the upper surface K of the substrate 102 and adjacent to the insulating region(s) 120a, 120b. In this configuration, each of the body terminal(s) 122a, 122b may be formed by introducing a dopant into a corresponding doping well 104a, 104b, and may be connected to the body terminal(s). Contact area(s) 136a, 136b of 122a, 122b.

In the configuration of FIG. 3 , the base terminals 122 a and 122 b are still capable of electrically biasing the substrate 102 below the channel region 112 and adjacent portions of the substrate 102 . Although the doping wells 104a, 104b do not extend below the top surface K of the substrate 102, a horizontal separation distance M between each end E1, E2 of the high resistance semiconductor material 106 and the corresponding doping well 104a, 104b may, for example, be Up to about five microns. The formation of high-impedance semiconductor material 106 prevents any noise from coupling from the substrate or adjacent components (which may be another MOSFET, diode, BJT, etc.). In this configuration, applying a voltage to body terminals 122a, 122b may affect the threshold voltage of transistor 110, thereby affecting the ability of transistor 110 to form a conductive path through channel region 112. Furthermore, the separation distance M may be less than the horizontal width of the insulating regions 120a, 120b to prevent current paths from forming between the doping well(s) 104a, 104b and the channel region 112 of the transistor 110.

Referring now to FIGS. 3 and 4 , specific embodiments of the IC structure 100 can also be used for active device(s) 140 formed on the substrate 102 without the need to form additional insulating material on or within the substrate 102 . As shown in FIG. 4 , the substrate 102 may span an indeterminate horizontal length from a transistor 110 to an active device 140 . As discussed herein, active component 140 may include any conceivable electrically active component that is formed within substrate 102 and operates differently than transistor 110 (e.g., a transistor, a capacitor, a resistor, and/or other electrically active component). ). The portion of separation region D shown in dashed lines represents an indeterminate length and, as discussed herein, may have a horizontal width of at least about thirty microns. Separation region D may include all portions of substrate 102 between substrate 102 and active component 140 that are free of other electrically active components and/or insulating materials formed on or within substrate 102 . Separation region D may be large enough to prevent any current within active element 140 from electrically biasing substrate 102 below channel region 112 , although no additional insulating material is present within separation region D. Likewise, the size and scale of the separation region D prevents electrical biasing of the doped wells 104a, 104b from significantly affecting the active device 140.

Specific embodiments of the present invention may provide several technical and commercial advantages, some of which are discussed here with examples. By providing a high-resistance semiconductor material 106 between the substrate 102 and the transistor 110 , the body terminal(s) 122 a , 122 b can effectively use powerful local control to bias the channel region 112 without the need for internal control within the first region 102 Other insulating and/or other high-resistance materials within other portions of substrate 100 . Embodiments of IC structure 100 provide a significantly reduced junction capacitance between substrate 102 and channel region 112 compared to regions of insulating material formed on or within substrate 102 (e.g., in conventional structures). , as the bias voltage is applied to the substrate 102 . These technical features are achieved by means of high-resistance semiconductor materials due to their inherent properties, which are relatively insulating materials and/or layers that typically form part of the body terminals of the transistor channel region. Thin. During operation, these features of IC structure 100 may prevent significant deviations between the expected value of the voltage gain across the body terminals of transistor 110 and its actual value. As also discussed herein, various embodiments of IC structure 100 prevent electrical biasing of substrate 102 beneath high-impedance semiconductor material 106 from interfering with active components 140 formed elsewhere on substrate 102 .

Descriptions of numerous specific embodiments of the invention have been presented for purposes of illustration, but not necessarily to limit the invention to the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the specific embodiments described. The terminology used herein is intended to best explain the principles of the specific embodiments, practical applications of technologies found on the market, and/or technical improvements, and/or to enable persons of ordinary skill in the art to understand the disclosure herein. Specific Examples.

100:Integrated circuit (IC) structure 102:Substrate 104a: First doping well 104b: Second doping well 106: High resistance semiconductor materials 110:Transistor 112: Channel area 114a, 114b: area 116: Gate dielectric layer 118: Gate structure 120a, 120b: Insulation area 122a, 122b: Substrate contact area 130: Interlayer dielectric (ILD) 132a, 132b: S/D contact area 134: Gate contact area 136a, 136b: Substrate contact area 140:Active components E1: first end E2: Second end J, K: top surface L: separation distance M: horizontal separation distance

These and other features of the invention will be more readily understood from the following detailed description of its many aspects, taken in conjunction with the accompanying drawings which illustrate various specific embodiments of the invention, in which:

1 illustrates a cross-sectional view of an integrated circuit (IC) structure with high-resistance semiconductor material between a substrate and a transistor in accordance with an embodiment of the present invention.

FIG. 2 shows another cross-sectional view of the IC structure and active components according to a specific embodiment of the present invention.

3 illustrates a cross-sectional view of an IC structure with high-resistance semiconductor material between a substrate and a transistor according to another embodiment of the present invention.

FIG. 4 shows another cross-sectional view of the IC structure and active components according to another specific embodiment of the present invention.

Please note that the drawings of the present invention are not necessarily to scale. The drawings are intended to depict only typical aspects of the invention and therefore should not be considered as limiting the scope of the invention. Within the drawings, the same numbers represent the same components between the drawings.

100: Integrated circuit (IC) structure

102:Substrate

104a: First doping well

104b: Second doping well

106: High resistance semiconductor materials

110:Transistor

112: Channel area

114a, 114b: area

116: Gate dielectric layer

118: Gate structure

120a, 120b: Insulation area

122a, 122b: substrate contact area

130: Interlayer dielectric (ILD)

132a, 132b: S/D contact area

134: Gate contact area

136a, 136b: Substrate contact area

E1: first end

E2: Second end

J: top surface

L: separation distance

Claims (19)

An integrated circuit (IC) structure includes: a substrate; a high-resistance semiconductor material on a portion of the substrate; and a transistor on a top surface of the high-resistance semiconductor material, the transistor including a a semiconductor channel region between a first source/drain (S/D) region and a second S/D region, wherein the high-resistance semiconductor material is vertically located between the transistor and the substrate; a first insulation a region on the substrate and horizontally adjacent to the first S/D region; and a first doping well on the substrate and horizontally adjacent to the first insulating region, wherein the first insulating region is located horizontally on the first between a doping well and the transistor; wherein a horizontal separation between the high-resistance semiconductor material and the first doping well is smaller than a horizontal width of the first insulating region. The IC structure as claimed in claim 1, further comprising: a second insulating region on the substrate and horizontally adjacent to the second S/D region; and a second doping well on the substrate and horizontally adjacent The second insulating region is horizontally located between the second doping well and the transistor. The IC structure of claim 2, wherein the high-resistance semiconductor material continuously extends from a first end below the first insulation region to a second end below the second insulation region. The IC structure of claim 1, wherein a portion of the substrate below the first insulating region is horizontally located between the high-resistance semiconductor material and the first doping well. The IC structure of claim 1, wherein the high-resistance semiconductor material includes polycrystalline silicon, and wherein the substrate, the first doping well, and the transistor do not contain polycrystalline silicon. The IC structure of claim 1, wherein the semiconductor channel region and the first doping well of the transistor have a first doping type, and wherein the first S/D region and the second S/D The region has a second doping type opposite the first doping type. The IC structure of claim 1 further includes a body terminal connected to the first doping well, wherein the body terminal is configured to electrically bias a portion of the substrate beneath the high-resistance semiconductor material. The IC structure of claim 1 further includes an active component located in the substrate, wherein the substrate includes a separation area horizontally located between the active component and the first doping well. The IC structure of claim 8, wherein a horizontal width of the separation area of the substrate prevents the active component from electrically biasing a portion of the substrate beneath the high-resistance semiconductor material. An integrated circuit (IC) structure includes: a substrate having a top surface; a high-resistance semiconductor material within the substrate, wherein a top surface of the high-resistance semiconductor material is coplanar with the top surface of the substrate; A transistor including a semiconductor channel located horizontally between a first source/drain (S/D) region and a second S/D region on the top surface of the high-resistance semiconductor material a region in which the high-resistance semiconductor material is vertically located between the transistor and the substrate; a first insulating region on the top surface of the substrate and horizontally adjacent to the first S/D region; a first doping region a well within the substrate and horizontally adjacent to the first insulating region, wherein the first insulating region is horizontally located between the first doped well and the first S/D region of the transistor; a first base terminal , on the first doping well; a second insulating region on the top surface of the substrate and horizontally adjacent to the second S/D region; a second doping well in the substrate and horizontally adjacent to the a second insulating region, wherein the second insulating region is located horizontally between the second doped well and the second S/D region of the transistor; and a second body terminal on the second doped well. The IC structure of claim 10, wherein the high-resistance semiconductor material continuously extends from a first end below the first insulation region to a second end below the second insulation region. The IC structure of claim 10, wherein a bottom surface of the first insulating region is located below a top surface of the first doped well, and wherein a bottom surface of the second insulating region is located below the second doped well. Under the top of the well. The IC structure of claim 10, further comprising an active component located in the substrate, wherein the substrate includes a separation area horizontally located between the active component and the first doping well or the second doping well. . The IC structure of claim 13, wherein a horizontal width of the separation area of the substrate prevents the active element from electrically biasing a portion of the substrate beneath the high-resistance semiconductor material. An integrated circuit (IC) structure includes: a substrate having a top surface; a high-resistance semiconductor material within the substrate, wherein a top surface of the high-resistance semiconductor material is coplanar with the top surface of the substrate; A transistor including a semiconductor channel located horizontally between a first source/drain (S/D) region and a second S/D region on the top surface of the high-resistance semiconductor material a region, wherein the high-resistance semiconductor material is vertically located between the transistor and the substrate; a first insulating region between the top surface of the substrate and the top surface of the high-resistance semiconductor material, and horizontally adjacent to the first S /D region; a second insulating region on the top surface of the substrate and the top surface of the high-resistance semiconductor material, and horizontally adjacent to the second S/D region; a first doping well on the substrate The top surface is horizontally adjacent to the first insulating region and the substrate, wherein the first insulating region is horizontally located between the first doped well and the transistor; a first base terminal, on the first doped In the well; a second doping well is on the top surface of the substrate and is horizontally adjacent to the first insulating region and the substrate, wherein the second insulating region is horizontally located between the second doping well and the transistor. between; and a second base terminal in the second doping well. The IC structure of claim 15, wherein the high-resistance semiconductor material extends continuously and horizontally from a first end below the first insulation region to a second end below the second insulation region. The IC structure of claim 15, wherein a bottom surface of the first insulating region is coplanar with a bottom surface of the first doped well, and wherein a bottom surface of the second insulating region is coplanar with the second doped well. The bottom surfaces of the wells are coplanar. The IC structure of claim 15, further comprising an active component located in the substrate, wherein the substrate includes a separation area horizontally located between the active component and the first doping well or the second doping well. . The IC structure of claim 18, wherein a horizontal width of the separation area of the substrate prevents the active component from electrically biasing a portion of the substrate beneath the high-resistance semiconductor material.