TWI829715B - Display panel and large format display apparatus using the same - Google Patents

Abstract

A display panel is provided. The display panel according to an embodiment includes a thin film transistor glass substrate, a plurality of micro light emitting diodes (LEDs) arranged on one surface of the thin film transistor glass substrate, and a plurality of side wirings formed at an edge of the thin film transistor glass substrate to electrically connect the one surface of the thin film transistor glass substrate to an opposite surface to the one surface.

Description

Display panel and large display device using the same

The devices and methods disclosed herein relate to a display panel and a large-scale display device using the same, and more particularly, to a display panel by arranging side wiring at the edge of a thin film transistor (TFT) substrate. The structure moves the bonding area of the driving circuit to the rear surface of the thin film transistor substrate to achieve a frameless display panel and a large display device using the same.

[Cross-reference to related applications]

This application claims Korean Patent Application No. 10-2018-0077668 filed with the Korean Intellectual Property Office on July 4, 2018, and Korean Patent Application No. 10-2018-0077668 filed with the Korean Intellectual Property Office on June 25, 2019. No. 10-2019-0075904, the full disclosure content of the above application is incorporated into this case for reference.

The display device displays multiple colors when operating on a pixel or sub-pixel basis, and its operation is controlled by a Thin Film Transistor (TFT) for each pixel or sub-pixel. Multiple thin film transistors can be disposed in what is generally referred to as It is a thin film transistor substrate on a flexible substrate, a glass substrate or a plastic substrate.

This kind of thin film transistor substrate has been used to drive displays, such as flexible devices, small-size wearable devices (eg, wearable watches, etc.), large-size televisions (TVs), etc. In order to drive the thin film transistor substrate, the thin film transistor substrate is connected to an external circuit (eg, an external integrated circuit (IC)) to apply current to the thin film transistor substrate or the driver circuit (eg, driver integrated circuit). Generally speaking, the thin film transistor substrate and each circuit can be connected through chip on glass (COG) bonding or film on glass (FOG) bonding. For these connections, it is necessary to provide a frame area with a specific area at the edge of the thin film transistor substrate.

Recently, research on bezel-less technology that removes or reduces the bezel area to maximize the display area (ie, active area) of the display panel has been steadily performed, for example, in U.S. Patent Publication No. US 9,367,094 (publication date: June 14, 2016). Currently, frameless display panels have been applied to small-sized display devices (such as smart phones) or large-sized display devices (such as display panels).

Provided is a display panel that achieves a frameless panel by arranging a side wiring structure at the edge of the thin film transistor substrate to move the bonding area of the driving circuit to the rear surface of the thin film transistor substrate, and a large display device using the same.

In addition, a method using μ-light-emitting diodes (light-emitting diodes) is provided. diode (LED) display device by arranging side wiring connecting the thin film transistor substrate to the drive circuit on the outside of the μ-LED mounting surface when a plurality of μ-LEDs are mounted on the thin film transistor substrate. A display panel with increased mounting density of μ-LEDs and a large-scale display device using the same are provided.

Furthermore, a display device is provided, in the case of a large format display (LFD) produced by connecting a plurality of frameless display panels, by connecting the outermost edges of the display panels adjacent to each other. A display panel in which a pitch between pixels is maintained to be the same as that of a single display to prevent pre-occurrence of seams between display panels, and a large display device using the same.

According to aspects of the present disclosure, a display panel is provided, which includes: a thin film transistor glass substrate; a plurality of micro-light emitting diodes (LEDs) arranged on one surface of the thin film transistor glass substrate; and A plurality of side wirings are formed at the edge of the thin film transistor glass substrate to electrically connect the one surface of the thin film transistor glass substrate to a surface opposite to the one surface.

The display panel may include each of the plurality of side wirings connected to the one surface, a side end surface, and the surface opposite to the one surface of the thin film transistor glass substrate.

The display panel may include: two ends of each of the plurality of side wirings are electrically connected to first and second connection pads formed at the edge of the thin film transistor glass substrate, respectively. .

The display panel may include: the edge of the thin film transistor glass substrate corresponds to a virtual area excluding an active area, in which the The plurality of micro-luminescent diodes are arranged on the thin film transistor glass substrate.

The display panel may include: the edge of the thin film transistor glass substrate is an area from an outermost part of the thin film transistor glass substrate to the active area.

The display panel may include the plurality of side wirings formed at predetermined intervals on side end surfaces of the thin film transistor glass substrate.

The display panel may include the plurality of side wirings provided on a plurality of grooves formed on the side end surface of the thin film transistor glass substrate.

The display panel may include the plurality of side wirings provided on side end surfaces of the thin film transistor glass substrate.

The display panel may include the plurality of side wirings formed inwardly from side end surfaces of the thin film transistor glass substrate.

The display panel may include: two ends of each of the plurality of side wirings are electrically connected to first and second connection pads formed at the edge of the thin film transistor glass substrate, respectively. .

The display panel may include: two ends of the wiring on each side cover the first connection pad and the second connection pad.

The display panel may include forming a protective layer covering the plurality of side wirings at the edge of the thin film transistor glass substrate.

The display panel may include: the protective layer is formed of an insulating material.

According to another aspect of the present disclosure, there is provided a large-scale display device manufactured by connecting a plurality of display panels, each of the plurality of display panels It includes: a thin film transistor glass substrate; a plurality of micro-light emitting diodes (LEDs) arranged on one surface of the thin film transistor glass substrate; and a plurality of side wirings formed at the edges of the thin film transistor glass substrate to connect The one surface of the thin film transistor glass substrate is electrically connected to the surface opposite to the one surface, wherein three micro-light emitting diodes constitute a pixel and are disposed in each of the plurality of display panels. A plurality of pixels are arranged at a first pitch, and pixels of adjacent display panels among the pixels of the plurality of display panels are arranged at a second pitch equal to the first pitch.

The display panel may include: the plurality of side wirings formed on the side end surface of the thin film transistor glass substrate, so that the plurality of side wirings do not extend from the side of the thin film transistor glass substrate. The end face is protruding.

The display panel may include first connection pads and second connection pads formed closer to side end surfaces of the thin film transistor glass substrate.

According to the above and other aspects, features and advantages of certain embodiments of the present disclosure, wires electrically connecting the front surface of the thin film transistor substrate to the rear surface of the thin film transistor substrate may be formed at the edge of the thin film transistor substrate . Therefore, the virtual area of the thin film transistor substrate can be minimized to easily achieve a borderless display panel.

When a large display device is implemented by connecting multiple frameless display panels, the seams may be inconspicuous at the connection portions between display panels, thereby improving display quality.

100, 101, 102, 103, 200, 200a, 200b, 300: display panel

100a: First display panel

100b: Second display panel

110, 110’, 210, 310: thin film transistor substrate

111: Front surface

112: Side end surface

113:Rear surface

121, 221, 321: first connection pad

123, 223, 323: Second connection pad

130, 130a, 130b, 230, 230a, 230b, 330: pixel

131:R/sub-pixel/μ-LED

132:G/sub-pixel/μ-LED

133:B/sub-pixel/μ-LED

137: Pixel drive circuit

150: Panel driver

151: first drive

153: Second drive

170, 270, 370, 570: side wiring

170a, 170b, 170c: Conductive metal materials

171:Part One

172:Part 2

173:Part 3

180:Protective layer

181:Self allocator

182: Movable components

183:Scraper

184, 186, 187: Mask

185: Discharge hole

190, 290: Large display device

211:hole

211a, 311a: groove

240:Virtual first cutting line

241:Virtual second cutting line

260: Large size glass

261: Spare thin film transistor substrate

400: Adhesive components

410:Tape

470:Conductive member/side wiring

550:Shading component

560:Conductive layer

A-A, C-C, E-E: lines

AA: active area

B, D: Part

D1: first interval

D2: second interval

DA, DA1, DA2: virtual area

G: scheduled gap

t, t1, t2: thickness

L: distance

L1: first length

L3: The third length

L4: The fourth length

P:thermal compression

Q: Direction

P1, P2, P3, P4, P5, P6: Pitch

W1: first width

W2: second width

W3: third width

Read the following description in conjunction with the accompanying drawings. The above description of certain embodiments of the present disclosure Other aspects, features and advantages will become more apparent in the accompanying drawings: Figure 1A is a front view illustrating a display panel according to an embodiment.

FIG. 1B is a block diagram illustrating a display panel according to an embodiment.

2 is a cross-sectional view taken along line A-A shown in FIG. 1A, according to an embodiment.

3 is a schematic diagram illustrating a process of forming side wirings by coating a conductive metal material on the edge of a thin film transistor substrate through an inkjet method according to an embodiment.

4 (a) and (b) are schematic diagrams illustrating a process of forming side wirings by coating a conductive metal material on the edge of a thin film transistor substrate through a stamping method according to an embodiment.

5 (a) and (b) are schematic diagrams illustrating a process of forming side wirings by coating a conductive metal material on the edge of a thin film transistor substrate through a screen printing method according to an embodiment.

(a) and (b) of FIG. 6 are schematic diagrams illustrating a process of forming side wirings by coating a conductive metal material on the edge of a thin film transistor substrate through a metal deposition method according to an embodiment.

7A is a top view showing an adhesive member according to an embodiment.

7B is a schematic diagram illustrating a thin film transistor substrate in which a plurality of side wirings are not formed according to an embodiment.

7C is a schematic diagram illustrating a process of forming side wiring on an edge portion of a thin film transistor substrate by a bonding method according to an embodiment.

7D is a schematic diagram illustrating a process of removing tape according to an embodiment.

8A is a diagram illustrating an edge portion of a thin film transistor substrate according to an embodiment. Schematic of the formed conductive layer.

8B is a schematic diagram illustrating a shielding member formed on a conductive layer according to an embodiment.

8C is a schematic diagram showing an edge portion of a thin film transistor substrate formed with a plurality of side wirings according to an embodiment.

FIG. 9A is a front view showing a display panel according to another embodiment of the present disclosure.

FIG. 9B is a front view of a display panel according to yet another embodiment of the present disclosure.

FIG. 9C is a front view of a display panel according to yet another embodiment of the present disclosure.

FIG. 10 is a front view illustrating a large-scale display device formed by connecting a plurality of display panels according to an embodiment.

FIG. 11 is an enlarged view showing part B shown in FIG. 10 according to the embodiment.

12 is a cross-sectional view illustrating a protective layer stacked on the side wiring to protect the side wiring formed on the edge of the thin film transistor substrate according to an embodiment.

13 is a front view showing a display panel according to another embodiment.

14 is a cross-sectional view taken along line C-C shown in FIG. 13, according to an embodiment.

15 , 16 , 17 and 18 are diagrams sequentially illustrating a manufacturing process of a display panel according to an embodiment.

19 is a front view showing a large-scale display device formed by connecting a plurality of display panels according to another embodiment.

FIG. 20 is an enlarged view showing part D shown in FIG. 19 according to the embodiment.

FIG. 21 is a front view showing a display panel according to yet another embodiment.

FIG. 22 is a cross-sectional view taken along line E-E shown in FIG. 21 .

The embodiments set forth in the present disclosure may omit detailed descriptions of related known functions or components to prevent any obscuring the subject matter. Furthermore, redundant descriptions of identical components will be omitted.

In addition, for ease of explanation, the suffix "part" used for the constituent elements in the present disclosure may be given or mixed, and may not have a specific meaning or may have a role of distinguishing itself.

The terminology used in this application is for describing particular embodiments only and is not intended to limit the disclosure. In this disclosure, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise.

Singular expressions may also include the plural meaning provided that the singular expression does not include a different meaning in the context. In this disclosure, terms such as "include" and "have/has" may be deemed to specify features, numbers, operations, elements, components, or combinations thereof in this disclosure without excluding the addition of a or the presence or possibility of multiple other features, numbers, operations, elements, components, or combinations thereof.

Terms such as "first" and "second" may be used to modify various elements regardless of order and/or importance. These terms are used to distinguish various components.

When an element (eg, a first constituent element) is referred to as being "operably or communicatively coupled to" or "connected to" another element (eg, a second constituent element), it will be understood that each constituent element can directly connected or indirectly connected via another constituent element (for example, a third constituent element). However, when a component is said to be "directly coupled to" or "directly connected to" another element, it should be understood that there may be no other constituent elements (eg, a third constituent element) therebetween.

The display panel according to the embodiment can form side wirings at the edge of the thin film transistor glass substrate, and electrically connect a plurality of light emitting elements disposed on the front surface of the thin film transistor substrate to the rear surface of the thin film transistor substrate. on the circuit. The thin film transistor substrate may include a glass substrate, a flexible substrate, or a plastic substrate, and the substrate with a plurality of thin film transistors formed on one surface thereof may be called a backplane. Glass substrates (hereinafter referred to as "thin film transistor substrates") may be used herein for illustrative purposes.

The edge of the thin film transistor substrate may be the outermost surface of the thin film transistor substrate. The edge of the thin film transistor substrate may include a virtual area from the outermost surface of the thin film transistor substrate to an active area where an image can be displayed. Therefore, the virtual region may include a side end surface of the thin film transistor substrate, a portion of a front surface and a rear surface of the thin film transistor substrate adjacent to the side end surface.

The light-emitting element may be a micro-light-emitting diode (μ-LED), and in this case, each μ-LED may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) Sub-picture elements. A single pixel may include three sub-pixels, namely R, G, and B, and each thin film transistor of the thin film transistor substrate may be formed based on the sub-pixels.

μ-LEDs can emit light by themselves and may not include a backlight unit, liquid crystal layer and polarizer, and may have a very thin glass layer arranged on top of it. Therefore, μ-LEDs can be formed to be thinner than organic light emitting diodes (OLEDs).

μ-LEDs can use inorganic materials and therefore may not suffer from burn-in. Therefore, compared to organic light-emitting diodes using organic materials, μ-LEDs can have three times higher brightness efficiency and half the power consumption. Therefore, when a display panel equipped with μ-LED is applied to a smartphone, the user can clearly see the smartphone screen in a bright space, and the battery can run longer.

μ-LEDs can be mounted on curvature substrates via roller transfer, and the components can be attached to substrates that stretch like rubber. Therefore, a freely convertible transparent display can be fabricated. This means that there are no restrictions on the actual substrate on which μ-LEDs are mounted.

μ-LEDs can be manufactured into ultra-small sizes of less than 100 microns, and when applied to wearable devices (such as smart watches, etc.), ultra-high resolution can be achieved. The transition time of μ-LEDs that can achieve ultra-high resolution, that is, the time it takes to completely change color, can be several nanoseconds. For example, when μ-LED is applied to a virtual reality (VR) or augmented reality (AR) headset, the image quality can be significantly improved.

The side wiring disposed on the edge of the thin film transistor substrate can electrically connect the first connection pad disposed on the front surface of the thin film transistor substrate to the second connection pad disposed on the rear surface of the thin film transistor substrate. The side wiring may be formed along the front surface, the side end surface and the rear surface of the thin film transistor substrate, and one end of the side wiring may be electrically connected to the first connection pad, and the other end of the side wiring may be electrically connected to the second connection pad. A part of the side wiring may be formed on the side end surface of the thin film transistor substrate to separate the thin film transistor substrate from the thin film transistor substrate. The side end surface of the crystal substrate protrudes by the thickness of the side wiring.

The side wiring formed at the edge of the thin film transistor substrate may be formed in a direction from the side end surface of the thin film transistor substrate to the inside of the thin film transistor substrate so as not to protrude from the side end surface of the thin film transistor substrate. A portion of the side wiring passing through the side end surface of the thin film transistor substrate may be formed in a trench provided on the side end surface of the thin film transistor substrate. The portion of the side wiring may completely fill the trench, or may be coated with a predetermined thickness along the inner circumferential surface of the trench. When the portion of the side wiring completely fills the trench, the surface of the portion of the side wiring may be located on the same surface as the side end surface of the thin film transistor substrate. Furthermore, when the portion of the side wiring is coated with a predetermined thickness along the inner circumferential surface of the trench, the surface of the portion of the side wiring may be located inside the thin film transistor substrate rather than at the side end surface of the thin film transistor substrate interior.

As described above, the display panel according to the above embodiments can achieve a frameless display panel by minimizing the virtual area and maximizing the active area on the front area of the thin film transistor substrate.

In a structure that implements a frameless display panel, the virtual area may be reduced and the active area may be relatively increased. Therefore, the mounting density of μ-LEDs per unit display panel can be increased.

When multiple bezel-less display panels are connected, a large display device (LFD) that maximizes the active area can be provided. In this case, the display panel may be formed to keep the pitch between pixels of display panels adjacent to each other the same as the pitch between pixels in a single display panel by minimizing the virtual area. Therefore, it is possible to prevent seams from occurring in the connection portion between the display panels.

Hereinafter, various embodiments of the present disclosure will be explained with reference to the accompanying drawings.

1A is a front view showing a display panel according to an embodiment, FIG. 1B is a block diagram showing the display panel according to an embodiment, and FIG. 2 is a cross-sectional view taken along line A-A shown in FIG. 1A.

The display panel 100 according to the embodiment may include: a thin film transistor substrate 110 in which a plurality of pixel driving circuits 137 may be formed; a plurality of pixels 130 arranged on the front surface of the thin film transistor substrate; a panel driver 150 to generate control signals and provide the generated control signals to each pixel driving circuit 137 formed on the thin film transistor substrate; side wiring 170 is formed at the edge of the thin film transistor substrate 110 to electrically connect the pixel driving circuit 137 to the panel. Drive 150.

1A, 1B and 2, a plurality of data signal lines and a plurality of gate signal lines can be formed on the thin film transistor substrate 110. The plurality of data signal lines are disposed in the horizontal direction to control the arrangement of the thin film transistor. For the plurality of pixels 130 on the front surface 111 of the crystal substrate, the plurality of gate signal lines are arranged in a vertical direction.

The front surface 111 of the thin film transistor substrate may include an active area (AA) for displaying images through the plurality of pixels 130 and a dummy area (DA) that does not include the active area. The dummy area DA may correspond to the edge of the thin film transistor substrate 110, and in the present disclosure, the dummy area and the edge of the thin film transistor substrate 110 may be considered the same.

Referring to FIG. 1A , the plurality of pixels 130 may be arranged in a matrix on the front surface of the thin film transistor substrate 110 . Each pixel 130 may include three sub-pixels R 131 , G 132 and B 133 corresponding to red, green and blue respectively. Sub-pixel 131, Each of 132 and 133 may include a micro-light emitting diode (μ-LED) that emits light of a sub-pixel color. In this disclosure, sub-pixels and μ-LEDs can be considered the same.

The R, G and B sub-pixels 131, 132 and 133 may be arranged in a matrix form in one of the plurality of pixels 130, or arranged in sequence. However, the arrangement of the R, G and B sub-pixels 131, 132 and 133 is not limited to this. The arrangement can vary in units of 130 pixels. Each pixel 130 may include a pixel driving circuit to drive a μ-LED corresponding to each of the R, G, and B sub-pixels 131, 132, and 133.

One pixel 130 may include three pixel driving circuits 137 to drive each R, G and B sub-pixels 131, 132 and 133 respectively.

The panel driver 150 may be connected to the thin film transistor substrate 110 using a chip-on-glass (COG) bonding method or a film-on-glass (FOG) bonding method. The panel driver 150 can drive the plurality of pixel driving circuits 137 and control the light emission of the plurality of μ-LEDs 131, 132 and 133 electrically connected to the plurality of pixel driving circuits 137. The panel driver 150 can control the plurality of pixel driving circuits line by line through the first driver 151 and the second driver 153 .

The first driver 151 can generate a control signal for each frame to sequentially control a plurality of horizontal lines formed on the front surface 111 of the thin film transistor substrate, and transmit the generated control signal to the Line-connected pixel drive circuit.

The first driver 151 may be called a gate driver.

The second driver 153 can generate a control signal for each frame to control a plurality of vertical lines formed on the front surface 111 of the thin film transistor substrate one by one. And the generated control signal is sent to the pixel driving circuit 137 connected to the line.

Furthermore, the second driver 153 may be called a data driver.

A plurality of side wirings 170 may be provided at certain intervals along the edge of the thin film transistor substrate 110 . The side wiring 170 can electrically connect the first connection pad 121 formed on the front surface 111 of the thin film transistor substrate to the second connection pad 123 formed on the rear surface 113 of the thin film transistor substrate. A plurality of first connection pads 121 may be provided at a predetermined distance along the upper side of the front surface 111 of the thin film transistor substrate and the left side of the front surface 111 of the thin film transistor substrate. The plurality of first connection pads 121 arranged along the upper side of the front surface 111 of the thin film transistor substrate can be electrically connected to the data signal lines, and the plurality of first connection pads 121 arranged along the left side of the front surface 111 of the thin film transistor substrate A connection pad 121 can be electrically connected to the gate signal line.

One end of the side wiring 170 can be electrically connected to the front pad, and the other end can be electrically connected to the rear pad, so that the first connection pad 121 of the front surface 111 of the thin film transistor substrate is connected to the rear surface of the thin film transistor substrate. The second connection pads 123 of 113 can be electrically connected to each other.

Referring to Figure 2, the side wiring 170 may include: a first portion 171 located on the front surface 111 of the thin film transistor substrate and at the edge of the thin film transistor substrate 110; a second portion 172 located on the side end surface 112 of the thin film transistor substrate; and a third portion 173 located on the rear surface 113 of the thin film transistor substrate. In this case, the side wiring 170 can protrude from the side end surface 112 by the thickness t of the side wiring 170 because the second portion 172 is disposed on the side end surface 112 of the thin film transistor substrate.

To prevent side wiring from protruding from the side end surface 112 of the thin film transistor substrate The second portion 172 of 170 is disconnected and an additional protective layer 180 can also be stacked on the side wiring 170 (see Figure 12). The thickness of the protective layer 180 may be equal to or smaller than the thickness of the side wiring 170 .

Referring to (b) of FIGS. 3 to 6 , the side wiring 170 can be formed at the edge of the thin film transistor substrate 110 through various processes. For ease of explanation, the plurality of pixels 130 arranged on the thin film transistor substrate 110 will be omitted in (b) of FIGS. 3 to 6 .

3 is a schematic diagram illustrating a process of forming side wirings by coating a conductive metal material on the edge of a thin film transistor substrate through an inkjet method.

Referring to FIG. 3 , side wirings may be formed by spraying conductive metal material 170 a in the form of ink dispensed from a dispenser 181 on the edge of the thin film transistor substrate 110 using an inkjet method. The conductive metal material 170a can be sequentially coated on the front surface, side end surfaces and rear surface of the thin film transistor substrate 110 to form side wiring.

(a) and (b) of FIG. 4 are schematic diagrams illustrating a process of forming side wirings by coating a conductive metal material on the edge of a thin film transistor substrate through a stamping method.

Referring to (a) and (b) of FIG. 4 , the conductive metal material 170 b in the form of paste can be applied on the edge of the thin film transistor substrate 110 by the movable member 182 . For example, the conductive metal material 170b can be sequentially coated on the front surface, side end surfaces and rear surface of the thin film transistor substrate 110 to form side wirings.

(a) and (b) of FIG. 5 are schematic diagrams illustrating a process of forming side wirings by coating a conductive metal material on the edge of a thin film transistor substrate through a screen printing method.

Referring to (a) and (b) of FIG. 5 , a mask 184 may be provided on the thin film transistor substrate 110 so that the discharge holes 185 formed in the mask may correspond to the side wirings of the thin film transistor substrate 110 . edge. The conductive metal material 170c in paste form disposed on the upper surface of the mask 184 can be pushed to the scraper 183 to be coated to the edge of the thin film transistor substrate 110 through the discharge hole 185. The conductive metal material 170c may be sequentially coated on the front surface, side end surfaces and rear surface of the edge of the thin film transistor substrate 110.

(a) and (b) of FIG. 6 are schematic diagrams illustrating a process of forming side wirings by coating a conductive metal material on the edge of a thin film transistor substrate through a metal deposition method.

The side wiring 170 may be formed on the edge of the thin film transistor substrate 110 by a metal deposition method, such as a sputtering deposition method. Masks 186 and 187 using tape or liquid resin may be formed on the thin film transistor substrate 110, and a conductive metal material may be deposited so that edges of the thin film transistor substrate 110 may be exposed. Depending on the metal deposition equipment, the conductive metal material may be deposited on the front surface, side surfaces, and rear surfaces of the thin film transistor substrate 110 simultaneously, or may be deposited on each surface sequentially.

Hereinafter, with reference to FIGS. 7A, 7B, 7C, and 7D, a bonding method for forming the side wiring 470 according to an embodiment of the present disclosure will be explained.

7A is a front view showing an adhesive member, FIG. 7B is a schematic diagram showing a thin film transistor substrate without forming a plurality of side wirings, and FIG. 7C is a schematic diagram showing side formation on an edge portion of the thin film transistor substrate by an adhesive method. 7D is a schematic diagram illustrating the process of removing tape.

Referring to FIGS. 7A and 7B , the adhesive member 400 may include an adhesive tape 410 and a plurality of conductive members 470 formed on the adhesive tape 410 .

The tape 410 may be formed of a material bondable to the plurality of conductive members 470 disposed on one surface of the tape 410 . Additionally, tape 410 may be formed from a material that loses its adhesion when heat is applied.

Therefore, when heat is applied to the tape 410, the plurality of conductive members 470 may be easily separated from the tape 410.

The plurality of conductive members 470 (or side wirings) may be formed of conductive material. In addition, when the conductive member 470 is attached to the edge portion of the thin film transistor substrate 110 , the conductive member 470 may form a side wiring that electrically connects the first connection pad 121 to the second connection pad 123 .

The conductive member 470 may be in a state before being bonded to the edge portion of the thin film transistor substrate 110 , and the side wiring 170 may be in a state after being bonded to the edge portion of the thin film transistor substrate 110 .

Each of the conductive members 470 may be a square or rectangular shape having a first width W1 and a first length L1.

The first width W1 may correspond to the second width W2 of the first connection pad 121 . For example, the first width W1 of the conductive member 470 may be determined based on the second width W2 of the first connection pad 121 that is electrically and physically connected to the conductive member 470 .

Specifically, the first width W1 may be equal to or larger than the second width W2. The conductive member 470 may cover the first connection pad 121 to partially surround the first connection pad. 121.

In addition, the first width W1 of the conductive member 470 may be determined based on the widths of the second connection pad 123 and the first connection pad 121 .

The first length L1 may be a length for connecting the first connection pad 121 to the second connection pad 123 while surrounding the edge portion of the thin film transistor substrate 110 .

For example, the first length L1 may be a distance from the first connection pad 121 to the second connection pad 123 including the front surface 111 , the side end surface 112 and the rear surface 113 of the thin film transistor substrate.

Furthermore, the plurality of conductive members 470 may be arranged to be spaced apart from each other by a first distance D1 on the tape 410 . The first interval D1 may be a distance between center lines of the plurality of conductive members 470 and may correspond to a second interval D2 which is a distance between center lines of the plurality of first connection pads 121 distance.

Accordingly, one conductive member 470 may connect a first connection pad 121 to a second connection pad 123 disposed on an opposite side of the one first connection pad 121 .

Referring to FIG. 7C , the adhesive member 400 may be bonded to an edge portion of the thin film transistor substrate 110 . A conductive member 470 may contact a first connection pad 121 disposed on the front surface 111 of the thin film transistor substrate, the side end surface 112 of the thin film transistor substrate, the rear surface 113 of the thin film transistor substrate, and the second connection pad 123 .

Therefore, the first connection pad 121 and the second connection pad 123 can be electrically connected.

When the adhesive member is bonded to the edge portion of the thin film transistor substrate 110, thermal compression (P) may be applied to the adhesive member 400. Therefore, the plurality of conductive members 470 It can be bonded and fixed to the edge portion of the thin film transistor substrate 110 .

In other words, the plurality of conductive members 470 may be bonded to the edge portion of the thin film transistor substrate 110 to form a plurality of side wirings.

Referring to FIG. 7D , the tape 410 may be removed from the plurality of conductive members 470 in the Q direction.

Referring to FIGS. 8A, 8B, and 8C, an etching method for forming the side wiring 570 according to the embodiment will be explained.

8A is a schematic view showing a conductive layer formed on an edge portion of a thin film transistor substrate, FIG. 8B is a schematic view showing a shielding member formed on the conductive layer, and FIG. 8C is a schematic view showing a conductive layer formed on an edge portion of a thin film transistor substrate. Schematic diagram of the edge portion of multiple side wiring.

Referring to FIG. 8A , a conductive layer 560 may be formed along an edge portion of the thin film transistor substrate 110 . The conductive layer 560 may be bonded to the first connection pad 121 , the front surface 111 of the thin film transistor substrate, the side end surface 112 of the thin film transistor substrate, the rear surface 113 of the thin film transistor substrate, and the second connection pad 123 .

Referring to FIG. 8B , shielding members 550 may be formed at edge portions of the thin film transistor substrate 110 at predetermined intervals to correspond to positions where the plurality of first connection pads 121 and the plurality of second connection pads 123 are provided.

The shielding member 550 can protect the conductive layer 560 disposed on the area where the shielding member 550 is formed from being etched during the etching process of the conductive layer 560 .

The shielding member 550 may correspond to the shape of the plurality of side wirings 570 to be formed. For example, the third width W3 of the shielding member 550 may correspond to the width W3 to be formed. The width of the plurality of side wirings 570.

The third width W3 may be equal to or larger than the second width W2 of the first connection pad 121 . The shielding member 550 may partially cover the first connection pad 121 .

The third width W3 of the shielding member 550 may be determined based on the width of the second connection pad 123 and the width of the first connection pad 121 .

Referring to FIG. 8B , an etching process of the conductive layer 560 may be performed. Etching may include wet etching and dry etching.

For example, the conductive layer 560 provided in the area where the shielding member 550 is formed may not be etched, and the conductive layer 560 provided in the area where the shielding member 550 is not formed may be etched.

Therefore, referring to FIG. 8C , the plurality of side wirings 570 may be formed to correspond to the positions where the first connection pad 121 and the second connection pad 123 are disposed.

The plurality of side wirings 570 can electrically and physically connect the first connection pad 121 to the second connection pad 123 .

Referring to FIGS. 9A , 9B and 9C , display panels 101 , 102 and 103 according to another embodiment of the present disclosure will be described.

FIG. 9A is a front view of a display panel according to another embodiment of the present disclosure, FIG. 9B is a front view of a display panel according to yet another embodiment of the present disclosure, and FIG. 9C is a front view of a display panel according to yet another embodiment of the present disclosure. Example of the front view of the display panel.

The plurality of side wirings 170 may be formed on two or more of four sides of the thin film transistor substrate 110 , and the two sides on which the plurality of side wirings 170 are formed may be different.

For example, on one of the four sides of the thin film transistor substrate 110, a first connection pad 121 and a second connection pad 123 for receiving the signal of the first driver 151 may be provided, and on the thin film transistor substrate On the other side of the four sides of 110, a first connection pad 121 and a second connection pad 123 for receiving the signal of the second driver 153 may be provided.

In other words, in order to drive the plurality of pixels 130, the side wiring 170 for transmitting the gate signal can be formed on one of the four sides of the thin film transistor substrate 110, and the side wiring 170 can be formed on four sides of the thin film transistor substrate 110. On the other side of the two sides, side wiring 170 for transmitting data signals may be provided.

For example, referring to FIG. 9A , the plurality of side wirings 170 and the first and second connection pads 121 and 123 connected by the plurality of side wirings 170 may be formed on the upper or lower side of the thin film transistor substrate 110 . superior.

Referring to FIG. 9B , the plurality of side wirings 170 and the first and second connection pads 121 and 123 connected by the plurality of side wirings 170 may be formed on the left or right side of the thin film transistor substrate 110 .

Referring to FIG. 9C , unlike the thin film transistor substrate 110 of the rectangular-shaped display panel 100 shown in FIG. 1A , the thin film transistor substrate 110' included in the display panel 103 may have a square shape.

For example, the lengths of four sides of the thin film transistor substrate 110' may be the same. Specifically, the third length L3 on the upper side and the fourth length L4 on the left side may be the same.

Therefore, by sequentially arranging the films of the square-shaped display panel 103 The transistor substrate 110' can implement high-brightness and high-tone display screens of various sizes.

FIG. 10 is a front view showing a large-scale display device formed by connecting a plurality of display panels according to an embodiment, and FIG. 11 is an enlarged view showing part B shown in FIG. 10 .

Referring to FIG. 10 , according to an embodiment, a large display device 190 may be formed by connecting multiple frameless display panels 100 .

Referring to FIG. 11 , pixels of the first display panel 100 a and the second display panel 100 b that are adjacent to each other may be provided with the same pitches P1 , P2 , and P3 . Specifically, the pitch P3 between the pixel 130a of the first display panel 100a and the pixel 130b of the second display panel 100b adjacent to the first display panel 100a may be the same as the pitch P3 of the pixel 130b of the second display panel 100b. P1 and P2.

In order to make the pitch of the pixels of each display panel equal to the pitch of each pixel 130a and 130b of the first display panel 100a and the second display panel 100b, the pitch of the pixel 130a of the first display panel 100a can be appropriately adjusted. The distance (L) between one end and one end of the pixel of the second display panel 100b.

Due to the thickness of the connecting member, a predetermined gap (G) may be formed between the first display panel 100a and the second display panel 100b adjacent to each other, however, each pixel may have the same pitch. Since the predetermined gap (G) is extremely small compared to the size of the large display device 190, when viewing an image displayed on the large display device 190, it is difficult to see with the naked eye due to the gap (G) in the connecting portion of the display panel. G) caused by seams. Therefore, the large-scale display device 190 formed by connecting multiple frameless display panels 100 can be implemented as a single display panel.

Explanation As shown in FIG. 1 , a plurality of side wirings 170 are formed on the upper side and left side of the thin film transistor substrate 110 , but it is not limited thereto. The plurality of side wirings 170 may be formed on one or more of four sides of the thin film transistor substrate 110 .

For example, the plurality of side wirings 170 may be formed on the upper or lower side of the thin film transistor substrate 110 , on the upper and right sides of the thin film transistor substrate 110 , or on the left and right sides of the thin film transistor substrate 110 . superior. The plurality of side wirings 170 may be formed on any one of the four sides of the thin film transistor substrate 110 , or on three of the four sides of the thin film transistor substrate 110 .

12 is a cross-sectional view showing a protective layer stacked on the side wiring to protect the side wiring formed on the edge of the thin film transistor substrate.

In addition, when a large display device is manufactured by connecting a plurality of display panels, and the plurality of side wirings 170 may be formed on one or more of the four sides of the thin film transistor substrate 110, adjacent to each other The side wirings of the display panel may be short-circuited according to the formation positions of the plurality of side wirings. For example, when the plurality of side wirings connect a plurality of display panels formed on the upper and lower sides of the thin film transistor substrate 110, the side wirings of the display panels adjacent to each other in the vertical direction may be short-circuited.

In order to prevent the short circuit phenomenon, referring to FIG. 12 , a protective layer 180 covering the plurality of side wirings 170 may be preferably formed. The protective layer 180 may perform an insulation function and a protection function to prevent the plurality of side wirings 170 from being damaged due to physical force and impact applied to the plurality of side wirings 170 from the outside.

Referring to FIG. 12 , the protective layer 180 may completely cover the second part 172 of the side wiring 170 , and partially cover part of the first part 171 and the third part 173 respectively. parts, but is not limited thereto, and may cover the entire area of the first part 171 , the second part 172 and the third part 173 . The protective layer 180 can be formed by various methods for forming the side wirings 170, such as an inkjet method, a stamping method, a deposition method, etc., see FIG. 15, FIG. 16, FIG. 17, and FIG. 18.

Referring to FIGS. 13 and 14 , the structure of the display panel 200 will be explained. When explaining the display panel 200 , descriptions of the same components as the display panel 100 will be omitted, and different embodiments of the side wiring 170 will be explained.

13 is a front view showing a display panel according to another embodiment, and FIG. 14 is a cross-sectional view taken along line C-C shown in FIG. 13 .

Referring to FIG. 13 , in the display panel 200 , a plurality of pixels 230 may be formed in a matrix pattern on the front surface of the thin film transistor substrate 210 , and a plurality of side wirings 270 may be formed at the edge of the thin film transistor substrate 210 .

The side wiring 270 may have substantially the same thickness t1 as the side end surface of the thin film transistor substrate 210 from the inside, so that the side wiring 270 does not protrude from the side end surface of the thin film transistor substrate 210 .

Referring to FIG. 14 , a trench 211 a in which the side wiring 270 is formed may be provided on the side end surface of the thin film transistor substrate 210 so that the side wiring 270 does not protrude from the side end surface of the thin film transistor substrate 210 . In this case, the first connection pad 221 and the second connection pad 223 electrically connected to the side wiring 270 may be formed on the front surface or the rear surface of the thin film transistor substrate 210 .

The first connection pad 221 and the second connection pad 223 may be formed at the edge of the thin film transistor substrate 210 so that the side wiring 270 is formed on the thin film transistor substrate 210 After being put on, it covers both ends of the side wiring 270 and can be electrically connected to the side wiring 270 .

The side wiring 270 may not protrude from the side end surface of the thin film transistor substrate 210, and thus the side wiring 270 may be prevented from being disconnected when the thin film transistor substrate 210 is carried or transported.

According to the display panel 200 of another embodiment of the present disclosure, the side wiring 270 can be inserted into the trench 211a, and by directly connecting the first connection pad 221 and the second connection pad 223, the virtual area DA1 of the thin film transistor substrate 210 can be smaller than The virtual area DA of the thin film transistor substrate 110 (shown in FIG. 2 ).

The process of forming the side wiring 270 at the edge of the thin film transistor substrate 210 will be shown sequentially in FIGS. 15 to 18 . However, the process of forming the side wiring 270 is not limited to this.

15 , 16 , 17 and 18 are diagrams sequentially illustrating a manufacturing process of a display panel according to another embodiment.

Referring to FIG. 15 , a large-sized glass 260 capable of manufacturing a plurality of thin film transistor substrates may be provided.

The glass 260 can be used as a thin film transistor substrate because transistors, gate signal lines, data signal lines, etc. can be formed in multiple virtual segmented areas through a photolithography process.

A plurality of holes 211 may be made to correspond to the plurality of virtual divided areas.

Referring to FIG. 16 , each of the plurality of holes 211 may be coated with a conductive metal material. The conductive metal material may completely fill each of the plurality of holes 211 .

After all the conductive metal materials are coated to the plurality of holes 211 , a plurality of spare thin film transistor substrates 261 may be formed along the virtual first cutting line 240 of the glass 260 .

Referring to FIG. 17 , the edge of each spare thin film transistor substrate 261 may be cut twice along the virtual second cutting line 241 . A portion of the virtual second cutting line 241 may be disposed through the center of each hole 211 . Therefore, the second cut can be performed more accurately than the first cut since the super mini size hole 211 can be cut in half by the second cut. Reference numeral 213 in FIG. 17 is the portion removed from the spare thin film transistor substrate 261 by the second cutting.

Referring to FIG. 18 , the hole 211 may be formed into a semicircular groove 211a by a second cutting. Therefore, multiple μ-LEDs can be mounted on the thin film transistor substrate 210 through various processes such as transfer technology.

FIG. 19 is a front view showing a large-scale display device formed by connecting a plurality of display panels according to another embodiment, and FIG. 20 is an enlarged view showing part D shown in FIG. 19 .

Referring to FIG. 19 , for example, a large display device 290 may be formed by connecting the plurality of display panels 200 a and 200 b. The large display device 290 may be formed at the edge of the thin film transistor substrate so that the plurality of side wirings 270 may not protrude from the side end surface of the thin film transistor substrate. Referring to FIG. 20 , the gaps G between the adjacent display panels 200 a and 200 b can be removed by forming the plurality of side wirings 270 so that the plurality of side wirings 270 are not separated from the side end surfaces of the thin film transistor substrate. protrude. Referring to Figure 20, the pixels of the display panels 200a and 200b arranged adjacent to each other Can be set at the same pitch P4, P5, P6. More specifically, the pitch P6 of the pixel 230a of the display panel 200a and the pixel 230b of the display panel 200b adjacent to the display panel 200a may be the same as the pitches P4 and P5 of the pixel 230b of the display panel 200b.

21 is a front view showing a display panel according to yet another embodiment, and FIG. 22 is a cross-sectional view taken along line E-E shown in FIG. 21 .

Referring to FIG. 21 , a display panel 300 according to yet another embodiment may have the same structure as the display panel 200 according to another embodiment of the present disclosure, but the thickness and shape of the side wiring 370 may be formed differently.

The side wiring 370 may be coated to have a predetermined thickness in the inner circumferential surface of the groove 311a of the display panel 300. To form the side wiring 370, a conductive metal material may be applied to the inner circumferential surface of each hole to have a predetermined thickness t2 so as not to completely fill the hole 211 of the glass 260 (see FIG. 15), and a second cutting may be performed.

Therefore, the side wiring 370 may be formed to have an approximately arc shape as shown in FIG. 21 , and the surface of the portion of the side wiring 370 may be disposed inwardly from the side end surface of the thin film transistor substrate 310 as shown in FIG. 22 .

Referring to FIG. 22 , the first connection pad 321 and the second connection pad 323 may be electrically connected to each end of the side wiring 370 at the front and back surfaces of the edge of the thin film transistor substrate 310 . As shown in FIG. 21 , the figure shows that parts of the first connection pad 321 and the second connection pad 323 are connected to both ends of the side wiring 370 , but it is not limited thereto. The first connection pad 321 and the second connection pad 323 can contact both ends of the side wiring 370 with a large cross-sectional area. Compared with the positions shown in FIG. 21 , the first connection pad 321 and the second connection pad 323 may be formed closer to the side end surface of the thin film transistor substrate 310 .

In the display panel 300 according to yet another embodiment, the dummy area DA2 of the thin film transistor substrate 310 may have a smaller area than the dummy area DA of the thin film transistor substrate 110 , and therefore the active area AA of the thin film transistor substrate 110 may Increase.

In the display panels 200 and 300, as shown in FIGS. 13 and 21, a plurality of pixels 230 and 330 may be formed in a matrix on the front surfaces of the thin film transistor substrates 210 and 310, and the plurality of side wirings 270 and 370 is formed on the upper and left sides of the thin film transistor substrates 210 and 310, but is not limited thereto. The plurality of side wirings 270 and 370 may be formed on one or more of four sides of the thin film transistor substrates 210 and 310 .

When a large display device is manufactured by connecting a plurality of display panels, a protective layer covering the plurality of side wirings 270 and 370 may be formed. Therefore, the plurality of side wirings 270 and 370 can be protected from short circuits that may occur in the adjacent display panels due to physical force and impact applied to the plurality of side wirings 270 and 370 from the outside. The short circuit occurs between 270 and 370.

According to various embodiments of the present disclosure, wires for electrically connecting the front surface and the rear surface of the thin film transistor substrate may be formed at the edge of the thin film transistor substrate to minimize the virtual area of the thin film transistor substrate. Therefore, the bezel-less display panel can efficiently utilize the area of the display panel.

When a large display device is formed by connecting multiple frameless display panels, seams may not appear at the portions where the display panels are connected, and therefore display quality may be improved.

Each of the components (eg, modules or programs) according to various embodiments They may include a single entity or multiple entities, and some of the subcomponents described above may be omitted or may include other components in various embodiments. Alternatively or additionally, some components may be integrated into one entity to perform the same or similar functions performed by each component prior to integration. According to various embodiments, operations performed by a module, program, or other component may be performed sequentially, in parallel, repeatedly, or heuristically, or at least some operations may be performed in a different order, or be omitted, or may be further Add another feature.

Although embodiments have been shown and described, those skilled in the art will understand that changes may be made in these embodiments without departing from the principles and spirit of the disclosure. Accordingly, the scope of the present disclosure may not be considered limited to the illustrated embodiments.

100‧‧‧Display Panel

110‧‧‧Thin film transistor substrate

121‧‧‧First connection pad

130‧‧‧pixels

131‧‧‧R/sub-pixel/μ-LED

132‧‧‧G/sub-pixel/μ-LED

133‧‧‧B/sub-pixel/μ-LED

170‧‧‧ side wiring

AA‧‧‧active area

A-A‧‧‧Line

DA‧‧‧Virtual Area

Claims (12)

A display panel, including: a thin film transistor glass substrate; a plurality of micro-light emitting diodes (LEDs) arranged on one surface of the thin film transistor glass substrate; and a plurality of side wirings formed on the thin film transistor at an edge of the glass substrate to electrically connect the one surface of the thin film transistor glass substrate to a surface opposite to the one surface, wherein each of the side wirings includes an electrical connection to a first surface of the thin film transistor glass substrate. The first end of the connection pad is electrically connected to the second end of the second connection pad, wherein the first connection pad is disposed on the one surface of the thin film transistor glass substrate, and the second connection pad Disposed on the surface of the thin film transistor glass substrate opposite to the one surface, and wherein the first end covers the first connection pad and the second end covers the second connection pad. The display panel as claimed in claim 1, wherein each of the plurality of side wirings is connected to the one surface, the side end surface and the side surface opposite to the one surface of the thin film transistor glass substrate. the surface. The display panel as claimed in claim 1, wherein the edge of the thin film transistor glass substrate corresponds to a virtual area, and the virtual area does not include the plurality of micro-light emitting diodes arranged in the Active area on thin film transistor glass substrate. The display panel as claimed in claim 3, wherein the edge of the thin film transistor glass substrate is an area from the outermost part of the thin film transistor glass substrate to the active area. The display panel according to claim 1, wherein the plurality of side wirings are formed on the side end surfaces of the thin film transistor glass substrate at predetermined intervals. The display panel according to claim 5, wherein the plurality of side wirings are provided on a plurality of grooves formed on the side end surface of the thin film transistor glass substrate. The display panel as claimed in claim 1, wherein the plurality of side wirings are disposed on the side end surfaces of the thin film transistor glass substrate. The display panel as claimed in claim 6, wherein the plurality of side wirings are formed inwardly from the side end surfaces of the thin film transistor glass substrate. The display panel according to claim 1, wherein a protective layer for covering the plurality of side wirings is formed at the edge of the thin film transistor glass substrate. As for the display panel described in item 9 of the patent application, the protective layer is formed of an insulating material. A large-scale display device is manufactured by connecting a plurality of display panels, wherein each of the plurality of display panels includes: a thin film transistor glass substrate; a plurality of micro-light emitting diodes (LEDs) arranged in on one surface of the thin film transistor glass substrate; and A plurality of side wirings are formed at the edge of the thin film transistor glass substrate to electrically connect the one surface of the thin film transistor glass substrate to the surface opposite to the one surface, three of which are micro-luminescent The diode constitutes one pixel, wherein a plurality of pixels provided in each of the plurality of display panels are arranged at a first pitch, and wherein adjacent ones of the pixels of the plurality of display panels The pixels of the display panel are arranged at a second pitch equal to the first pitch, wherein two ends of each of the plurality of side wirings are electrically connected to the first connection pad and the second connection pad respectively, Wherein the first connection pad is disposed on the one surface of the thin film transistor glass substrate, and the second connection pad is disposed on the surface of the thin film transistor glass substrate opposite to the one surface. on, and wherein the two ends of each side wiring cover the first connection pad and the second connection pad. The large-scale display device as claimed in claim 11, wherein the plurality of side wirings are formed on the side end surfaces of the thin film transistor glass substrate so that the plurality of side wirings do not extend from the thin film transistor. The side end surface of the glass substrate protrudes.

Images