TWI829477B - Memory device and method of fabricating the same - Google Patents

Abstract

Provided is a memory device including a gate stack structure, at least three channel pillars, a charge storage structure, at least three source line, and at least three bit lines. The gate stack structure is disposed above a substrate. The gate stack structure includes a plurality of gate electrode layers and a plurality of insulating layers stacked vertically and alternately each other. The at least three channel pillars extend through the gate stack structure. The at least three channel pillars are electrically isolated from one another. The charge storage structure is disposed between the plurality of gate electrode layers and the at least three channel pillars. The at least three source line are disposed below the gate stack structure and electrically connected to the at least three channel pillars. The at least three bit lines are disposed above the gate stack structure, and electrically connected to the at least three channel pillars.

Description

Memory device and method of manufacturing same

Embodiments of the present invention relate to semiconductor devices and manufacturing methods thereof, and in particular, to memory devices and manufacturing methods thereof.

The advantage of flash memory is that the stored data will not disappear even if the power is turned off, so it has become a widely used memory component in many electronic components. Although the development of three-dimensional NAND flash memory with the evolution of manufacturing processes will increase the concentration of memory components, there are still many related problems.

Embodiments of the present invention provide a memory device. The memory device includes a gate stack structure, at least three channel pillars, a charge storage structure, at least three source lines and at least three bit lines. The gate stack structure is disposed above the substrate. The gate stack structure includes a plurality of gate conductive layers and a plurality of insulating layers stacked vertically alternately. At least three channel pillars extend through the gate stack structure. At least three channel columns are electrically isolated from each other. The charge storage structure is disposed in the gate conductive layer and surrounds at least three channel pillars. At least three source lines are located under the gate stack structure and are electrically connected to at least three channel pillars. At least three bit lines are located on the gate stack structure and are electrically connected to at least three channel column.

Embodiments of the present invention provide a method of manufacturing a flash memory element. At least three source lines are formed above the substrate. A stack structure is formed on at least three source lines. The stacked structure includes a plurality of gate conductive layers and a plurality of insulating layers stacked alternately with each other. Holes are formed in the stacked structure. Charge storage structures are formed on the sidewalls of the holes. A semiconductor layer is formed in the hole. The semiconductor layer is patterned to form at least three channel pillars. At least three channel posts connect at least three source lines. An insulating layer is formed in the remaining space of the hole. At least three bit lines are formed on the gate stack structure. At least three bit lines are electrically connected to at least three channel columns.

Embodiments of the present invention provide a method for manufacturing a memory element. At least three source lines are formed above the substrate. A stack structure is formed on at least three source lines. The stacked structure includes a plurality of first material layers and a plurality of second material layers alternately stacked. Holes are formed in the stacked structure. A semiconductor layer is formed in the hole. Filled pillars are formed in the semiconductor layer. A plurality of second material layers are removed to form a plurality of horizontal openings. Multiple charge storage structures and multiple gate conductive layers are formed in multiple horizontal openings. The semiconductor pillars in the holes are patterned to form at least three channel pillars. At least three channel posts are connected to at least three source lines. The insulation fills the remaining space of the hole. At least three bit lines are formed on the gate stack structure. At least three bit lines are electrically connected to at least three channel posts.

Embodiments of the present invention provide a phase change memory element, including a gate stack structure, at least three pillars, at least three source lines and at least three bit lines. The gate stack structure is disposed on the substrate, wherein the gate stack structure includes a plurality of gate conductive layers and a plurality of insulating layers stacked vertically alternately. At least three channel pillars extend through the gate stack structure, wherein the at least three channel pillars are electrically isolated from each other, and wherein each channel pillar The outer area is the semiconductor channel area, and the inner area of each channel column is the phase change storage area. At least three source lines are located under the gate stack structure, and electrical connections are located under at least three channel pillars. At least three bit lines are located on the gate stack structure and are electrically connected to at least three channel columns.

100, 200: base

101, 132, 201, 232: Wire

102, 102a, 102b, 102c, 130, 130a, 130b, 130c, 202, 202a, 202b, 202c, 230, 230a, 230b, 230c, 230d: Plug

103, 128, 203, 228: dielectric layer

104, 204: First material layer/insulating layer

105, 205: stacked structure

106, 206: Second material layer/gate conductive layer

107, 207: hole

108, 208: Charge storage structure

110, 210: barrier layer

112, 212: Storage layer

114, 214: tunneling layer

116:Curtain layer

118, 118a, 118b, 118c, 218, 218a, 218b, 218c: channel column

118’, 218’, 418’: semiconductor layer

120, 220: packed column

122:Patterned hard mask

124, 124a, 224a, 424, 424a: opening

126, 226, 426: Insulation column

150, 160, 250, 260: Internal wiring structure

205G: Gate stack structure

209:Horizontal opening

222:Slit trench

223:Curtain layer

225: Slit structure

240: Gate conductive layer

408: Internal area/phase change storage area/inner phase change storage area

408’: Phase change layer

410: Gate oxide layer/gate dielectric layer

418: External area/semiconductor channel area/outer channel area

428, 428a, 428b, 428c: columns

B, B1, B2, B3: block

BL, BLa, BLb, BLc, ...., BLj: bit lines

D1: Direction

I-I', II-II', III-III': line

P1, P2, P3: part

SL, SLa, SLb, SLc, SLd, SLe: source line

WL1, WL2: character lines

θ1, θ2, θ3, θ4: included angle

1A to 1K and 3A to 3G are schematic cross-sectional views and three-dimensional schematic views of intermediate stages of manufacturing methods of three-dimensional flash memory devices with a gate-first process according to different embodiments of the present invention.

FIGS. 2A to 2C are schematic top views along line II′ of FIGS. 1F to 1H .

4A to 4C are schematic top views along line II-II' of FIGS. 3A to 3D.

5A to 5J are a schematic cross-sectional view and a schematic perspective view of an intermediate stage of a manufacturing method of a three-dimensional flash memory device with a gate-last process according to another embodiment of the present invention.

6A to 6D are schematic top views of an intermediate stage of a method of manufacturing a three-dimensional flash memory device according to another embodiment of the present invention.

7A to 7B are a schematic cross-sectional view and a schematic perspective view of an intermediate stage of a manufacturing method of a three-dimensional phase change memory element.

8A to 8D are schematic top views of an intermediate stage of the manufacturing method of a three-dimensional phase change memory device with a first gate according to an embodiment of the present invention.

9 is a schematic top view illustrating the operation of the three-dimensional phase change memory device.

1A to 1K are a schematic cross-sectional view and a schematic three-dimensional view of an intermediate stage of a manufacturing method of a three-dimensional flash memory device with a gate-first process according to an embodiment of the present invention. FIGS. 2A to 2C are schematic top views along line II′ of FIGS. 1F to 1H .

Referring to Figures 1A, 1I, and 1J, a substrate 100 is provided. The substrate 100 may include a component layer (not shown) on the semiconductor substrate and an interconnect structure 150 on the component layer. The interconnect structure 150 may include conductors 101, dielectric layers 103, plugs 102, etc., but is not limited thereto. The wire 101 can be used as the source line SL, as shown in FIG. 1A and FIG. 1J. The source line SL may include source lines SLa, SLb, and SLc, as shown in FIG. 1K. Materials in wire 101 include doped polysilicon, copper or tungsten. A dielectric layer 103 is formed on the conductive lines 101 . The material of the dielectric layer 103 includes silicon oxide. The plug 102 is formed in the dielectric layer 103 and is electrically connected to the wire 101 . The plug 102 may, for example, include plugs 102a, 102b, and 102c, which are electrically connected to the source lines SLa, SLb, and SLc respectively, as shown in FIG. 1K.

Referring to FIG. 1A , a stack structure (also called a gate stack structure) 105 is formed on a substrate 100 . The stacked structure 105 includes a plurality of first material layers 104 and a plurality of second material layers 106, which are stacked alternately with each other. The first material layer 104 may be an insulating layer, such as silicon oxide. The second material layer 106 may be a conductive layer, such as doped polysilicon. The second material layer 106 is also called the gate conductive layer 106 and can be used as a word line. In this embodiment, both the bottom layer and the top layer of the stacked structure 105 are the first material layer 104, but the invention is not limited thereto. In addition, in this embodiment, the three-layer first material layer 104 and the two-layer second material layer 106 are used as an example for description, but the invention is not limited thereto.

A patterning process is performed to remove portions of the stacked structure 105 to form one or more holes 107 extending through the stacked structure 105 .

Referring to FIG. 1B , charge storage structures 108 are formed on the sidewalls of holes 107 . Charge storage structure 108 includes a dielectric. In some embodiments, the charge storage structure 108 includes, for example, a barrier layer 110, a storage layer 112, and a tunneling layer 114. In some embodiments, the material of the barrier layer 110 may be a high dielectric constant material with a dielectric constant greater than or equal to 7, a ferroelectric material such as aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), lanthanum oxide ( La ₂ O ₅ ), etc., transition metal oxides, lanthanide element oxides, or combinations thereof. Next, a mask layer 116 is formed on the charge storage structure 108 . Mask layer 116 may be silicon nitride.

Referring to FIG. 1C , an etch back process is performed to remove the mask layer 116 and the charge storage structure 108 , and expose a portion of the plug 102 and the dielectric layer 103 .

Referring to FIG. 1D , the mask layer 116 is removed to expose the sidewalls of the tunnel layer 114 .

Referring to FIG. 1E , a semiconductor layer (or channel layer) 118 ′ is formed in the hole 107 . The semiconductor layer 118' is formed by, for example, using a chemical vapor deposition method to form semiconductor material above the stacked structure 105 and in the holes 107, and then performing a chemical mechanical polishing process to remove the semiconductor material above the stacked structure 105.

Referring to FIGS. 1F and 2A , a patterned hard mask 122 is formed over the stacked structure 105 . Then, a first-stage etching process is performed on the semiconductor layer 118' to form the opening 124. Semiconductor layer 118' is exposed in opening 124. The first stage etching process is, for example, a dry etching process.

Referring to FIGS. 1G, 2B, 1I, and 1K, a second-stage etching process is performed to expand the opening 124 into the opening 124a. The second stage etching process is, for example, a wet etching process. The end of the opening 124 a exposes the sidewall of the tunneling layer 114 of the charge storage structure 108 . The semiconductor layer 118' is divided into a plurality of channel pillars 118. In some embodiments, channel columns 118 may include channel columns 118a, 118b, and 118c that are separate from each other. The channel posts 118a, 118b, and 118c are electrically connected to the plugs 102a, 102b, and 102c respectively. Viewed from a top view, the shape of the channel column 118a, 118b or 118c is, for example, a sector or a part of an annular shape. The sector here consists of two radii and an arc.

1H and 2C, an insulating pillar 126 is formed in the opening 124a so that the channel pillars 118a, 118b, 118c are electrically isolated from each other. The material of the insulating pillar 126 is, for example, silicon oxide. The insulating pillar 126 is formed by, for example, forming a Y-shaped opening 124a through the stacked structure 105 and filling the opening 124a, and then performing an etching back or chemical mechanical polishing process to remove the insulating material on the stacked structure 105. Viewed from a top view, the shape of the insulating pillar 126 is, for example, Y-shaped as shown in FIG. 2C . Insulating posts 126 electrically isolate channel posts 118a, 118b, and 118c from each other, as shown in Figures 2C, 1I, and 1K.

Referring to FIG. 1J , an interconnect structure 160 is formed on the stacked structure 105 . The interconnect structure 160 may include a dielectric layer 128, a plug 130, a conductor 132, etc., but is not limited thereto. Dielectric layer 128 is formed over stacked structure 105 . Dielectric layer 128 may include a single layer or multiple layers. Plug 130 (eg, 130a, 130b, or 130c) is formed in dielectric layer 128 and may be electrically connected to channel post 118a, 118b, or 118c, as shown in FIG. 1K. The material of plug 130 may include tungsten. The wire 132 may be a bit line BL, formed in the dielectric layer 128, and electrically connected to the plug 130. The bit line BL may, for example, include bit lines BLa, BLb, and BLc, which are electrically connected to the plugs 130a, 130b, and 130c respectively, as shown in FIG. 1K. The material of wire 132 may include copper or tungsten.

Referring to FIGS. 1I, 1J and 1K, a plurality of second material layers 106 serving as word lines WL1 and WL2 are stacked on the substrate 100 and are electrically isolated from each other by the first material layer 104. A plurality of channel posts 118, such as three channel posts 118a, 118b, and 118c, extend through the plurality of second material layers 106. The charge storage structure 108 is located in the channel pillar 118a, between 118b, 118c and the plurality of second material layers 106. As shown in FIG. 1K , the channel pillars 118a, 118b, and 118c are respectively electrically connected to the source lines SLa, SLb, and SLc through the plugs 102a, 102b, and 102c located below. The channel pillars 118a, 118b, and 118c are electrically connected to the bit lines BLa, BLb, and BLc through the plugs 130a, 130b, and 130c disposed above respectively.

3A to 3G are a schematic cross-sectional view and a schematic three-dimensional view of an intermediate stage of a manufacturing method of a three-dimensional flash memory device using a gate-first process according to an embodiment of the present invention. 4A to 4C are schematic top views along line II-II' of FIGS. 3B to 3D.

Referring to FIGS. 1D and 3A , the charge storage structure 108 is formed in the hole 107 of the stacked structure 105 according to the above method. Next, a semiconductor layer 118' is formed on the charge storage structure 108. In this embodiment, the semiconductor layer 118' is a conformal layer and does not fill the hole 107. Afterwards, a packed column 120 is formed in the remaining space of the hole 107 . The material of the packed column 120 is, for example, silicon nitride. The method of forming the filling pillar 120 is, for example, filling the filling material into the remaining space of the hole 107 , and then performing an etch back process or a chemical mechanical polishing process to remove the filling material above the stacked structure 105 .

Referring to FIGS. 3B and 4A , a patterned hard mask layer 122 is formed on the stacked structure 105 . Afterwards, a first-stage etching process is performed to etch the semiconductor layer 118′ to form the opening 124. Opening 124 includes three spaces separated by packed columns 120 . The first stage of the etching process is, for example, a dry etching process.

Referring to FIG. 3C and FIG. 4B, a second-stage etching process is performed to expand the opening 124 to form the opening 124a. The second stage etching process is, for example, a wet etching process. The end of the opening 124a exposes the tunnel layer 114 of the charge storage structure 108 and the sidewalls of the filling pillars 120, and the semiconductor layer 118' is divided into a plurality of channel pillars 118. In some embodiments, the plurality of channel pillars 118 in the tunneling layer 114 may include channels that are separate from each other. Pillars 118a, 118b and 118c. The channel posts 118a, 118b, and 118c are electrically connected to the plugs 102a, 102b, and 102c respectively. Viewed from a top view, the shape of the channel column 118 is, for example, a portion of a ring.

The mask layer 122 is removed with reference to Figures 3D, 3E, and 4C. An insulating pillar 126 is formed in the opening 124a. As shown in FIGS. 3E and 4C , the insulating pillar 126 includes three parts P1 , P2 and P3 surrounding the packed pillar 120 . Each portion of insulating pillar 126 (eg, P1, P2, or P3) contacts charge storage structure 108, while channel pillars 118a, 118b, and 118c are electrically isolated from each other by insulating pillar 126 and packed pillar 120. The material of the insulating pillar 126 is, for example, silicon oxide.

Referring to FIGS. 3F and 3G , an interconnect structure 160 is formed on the stacked structure 105 .

5A to 5J are a schematic cross-sectional view and a schematic perspective view of an intermediate stage of a three-dimensional flash memory device manufacturing method with a gate-last process according to another embodiment of the present invention. 6A to 6D are schematic top views of an intermediate stage of a method for manufacturing a three-dimensional flash memory device according to another embodiment of the present invention.

Referring to Figure 5A, a substrate 200 is provided. The substrate 200 may further include a component layer (not shown) on the semiconductor substrate and an interconnect structure 250 on the component layer. The element layer may be the same as or different from that described in the above embodiment, and will not be described again here.

Referring to FIGS. 5A and 5J , the interconnection structure 250 may include wires 201, dielectric layers 203, plugs 202, etc., but is not limited thereto. The wire 201 may serve as the source line SL. In some embodiments, the source line SL may include source lines SLa, SLb, and SLc, as shown in FIG. 5J. The plug 202 may include plugs 202a, 202b, and 202c, which are electrically connected to the source lines SLa, SLb, and SLc respectively, as shown in FIG. 5J. The materials of the conductor 201, the dielectric layer 203, and the plug 202 are different from the materials of the conductor 101, the dielectric layer 103, and the plug 102. The materials can be the same or different.

Referring to FIG. 5A , a stack structure 205 is formed on a substrate 200 . The stacked structure 205 includes a plurality of first material layers 204 and a plurality of second material layers 206 stacked alternately with each other. The first material layer 204 may be an insulating layer, such as silicon oxide. The second material layer 206 may be an insulating layer, such as silicon nitride. The second material layer 206 may serve as a sacrificial layer. In this embodiment, both the bottom layer and the top layer of the stacked structure 205 are the first material layer 204, but the invention is not limited thereto. In addition, in this embodiment, three first material layers 204 and two second material layers 206 are used as an example for description, but the invention is not limited thereto.

Referring to FIG. 5A , next, a patterning process is performed to remove a portion of the stacked structure 205 to form one or more holes 207 through the stacked structure 205 . The shape and formation method of hole 207 may be the same as or different from the shape and formation method of hole 107 .

Referring to FIG. 5B , a semiconductor layer (or channel layer) 218 ′ is formed in the hole 207 . In this embodiment, the semiconductor layer 218' does not fill the hole 207. Afterwards, a packed column 220 is formed in the remaining space of the hole 207 . The materials and formation methods of packed column 220 may be the same as or different from those of packed column 120 .

Referring to FIG. 5C , a lithography and etching process is performed to form slit trenches 222 in the stacked structure 205 . The slit trench 222 divides the stacked structure 205 into a plurality of blocks B, such as blocks B1, B2, and B3, as shown in FIGS. 6A to 6D. The sidewalls of the first material layer 204 and the second material layer 206 of each block B are exposed in the slit trench 222 . Next, an etchant is used to remove the second material layer 206 of the stacked structure 205 . Therefore, the horizontal opening 209 is formed, and the first material layer 204 and the semiconductor layer 218' are exposed in the horizontal opening 209.

Referring to FIG. 5D , a tunnel layer 214 , a storage layer 212 , a barrier layer 210 and a gate conductive layer 240 are formed in the slit trench 222 and the horizontal opening 209 . Tunnel layer 214, The storage layer 212 and the barrier layer 210 are, for example, conformal layers. Materials in the tunnel layer 214, the storage layer 212, and the barrier layer 210 include dielectrics. The gate conductive layer 240 is, for example, tungsten.

Referring to FIG. 5E , in some embodiments, an etch back process is performed to remove the gate conductive layer 240 in the slit trench 222 . The remaining tunnel layer 214, storage layer 212, and barrier layer 210 in the horizontal opening 209 form the charge storage structure 208. The gate conductive layer 240 can serve as word lines WL1 and WL2. The conductive layer 240 and the first material layer 204 form the gate stack structure 205G. In other embodiments, an etch-back process is performed to remove the gate conductive layer 240 , the tunneling layer 214 , the storage layer 212 and the barrier layer 210 (not shown) in the slit trench 222 .

Referring to FIGS. 5F and 5J , a mask layer 223 is formed on the substrate 200 . Mask layer 223 may be a patterned photoresist layer. Then, using the mask layer 223 as a mask, an etching process is performed on the etching semiconductor layer 218' to form the opening 224a. The etching process for forming the opening 224a may be the same as or different from the etching process for forming the opening 124a. The tunnel layer 114 and the sidewalls of the filling pillars 220 are exposed in the ends of the openings 124a. The semiconductor layer 218' is divided into a plurality of channel pillars 218. In some embodiments, the plurality of channel pillars 218 in the tunneling layer 214 may include channel pillars 218a, 218b, and 218c that are spaced apart from each other. The channel posts 218a, 218b, and 218c are electrically connected to the plugs 202a, 202b, and 202c shown in the lower figure of Figure 5J, respectively.

Referring to Figures 5G and 5H, mask layer 223 is removed. An insulating pillar 226 is formed in the opening 224a, and a slit structure 225 is formed in the slit trench 222. As shown in FIGS. 5H and 5J , the insulating pillar 226 may include three parts P1 , P2 and P3 separated by the packed pillar 220 . The insulating pillar 226 is in contact with the charge storage structure 208, and the channel pillars 218a, 218b, and 218c are electrically isolated from each other. The material of the insulating pillar 226 and the slit structure 225 is, for example, silicon oxide.

Referring to FIGS. 5I and 5J , an interconnect structure 260 is formed on the gate stack structure 205G. The interconnect structure 260 may include a dielectric layer 228, a plug 230, a conductor 232, etc., but is not limited thereto.

Referring to Figures 5I and 5J, in some embodiments, plug 230 includes plugs 230a, 230b, and 230c. The plugs 230a, 230b and 230c are electrically connected to the source lines BLa, BLb and BLc respectively, as shown in Figure 5J. The wire 232 may be a bit line BL, formed in the dielectric layer 228, and electrically connected to the plug 230. The bit line BL may include bit lines BLa, BLb, and BLc, which are electrically connected plugs 230a, 230b, and 230c respectively, as shown in FIG. 5J.

Referring to FIG. 5H, FIG. 5I, and FIG. 5J, multiple gate conductive layers 240 serving as word lines WL1 and WL2 are stacked on the substrate 200 and are electrically isolated from each other through multiple first material layers 204. A plurality of channel posts 218, such as three channel posts 218a, 218b, and 218c, extend through the plurality of gate conductive layers 240. The charge storage structure 208 is located between the channel pillars 218a, 218b, 218c and the plurality of gate conductive layers 240. The channel pillars 218a, 218b, and 218c are electrically connected to the source lines SLa, SLb, and SLc respectively through the plugs 202a, 202b, and 202c. Channel pillars 218a, 218b, and 218c are electrically connected to bit lines BLa, BLb, and BLc through plugs 230a, 230b, and 230c, respectively.

Referring to Figure 5J, Figure 6A and Figure 6B, in some embodiments, there are three plugs 230 (for example, 230a, 230b, 230c) in the area surrounded by the charge storage structure 208, which are electrically connected to the three channel columns 218 ( For example 218a, 218b and 218c). Referring to Figures 6C and 6D, in some embodiments, there are four plugs 230 (for example, 230a, 230b, 230c, 230d) in the area surrounded by the charge storage structure 208, respectively electrically connected to four channel columns (not shown). ). In some embodiments, the angle α between the line connecting the centers of plugs 230c and 230d and the Y-axis is 26.565 degrees. However, embodiments of the present disclosure are not limited to Here it is.

Referring to FIGS. 6A to 6D , in the embodiment of the present invention, angles θ1 , θ2 , θ3 , and θ4 between the extension direction of the bit line BL and the extension direction of the source line SL are acute angles. Referring to FIGS. 6A to 6D , for example, the bit lines BLa, BLb, ..., BLj extend along the Y-axis direction, and the source lines Sla, SLb, SLc, SLd, SLe extend along the D1 direction. The angles θ1, θ2, θ3, and θ4 between the D1 direction and the Y direction are acute angles.

Referring to FIG. 6A , in some embodiments, the charge storage structures 208 are spaced further apart, more loosely packed, and each bit line BL (eg, BLa, BLb, . ... or BLi) only overlaps a single plug 230 (eg, 230a, 230b, or 230c). Referring to FIGS. 6B to 6D , in some other embodiments, the spacing between the charge storage structures 208 is smaller and the packing is denser, and each bit line BL (eg, BLa, BLa, etc.) in the same block (eg, B2) BLb, ... or BLj) overlap with a single or multiple plugs 230 (eg, 230a, 230b, and/or 230c).

Referring to FIGS. 6A-6D , in some embodiments, source line SL (eg, B2 ) in the same block may overlap one, two, or more plugs 202 in the same charge storage structure 208 . Source lines SL in the same block (eg, B2) may overlap one, two, or more plugs 202 in different charge storage structures 208.

In the above embodiment, the channel pillars 118a, 118b, 118c or 218a, 218b, 218c are within the range of the inner wall of the charge storage structure 108 or 208, but the invention is not limited thereto.

In other embodiments, multiple pillars may be used with other memory types besides charge storage. For example, charge storage structures can be replaced by ferroelectric storage structures for.

7A to 7B are a schematic cross-sectional view and a schematic perspective view of an intermediate stage of a manufacturing method of a three-dimensional phase change memory element.

In other embodiments shown in Figures 7A and 7B, posts 428 (eg, 428a, 428b, and 428c) are separated and isolated by insulating posts 426. Each separate and isolated column 428 (eg, 428a, 428b, or 428c) includes an outer region 418 and an inner region 408. The outer region 418 is a semiconductor channel region 418 . Semiconductor channel region 418 is also referred to as outer channel region 418 (eg, 418a, 418b, and 418c). The inner area 408 is the phase change storage area 408, also known as the inner phase change storage area 408 (eg, 408a, 408b, and 408c). Posts 428 (eg, 428a, 428b, and 428c) fill hole 107, which is surrounded by gate oxide 410 coupled to surrounding word lines WL1 and WL2.

8A to 8D are schematic top views of intermediate stages of a manufacturing method of a three-dimensional phase change memory device with a gate-first process according to an embodiment of the present invention. Figures 8A to 8D are schematic top views of line III-III' in Figure 7A.

Referring to FIG. 8A , a gate dielectric layer 410 is formed in the hole 107 in the stacked structure 105 (shown in FIG. 7A ) by a method similar to the charge storage structure 108 (shown in FIGS. 1B to 1D ). A semiconductor layer (or channel layer) 418' and a phase change layer 408' are formed in the hole 107. The gate dielectric layer 410 is, for example, silicon oxide, or a high dielectric constant material with a dielectric constant greater than or equal to 7, or a ferroelectric material such as aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), or lanthanum oxide. (La ₂ O ₅ ), transition metal oxides, lanthanide oxides, or combinations thereof. The semiconductor layer 418' is, for example, undoped polysilicon. Phase change layer 408' may include a chalcogenide material, such as an indium (In)-antimony (Sb)-tellurium (Te) (IST) material.

Referring to FIG. 8B , a graph is formed over the stacked structure 105 (shown in FIG. 7A ). Customized hard cover (not shown). Afterwards, a first-stage etching process, such as a dry etching process, is performed on the phase change layer 408' and the semiconductor layer 418' to form the opening 424. Openings 424 divide phase change layer 408' into phase change storage regions 408 (e.g., 408a, 408b, and 408c).

Referring to FIG. 8C and FIG. 7A, a second stage etching process, such as a wet etching process, is performed to expand the opening 424 into an opening 424a. The sidewalls of the opening 424a expose the semiconductor layer 418' and the phase change layer 408', and the end of the opening 424a exposes the semiconductor layer 418'. Opening 424a divides semiconductor layer 418' and phase change layer 408' into a plurality of pillars 428 (e.g., pillars 428a, 428b, and 428c). Each of the plurality of posts 428 (eg, 428a, 428b, and 428c) includes an outer region 418 and an inner region 408. The outer region 418 is the outer channel region 418 (eg, 418a, 418b, and 418c). Internal area 408 is phase change storage area 408 (eg, 408a, 408b, and 408c).

Referring to Figures 8D and 7A, opening 424a is filled with insulating posts 426 to isolate posts 428 (eg, 428a, 428b, and 428c).

Referring to FIG. 7B , an interconnect structure 160 is formed on the stacked structure 105 according to the above method.

Figure 9 shows a schematic top view of the operation of a three-dimensional phase change memory device.

Referring to FIG. 9 , a bias voltage is applied to the unselected word lines to make the channel conductive, and a bias voltage is applied to the selected word line to make the channel non-conductive. When on, the channel's resistive path should be much lower than the phase change region next to it, so it will draw all or almost all of the current. On the other hand, when not conducting, current flows through the phase change region at the same height as the word line to obtain the desired read or write operation.

In summary, in various embodiments of the present invention, each charge storage structure or each phase change storage area is coupled with three channel pillars, so that the memory unit can be more compact. Densely arranged, thereby increasing the number of memory cells per chip area and increasing the density of memory cells.

It will be apparent to those skilled in the art that various modifications and changes can be made in the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and changes provided they come within the scope of the appended claims and their equivalents.

106: Second material layer/gate conductive layer

108:Charge storage structure

118a, 118b, 118c: channel column

126:Insulation column

WL1, WL2: character lines

Claims (10)

A memory element, including: a gate stack structure disposed on a substrate, wherein the gate stack structure includes a plurality of gate conductive layers and a plurality of insulating layers vertically stacked alternately; at least three channel columns extending through The gate stack structure, wherein the at least three channel columns are electrically isolated from each other; the charge storage structure is disposed on the inner walls of the plurality of gate conductive layers and surrounds the at least three channel columns; at least three a source line disposed below the gate stack structure and electrically connected to the at least three channel pillars; and at least three bit lines disposed above the gate stack structure and electrically connected to the At least three channel columns. The memory element according to claim 1, further comprising an insulating pillar disposed between the at least three channel pillars, wherein the insulating pillars are Y-shaped when viewed from a top view, and the at least three channel pillars Has a fan-shaped or partially ring-shaped shape. The memory device of claim 1, wherein the at least three bit lines extend in a first direction, the at least three source lines extend in a second direction, and the first direction and the second The angle between directions is an acute angle. A method for manufacturing a memory element, including: forming at least three source lines on a substrate; forming a stacked structure on the at least three source lines, wherein the stacked structure includes a plurality of gate conductive layers and a plurality of Insulating layers are stacked alternately with each other; holes are formed in the stacked structure; charge storage structures are formed on the sidewalls of the holes; forming a semiconductor layer in the hole; patterning the semiconductor layer to form at least three channel pillars within the charge storage structure, wherein the at least three channel pillars connect the at least three source lines; Insulating pillars are formed in the remaining spaces of the holes; and at least three bit lines are formed on the gate stack structure, wherein the at least three bit lines are electrically connected to the at least three channel pillars. The memory element manufacturing method according to claim 4, wherein the semiconductor layer is formed in the hole so that the hole is completely filled with the semiconductor layer, wherein patterning the semiconductor layer and forming the insulating pillar includes : forming a first opening in the semiconductor layer, wherein the semiconductor layer is exposed to an end of the first opening; the first opening is expanded to form a second opening, wherein the charge storage structure is exposed to the second the end of the opening; and forming the insulating column in the second opening, wherein the first opening and the second opening have a Y shape when viewed from a top view. The memory element manufacturing method according to claim 5, wherein the semiconductor layer is formed in the hole so that the hole is not completely filled by the semiconductor layer, and the method further includes forming A filling pillar method, wherein patterning the semiconductor layer and forming the insulating pillar includes: forming the first opening in the semiconductor layer, wherein the semiconductor layer and the filling pillar are exposed to the first opening an end; the first opening expands to form the second opening, wherein the charge storage structure and the filling pillar are exposed to the end of the second opening; and the insulating pillar is formed in the second opening. A memory element manufacturing method, including: forming at least three source lines on a substrate; forming a stacked structure on the at least three source lines, wherein the stacked structure includes a plurality of first material layers and a plurality of second material layers are alternately stacked; forming holes in the stacked structure; forming semiconductor layers in the holes; forming filling pillars in the semiconductor layers; removing the plurality of second material layers to form a plurality of horizontal openings ; forming a plurality of charge storage structures and a plurality of gate conductive layers in the plurality of horizontal openings; patterning the semiconductor layer in the holes to form at least three channel pillars, wherein the plurality of charge storage structures Connecting the at least three channel pillars; forming an insulating pillar in the remaining space of the hole; and forming at least three bit lines on the gate stack structure, wherein the at least three bit lines are electrically Connect the at least three channel columns. The memory element manufacturing method according to claim 7, wherein patterning the semiconductor layer and forming the insulating pillar includes: forming a first opening in the semiconductor layer, wherein the semiconductor layer and the filling pillar are exposed at the end of the first opening; the first opening expands to form a second opening, wherein the charge storage structure and the filling column are exposed to the end of the second opening; and forming in the second opening The insulating pillar. The memory element manufacturing method of claim 5, 6 or 8, wherein forming the first opening includes a dry etching process, and forming the second opening includes a wet etching process. The memory element manufacturing method according to claim 7, wherein the at least three channel columns are electrically isolated from each other, wherein the outer region of each channel column is a semiconductor channel region, and the inner region of each channel column is a phase change In the storage area, the material of the charge storage structure is a dielectric.

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