TWI825315B - Assigning method and assigning system for graphic resource - Google Patents

Abstract

An assigning method and an assigning system for graphic resource are disclosed. The method includes: obtaining first correlation information between a first graphic processing unit among a plurality of graphic processing units and at least one central processing unit; obtaining second correlation information between the first graphic processing unit and at least one second graphic processing unit among the graphic processing units; establishing a group topology structure of the graphic processing units according to the first correlation information and the second correlation information; and performing a graphic resource assignment of the graphic processing units according to the group topology structure.

Description

Graphics resource allocation method and allocation system

The present invention relates to a system resource allocation technology, and in particular to a graphics resource allocation method and allocation system.

With the advancement of technology, the requirements for the computing speed of computer systems are becoming higher and higher. Therefore, some computer systems can be configured with multiple graphics processing units (Graphic Processing Units, GPUs) to assist the central processing unit (Central Processing Unit, CPU) in performing graphics-related operations. However, in the existing working mechanism, the graphics processing work related to a certain central processing unit is often randomly assigned to one or more graphics processing units for processing, without taking into account the graphics processing unit that receives the graphics processing work. Whether the communication path (or signal transmission path) between the unit and the central processing unit is too complex, resulting in reduced system performance.

The present invention provides a graphics resource allocation method and allocation system, which can be Effectively improve graphics processing efficiency.

Embodiments of the present invention provide a graphics resource allocation method, which includes: obtaining first association information between a first graphics processing unit among a plurality of graphics processing units and at least one central processing unit; obtaining the first graphics processing unit Second association information between the unit and at least one second graphics processing unit among the plurality of graphics processing units; establishing a group of the plurality of graphics processing units based on the first association information and the second association information a topology structure; and performing graphics resource allocation of the plurality of graphics processing units according to the grouped topology structure.

Embodiments of the present invention further provide a graphics resource allocation system, which includes at least one central processing unit, multiple graphics processing units, a storage device, and a graphics resource allocator. The plurality of graphics processing units are coupled to the at least one central processing unit. The storage device is coupled to the at least one central processing unit and the plurality of graphics processing units. The graphics resource allocator is coupled to the storage device. The graphics resource allocator is used to obtain first association information between a first graphics processing unit of the plurality of graphics processing units and the at least one central processing unit from the storage device. The graphics resource allocator is further configured to obtain second association information between the first graphics processing unit and at least one second graphics processing unit among the plurality of graphics processing units from the storage device. The graphics resource allocator is further configured to establish a group topology structure of the plurality of graphics processing units according to the first association information and the second association information. The graphics resource allocator is further configured to perform graphics resource allocation of the plurality of graphics processing units according to the group topology structure.

Based on the above, according to the relationship between the first graphics processing unit and the central processing unit After obtaining the first association information and the second association information between the first graphics processing unit and at least one second graphics processing unit, a grouping topology structure of multiple graphics processing units may be established. Then, according to the group topology, the graphics resources of the multiple graphics processing units can be properly allocated, thereby effectively improving graphics processing efficiency.

10: Graphics resource allocation system

11(1)~11(n): Central processing unit

12(1)~12(m): Graphics processing unit

13:Storage device

131,132: Form information

14: Graphics resource allocator

21(1)~21(4):Interface

31,41:Related information

51~53: Group topology structure

S601~S604: steps

FIG. 1 is a schematic diagram of a graphics resource allocation system according to an embodiment of the present invention.

FIG. 2 is a schematic diagram illustrating the physical coupling relationship between a central processing unit and a graphics processing unit according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of first associated information according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of second associated information according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of a grouping topology according to an embodiment of the present invention.

FIG. 6 is a flowchart of a graphics resource allocation method according to an embodiment of the present invention.

Figure 1 illustrates the allocation of graphics resources according to an embodiment of the present invention. Schematic diagram of the system. Referring to Figure 1, the system (also known as the graphics resource allocation system) 10 can be implemented on various electronic devices with data processing and graphics processing functions (or computer device).

The system 10 includes central processing units (CPUs) 11(1)˜11(n), graphics processing units (GPUs) 12(1)˜12(m), a storage device 13 and a graphics resource allocator 14. Each of the central processing units (CPU) 11(1)~11(n) may refer to a central processing unit chip. Each of the graphics processing units 12(1)~12(m) may refer to a graphics processing unit chip. In terms of operation, the central processing units 11(1)~11(n) and the graphics processing units 12(1)~12(m) can operate cooperatively to jointly complete data processing and graphics processing tasks. The total number of central processing units 11(1)~11(n) and the total number of graphics processing units 12(1)~12(m) are determined by practical needs and are not limited by the present invention.

The storage device 13 is used to store data. The storage device 13 may include volatile memory modules and non-volatile memory modules. Volatile memory modules may include random access memory (RAM) and other memory media that can store data volatilely. Non-volatile memory modules may include memory media that can store data in a non-volatile manner, such as read-only memory (ROM) and/or flash memory.

The graphics resource allocator 14 is coupled to the central processing units 11(1)˜11(n), the graphics processing units 12(1)˜12(m), and the storage device 13. In one embodiment, the graphics resource allocator 14 may be implemented as a programmable general-purpose or special-purpose microprocessor, a digital signal processor (Digital Signal Processor, DSP), a programmable controller, or a special application integrated device. Application Specific Integrated Circuits, ASIC), programmable logic device (Programmable Logic Device, PLD) or other similar devices or a combination of these devices. In one embodiment, the graphics resource allocator 14 can also be implemented as program code and stored in the storage device 13 .

Table information 131 and 132 are stored in the storage device 13 . For example, the table information 131 and 132 are obtained by the system after the central processing units 11(1)~11(n) and the graphics processing units 12(1)~12(m) are installed on the motherboard (not shown) of the system 10. 10's operating system (such as Windows operating system) or system tools such as BIOS automatically scan related hardware information and automatically generate it.

The table information 131 records the related information between the central processing units 11(1)~11(n) and the graphics processing units 12(1)~12(m). In particular, the table information 131 may record a certain graphics processing unit (also referred to as the first graphics processing unit) among the graphics processing units 12(1)~12(m) and the central processing units 11(1)~11(n). The associated information between them (also known as the first associated information). For example, the first associated information may include the core of a certain central processing unit (also referred to as the first central processing unit) that the first graphics processing unit presets to preferentially use among the central processing units 11(1)˜11(n). Number (core number) information.

The table information 132 records the related information between the graphics processing units 12(1)~12(m). In particular, the table information 132 may record the association information (also referred to as the second graphics processing unit) between the first graphics processing unit and the remaining graphics processing units (also referred to as the second graphics processing units) among the graphics processing units 12(1)˜12(m). Also known as second associated information). For example, the second association information may include proximity level information between the first graphics processing unit and the second graphics processing unit.

The graphics resource allocator 14 can read the table information 131 from the storage device 13 and 132 to obtain the first associated information and the second associated information. According to the first correlation information and the second correlation information, the graphics resource allocator 14 can establish a group topology structure of the graphics processing units 12(1)˜12(m). Thereafter, the graphics resource allocator 14 may perform graphics resource allocation for the graphics processing units 12(1)˜12(m) according to the established group topology structure. For example, when it is necessary to perform a graphics processing task related to at least one of the central processing units 11(1)˜11(n), the graphics resource allocator 14 can obtain the data from the graphics processing unit 12 ( Select the appropriate graphics processing unit among 1)~12(m) and assign this graphics processing task to the selected graphics processing unit for processing.

FIG. 2 is a schematic diagram illustrating the physical coupling relationship between a central processing unit and a graphics processing unit according to an embodiment of the present invention. Please refer to Figures 1 and 2, assuming that the central processing units 11(1)~11(n) include central processing units 11(1) and 11(2) and the graphics processing units 12(1)~12(m) include graphics processing units. Units 12(1)~12(8).

Central processing units 11(1) and 11(2) are connected to graphics processing units 12(1)~12(8) via interfaces 21(1)~21(4). For example, central processing unit 11(1) is connected to graphics processing units 12(1) and 12(2) via interface 21(1) and to graphics processing units 12(3) and 12(4) via interface 21(2). . Central processing unit 11(2) is connected to graphics processing units 12(5) and 12(6) via interface 21(3) and to graphics processing units 12(7) and 12(8) via interface 21(4). The interfaces 21(1)~21(4) may respectively include PCIe switches or other types of physical connection interfaces.

It should be noted that in the embodiment of FIG. 2 , when the upper-layer central processing units 11(1) and 11(2) allocate graphics processing tasks to the lower-layer graphics processing units 12(1)~12(8) or when the upper-layer central processing units 11(1) and 11(2) receive the processing results of the graphics processing tasks from the lower-layer graphics processing units 12(1)~12(8), the central processing The unit 11(1) can directly communicate with the graphics processing units 12(1)~12(4) via the interfaces 21(1) and 21(2), and the central processing unit 11(2) can directly communicate with the graphics processing units 12(1) through the interface 21(3). 21(4) communicates with the graphics processing units 12(5)~12(8). However, if it involves the exchange of tasks and/or processing results across central processing units, the central processing unit 11(1) must communicate with the graphics processing units 12(5)~12(8) through the central processing unit 11(2). , and the central processing unit 11(2) must communicate with the graphics processing units 12(1)~12(4) through the central processing unit 11(1).

Based on the above communication limitations, if a graphics processing unit is randomly selected to assist a specific central processing unit in graphics processing, poor selection of the graphics processing unit may cause delays in signal transmission, which in turn leads to a decrease in overall graphics processing performance. In one embodiment, the established grouping topology may at least partially reflect the physical coupling relationship between the upper-layer central processing unit and the lower-layer graphics processing unit. Therefore, when graphics processing resources need to be allocated, the graphics resource allocator 14 can select one or more appropriate graphics processing units according to this group topology to assist a specific central processing unit in performing graphics operations, thereby improving the overall graphics processing performance. decline.

For convenience of explanation, it is assumed below that the numbers of the central processing units 11(1) and 11(2) are CPU#1 and CPU#2 respectively. In addition, it is assumed that the numbers of the graphics processing units 12(1)~12(8) are respectively GPU#1, GPU#2, GPU#4, GPU#5, GPU#3, GPU#6, GPU#7 and GPU#8. .

FIG. 3 is a schematic diagram of first associated information according to an embodiment of the present invention. FIG. 4 is a schematic diagram of second associated information according to an embodiment of the present invention. Referring to FIGS. 1 to 3 , it is assumed that the first related information includes related information 31 . The association information 31 may reflect the association between the central processing units 11(1)~11(2) and the graphics processing units 12(1)~12(8). For example, the related information 31 may reflect that the core numbers of the central processing units that are preset and preferentially used by the graphics processing units GPU#1~GPU#8 are respectively CPU core#1, CPU core#1, CPU core#2, and CPU core#. 1. CPU core#1, CPU core#2, CPU core#2 and CPU core#2. Wherein, CPU core#1 is, for example, the core number of the central processing unit 11(1), and CPU core#2 is, for example, the core number of the central processing unit 11(2).

According to the association information 31, the graphics resource allocator 14 can obtain the group to which each graphics processing unit belongs. For example, according to the related information 31, the graphics resource allocator 14 can determine that the graphics processing units GPU#1~GPU#8 belong to group 1, group 1, group 2, group 1, group 1, group 2, respectively. Group 2 and Group 2. The graphics processing units belonging to group 1 may include at least some of the graphics processing units (eg, graphics processing units GPU#1, GPU#2, GPU#4, GPU#5) that are preset to preferentially use the central processing unit CPU#1. The graphics processing units belonging to group 2 may include at least some of the graphics processing units (eg, graphics processing units GPU#3, GPU#6, GPU#7, GPU#8) that preferentially use the central processing unit CPU#2.

Referring to FIGS. 1 to 4 , it is assumed that the second related information includes related information 41 . The correlation information 41 may reflect the correlation between the graphics processing units 12(1)~12(8). For example, the associated information 41 may reflect a specific graphics processing unit (ie, the first graphics processing unit) Proximity level information with other graphics processing units (ie, the second graphics processing unit).

In one embodiment, the proximity rank information can be represented by Rank 1, which is a closer distance between multiple graphics processing units, and Rank 2, which is a farther distance between multiple graphics processing units. For example, the related information 41 may record that the distance between the graphics processing unit GPU#1 and the graphics processing units GPU#2, GPU#3, GPU#4, and GPU#5 is relatively close, and that the distance between the graphics processing unit GPU#1 and the graphics processing units GPU#6, GPU#5 is relatively close. The distance between #7 and GPU#8 is relatively long; the distance between the graphics processing unit GPU#2 and the graphics processing units GPU#1, GPU#4 and GPU#5 is relatively close, and the distance between it and the graphics processing unit GPU#3 , GPU#6, GPU#7 and GPU#8 are far apart; the distance between graphics processing unit GPU#3 and graphics processing unit GPU#1, GPU#6, GPU#7 and GPU#8 is relatively close. , and the distance between it and the graphics processing units GPU#2, GPU#4, and GPU#5 is relatively long.

It should be noted that the information recorded in the related information 41 may not completely accurately reflect the real relationship between the upper-layer central processing units 11(1) and 11(2) and the lower-layer graphics processing units 12(1)~12(8). Entity coupling relationship. For example, for the graphics processing unit GPU#1, the related information 41 reflects that the graphics processing unit GPU#3 belongs to a nearby graphics processing unit. However, in fact, the graphics processing unit GPU#3 is connected to another central processing unit. Unit 11(2), not central processing unit 11(1). Therefore, if the group topology structure is established solely based on the related information 41, misjudgment may occur, which will affect subsequent graphics processing performance.

Therefore, in one embodiment, when establishing a group topology, the graphics resource allocator 14 can select, for each graphics processing unit, graphics processing units that belong to the same group and are close to each other (also known as the third graphics unit). processing unit). For example, according to Related information 41, the graphics resource allocator 14 may select the graphics processing units GPU#2, GPU#3, GPU#4 and GPU#5 as the graphics processing units closest to the graphics processing unit GPU#1, and select the graphics processing unit GPU# 1. GPU#4 and GPU#5 are used as the graphics processing units closest to the graphics processing unit GPU#2, and the graphics processing units GPU#1, GPU#6, GPU#7, and GPU#8 are selected as the graphics processing units GPU#2. #3 nearest graphics processing unit. Then, based on whether the selected third graphics processing unit and the corresponding first graphics processing unit belong to the same group, the graphics resource allocator 14 may determine the number of components related to the first graphics processing unit in the finally established group topology structure. Group topology structure (also known as the first group topology structure).

FIG. 5 is a schematic diagram of a grouping topology according to an embodiment of the present invention. Please refer to FIGS. 1 to 5 . According to the associated information 31 and 41 , when establishing the group topology 51 of the graphics processing unit GPU#1 belonging to the group 1, the graphics processing unit GPU# belonging to the same group 1 is the closest neighbor. The graphics processing units GPU#2, GPU#4 and GPU#5 of 1 will be retained in the group topology structure 51, and belong to different group 2 but are mistakenly recorded as the graphics processing units that are also the closest graphics processing unit GPU#1 Unit GPU#3 will be removed from the cluster topology 51.

When establishing the grouping topology 52 of the graphics processing unit GPU#2 belonging to the group 1, the graphics processing units GPU#1, GPU#4 and GPU# belonging to the same group 1 and closest to the graphics processing unit GPU#2 5 will be retained in group topology 52. When establishing the grouping topology 53 of the graphics processing unit GPU#3 belonging to the group 2, the graphics processing units GPU#6, GPU#7 and GPU# belonging to the same group 2 and closest to the graphics processing unit GPU#3 8 will be retained in group topology 53, The graphics processing unit GPU#1 that belongs to a different group 1 but is mistakenly recorded as the closest neighbor to the graphics processing unit GPU#3 will be removed from the grouping topology 53 . By analogy, the group topology structures corresponding to the other graphics processing units GPU#4~GPU#8 can also be established.

Thereafter, when wanting to allocate graphics resources required for graphics operations, the graphics resource allocator 14 may select the graphics processing unit GPU#1 and the graphics processing units GPU#2, GPU#4 and GPU#5 that all belong to the group topology 51 At least one of the graphics processing units GPU#3 and the graphics processing units GPU#6, GPU#7 and GPU#8 that belong to the group topology structure 53 is selected to perform graphics operations collaboratively. Graphics operations, etc. Compared with randomly selecting available graphics processing units for graphics processing, selecting graphics processing units according to the group topology established in the aforementioned embodiments can effectively improve the overall graphics computing performance.

It should be noted that although FIG. 2 is used as an example of the physical coupling relationship between the upper-layer central processing unit and the lower-layer graphics processing unit in the foregoing embodiments, the present invention is not limited thereto. In another embodiment, the physical coupling relationship between the upper-layer central processing unit and the lower-layer graphics processing unit may also have other coupling forms, such as more layers or connections via more or less interfaces, etc., The invention is not limited. In addition, regardless of the physical coupling relationship between the upper central processing unit and the lower graphics processing unit, once the central processing unit and the graphics processing unit are installed on the motherboard, the table information 131 and 132 of Figure 1 can be automatically generated . Thereafter, the corresponding grouping topology structure can be established based on the table information 131 and 132, which will not be repeated here.

FIG. 6 is a flowchart of a graphics resource allocation method according to an embodiment of the present invention. Referring to FIG. 6 , in step S601 , first association information between a first graphics processing unit among a plurality of graphics processing units and at least one central processing unit is obtained. In step S602, second association information between the first graphics processing unit and at least one second graphics processing unit among the plurality of graphics processing units is obtained. In step S603, a group topology structure of the plurality of graphics processing units is established according to the first association information and the second association information. In step S604, graphics resource allocation of the plurality of graphics processing units is performed according to the group topology structure.

However, each step in Figure 6 has been described in detail above and will not be described again here. It is worth noting that each step in Figure 6 can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. In addition, the method in Figure 6 can be used in conjunction with the above example embodiments or can be used alone, and is not limited by the present invention.

In summary, embodiments of the present invention can group graphics processing units according to the first association information. Then, according to the grouping result and the second association information, the grouping topology structure of the graphics processing unit can be established. According to the established group topology, the graphics resources of multiple graphics processing units can be properly allocated and used, thereby effectively improving future graphics processing efficiency.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.

S601~S604: steps

Claims (10)

A method for allocating graphics resources, including: obtaining a first association information between a first graphics processing unit among a plurality of graphics processing units and at least one central processing unit, wherein the first association information reflects the first graphics processing unit Correlation between the unit and the at least one central processing unit; obtaining a second association information between the first graphics processing unit and at least a second graphics processing unit among the plurality of graphics processing units, wherein the second The correlation information reflects the correlation between the first graphics processing unit and the at least one second graphics processing unit; establishing a group topology structure of the plurality of graphics processing units based on the first correlation information and the second correlation information; and performing a graphics resource allocation of the plurality of graphics processing units according to the group topology structure. The method of allocating graphics resources as described in claim 1, wherein the step of establishing the group topology structure of the plurality of graphics processing units according to the first association information and the second association information includes: obtaining according to the first association information A first group to which the first graphics processing unit belongs; selecting at least one of the at least one second graphics processing unit as a third graphics closest to the first graphics processing unit according to the second association information processing unit; and determining the group according to whether the third graphics processing unit belongs to the first group A first group topology structure related to the first graphics processing unit in the topology structure. The graphics resource allocation method as described in claim 2, wherein the first group topology related to the first graphics processing unit in the group topology structure is determined based on whether the third graphics processing unit belongs to the first group. The steps of structuring include: if the third graphics processing unit belongs to the first group, retaining the third graphics processing unit in the first group topology; and if the third graphics processing unit does not belong to the first group A group is used to remove the third graphics processing unit from the first group topology. The method for allocating graphics resources as described in claim 1, wherein the first associated information records a core number of a first central processing unit that the first graphics processing unit presets to preferentially use in the at least one central processing unit. information. The graphics resource allocation method of claim 1, wherein the second association information records a proximity level information between the first graphics processing unit and the at least one second graphics processing unit. A graphics resource allocation system includes: at least one central processing unit; a plurality of graphics processing units coupled to the at least one central processing unit; a storage device; and a graphics resource allocator coupled to the at least one central processing unit unit, the storage device and the plurality of graphics processing units, wherein the graphics resource allocator is used to obtain from the storage device a first graphics processing unit in the plurality of graphics processing units and the at least one central processing unit. A first association information, wherein the first association information reflects the association between the first graphics processing unit and the at least one central processing unit, the graphics resource allocator is further used to obtain the first graphics processing unit from the storage device A second association information between the unit and at least one second graphics processing unit among the plurality of graphics processing units, wherein the second association information reflects the relationship between the first graphics processing unit and the at least one second graphics processing unit. The graphics resource allocator is further used to establish a group topology structure of the plurality of graphics processing units according to the first correlation information and the second correlation information, and the graphics resource allocator is further used to establish a group topology structure of the plurality of graphics processing units according to the grouping. The topology structure performs a graphics resource allocation of the plurality of graphics processing units. The graphics resource allocation system of claim 6, wherein the operation of establishing the group topology structure of the plurality of graphics processing units based on the first correlation information and the second correlation information includes: obtaining according to the first correlation information A first group to which the first graphics processing unit belongs; selecting at least one of the at least one second graphics processing unit as a third graphics closest to the first graphics processing unit according to the second association information a processing unit; and determining a first group topology structure related to the first graphics processing unit in the group topology structure based on whether the third graphics processing unit belongs to the first group. The graphics resource allocation system of claim 7, wherein the first group topology related to the first graphics processing unit in the group topology structure is determined based on whether the third graphics processing unit belongs to the first group. The operations of the group structure include: if the third graphics processing unit belongs to the first group, retaining the third graphics processing unit in the first group topology structure; and if the third graphics processing unit does not belong to the first group A group is used to remove the third graphics processing unit from the first group topology. The graphics resource allocation system of claim 6, wherein the first associated information records a core number of a first central processing unit that the first graphics processing unit presets to preferentially use in the at least one central processing unit. information. The graphics resource allocation system of claim 6, wherein the second association information records a proximity level information between the first graphics processing unit and the at least one second graphics processing unit.

Images