TWI824878B - Display device - Google Patents

Abstract

A display device including display panel, a plurality of multiplexers and a plurality of impedance circuits is provided. The display panel has a plurality of sub-pixels arranged in an array, a plurality of data lines and a plurality of gate lines, and each of the plurality of sub-pixels is electrically connected to one of the plurality of data lines and one of the plurality of gate lines. The plurality of multiplexers are respectively arranged between a group of data lines among the plurality of data lines and a data terminal, and each of the plurality of multiplexers receives a sub-pixel voltage from the data terminal and provides the sub-pixel voltage to a first data line in the group of data lines during sub-pixel charging. The plurality of impedance circuits are respectively arranged between one of the plurality of data lines and a ground terminal, and part of impedance circuits in the plurality of impedance circuits receive a ground voltage from the ground terminal and provide the ground voltage to at least one second data line in the group of data lines during the sub-pixel charging.

Description

display device

The present invention relates to a display technology, and in particular to a display device.

Near-field communication (NFC) technology provides short-range wireless connections to achieve two-way interactive communication between electronic devices. This technology uses antenna coils to induce each other at an operating frequency of 13.56 MHz (Mega Hertz, MHz). One group is used as the induction coil of the NFC reader (NFC Reader), and the other group is used as the NFC tag (NFC reader). tag) induction coil is used. The NFC reader is the device that initiates communication, and the NFC tag (or card) is the device that responds to the request from the initiator and accepts the device with which communication is about to occur.

Since NFC is a high-frequency signal, it is easily affected by the environment. Specifically, when the antenna trace area overlaps the panel, because there are many metal traces on the panel, the panel traces will transmit the in-plane signal to the antenna through coupling. However, this signal is complicated for the NFC reader. Signal. In addition, if the antenna is placed on one side of the panel or on the same plane, the metal traces on the panel will form a loop and send the signal back to the NFC reader through load modulation, which will cause the NFC reader to receive abnormally.

In view of this, how to effectively reduce noise and reduce abnormal situations in a display device with NFC function to improve communication capabilities will be an important issue for those skilled in the art.

The present invention provides a display device that can reduce interference noise to improve wireless signal transmission performance.

The display device of the present invention includes a display panel, a plurality of multiplexers and a plurality of impedance circuits. The display panel has a plurality of sub-pixels, a plurality of data lines and a plurality of gate lines arranged in an array. Each of the plurality of sub-pixels is electrically connected to one of the plurality of data lines and the plurality of gate lines. one of. A plurality of multiplexers are each disposed between a group of data lines among the plurality of data lines and a data terminal. Each of the plurality of multiplexers receives a sub-pixel voltage from the data terminal during sub-pixel charging and provides The sub-pixel voltage is applied to the first data line in a group of data lines. The plurality of impedance circuits are respectively disposed between one of the plurality of data lines and the ground terminal. Some of the plurality of impedance circuits receive the ground voltage from the ground terminal during sub-pixel charging and provide the ground voltage to a set of data. at least one second data line among the lines.

Based on the above, the display device of the embodiment of the present invention is provided with a multiplexer between a group of data lines and the data terminal, and an impedance circuit is provided between each data line and the ground terminal, and during the sub-pixel charging period, The sub-pixel voltage is provided from the data terminal to one data line in the group of data lines through the multiplexer, and the ground voltage is provided to the other data lines in the group of data lines through the impedance circuit. In this way, all data lines are driven The signals generated by the dynamic circuit can be substantially or almost the same, so interference noise can be reduced to improve wireless signal transmission performance.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings.

100:Display device

110:Display panel

120:Drive circuit

200:Waveform

CT1-CT3: During sub-pixel charging

D1, D2, D3, D4, D5, D6: data lines

DT1-DT3: Sub-pixel discharge period

DO1, DO2: data side

G1, G2, G3: Gate lines

GND: ground terminal

MUX3_1, MUX3_2: multiplexer

P11, P12, P13, P14, P15, P16, P21, P22, P23, P24, P25, P26, P31, P32, P33, P34, P35, P36: sub-pixels

PT: precharge period

RC1, RC2, RC3, RC4, RC5, RC6: impedance circuit

RE: Resistance element

SW, SW1, SW2, SW3: switching elements

SWB, SWB’, SWG, SWG’, SWR, SWR’: control signal

FIG. 1 is a schematic diagram of a display device according to an embodiment of the present invention.

FIG. 2 is a schematic waveform diagram of a signal according to the embodiment of FIG. 1 of the present invention.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or sections or parts thereof shall not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element", "first component", "first region", "first layer" or "first section" discussed below could be termed a "second element", "second component", "first section" "Second Area", "Second Layer" or "Second Section" or portion without departing from the teachings of this article.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the content clearly dictates otherwise, the singular forms "a", "an" and "the" are intended to include the plural forms including "at least One". "Or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will also be understood that when used in this specification, the terms "comprises" and/or "includes" designate the presence of stated features, regions, integers, steps, operations, elements and/or components but do not exclude one or more The presence or addition of other features, regions, steps, operations, elements, parts and/or combinations thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be construed to have meanings consistent with their meanings in the context of the relevant technology and the present invention, and are not to be construed as idealistic or excessive Formal meaning, unless expressly defined as such herein.

FIG. 1 is a schematic diagram of a display device according to an embodiment of the present invention. Referring to FIG. 1 , the display device 100 includes a display panel 110 , a plurality of multiplexers (eg, multiplexers MUX3_1 and MUX3_2 ), and a plurality of impedance circuits (eg, impedance circuits RC1 - RC6 ). The display panel 110 has a plurality of sub-pixels (such as sub-pixels P11-P16, P21-P26, P31-P36) arranged in an array, a plurality of data lines (such as data lines D1-D6) and a plurality of gate lines. (For example, gate lines G1-G3). Each of the plurality of sub-pixels (such as the sub-pixels P11-P16, P21-P26, P31-P36) is electrically connected to one and more of the plurality of data lines (such as the data lines D1-D6). One of the gate lines (for example, the gate lines G1-G3) is arranged at the intersection of the plurality of data lines and the plurality of gate lines. Moreover, each sub-pixel can be adjusted according to each gate drive signal. Turn on the corresponding transistor (such as a thin film transistor).

The multiplexers of this embodiment can be respectively disposed between a group of data lines among the multiple data lines and the corresponding data terminal, and each of the multiplexers generates data from the data during sub-pixel charging. The terminal receives the sub-pixel voltage and provides the sub-pixel voltage to a first data line in a group of data lines. For example, the multiplexer MUX3_1 is disposed between the data lines D1, D3, D5 and the data terminal DO1, and the multiplexer MUX3_1 receives the sub-pixel voltage from the data terminal DO1 and provides the sub-pixel voltage to the data line D1 ( Also called the first data line).

The plurality of impedance circuits in this embodiment can be respectively disposed between one of the plurality of data lines and the ground terminal, and some of the plurality of impedance circuits receive the ground voltage from the ground terminal during sub-pixel charging. A ground voltage is provided to at least one second data line in a set of data lines. For example, impedance circuits RC1, RC2, and RC3 are respectively set between data lines D1, D5, D3 and the ground terminal GND, and part of the impedance circuits RC1, RC2, and RC3 receive signals from the ground terminal GND. Ground voltage and provide ground voltage to data lines D3 and D5 (also known as the second data line).

It should be noted that in this embodiment, the data line provided with the sub-pixel voltage is called the first data line, and the data line provided with the ground voltage is called the second data line, and those with ordinary knowledge in the art can refer to The above examples deduce each situation.

In one embodiment, during the precharge period or the sub-pixel discharge period after the sub-pixel charging period, all impedance circuits in the plurality of impedance circuits receive the ground voltage from the ground terminal and provide the ground voltage to a group of data lines. All data lines. For example Say, all impedance circuits RC1, RC2, and RC3 receive ground voltage from the ground terminal GND and provide ground voltage to all data lines D1, D5, and D3.

In one embodiment, the display device 100 further includes a driving circuit 120 . The driving circuit 120 is coupled to the multiplexers MUX3_1, MUX3_2 and the impedance circuits RC1-RC6, and outputs control signals SWR, SWG, SWB, SWR', SWG', SWB' to control the multiplexers MUX3_1, MUX3_2 to provide sub-pixel voltages to Data lines D1, D4 (or data lines D5, D2 or data lines D3, D6) and control part of the impedance circuit to provide ground voltage to data lines D5, D3, D2, D6 (or data lines D1, D3, D4, D6 or data lines Lines D1, D5, D4, D2).

In FIG. 1 , the present invention takes as an example a display device in which two multiplexers MUX3_1 and MUX3_2 correspond to six sub-pixels P11-P16, P21-P26 or P31-P36 (ie, 2:6). It is worth mentioning that each pixel in the display panel includes three sub-pixels, namely R sub-pixel, G sub-pixel and B sub-pixel. That is to say, in the embodiment of the present invention, the sub-pixels P11, P14, P21, P24, P31, and P34 are R sub-pixels, and the sub-pixels P12, P15, P22, P25, P32, and P35 are G sub-pixels. , sub-pixels P13, P16, P23, P26, P33, and P36 are B sub-pixels.

The specific configuration of the display device 100 is as follows. The multiplexer MUX3_1 is arranged between the data terminal DO1 and the data lines D1, D3, and D5 (also called the first group of data lines). The multiplexer MUX3_2 is arranged between the data terminal DO2 and the data lines. Between D2, D4, and D6 (also known as the second set of data lines). Specifically, during sub-pixel charging, the multiplexer MUX3_1 receives the first sub-pixel voltage from the data terminal DO1 and provides the first sub-pixel voltage to the data line D1, D5 or D3 (also known as the first data line ), and multiplexer MUX3_2 Receive the second sub-pixel voltage from the data terminal DO2 and provide the second sub-pixel voltage to the data line D4, D2 or D6 (also called the first data line). Here, it is worth noting that the first set of data lines (ie, data lines D1, D3, and D5) and the second set of data lines (ie, data lines D2, D4, and D6) are arranged in a crosswise manner.

In an embodiment, the multiplexer MUX3_1 and the multiplexer MUX3_2 each include switching elements SW1-SW3. The switching element SW1 receives the control signal SWR, and is turned on or off according to the control signal SWR. The switching element SW2 receives the control signal SWG, and is turned on or off according to the control signal SWG. The switching element SW3 receives the control signal SWB, and It is turned on or off according to the control signal SWB.

In one embodiment, the impedance circuits RC1-RC6 each include a switching element SW and an impedance element RE. The switching element SW is disposed between one of the data lines D1-D6 and the impedance element RE. The impedance element RE is disposed between the switching element SW. and the ground terminal GND. The switching elements SW of the impedance circuits RC1 and RC4 receive the control signal SWR' and are turned on or off according to the control signal SWR'. The switching elements SW of the impedance circuits RC2 and RC5 receive the control signal SWG' and are turned on or off according to the control signal SWG'. is turned on or off, and the switching elements SW of the impedance circuits RC3 and RC6 receive the control signal SWB' and are turned on or off according to the control signal SWB'. Furthermore, the impedance element RE includes at least one of a diode, a resistor, and an inductor. In one embodiment, the resistance values RZ of the impedance elements RE in the impedance circuits RC1-RC6 are all the same.

In one embodiment, the display device 100 further includes a near-field wireless communication reader (not shown in the figure), and the near-field wireless communication reader is disposed below or on the side of the display device 100 .

FIG. 2 is a schematic waveform diagram of a signal according to the embodiment of FIG. 1 of the present invention. Details regarding the operation of display device 100. Please refer to FIGS. 1 and 2 simultaneously. The waveform 200 shows that the display time interval can be divided into a precharge period PT, a plurality of sub-pixel charging periods CT1-CT3, and a plurality of sub-pixel discharge periods DT1-DT3. In addition, in the embodiment of FIG. 2 , the multiplexers MUX3_1 and MUX3_2 can make the switching elements SW1, SW2, and SW3 mutually conductive with each other according to the control signals SWR, SWG, and SWB. The switching elements SW of the impedance circuits RC1-RC6 can make the switching elements SW according to the control signals. SWR', SWG', and SWB' cause the switching elements SW to conduct each other alternately.

Specifically, when the display device 100 operates in the precharge period PT before the sub-pixel charging period CT1, the control signals SWR, SWG, and SWB may be set to a disabled state (such as a low voltage level), and the control signals SWR', SWG', SWB' can be set to an enabled state (such as a high voltage level), so that the switching elements SW1, SW2, SW3 of the multiplexer MUX3_1 can be turned off and the impedance circuits RC1, RC2, RC3 The switching element SW can be turned on. In this case, the resistance between the data lines D1, D3, and D5 and the driving circuit 120 is equal to the sum of the resistance RZ of the impedance elements RE in the impedance circuits RC1, RC2, and RC3 (that is, 3RZ).

When the display device 100 operates in the sub-pixel charging period CT1, SWG, SWB, and SWR' may be set to a disabled state (such as a low voltage level), and the control signals SWR, SWG', and SWB' may be set to Enabled state (for example, a high voltage level), so that the switching elements SW2 and SW3 of the multiplexer MUX3_1 and the switching element SW of the impedance circuit RC1 can be turned off and the switching element SW1 and the switching element SW of the impedance circuit RC2 and RC3 can be turned on. In this case, data lines D1, D3, D5 The resistance to the driving circuit 120 is equal to the sum of the resistance RZ of the impedance elements RE in the impedance circuits RC2 and RC3 plus the resistance RIC of the driving circuit 120 (ie, 2RZ+RIC).

When the display device 100 operates in the sub-pixel discharge period DT1 after the sub-pixel charging period CT1, the control signals SWR, SWG, and SWB may be set to a disabled state (such as a low voltage level), and the control signal SWR' , SWG', SWB' can be set to the enabled state (such as a high voltage level), so that the switching elements SW1, SW2, SW3 of the multiplexer MUX3_1 can be turned off and the switching of the impedance circuits RC1, RC2, RC3 Element SW can be turned on. In this case, the resistance between the data lines D1, D3, and D5 and the driving circuit 120 is equal to the sum of the resistance RZ of the impedance elements RE in the impedance circuits RC1, RC2, and RC3 (that is, 3RZ).

When the display device 100 operates in the sub-pixel charging period CT2, SWR, SWB, and SWG' may be set to a disabled state (such as a low voltage level), and the control signals SWG, SWR', and SWB' may be set to Enabled state (for example, a high voltage level), so that the switching elements SW1 and SW3 of the multiplexer MUX3_1 and the switching element SW of the impedance circuit RC2 can be turned off and the switching element SW2 and the switching element SW of the impedance circuit RC1 and RC3 can be turned on. In this case, the resistance between the data lines D1, D3, D5 and the driving circuit 120 is equal to the sum of the resistance RZ of the impedance elements RE in the impedance circuits RC1 and RC3 plus the resistance RIC of the driving circuit 120 (i.e. 2RZ+RIC ).

When the display device 100 operates in the sub-pixel discharge period DT2 after the sub-pixel charging period CT2, the control signals SWR, SWG, and SWB may be set to a disabled state (such as a low voltage level), and the control signal SWR' , SWG', SWB' can be set to the enabled state (such as a high voltage level), so that the multiplexer MUX3_1 The switching elements SW1, SW2, and SW3 of the impedance circuits RC1, RC2, and RC3 can be turned off and the switching elements SW of the impedance circuits RC1, RC2, and RC3 can be turned on. In this case, the resistance between the data lines D1, D3, and D5 and the driving circuit 120 is equal to the sum of the resistance RZ of the impedance elements RE in the impedance circuits RC1, RC2, and RC3 (that is, 3RZ).

When the display device 100 operates in the sub-pixel charging period CT3, SWR, SWG, and SWB' may be set to a disabled state (such as a low voltage level), and the control signals SWB, SWR', and SWG' may be set to Enabled state (for example, a high voltage level), so that the switching elements SW1 and SW2 of the multiplexer MUX3_1 and the switching element SW of the impedance circuit RC3 can be turned off and the switching element SW3 and the switching element SW of the impedance circuit RC1 and RC2 can be turned on. In this case, the resistance between the data lines D1, D3, D5 and the driving circuit 120 is equal to the sum of the resistance RZ of the impedance elements RE in the impedance circuits RC1 and RC2 plus the resistance RIC of the driving circuit 120 (i.e. 2RZ+RIC ).

When the display device 100 operates in the sub-pixel discharge period DT3 after the sub-pixel charging period CT3, the control signals SWR, SWG, and SWB may be set to a disabled state (such as a low voltage level), and the control signal SWR' , SWG', SWB' can be set to the enabled state (such as a high voltage level), so that the switching elements SW1, SW2, SW3 of the multiplexer MUX3_1 can be turned off and the switching of the impedance circuits RC1, RC2, RC3 Element SW can be turned on. In this case, the resistance between the data lines D1, D3, and D5 and the driving circuit 120 is equal to the sum of the resistance RZ of the impedance elements RE in the impedance circuits RC1, RC2, and RC3 (that is, 3RZ).

In one embodiment, depending on the anti-noise capability of the driving circuit 120, the resistance RZ can be 80% to 120% of the resistance RIC, thereby improving the communication capability. implemented in a For example, the impedance element RE can be disposed inside a printed circuit board (PCB), flexible printed circuit (FPC), glass substrate (Glass substrate) or integrated circuit (IC). As long as it is electrically connected to the data line.

In the embodiment of FIG. 2 , the display device 100 continues to operate in the next display time interval, and the signals in the next display time interval are the same as those in the above display time interval, so no further details will be given here. It should be noted that in the embodiment of FIG. 2 , the operating relationship between the multiplexer MUX3_2 and the data lines D4, D2, D6 and the driving circuit 120 can be based on the above-mentioned relationship between the multiplexer MUX3_1 and the data lines D1, D1 and D6. The operation is performed based on the operational relationship between D5, D3 and the driving circuit 120, which will not be described in detail here.

According to the description of FIG. 2 , in the display device 100 of the present invention, during the pre-charging period, the sub-pixel charging period, or the sub-pixel discharging period after the sub-pixel charging period, the driving circuit 120 can control each switching element to be turned on. Or disconnected so that the signals generated by the data lines D1-D6 to the driving circuit 120 are substantially or almost the same, thereby effectively reducing noise and reducing abnormal situations in the display device with NFC function to improve communication capabilities.

To sum up, the display device according to the embodiment of the present invention is provided with a multiplexer between a group of data lines and the data terminal, an impedance circuit is provided between each data line and the ground terminal, and the sub-pixel is charged During this period, the sub-pixel voltage is provided from the data terminal to one of the data lines in the group of data lines through the multiplexer, and the ground voltage is provided to the other data lines in the group of data lines through the impedance circuit. In this way, the signals generated from each data line to the driving circuit can be substantially or almost the same, thus reducing interference noise. to improve wireless signal transmission performance.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.

100:Display device

110:Display panel

120:Drive circuit

D1, D2, D3, D4, D5, D6: data lines

DO1, DO2: data side

G1, G2, G3: Gate lines

GND: ground terminal

MUX3_1, MUX3_2: multiplexer

P11, P12, P13, P14, P15, P16, P21, P22, P23, P24, P25, P26, P31, P32, P33, P34, P35, P36: sub-pixels

RC1, RC2, RC3, RC4, RC5, RC6: impedance circuit

RE: Resistance element

SW, SW1, SW2, SW3: switching elements

SWB, SWB’, SWG, SWG’, SWR, SWR’: control signal

Claims (10)

A display device including: A display panel having a plurality of sub-pixels, a plurality of data lines and a plurality of gate lines arranged in an array, each of the plurality of sub-pixels being electrically connected to one of the plurality of data lines. and one of the plurality of gate lines; A plurality of multiplexers, each disposed between a group of data lines among the plurality of data lines and a data terminal, each of the multiplexers receiving data from the data during a sub-pixel charging period The terminal receives a sub-pixel voltage and provides the sub-pixel voltage to a first data line in the set of data lines; and A plurality of impedance circuits are each disposed between one of the plurality of data lines and a ground terminal. Some of the impedance circuits in the plurality of impedance circuits receive signals from the ground terminal during charging of the sub-pixel. A ground voltage is provided to at least a second data line in the set of data lines. The display device of claim 1, wherein during a precharge period or a sub-pixel discharge period after the sub-pixel charging period, all impedance circuits in the plurality of impedance circuits receive signals from the ground terminal. The ground voltage is provided to all data lines in the set of data lines. The display device as described in claim 1 further includes: A driving circuit coupled to the multiplexers and the impedance circuits for outputting a plurality of control signals to control the multiplexers to provide the sub-pixel voltages to the first data line and controls the partial impedance circuit to provide the ground voltage to the at least one second data line. The display device according to claim 1, wherein the multiplexers include: A first multiplexer is disposed between a first data terminal and a first group of data lines among the plurality of data lines, and is used to receive a first sub-pixel from the first data terminal during charging of the sub-pixel. pixel voltage and providing the first sub-pixel voltage to the first data line in the first set of data lines; and A second multiplexer is disposed between a second data terminal and a second group of data lines among the plurality of data lines, and is used to receive a second sub-pixel from the second data terminal during charging of the sub-pixel. pixel voltage and providing the second sub-pixel voltage to the first data line in the second set of data lines. The display device of claim 4, wherein the first multiplexer and the second multiplexer each include a first switching element, a second switching element and a third switching element, and the first switching element receives a first control signal, and is turned on or off according to the first control signal, the second switching element receives a second control signal, and is turned on or off according to the second control signal, and The third switching element receives a third control signal and is turned on or off according to the third control signal. The display device according to claim 4, wherein the first group of data lines and the second group of data lines are arranged crosswise. The display device of claim 1, wherein each of the plurality of impedance circuits includes a switching element and an impedance element, and the switching element is disposed between one of the plurality of data lines and the impedance element. , the impedance element is disposed between the switching element and the ground terminal, the switching element receives a control signal, and is turned on or off according to the control signal. The display device of claim 7, wherein the impedance element includes at least one of a diode, a resistor, and an inductor. The display device according to claim 7, wherein the resistance values of the impedance elements in the plurality of impedance circuits are all the same. The display device as described in claim 1 further includes: A short-range wireless communication reader is provided below or on the side of the display panel.

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