TWI824399B - Interdigitated varactor diode and manufacturing method thereof - Google Patents
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Abstract
一種指叉型變容二極體,包含一基板、一磊晶結構、一電極單元,及一介電單元。該磊晶結構設置於該基板上,包括一頂面、自該頂面依序向下的第一型摻雜磊晶積層、一第二型摻雜磊晶積層、多個自該頂面向下延伸而彼此間隔排列的凹槽,及多個藉由該等凹槽彼此間隔的凸部,且該第二型摻雜磊晶積層會自該等凹槽對外裸露。該電極單元包括多個設置於該等凹槽內的底電極,及多個設置於該等凸部的頂電極,該等頂、底電極分別與該磊晶結構成歐姆接觸,且以並聯的形式對外電連接。該介電單元披覆於該磊晶結構與該電極單元,且令該等頂電極的部分表面露出。An interdigital varactor diode includes a substrate, an epitaxial structure, an electrode unit, and a dielectric unit. The epitaxial structure is disposed on the substrate and includes a top surface, a first-type doped epitaxial layer sequentially downward from the top surface, a second-type doped epitaxial layer, and a plurality of first-type doped epitaxial layers sequentially downward from the top surface. Grooves are extended and spaced apart from each other, and a plurality of convex portions are spaced apart from each other by the grooves, and the second type doped epitaxial layer is exposed from the grooves. The electrode unit includes a plurality of bottom electrodes disposed in the grooves and a plurality of top electrodes disposed on the protrusions. The top and bottom electrodes respectively form ohmic contact with the epitaxial structure and are connected in parallel. form of external electrical connection. The dielectric unit covers the epitaxial structure and the electrode unit, and exposes part of the surface of the top electrodes.
Description
本發明是有關於一種變容二極體及其製作方法,特別是指一種具有指叉結構的變容二極體及其製作方法。The present invention relates to a varactor diode and a manufacturing method thereof, in particular to a varactor diode with an interdigitated structure and a manufacturing method thereof.
變容二極體元件主要是基於半導體之PN介面的電容可變原理(即在其PN介面施加一反向偏壓時,其電容值會隨著電壓的不同而產生變化)而成為頻射電路或調諧電路等電路設計中的常用元件,且被廣泛地應用於無線通訊、航太等領域。目前來說,該變容二極體元件大致包含一具有一平台(msea)結構的半導體磊晶層、一個設置於該平台結構上而與該半導體磊晶層的p型磊晶層連接的陽極,及一個環設於該平台結構,且與該半導體磊晶層的n型磊晶積層連接的陰極。The varactor diode element is mainly based on the variable capacitance principle of the PN interface of the semiconductor (that is, when a reverse bias voltage is applied to the PN interface, its capacitance value will change with different voltages) and becomes a frequency radio circuit. Or tuned circuits and other common components in circuit design, and are widely used in wireless communications, aerospace and other fields. Currently, the varactor element generally includes a semiconductor epitaxial layer with a platform (msea) structure, an anode disposed on the platform structure and connected to the p-type epitaxial layer of the semiconductor epitaxial layer. , and a cathode ring disposed on the platform structure and connected to the n-type epitaxial layer of the semiconductor epitaxial layer.
然而,該變容二極體元件本身的寄生電阻會於作動時造成損耗,並隨之產生電阻電容延遲(RC-Delay),而對整體電路設計造成影響。因此,如何降低該變容二極體元件的寄生電阻,並提升其Q值,為相關領域研究的重點。However, the parasitic resistance of the varactor element itself will cause losses during operation, and subsequently generate resistance-capacitance delay (RC-Delay), which will affect the overall circuit design. Therefore, how to reduce the parasitic resistance of the varactor element and improve its Q value has become the focus of research in related fields.
因此,本發明的目的,即在提供一種指叉型變容二極體,以降低整體寄生電阻,並提升Q值。Therefore, the purpose of the present invention is to provide an interdigitated varactor diode to reduce the overall parasitic resistance and improve the Q value.
於是,本發明指叉型變容二極體,包含一基板、一磊晶結構、一電極單元、一介電單元。Therefore, the interdigitated varactor diode of the present invention includes a substrate, an epitaxial structure, an electrode unit, and a dielectric unit.
該磊晶結構設置於該基板上,包括一反向於該基板的頂面、自該頂面依序向下的第一型摻雜磊晶積層、一第二型摻雜磊晶積層、多個自該頂面向下延伸而成長條狀,且沿同一方向彼此間隔排列的凹槽,及多個藉由該等凹槽彼此間隔,且成條狀的凸部,且該第二型摻雜磊晶積層會自該等凹槽對外裸露。The epitaxial structure is disposed on the substrate and includes a first-type doped epitaxial layer, a second-type doped epitaxial layer, and multiple A plurality of strip-shaped grooves extending downward from the top surface and spaced apart from each other along the same direction, and a plurality of strip-shaped convex portions spaced apart from each other by the grooves, and the second type doping The epitaxial layer will be exposed from the grooves.
該電極單元包括多個分別設置於該等凹槽內且成長條狀的底電極,及多個分別設置於該等凸部之頂面的頂電極,該等頂電極分別與該第一型摻雜磊晶積層成歐姆接觸,且以並聯方式對外電連接,該等底電極分別與該第二型摻雜磊晶積層成歐姆接觸,且以並聯的形式對外電連接。The electrode unit includes a plurality of strip-shaped bottom electrodes respectively disposed in the grooves, and a plurality of top electrodes respectively disposed on the top surfaces of the protrusions. The top electrodes are respectively connected with the first type doped The hybrid epitaxial layer forms an ohmic contact and is electrically connected to the outside in a parallel manner. The bottom electrodes respectively form an ohmic contact with the second type doped epitaxial layer and are electrically connected to the outside in a parallel manner.
該介電單元披覆於該磊晶結構與該電極單元,且該等頂電極及該等底電極可穿過該介電單元對外電連接。The dielectric unit covers the epitaxial structure and the electrode unit, and the top electrodes and the bottom electrodes can be electrically connected to the outside through the dielectric unit.
本發明的另一目的,即在提供一種指叉型變容二極體的製作方法。Another object of the present invention is to provide a method for manufacturing an interdigitated varactor diode.
於是,本發明指叉型變容二極體的製作方法,包含一提供步驟、一接觸墊形成步驟、一第一介電層形成步驟、一底電極設置步驟、一第二介電層形成步驟,及一頂電極設置步驟。Therefore, the manufacturing method of the interdigitated varactor diode of the present invention includes a providing step, a contact pad forming step, a first dielectric layer forming step, a bottom electrode setting step, and a second dielectric layer forming step. , and a top electrode setting step.
該提供步驟是提供一磊晶半成品,該磊晶半成品具有一基板,及一設置於該基板表面的磊晶積層,該磊晶積層具有自該基板表面依序向上的一第二型摻雜磊晶積層,及一第一型摻雜磊晶積層。The providing step is to provide an epitaxial semi-finished product. The epitaxial semi-finished product has a substrate and an epitaxial laminated layer disposed on the surface of the substrate. The epitaxial laminated layer has a second type doped epitaxial layer sequentially upward from the surface of the substrate. a crystal laminated layer, and a first type doped epitaxial laminated layer.
該接觸墊形成步驟是於該磊晶積層的預定位置形成多個以導電材料構成,且與該磊晶積層成歐姆接觸的接觸墊,並以蝕刻方式自該磊晶積層的頂面且對應該等接觸墊以外的區域向下蝕刻至令該第二型摻雜磊晶積層露出,形成多個沿同一方向彼此間隔排列且成長條狀的凹槽,及多個藉由該等凹槽彼此間隔排列且成長條狀的凸部,而得到一磊晶結構,及對應形成於該磊晶結構的該等凸部頂面的接觸墊,再分別於該等凹槽內形成多個由導電材料構成,且與該磊晶結構成歐姆接觸的接觸墊。The step of forming contact pads is to form a plurality of contact pads made of conductive material and in ohmic contact with the epitaxial layer at predetermined positions of the epitaxial layer, and etching from the top surface of the epitaxial layer corresponding to the The areas other than the contact pads are etched downward to expose the second-type doped epitaxial layer, forming a plurality of elongated grooves spaced apart from each other in the same direction, and a plurality of grooves spaced apart from each other. Arrange and grow strip-shaped protrusions to obtain an epitaxial structure, and corresponding contact pads formed on the top surfaces of the protrusions of the epitaxial structure, and then form a plurality of conductive materials in the grooves. , and form a contact pad in ohmic contact with the epitaxial structure.
該第一介電層形成步驟是以介電絕緣材料形成一覆蓋於該磊晶結構與該等接觸墊的第一介電層。The first dielectric layer forming step is to use a dielectric insulating material to form a first dielectric layer covering the epitaxial structure and the contact pads.
該底電極設置步驟是於該第一介電層形成多個令位於該等凹槽中的接觸墊的表面露出的第一開口,並透過該等第一開口分別於該等凹槽內之接觸墊露出的表面上設置多個以導電材料構成的底電極部,而形成多個分別位於該等凹槽內,且由相應的該接觸墊與該底電極部共同定義而成的底電極。The bottom electrode setting step is to form a plurality of first openings in the first dielectric layer to expose the surfaces of the contact pads located in the grooves, and to make contacts in the grooves through the first openings. A plurality of bottom electrode portions made of conductive material are provided on the exposed surface of the pad to form a plurality of bottom electrodes respectively located in the grooves and defined by the corresponding contact pads and the bottom electrode portion.
該第二介電層形成步驟是以介電絕緣材料形成一覆蓋於該第一介電層、該等底電極,及位於該等凸部的接觸墊的第二介電層。The second dielectric layer forming step is to use a dielectric insulating material to form a second dielectric layer covering the first dielectric layer, the bottom electrodes, and the contact pads located on the protrusions.
該頂電極設置步驟是形成多個貫穿該第二介電層及該第一介電層以令位於該等凸部的接觸墊的表面露出的第二開口,並自裸露的該等接觸墊上形成多個頂電極部,而令該等頂電極部分別與相應的接觸墊共同定義成多個供對外電連接的頂電極。The top electrode disposing step is to form a plurality of second openings penetrating the second dielectric layer and the first dielectric layer to expose the surfaces of the contact pads located on the protrusions, and forming from the exposed contact pads. A plurality of top electrode portions are defined together with corresponding contact pads to form a plurality of top electrodes for external electrical connection.
本發明的功效在於:本發明指叉型變容二極體透過使該磊結結構以及設置其上的該電極單元成彼此交替排列的結構,而能經由並聯的形式來降低陽極(即該等頂電極)的整體電阻,進而降低該指叉型變容二極體整體的陽極寄生電阻,減緩在運作時電阻電容延遲所帶來的影響,並提升整體的Q值。The effect of the present invention is that the interdigitated varactor diode of the present invention can reduce the anode (i.e., the The overall resistance of the top electrode), thereby reducing the overall anode parasitic resistance of the interdigitated varactor diode, slowing down the impact of resistor-capacitance delay during operation, and improving the overall Q value.
在本發明被詳細描述前,應當注意在以下的說明內容中,類似的元件是以相同的編號來表示。且有關本發明之相關技術內容、特點與功效,在以下配合參考圖式之實施例的詳細說明中,將可清楚的呈現。此外,要說明的是,本發明圖式僅為表示元件間的結構及/或位置相對關係,與各元件的實際尺寸並不相關。Before the present invention is described in detail, it should be noted that in the following description, similar elements are designated with the same numbering. The relevant technical contents, features and effects of the present invention will be clearly presented in the following detailed description of the embodiments with reference to the drawings. In addition, it should be noted that the drawings of the present invention only represent the relative structure and/or positional relationship between components, and are not related to the actual size of each component.
配合參閱圖1與圖2,本發明指叉型變容二極體,包含一基板2、一磊晶結構3、一電極單元4,及一介電單元5。其中,圖1顯示該指叉型變容二極體的俯視結構,圖2則為沿圖1中II-II割面線的剖視結構。1 and 2 together, the interdigitated varactor diode of the present invention includes a
該磊晶結構3設置於該基板2上,包括一反向於該基板2的頂面31、自該頂面31依序向下的第一型摻雜磊晶積層32、一第二型摻雜磊晶積層33、多個自該頂面31向下延伸至該第二型摻雜磊晶積層33並沿一第一方向X而成長條狀,且沿一與該第一方向X相交的第二方向Y彼此間隔排列的凹槽34,及多個藉由該等凹槽34彼此間隔且成條狀的凸部35。在本實施例中,該第二型摻雜磊晶積層33為n型磊晶積層,該第一型摻雜磊晶積層32為p型磊晶層,因此該等凹槽34是自該p型磊晶層表面向下延伸至使該n型磊晶積層對外露出。The
該電極單元4由導電材料構成,包括多個底電極41,及多個頂電極42。在本實施例中,是以該等底電極41為陰極,該等頂電極42為陽極為例,但並不以此為限。The electrode unit 4 is made of conductive material and includes a plurality of
詳細的說,該等底電極41分別設置於該等凹槽34內沿該第一方向X延伸成長條狀,並與相鄰的該等凸部35成一距離間隔,且每一個底電極41具有一與該第二型摻雜磊晶積層33(即該n型磊晶積層)成歐姆接觸的接觸墊411,及一形成於該接觸墊411頂面用以對外電連接的底電極部412,且該等底電極41以並聯的形式對外電連接。In detail, the
該等頂電極42分別設置於該等凸部35上並沿該第一方向X延伸成長條狀,且每一個頂電極42具有一與該第一型摻雜磊晶積層32(即該p型磊晶層)成歐姆接觸的接觸墊421,及一形成於該接觸墊421頂面用以對外電連接的頂電極部422,且該等頂電極42會以並聯方式對外電連接。要說明的是,在本實施例中,分別與該n型磊晶積層、p型磊晶層成歐姆接觸的接觸墊411、421是由不同的導電材料所構成。由於與不同半導體材料形成歐姆接觸的相關導電材料的選擇為本技術領域者所周知且非為本發明之重點,因此不再多加贅述。The
要說明的是,該等底、頂電極41、42各自延伸成長條指叉狀並彼此交錯,且該等底、頂電極41、42的一側可分別利用排線或導線(圖未示)彼此並聯連接以令該等底、頂電極41、42能以並聯的形式對外電連接,然實際實施時,只要可令該等底、頂電極41、42能以並聯的形式對外電連接即可,但並不以前述之舉例為限。It should be noted that the bottom and
該介電單元5披覆於該磊晶結構3與該電極單元4,且可令該等底電極41及該等頂電極42的部分表面露出。詳細的說,該介電單元5包括一第一介電層51,及一第二介電層52。該第一介電層51可選自氮化物、氧化物或氮氧化物等介電絕緣材料,披覆於該磊晶結構3與該電極單元4,且令每一個底電極41的部分表面經由相應的一第一開口511露出而可對外電連接。該第二介電層52由與該第一介電層51相同或不同的介電絕緣材料構成,披覆於該第一介電層51、該等底電極41及該等頂電極42,且該等頂電極42可藉由多個貫穿該第一介電層51及該第二介電層52的第二開口521對外電連接。透過該介電單元5的設置可令該等頂電極42及該等底電極41之間保持電性絕緣,並可降低運作時彼此間的串擾影響。The
相較於習知的變容二極體僅具有一個設置於平台(mesa)結構上且與p型磊晶層連接的陽極,及一個環設於該陽極且與該n型磊晶積層連接的陰極,本發明指叉型變容二極體透過令該電極單元4的底、頂電極41、42彼此交替排列成指叉型結構,而能藉由維持該等底、頂電極41、42的總面積以保持既有的P-N結電容特性,同時經由並聯的形式連接該等頂電極42(陽極)來降低陽極的整體電阻,而可降低該指叉型變容二極體整體的陽極寄生電阻,減緩在運作時電阻電容延遲(RC Delay)所帶來的影響,並提升整體的Q值,降低電路損耗。Compared with the conventional varactor diode, it only has an anode arranged on a mesa structure and connected to the p-type epitaxial layer, and a ring arranged on the anode and connected to the n-type epitaxial layer. Cathode, the interdigitated varactor diode of the present invention can maintain the interdigitated structure by arranging the bottom and
配合參閱圖3,在另一實施態樣中,該電極單元4還包括一成平板狀且與該等頂電極42連接的共用電極43,使該等頂電極42可透過該共用電極43以並聯的形式對外電連接。其中,該共用電極43可選自厚度介於2μm至4μm的鈦金合金,或是厚度介於2μm至15μm的金屬銅。Referring to FIG. 3 , in another embodiment, the electrode unit 4 further includes a flat-shaped common electrode 43 connected to the
要說明的是,當該等頂電極42是透過該共用電極43對外電連接時,該指叉型變容二極體還包含一絕緣支撐層6。該絕緣支撐層6會填滿該等凹槽34,並延伸至覆蓋並等凸部35的部份表面而令該絕緣支撐層6的頂面可實質與該等頂電極42具有相同高度,而可提供一較為平坦的表面以支撐該共用電極43。It should be noted that when the
本發明指叉型變容二極體利用該共用電極43以並聯形式連接該等頂電極42,能進一步降低該指叉型變容二極體的接面電阻,以進一步降低電路損耗,並提升Q值,還能提升陽極(即該共用電極43與該等頂電極42)的厚度,而有助於散熱,以改善熱效應所帶來的影響。The interdigitated varactor diode of the present invention uses the common electrode 43 to connect the
配合參閱圖4,茲將就以下說明前述該指叉型變容二極體的製作方法。該製作方法包含一提供步驟81、一接觸墊形成步驟82、一第一介電層形成步驟83、一底電極設置步驟84、一第二介電層形成步驟85、一絕緣支撐層形成步驟86,及一頂電極設置步驟87。With reference to Figure 4, the manufacturing method of the aforementioned interdigitated varactor diode will be described below. The manufacturing method includes a providing step 81, a contact pad forming step 82, a first dielectric layer forming step 83, a bottom electrode setting step 84, a second dielectric layer forming step 85, and an insulating support layer forming step 86. , and a top electrode setting step 87.
該提供步驟81是提供一磊晶半成品(圖未示),該磊晶半成品具有該基板2,及一設置於該基板2表面的磊晶積層,且該磊晶積層具有自該基板2表面依序向上的一第二型摻雜磊晶積層33(即n型磊晶積層),及一第一型摻雜磊晶積層32(即p型磊晶層)。The providing step 81 is to provide an epitaxial semi-finished product (not shown). The epitaxial semi-finished product has the
該接觸墊形成步驟82是分別於是於該磊晶積層的預定位置形成多個以導電材料構成,且與該磊晶積層成歐姆接觸的接觸墊421,之後,以蝕刻方式自該磊晶積層的頂面且對應該等接觸墊421以外的區域向下蝕刻至令該第二型摻雜磊晶積層33露出,形成沿該第二方向Y彼此間隔排列且沿該第一方向X延伸成長條狀的該等凹槽34,以及藉由該等凹槽34彼此間隔排列且成長條狀的該等凸部35,而得到該磊晶結構3,及多個對應形成於該磊晶結構3的凸部35頂面的接觸墊421,接著,分別於該等凹槽34底面形成多個由導電材料構成,且與該磊晶結構3成歐姆接觸的接觸墊411,亦即該等凹槽34是自該p型磊晶層表面(即該磊晶結構3的頂面31)向下延伸至使該n型磊晶積層對外露出,且該等接觸墊421分別位於該等凸部35上,而與該p型磊晶層成歐姆接觸,位於該等凹槽34內的接觸墊411則與該n型磊晶積層成歐姆接觸。由於令導電材料與半導體材料之間形成歐姆接觸的製程方法與材料選擇為本技術領域者所周知,且非為本發明之重點,因此不再多加贅述。在本實施例中,該等凹槽34的至少其中一側會彼此連通。The contact pad forming step 82 is to form a plurality of
該第一介電層形成步驟83是將介電絕緣材料以沉積方式形成覆蓋於該磊晶結構3與該等接觸墊411、421的該第一介電層51。The first dielectric layer forming step 83 is to deposit a dielectric insulating material to form the
該底電極設置步驟84是利用蝕刻方式於該第一介電層51上形成多個令位於該等凹槽34中的接觸墊411的表面露出的第一開口511,並透過該等第一開口511分別於該等凹槽34內之接觸墊411露出的表面上以沉積方式形成多個以導電材料構成的底電極部412,使該等底電極部412分別與相應的接觸墊411共同定義而得到該等底電極41。The bottom electrode setting step 84 is to use etching to form a plurality of
該第二介電層形成步驟85是將介電絕緣材料以沉積方式形成全面覆蓋於該第一介電層51、該等底電極41,及位於該等凸部35上之接觸墊421的該第二介電層52。The second dielectric layer forming step 85 is to deposit a dielectric insulating material to completely cover the
該絕緣支撐層形成步驟86是以高分子材料形成填滿該等凹槽34並覆蓋於該第二介電層52,而形成具有平坦頂面的該絕緣支撐層6。The insulating support layer forming step 86 is to fill the
該頂電極設置步驟87是自該絕緣支撐層6的頂面對應該等凸部35的位置向下形成多個至令相應的接觸墊421對外露出的第二開口521,再分別自該等第二開口521沉積形成與該等接觸墊421電連接的多個頂電極部422,令該等頂電極部422分別與相應的接觸墊421共同定義成供對外電連接的該等頂電極42,之後,再以導電材料沉積形成覆蓋該絕緣支撐層6表面,並與該等頂電極部422電連接的該共用電極43,即可得到如圖3所示的該指叉型變容二極體。The top electrode setting step 87 is to form a plurality of
此外,要說明的是,當該指叉型變容二極體是如圖2所示未設置有該共用電極43時,則該頂電極設置步驟87是直接自該第二介電層52的頂面且對應該等凸部35的位置向下形成令相應的接觸墊421對外露出的該等第二開口521,之後,再分別自該等第二開口521沉積形成與該等接觸墊421電連接的多個頂電極部422,形成該等頂電極42,即可得到該如圖2所示的指叉型變容二極體。In addition, it should be noted that when the interdigital varactor diode is not provided with the common electrode 43 as shown in FIG. 2 , the top electrode setting step 87 is directly performed from the
要說明的是,在一些實施例中,也可以視製程需求,在執行該底電極設置步驟84時,同時於該第一介電層51對應該等凸部35的位置向下形成多個至令相應的接觸墊421對外露出的開口,並在形成該等底電極部412的同時,以導電材料形成該等頂電極部422,以製得該等底、頂電極41、42,之後,再執行該第二介電層形成步驟85,形成覆蓋該等底、頂電極41、42上的第二介電層52,並依序形成該絕緣支撐層6、該等第二開口521,及該共用電極43,而不以前述之製程順序為限制。It should be noted that in some embodiments, depending on the process requirements, when performing the bottom electrode setting step 84 , a plurality of ? The openings of the
綜上所述,本發明指叉型變容二極體透過使該磊結結構3以及設置其上的該電極單元4成彼此交替排列(例如指叉型)的結構,而能經由並聯的形式來降低陽極的整體電阻,進而降低該指叉型變容二極體整體的陽極寄生電阻,減緩在運作時因電阻電容延遲所帶來的影響,並提升整體的Q值。此外,藉由配置該共用電極43還能進一步降低該指叉型變容二極體的接面電阻,以降低電路損耗,並提升Q值,還能提升陽極(即該共用電極43與該等頂電極42)的厚度,而有助於散熱,並改善熱效應所帶來的影響,故確實能達成本發明的目的。To sum up, the interdigitated varactor diode of the present invention can be connected in parallel by arranging the
惟以上所述者,僅為本發明的實施例而已,當不能以此限定本發明實施的範圍,凡是依本發明申請專利範圍及專利說明書內容所作的簡單的等效變化與修飾,皆仍屬本發明專利涵蓋的範圍內。However, the above are only examples of the present invention and should not be used to limit the scope of the present invention. All simple equivalent changes and modifications made based on the patent scope of the present invention and the content of the patent specification are still within the scope of the present invention. within the scope covered by the patent of this invention.
2:基板 3:磊晶結構 31:頂面 32:第一型摻雜磊晶積層 33:第二型摻雜磊晶積層 34:凹槽 35:凸部 4:電極單元 41:底電極 411:接觸墊 412:底電極部 42:頂電極 421:接觸墊 422:頂電極部 43:共用電極 5:介電單元 51:第一介電層 511:第一開口 52:第二介電層 521:第二開口 6:絕緣支撐層 81:提供步驟 82:接觸墊形成步驟 83:第一介電層形成步驟 84:底電極設置步驟 85:第二介電層形成步驟 86:絕緣支撐層形成步驟 87:頂電極設置步驟 X:第一方向 Y:第二方向2: Substrate 3: Epitaxial structure 31: Top surface 32: First type doped epitaxial layer 33: Second type doped epitaxial layer 34: Groove 35: Projection 4: Electrode unit 41: Bottom electrode 411: Contact pad 412: bottom electrode part 42: top electrode 421: contact pad 422: top electrode part 43: common electrode 5: dielectric unit 51: first dielectric layer 511: first opening 52: second dielectric layer 521: Second opening 6: Insulating support layer 81: Providing step 82: Contact pad forming step 83: First dielectric layer forming step 84: Bottom electrode setting step 85: Second dielectric layer forming step 86: Insulating support layer forming step 87 : Top electrode setting steps X: First direction Y: Second direction
本發明的其他的特徵及功效,將於參照圖式的實施方式中清楚地呈現,其中: 圖1是一俯視示意圖,說明本發明指叉型變容二極體的一磊晶結構,及一電極單元的相對位置; 圖2是一側視示意圖,說明該指叉型變容二極體對應於圖1之II-II割面線處的剖視結構; 圖3是一側視示意圖,說明該指叉型變容二極體的另一結構態樣;及 圖4是一流程圖,說明本發明指叉型變容二極體的製作方法。Other features and effects of the present invention will be clearly presented in the embodiments with reference to the drawings, in which: Figure 1 is a top view schematic diagram illustrating an epitaxial structure of the interdigitated varactor diode of the present invention, and an The relative position of the electrode unit; Figure 2 is a schematic side view, illustrating the cross-sectional structure of the interdigitated varactor diode corresponding to the II-II cut plane line in Figure 1; Figure 3 is a schematic side view, illustrating Another structural aspect of the interdigitated varactor diode; and FIG. 4 is a flow chart illustrating the manufacturing method of the interdigitated varactor diode of the present invention.
34:凹槽 34: Groove
35:凸部 35:convex part
4:電極單元 4:Electrode unit
41:底電極 41: Bottom electrode
42:頂電極 42:Top electrode
5:介電單元 5: Dielectric unit
X:第一方向 X: first direction
Y:第二方向 Y: second direction
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|---|---|---|---|---|
| US20120139020A1 (en) * | 2010-01-08 | 2012-06-07 | Semiconductor Manufacturing International (Shanghai) Corporation | Method and structure for high q varactor |
| TW201904013A (en) * | 2017-02-28 | 2019-01-16 | 穩懋半導體股份有限公司 | Integrated structures of acoustic wave device and varactor, and acoustic wave device, varactor and power amplifier, and fabrication methods thereof |
| US20200105747A1 (en) * | 2018-09-28 | 2020-04-02 | Intel Corporation | Finfet varactor quality factor improvement |
| US20210020790A1 (en) * | 2019-07-15 | 2021-01-21 | Qualcomm Incorporated | Integration of vertical gan varactor with hemt |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120139020A1 (en) * | 2010-01-08 | 2012-06-07 | Semiconductor Manufacturing International (Shanghai) Corporation | Method and structure for high q varactor |
| TW201904013A (en) * | 2017-02-28 | 2019-01-16 | 穩懋半導體股份有限公司 | Integrated structures of acoustic wave device and varactor, and acoustic wave device, varactor and power amplifier, and fabrication methods thereof |
| US20200105747A1 (en) * | 2018-09-28 | 2020-04-02 | Intel Corporation | Finfet varactor quality factor improvement |
| US20210020790A1 (en) * | 2019-07-15 | 2021-01-21 | Qualcomm Incorporated | Integration of vertical gan varactor with hemt |
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