TWI822561B - Device to improve current limiting response speed and waveform - Google Patents

Abstract

In a device for improving current limiting response speed and waveform, a signal processing module is configured to receive an output signal generated by an inverter and output a first signal to a first current limiting unit and a second signal to a second limiting unit. Current unit; when the output signal is a positive half cycle, the first current limiting unit generates a first current limiting signal to the output port, and the signal processing module turns on a second switch connected in parallel with the second current limiting unit. The unit releases the remaining power of the second current limiting unit; when the output signal is a negative half cycle, the second current limiting unit generates a second current limiting signal to the output port, the signal processing module is turned on and the first A first switch unit connected in parallel with the current limiting unit releases the residual power of the first current limiting unit; the present invention can prevent the generated first current limiting signal and the second current limiting signal from having surges.

Description

Device to improve current limiting response speed and waveform

A current limiting device, especially a device that improves the current limiting response speed and waveform.

For a power supply, when it outputs an AC power supply that provides a fixed current amount to an electrical appliance, the power supply needs to use a current flow limiting function. While the power supply limits the current flow, the power supply also needs to respond to the speed and waveform of the current limit. In other words, the power supply will hope to perform the current limiting function while maintaining the original input waveform, and how quickly and accurately the power supply can maintain the original waveform when limiting the current refers to the power supply's A current-limiting response quality. In the most ideal situation, the power supply can respond to the waveform quickly enough while limiting current, so as not to lose the subtle characteristics of the original waveform, but respond quickly without generating surges and distortion. A current limiting circuit of a conventional power supply is responsible for performing the aforementioned functions of limiting current flow and responding to waveforms. However, the conventional current limiting circuit cannot avoid the generation of surges during current limiting during response.

Please refer to Figure 9. The voltage unit on the vertical axis of Figure 9 is volt (Volt; V), and the time unit on the horizontal axis is millisecond (millisecond; ms). When the conventional current limiting circuit needs to output a voltage waveform 1' of 50 Hertz (Hz), a surge occurs at the peak of the rising edge and the falling edge of the voltage waveform 1'. trough value. A current waveform corresponding to the voltage waveform is proportional to the voltage waveform, so it will not be shown again here. The generation of these surges is not the original waveform characteristics that should be there, and these surges negatively affect the quality of the current-limiting output signal. The main reason for generating these surges is that when the conventional current limiting circuit responds quickly to changes in the waveform of the signal, the waveform changes from a low negative value to a high positive value in one unit of time. Distortion caused by the excessive change from a high positive value to a low negative value.

Please refer to Figure 10. When the conventional current limiting circuit needs to output the voltage waveform 1' of 100 Hz, this surge problem also exists. It also exists at the peak of the positive edge of the waveform and the valley of the negative edge of the waveform.

Please refer to Figure 11. The time unit on the horizontal axis of Figure 11 is microsecond (μs). When the conventional current limiting circuit needs to output the voltage waveform 1' of 500Hz, not only the problem of surge also exists, but more precisely, the overall distortion of the two waveforms of the response is the same as that of the 100Hz shown in Figure 10 and the 100Hz shown in Figure 9 The voltage waveform 1' showing 50Hz is different from the two. Therefore, in addition to generating surges and distortion during the current limiting response, another problem with conventional current limiting circuits is that the frequency domain width of the current limiting response is limited. For example, with the same original waveform, the waveform of the current limiting response at 50 Hz can maintain a rough waveform. Characteristics, but the waveform of the current limit response at 500Hz is greatly distorted.

The present invention provides a device for improving the current limiting response speed and waveform, which can avoid the generation of surges during the current limiting response, and can have a wider frequency domain width of the current limiting response than conventional current limiting circuits.

The device for improving current limiting response speed and waveform of the present invention is powered by an inverter output terminal connected to an inverter to receive an output signal generated by the inverter, and includes: a signal processing module having a A signal input terminal, a first signal output terminal, a second signal output terminal and a control signal output terminal; wherein, the signal input terminal is electrically connected to the inverter output terminal to receive the output signal; wherein, the signal processing The module generates a first signal, a second signal and a control signal according to the output signal, and outputs the first signal through the first signal output terminal, and outputs the second signal through the second signal output terminal, and The control signal is output through the control signal output terminal; wherein the phase difference between the first signal and the second signal is 180 degrees; an output port; A first current limiting unit has a first current limiting input terminal and a first current limiting output terminal; wherein the first current limiting input terminal is electrically connected to the first signal output terminal of the signal processing module to receive The first signal, and the first current limiting output terminal is electrically connected to the output port; a first switch unit is connected in parallel to the first current limiting unit and is electrically connected to the control signal output terminal of the signal processing module to receive the control signal; a second current limiting unit having a second current limiting input terminal and a second current limiting output terminal; wherein the second current limiting input terminal is electrically connected to the second signal output of the signal processing module terminal to receive the second signal, and the second current limiting output terminal is electrically connected to the output port; a second switch unit is connected in parallel to the second current limiting unit and is electrically connected to the control signal output of the signal processing module terminal to receive the control signal; wherein, when the output signal is a positive half cycle, the first current limiting unit generates a first current limiting signal to the output port according to the first signal, and the signal processing module The first switch unit is controlled to be non-conductive according to the control signal, and the signal processing module controls the second switch unit to be conductive according to the control signal; wherein, when the output signal is a negative half cycle, the second current limiting unit is controlled according to The second signal generates a second current limiting signal to the output port, and the signal processing module controls the first switch unit to be turned on based on the control signal. The signal processing module controls the second switch unit to be turned on based on the control signal. conduction.

When the output signal is in the positive half cycle, when the first current limiting unit outputs the first current limiting signal to the output port, the second current limiting unit does not output a signal. Furthermore, due to the conduction of the second switch unit, the second current limiting unit can release residual power to return the potential of the second current limiting unit to zero volt (Volt; V). In this way, when the output signal changes to the negative half cycle and the second current limiting unit outputs the second current limiting signal to the output port, the second current limiting signal can directly start changing from the potential of zero volts without the need for Changing from a high positive value to a low negative value can avoid distortion caused by excessive numerical changes, thereby avoiding the generation of surges.

In contrast, when the output signal is in the negative half cycle, the first current limiting unit does not output the first current limiting signal, and due to the conduction of the first switching unit, the first current limiting unit can release the remaining power to enable The potential of the first current limiting unit returns to zero volts. In this way, when the output signal changes to the positive half cycle and the first current limiting unit starts to output the first current limiting signal, the first current limiting signal can directly start changing from the potential of zero volts without going negative from the low level. The value is changed to a high positive value to avoid the generation of surges and improve the signal quality of the current limit response.

Moreover, because the present invention can improve the signal quality of the current limiting response, the present invention can also have a wider frequency domain width of the current limiting response. Compared with the prior art, the present invention can retain the current limiting response waveform of the high-frequency original signal.

1: Device to improve current limiting response speed and waveform

2:Inverter

2A: First inverter

2B: Second inverter

3: Inverter output terminal

10: The first current limiting unit

11: The first current limiting input terminal

12: The first current limiting output terminal

20: Second current limiting unit

21: Second current limiting input terminal

22: Second current limiting output terminal

30: First switch unit

40: Second switch unit

50:Signal processing module

51: First signal output terminal

52: Second signal output terminal

53: Signal input terminal

54: Control signal output terminal

55: First inversion unit

56:Second inversion unit

57: Processing unit

58: The first accurate output terminal

59: Second level output terminal

60:Output port

70:Inverter control module

551: First input terminal 551

552: First output terminal

561: Second input terminal

562: Second output terminal

BJT1: The first bipolar transistor

BJT2: The second bipolar transistor

D1: The first current limiting diode

D2: Second current limiting diode

GND: ground

OP1: First inversion operator

OP2: Second inversion operator

OP3: First inverting closed loop amplifier

OP4: Second inverting closed loop amplifier

C ₁₁ : first series capacitor

C ₁₂ : first parallel capacitor

C ₂₁ : Second series capacitor

C ₂₂ : Second parallel capacitor

R ₀ : Original input resistance

R ₁ : first input resistance

R ₂ : second input resistance

R ₃ : first calculation resistance

R ₄ : Second input resistance

R ₅ : Second calculation resistance

R ₁₀ : first voltage dividing resistor

R ₁₁ : first current limiting output resistor

R ₂₀ : second voltage dividing resistor

R ₂₁ : Second current limiting output resistor

R ₃₀ : first switch resistance

R ₄₀ : second switch resistance

1’: Voltage waveform

Figure 1 is a block diagram of a device for improving current limiting response speed and waveform according to the present invention.

FIG. 2 is a circuit diagram of an embodiment of the device for improving current limiting response speed and waveform according to the present invention.

FIG. 3 is a circuit diagram of a device for improving current limiting response speed and waveform according to one embodiment of the present invention.

Figure 4 is a signal diagram of the current limiting response signal generated at 50 Hz by the device for improving the current limiting response speed and waveform of the present invention.

FIG. 5 is a signal diagram of the current limiting response signal generated at 100 Hz by the device for improving the current limiting response speed and waveform of the present invention.

FIG. 6 is a signal diagram of a current limiting response signal generated at 500 Hz by the device for improving current limiting response speed and waveform of the present invention.

FIG. 7 is a signal diagram of a current limiting response signal generated at 1000 Hz by the device for improving the current limiting response speed and waveform of the present invention.

FIG. 8 is a signal diagram of a current limiting response signal generated at 2000 Hz by the device for improving the current limiting response speed and waveform of the present invention.

FIG. 9 is a signal diagram of a current limiting response signal generated by a conventional current limiting circuit at 50 Hz.

FIG. 10 is a signal diagram of a current limiting response signal generated by a conventional current limiting circuit at 100 Hz.

FIG. 11 is a signal diagram of a current limiting response signal generated by a conventional current limiting circuit at 500 Hz.

Referring to FIG. 1 , the present invention provides a device 1 for improving current limiting response speed and waveform. The device 1 for improving current limiting response speed and waveform is connected to an inverter output terminal 3 of an inverter 2 for receiving an output signal generated by the inverter 2 . The output signal output from the inverter output terminal 3 to the device 1 for improving current limiting response speed and waveform of the present invention is a periodic signal, but the waveform of the output signal is not limited. In an embodiment of the present invention, the output signal is a sinusoidal wave.

The device 1 for improving current limiting response speed and waveform of the present invention includes a first current limiting unit 10, a second current limiting unit 20, a first switching unit 30, a second switching unit 40, and a signal processing module. 50 and one output port 60.

The signal processing module 50 has a first signal output terminal 51 , a second signal output terminal 52 , a signal input terminal 53 and a control signal output terminal 54 . The signal input terminal 53 is electrically connected to the inverter output terminal 3 to receive the output signal. The signal processing module 50 generates a first signal, a second signal and a control signal according to the output signal, and the signal processing module 50 outputs the first signal through the first signal output terminal 51 and through the third The two signal output terminals 52 output the second signal, and the control signal output terminal 54 outputs the control signal. The first signal and the second signal have a phase difference of 180 degrees.

The first current limiting unit 10 has a first current limiting input terminal 11 and a first current limiting output terminal 12 . The first current limiting input terminal 11 is electrically connected to the first signal output terminal 51 of the signal processing module 50 to receive the first signal, and the first current limiting output terminal 12 is electrically connected to the output port 60 . In addition, the second current limit The unit 20 has a second current limiting input terminal 21 and a second current limiting output terminal 22 . The second current limiting input terminal 21 is electrically connected to the second signal output terminal 52 of the signal processing module 50 to receive the second signal, and the second current limiting output terminal 22 is also electrically connected to the output port 60 .

The first switch unit 30 is connected in parallel with the first current limiting unit 10 , the second switch unit 40 is connected in parallel with the second current limiting unit 20 , and the first switch unit 30 and the second switch unit 40 are electrically connected to the signal processing unit respectively. The control signal output terminal 54 of the module 50 receives the control signal.

When the output signal is a positive half cycle, the first current limiting unit 10 generates a first current limiting signal to the output port 60 according to the first signal, and the signal processing module 50 controls the first current limiting signal according to the control signal. One switch unit 30 is not conductive, and the second switch unit 40 is controlled to be conductive. At the same time, the second current limiting unit 20 does not output a signal. The turned-on second switch unit 40 allows the second current limiting unit 20 that does not output a signal to release any residual power, causing the potential of the second current limiting unit 20 to return to zero volt (Volt; V).

When the output signal is a negative half cycle, the second current limiting unit 20 generates a second current limiting signal to the output port 60 according to the second signal, and the signal processing module 50 controls the output port 60 according to the control signal. The first switch unit 30 is turned on, and the second switch unit 40 is controlled not to be turned on. At the same time, the first current limiting unit 10 does not output a signal. The turned-on first switch unit 30 allows the first current limiting unit 10 that does not output a signal to release any residual power, causing the potential of the first current limiting unit 10 to return to zero volts.

In this way, when the output signal changes from the positive half cycle to the negative half cycle and the second current limiting unit 20 starts to output the second current limiting signal to the output port 60, the second current limiting signal can directly change from zero to zero. The potential of the volt begins to change without changing from a high positive value to a low negative value. This avoids distortion caused by excessive numerical changes and avoids the generation of surges. When the output signal changes from the negative half cycle to the positive half cycle and the first current limiting unit 10 starts to output the first current limiting signal to the output port 60, the first current limiting signal can also directly change from zero volts. The potential begins to change without changing from a low negative value to a high positive value, thereby avoiding the generation of surges and improving the signal quality of the current limit response. Moreover, because the present invention can improve the current limiting response signal quality, and the present invention can have a wider frequency domain width of current limiting response. Compared with the prior art, the present invention can retain the current limiting response waveform of the high-frequency original signal.

Please refer to Figure 2. In one embodiment of the present invention, a plurality of inverters are connected for power supply, such as a first inverter 2A and a second inverter 2B shown in Figure 2. The first inverter 2A and the second inverter 2B are controlled by an inverter control module 70 . Taking the first inverter 2A as an example, the first inverter 2A includes four switches. The inverter control module 70 can generate a pulse-width modulation signal (PWM signal) to control the on and off states of the four switches in the first inverter 2A, thereby controlling the first The inverter 2A generates the output signal input to the device 1 for improving current limiting response speed and waveform. The mode in which the inverter control module 70 generates the pulse width modulation signal is not limited, but the output signal received by the device 1 for improving the current limiting response speed and waveform is periodic. As mentioned above, in this embodiment, the output signal received by the signal processing module 50 of the device 1 for improving current limiting response speed and waveform from the first inverter 2A is a sine wave.

The signal processing module 50 includes a first inversion unit 55 , a second inversion unit 56 and a processing unit 57 .

The first inversion unit 55 includes a first input terminal 551 and a first output terminal 552 . The first input terminal 551 is electrically connected to the signal input terminal 53 , and the first output terminal 552 is electrically connected to the first signal output terminal 51 . The second inversion unit 56 includes a second input terminal 561 and a second output terminal 562 . The second input terminal 561 is electrically connected to the first output terminal 552, and the second output terminal 562 is electrically connected to the second signal output terminal 52.

The processing unit 57 is electrically connected to the signal input terminal 53 and the control signal output terminal 54 respectively. The processing unit 57 receives the input signal from the first inverter 2A, and the processing unit 57 senses whether the input signal is the positive half cycle or the negative half cycle. When the processing unit 57 senses that the input signal is the positive half cycle, the processing unit 57 generates the control signal to control the first switch unit 30 to be non-conductive and to control the second switch unit 40 to be conductive. When the processing unit 57 senses that the input signal is the negative half cycle, the processing The unit 57 generates the control signal to control the first switch unit 30 to be conductive and to control the second switch unit 40 to be non-conductive.

In this embodiment, the device 1 for improving current limiting response speed and waveform further includes an original input resistor R ₀ , a first input resistor R ₁ and a second input resistor R ₂ . The original input resistor R ₀ is disposed between the first input terminal 551 and the signal input terminal 53 . The first input resistor R ₁ is disposed between the first signal output terminal 51 of the signal processing module 50 and the first current limiting input terminal 11 of the first current limiting unit 10 , and the second input resistor R ₂ is provided between the second signal output terminal 52 of the signal processing module 50 and the second current limiting input terminal 21 of the second current limiting unit 20 .

Please refer to FIG. 3 , the first inversion unit 55 further includes a first inversion operator OP1 and a first operation resistor R ₃ , and the second inversion unit 56 further includes a second inversion unit OP1 and a first operation resistor R 3 . Secondary inverting operator OP2, a second input resistor R ₄ and a second operation resistor R ₅ .

The non-inverting input terminal of the first inverting operator OP1 is electrically connected to the first input terminal 551, the inverting input terminal of the first inverting operator OP1 is electrically connected to a ground GND, and the first inverting operator OP1 is electrically connected to the ground GND. The output terminal of the inverting operator OP1 is electrically connected to the first output terminal 552. The first operation resistor R ₃ is electrically connected between the non-inverting input terminal and the output terminal of the first inversion operation device OP1. In this way, the output of the first inverting operator OP1 is the output of an inverting closed-loop amplifier, and its output voltage is the inverse of its input voltage multiplied by the first operation resistor _R3 divided by the original input resistance R ₀ gain ratio.

The second input resistor R ₄ and the second operational resistor R ₅ are connected in series between the second input terminal 561 and the second output terminal 562 , and the second input resistor R ₄ and the second The intersection of the secondary operation resistor R ₅ is electrically connected to the non-inverting input end of the second inverting operator OP2. The non-inverting input terminal of the second inverting operator OP2 is electrically connected to the second input terminal 561 through the second input resistor _R4 . The inverting input terminal of the second inverting operator OP2 is electrically connected to the second input resistor R4. The ground GND is connected, and the output terminal of the second inverting operator OP2 is electrically connected to the second output terminal 562 . In this way, the output voltage of the second inverting operator OP2 is the inverse of its input voltage multiplied by the gain ratio of the second operation resistor R ₅ divided by the second input resistor R ₄ .

In addition, the first current limiting unit 10 includes a first inverting closed-loop amplifier OP3, a first voltage dividing resistor R ₁₀ , a first series capacitor C ₁₁ and a first parallel capacitor C ₁₂ . The second current limiting unit 20 includes a second inverting closed-loop amplifier OP4, a second voltage dividing resistor R ₂₀ , a second series capacitor C ₂₁ and a second parallel capacitor C ₂₂ .

The first inverting closed-loop amplifier OP3 includes a first non-inverting input terminal, a first inverting input terminal and a first output terminal. The first non-inverting input terminal is electrically connected to the ground GND, the first inverting input terminal receives the first signal through the first current-limiting input terminal 11, and the first output terminal is electrically connected to the first current-limiting output. End 12. The first voltage dividing resistor R ₁₀ is electrically connected between the first inverting input terminal and the first output terminal of the first inverting closed-loop amplifier OP3. The first series capacitor C ₁₁ is connected in series between the first voltage dividing resistor R ₁₀ and the first current limiting output terminal 12 , and the first parallel capacitor C ₁₂ is connected in parallel between the first current limiting input terminal 11 and the first current limiting input terminal 11 . between a current limiting output terminal 12. The arrangement of the first series capacitor C ₁₁ and the first parallel capacitor C ₁₂ can help stabilize the signal quality of the first current limiting signal output by the first output end of the first inverting closed-loop amplifier OP3.

The second inverting closed-loop amplifier OP4 includes a second non-inverting input terminal, a second inverting input terminal and a second output terminal. The second non-inverting input terminal is electrically connected to the ground GND, the second inverting input terminal receives the second signal through the second current-limiting input terminal 21, and the second output terminal is electrically connected to the second current-limiting output. End 22. The second voltage dividing resistor R ₂₀ is electrically connected between the second inverting input terminal and the second output terminal of the second inverting closed-loop amplifier OP4. The second series capacitor C ₂₁ is connected in series between the second voltage dividing resistor R ₂₀ and the second current limiting output terminal 22 , and the second parallel capacitor C ₂₂ is connected in parallel between the second current limiting input terminal 21 and the second current limiting input terminal 21 . between the two current limiting output terminals 22. The arrangement of the second series capacitor C ₂₁ and the second parallel capacitor C ₂₂ can help stabilize the signal quality of the second current limiting signal output by the second output terminal of the second inverting closed-loop amplifier OP4.

Further, the device 1 for improving current limiting response speed and waveform includes a first current limiting output resistor R ₁₁ , a second current limiting output resistor R ₂₁ , a first current limiting diode D1 and a second current limiting diode. pole body D2, and the signal processing module 50 further has a first level output terminal 58 and a second level output terminal 59.

The first current limiting output resistor R ₁₁ is electrically connected between the first level output terminal 58 of the signal processing module 50 and the first current limiting input terminal 11 . The first level output terminal 58 is electrically connected to the first inverting input terminal of the first inverting closed-loop amplifier OP3 through the first current-limiting output resistor R ₁₁ , and the signal processing module 50 passes through the first current-limiting output resistor R 11 . The quasi-output terminal 58 outputs a first current limiting level to the first inverting input terminal of the first inverting closed-loop amplifier OP3. The first inverting closed-loop amplifier OP3 in the first current limiting unit 10 can determine the first current limiting output terminal 12 by comparing the first current limiting level and the voltage value of the first signal. A change in the current limiting signal achieves the purpose of positive half-cycle current limiting response.

The second current limiting output resistor R ₂₁ is electrically connected between the second level output terminal 59 and the second current limiting input terminal 21 of the signal processing module 50 . The second level output terminal 59 is electrically connected to the second inverting input terminal of the second inverting closed-loop amplifier OP4 through the second current limiting output resistor R ₂₁ , and the signal processing module 50 passes through the second level output resistor R 21 . The quasi-output terminal 59 outputs a second current limiting level to the second inverting input terminal of the second inverting closed-loop amplifier OP4. The second inverting closed-loop amplifier OP4 in the second current limiting unit 20 can determine the second current limiting output terminal 22 output by comparing the second current limiting level and the voltage value of the second signal. The change of the second current limiting signal achieves the purpose of negative half-cycle current limiting response.

The first switching unit 30 includes a first bipolar transistor BJT1 and a first switching resistor R ₃₀ . The first bipolar transistor BJT1 includes a first collector, a first base and a first emitter, and the first bipolar transistor BJT1 is an NPN type bipolar transistor. Bipolar transistor (BJT). The first emitter of the first bipolar transistor BJT1 is electrically connected to the first current limiting output terminal 12 , the first collector is electrically connected to the first current limiting input terminal 11 , and the first base is electrically connected to the There is a first switching resistor R ₃₀ , and the first base is electrically connected to the control signal output terminal 54 of the signal processing module 50 through the first switching resistor R ₃₀ .

The second switch unit 40 includes a second bipolar transistor BJT2 and a second switch resistor R ₄₀ . The second bipolar transistor BJT2 includes a second collector, a second base and a second emitter, and the second bipolar transistor BJT2 is a PNP type bipolar transistor. Bipolar transistor (BJT). The second emitter of the second bipolar transistor BJT2 is electrically connected to the second current limiting output terminal 22 , the second collector is electrically connected to the second current limiting input terminal 21 , and the second base is electrically connected to the The second switch resistor R ₄₀ is used, and the second base is electrically connected to the control signal output terminal 54 of the signal processing module 50 through the second switch resistor R ₄₀ .

The first current limiting diode D1 includes a first anode and a first cathode. The first anode is electrically connected to the first current limiting output terminal 12 , and the first cathode is electrically connected to the output port 60 . In addition, the second current limiting diode D2 includes a second anode and a second cathode, the second cathode is electrically connected to the second current limiting output terminal 22 , and the second anode is electrically connected to the output port 60 .

Based on the components shown in Figure 3 above, please refer to the following description of operation. The output signal received by the signal processing module 50 through the signal input terminal 53 will be sent to the processing unit 57 and the first inversion operator OP1 respectively.

The processing unit 57 generates two voltage level values of the first current limiting level and the second current limiting level according to the output signal, and the first current limiting level and the second current limiting level are They are used to limit changes in voltage to correspond to changes in limiting current. This is because when the resistance of the back-end attached circuit remains unchanged, changes in voltage are proportional to changes in current. The processing unit 57 outputs the first current limiting level to the first inverting input terminal of the first inverting closed-loop amplifier OP3 through the first level output terminal 58, and through the second level output terminal 59 The second current limiting level is output to the second inverting input terminal of the second inverting closed-loop amplifier OP4. Furthermore, the processing unit 57 also senses whether the output signal is a positive half cycle or a negative half cycle. As mentioned above, when the processing unit 57 senses that the output signal is the positive half cycle, the processing unit 57 57 generates the control signal to enable the second switching unit 40 to conduct the collector and emitter of the second bipolar transistor BJT2, and disable the first switching unit 30 to enable the first bipolar transistor BJT1 The collector and emitter are not conducting. On the contrary, when the processing unit 57 senses that the output signal is the negative half cycle, the processing unit 57 generates the control signal to enable the first switch unit 30 so that the collector and emitter of the first bipolar transistor BJT1 The second switch unit 40 is turned on, and the second switch unit 40 is disabled, so that the collector and emitter of the second bipolar transistor BJT2 are not turned on.

The output signal sent to the first inverting operator OP1, after passing through the inversion and gain of the first inverting operator OP1, flows to the second inverting operator OP2 and the second inverting operator OP2 as the first signal respectively. flows to the first inverting input terminal of the first inverting closed loop amplifier OP3. The first signal flowing to the second inverting operator OP2 will again pass through the inversion and gain of the second inverting operator OP2 and then become the second signal flowing to the second inverting closed loop amplifier OP4. Second inverting input terminal. In other words, the phase difference between the first signal and the second signal is caused by the inversion sum gain of the second inversion operator OP2. In this embodiment, the first operation resistor R ₃ is equal to the original input resistance R ₀ , so the absolute value of the first signal output by the first inversion operator OP1 is equal to the absolute value of the output signal. Moreover, the second input resistor R ₄ and the second operation resistor R ₅ are also equal, so the absolute value of the second signal output by the second inverting operator OP2 is equal to the absolute value of the first signal.

When the output signal received by the signal input terminal 53 is in the positive half cycle, it is finally output to the output port after two inversions by the first inverting operator OP1 and the first inverting closed-loop amplifier OP3 The first current limiting signal 60 is also positive, so the first current limiting unit 10 is responsible for the operation during the positive half cycle of the output signal. The signal finally output to the output port 60 after three inversions by the first inverting operator OP1, the second inverting operator OP2 and the second inverting closed-loop amplifier OP4 is theoretically a negative number. , but because the negative power terminal of the second inverting closed-loop amplifier OP4 of the second current limiting unit 20 is grounded, the second inverting closed-loop amplifier OP4 will only output a voltage of zero volts, that is, the so-called second limit The stream unit 20 will not operate when the output signal is a positive half cycle.

When the output signal received by the signal input terminal 53 is in the negative half cycle, the three times of the first inverting operator OP1, the second inverting operator OP2 and the second inverting closed-loop amplifier OP4 The second current limiting signal finally output to the output port 60 after inversion is positive, so the second current limiting unit 20 is responsible for the operation during the negative half cycle of the output signal. The signal finally output to the output port 60 after two inversions by the first inverting operator OP1 and the first inverting closed-loop amplifier OP3 is theoretically a negative number, but because of the first current limiting unit The negative power terminal of the first inverting closed-loop amplifier OP3 of 10 is grounded, so the first inverting closed-loop amplifier OP3 will only output a voltage of zero volts, that is, the so-called first current limiting unit 10 will not output the signal. It operates during the negative half cycle.

When the output signal is in the positive half cycle, there is residual voltage in the second series capacitor C ₂₁ and the second parallel capacitor C ₂₂ of the second current limiting unit 20 when the second bipolar transistor BJT2 is turned on. Release the power so that when the output signal becomes a negative half cycle and the second current limiting unit 20 starts to operate, the second series capacitor C ₂₁ and the second parallel capacitor C ₂₂ can start from zero because they have been completely discharged. The negative characteristics begin to change. In other words, when the output signal just becomes a negative half cycle, the second current limiting level and the voltage value of the second signal are very small, so the present invention can release the second series capacitor C ₂₁ and the second parallel capacitor C 21 . The relatively high voltage value in the capacitor C ₂₂ prevents a surge caused by the residual power of the second series capacitor C ₂₁ and the second parallel capacitor C ₂₂ when the output signal just becomes a negative half cycle.

When the output signal is in the negative half cycle, the residual voltage in the first series capacitor C ₁₁ and the first parallel capacitor C ₁₂ of the first current limiting unit 10 can be applied to the first bipolar transistor BJT1 When it is turned on, power is released, so that when the output signal becomes a positive half cycle and the first current limiting unit 10 starts to operate, the first series capacitor C ₁₁ and the first parallel capacitor C ₁₂ have been completely discharged, so they can Starting from zero negative special. In other words, when the output signal just becomes a positive half cycle, the first current limiting level and the voltage value of the first signal are very small, so the present invention can release the first series capacitor C ₁₁ and the first parallel capacitor C 11 . A relatively high voltage value in the capacitor C ₁₂ is used to prevent a surge caused by the residual power of the first series capacitor C ₁₁ and the first parallel capacitor C ₁₂ when the output signal just becomes a positive half cycle.

The first current limiting signal and the second current limiting signal finally generated by the present invention will be responsible for telling the inverter control module 70 how to cooperate with the current limiting adjustment when the output signal is a positive half cycle and a negative half cycle respectively. Generate PWM signal. The adjusted PWM signal will then be used to control one or more inverters, such as controlling the first inverter 2A, to generate new signals. The signal generated in this new round is a current limiting response signal, and this current limiting response signal will be input into the invention again as an output signal. Therefore, the device 1 for improving the current limiting response speed and waveform compares the output signal with the adjustment voltage command, that is, by comparing the first signal with the first current limiting level, and comparing the second signal with the third current limiting level. The second current limiting level can generate the current limiting response signal in response to the voltage adjustment command. The comparison between the first signal and the first current limiting level can be achieved by adjusting the first input resistor R ₁ and the first current limiting bit through which the first signal enters the first current limiting unit 10 The specific gravity is adjusted according to the voltage value of the first current-limiting output resistor R ₁₁ passing through the first current-limiting unit 10, so that the changing speed of the current-limiting response of the output signal during the positive half cycle can be adjusted. In the same way, the comparison between the second signal and the second current limiting level can be achieved by adjusting the second input resistor R 2 and the second input resistor R ₂ through which the second signal enters the second current limiting unit 20 . The current limiting bit is adjusted according to the voltage value of the second current limiting output resistor R ₂₁ passing through the second current limiting unit 20, so that the changing speed of the current limiting response of the output signal during the negative half cycle can be adjusted.

Please refer to Figure 4. In this embodiment, the processing unit 57 is an oscilloscope, and the oscilloscope can be used to detect the waveform of the current limit response signal, that is, to display a voltage waveform of the output signal. . Since the current waveform of the output signal changes in proportion to the voltage wave, it will not be shown again here. In the example of FIG. 4 , the voltage unit on the vertical axis is volt (Volt; V), and the time unit on the horizontal axis is millisecond (millisecond; ms). The frequency of the output signal is 50 Hertz (Hz), and the voltage waveform is a periodic square wave. As shown in Figure 4, the voltage waveform does not generally have surges as the voltage waveform generated by the conventional technology at the same 50Hz as shown in Figure 9. The improved current limiting response speed and waveform can be verified from the voltage waveform shown in Figure 4. The function of device 1. The device 1 for improving current limiting response speed and waveform can avoid the generation of surges during current limiting response.

Please refer to Figure 5. In the example of Figure 5, the frequency of the output signal is 100Hz. Compared with the voltage waveform generated by the conventional technology at the same 100 Hz shown in Figure 10, the voltage waveform generated by the present invention can still avoid the generation of surges, which is an improvement over the existing conventional technology.

Please refer to Figure 6. In the example of Figure 6, the time unit on the horizontal axis is microsecond (μs), and the frequency of the output signal is 500Hz. Compared with the voltage waveform generated by the conventional technology at the same 500Hz shown in Figure 11, the voltage waveform generated by the present invention not only does not generate surges nor is it distorted, that is, it can roughly retain the waveform characteristics of the output signal at 100Hz. appearance. It can be seen that the device 1 for improving the current limiting response speed and waveform can maintain the high quality of the current limiting response waveform, and the device 1 for improving the current limiting response speed and waveform can have a wider operating frequency than the conventional technology.

Please refer to Figures 7 and 8. In the example of Figure 7, the frequency of the output signal is 1000Hz, and in the example of Figure 8, the frequency of the output signal is 2000Hz. It can be seen that even if the output signal is a high frequency of 1000Hz or 2000Hz, the voltage waveform generated by the present invention can still avoid the generation of surges during the current limit response output, and can still better maintain the signal waveform. It can be seen that the device 1 for improving the current limiting response speed and waveform has a wider operating frequency than the previous technology.

1: Device to improve current limiting response speed and waveform

2:Inverter

3: Inverter output terminal

10: The first current limiting unit

11: The first current limiting input terminal

12: The first current limiting output terminal

20: Second current limiting unit

21: Second current limiting input terminal

22: Second current limiting output terminal

30: First switch unit

40: Second switch unit

50:Signal processing module

51: First signal output terminal

52: Second signal output terminal

53: Signal input terminal

54: Control signal output terminal

60:Output port

Claims (10)

A device for improving current limiting response speed and waveform. The power supply is connected to an inverter output end of an inverter to receive an output signal generated by the inverter. It includes: a signal processing module having a signal input end. , a first signal output terminal, a second signal output terminal and a control signal output terminal; wherein the signal input terminal is electrically connected to the inverter output terminal to receive the output signal; wherein the signal processing module is based on The output signal generates a first signal, a second signal and a control signal, and the first signal is output through the first signal output terminal, and the second signal is output through the second signal output terminal, and through the control The signal output terminal outputs the control signal; wherein the phase difference between the first signal and the second signal is 180 degrees; an output port; a first current limiting unit having a first current limiting input terminal and a first current limiting Output terminal; wherein, the first current-limiting input terminal is electrically connected to the first signal output terminal of the signal processing module to receive the first signal, and the first current-limiting output terminal is electrically connected to the output port; a first A switch unit is connected in parallel to the first current limiting unit and is electrically connected to the control signal output end of the signal processing module to receive the control signal; a second current limiting unit has a second current limiting input end and a a second current-limiting output terminal; wherein the second current-limiting input terminal is electrically connected to the second signal output terminal of the signal processing module to receive the second signal, and the second current-limiting output terminal is electrically connected to the output port; a second switch unit, connected in parallel to the second current limiting unit, and electrically connected to the control signal output end of the signal processing module to receive the control signal; wherein, when the output signal is a positive half cycle, The first current limiting unit generates a first current limiting signal to the output port according to the first signal, and the signal processing module controls the first switching unit to be non-conductive according to the control signal. The signal controls the second switching unit to be turned on; wherein, when the output signal is a negative half cycle, the second current limiting unit generates a The second current limiting signal is sent to the output port, and the signal processing module controls the first switch unit to be conductive according to the control signal, and the signal processing module controls the second switch unit to be non-conductive according to the control signal. The device for improving current limiting response speed and waveform as described in claim 1 further includes: a first input resistor, which is provided at the first signal output end of the signal processing module and the first current limiting unit. between a current limiting input terminal; and a second input resistor, disposed between the second signal output terminal of the signal processing module and the second current limiting input terminal of the second current limiting unit. As for the device for improving current limiting response speed and waveform described in claim 1, the signal processing module includes: a first-time inverting unit, including a first-time input terminal and a first-time output terminal; wherein, the The first input terminal is electrically connected to the signal input terminal, and the first output terminal is electrically connected to the first signal output terminal; a second inversion unit includes a second input terminal and a second output terminal; Wherein, the second input terminal is electrically connected to the first output terminal, and the second output terminal is electrically connected to the second signal output terminal; a processing unit is electrically connected to the signal input terminal and the control signal output terminal respectively, The output signal is received from the inverter, and the output signal is sensed to be the positive half cycle or the negative half cycle; wherein, when the processing unit senses that the output signal is the positive half cycle, the processing unit generates The control signal is used to control the first switching unit to be non-conductive and to control the second switching unit to be conductive; wherein, when the processing unit senses that the output signal is the negative half cycle, the processing unit generates the control signal to control the third switching unit. One switch unit is turned on and the second switch unit is controlled not to be turned on. The device for improving current limiting response speed and waveform as described in claim 1, wherein: the first current limiting unit includes: A first inverting closed-loop amplifier includes a first inverting input terminal and a first output terminal; wherein the first inverting input terminal receives the first signal through the first current limiting input terminal, and the first inverting input terminal receives the first signal through the first current limiting input terminal. The output terminal is electrically connected to the first current limiting output terminal; a first voltage dividing resistor is electrically connected between the first inverting input terminal and the first output terminal; wherein, the signal processing module further has a first level output terminal; the first level output terminal is electrically connected to the first inverting input terminal, and the signal processing module outputs a first current limiting level to the first inverting input terminal through the first level output terminal input terminal. The device for improving current limiting response speed and waveform as described in claim 4, wherein at least one capacitor is further electrically connected between the first inverting input terminal and the first output terminal of the first inverting closed-loop amplifier. The device for improving current limiting response speed and waveform as described in claim 1, further comprising: a first current limiting diode, including a first anode and a first cathode; wherein the first anode is electrically connected to the first The first current limiting output end of a current limiting unit, the first cathode is electrically connected to the output port; and a second current limiting diode, including a second anode and a second cathode; wherein, the second anode The second cathode is electrically connected to the output port, and the second cathode is electrically connected to the second current limiting output end of the second current limiting unit. The device for improving current limiting response speed and waveform as described in claim 1, wherein: the second current limiting unit includes: a second inverting closed-loop amplifier including a second inverting input terminal and a second output terminal ; wherein, the second inverting input terminal receives the second signal through the second current limiting input terminal, and the second output terminal is electrically connected to the second current limiting output terminal; a second voltage dividing resistor is electrically connected to the between the second inverting input terminal and the second output terminal; Wherein, the signal processing module further has a second level output terminal; the second level output terminal is electrically connected to the second inverting input terminal, and the signal processing module outputs a second level output terminal through the second level output terminal. The second current limiting level is connected to the second inverting input terminal. The device for improving current limiting response speed and waveform as described in claim 7, wherein at least one capacitor is further electrically connected between the second inverting input terminal and the second output terminal of the second inverting closed-loop amplifier. The device for improving current limiting response speed and waveform as described in claim 1, wherein the first switching unit includes: a first bipolar transistor, including a first emitter and a first collector. ) and a first base (Base), and is an NPN-type bipolar transistor; wherein, the first emitter is electrically connected to the first current-limiting output terminal, and the first collector is electrically connected to the first current-limiting output terminal. The input end, and the first base is electrically connected to the signal processing module; wherein, when the output signal is the negative half cycle, the signal processing module outputs the control signal to the first base to cause the first dual The first emitter and the first terminal of the polar transistor can be turned on. The device for improving current limiting response speed and waveform as described in claim 1, wherein the second switching unit includes: a second bipolar transistor, including a second emitter (Emitter) and a second collector (Collector). ) and a second base (Base), and is a PNP type bipolar transistor; wherein, the second emitter is electrically connected to the second current limiting output terminal, and the second collector is electrically connected to the second current limiting output. The input end, and the second base is electrically connected to the signal processing module; wherein, when the signal processing module senses that the output signal is a positive half cycle, the signal processing module outputs a second enable signal to The second base conducts the second emitter and the second collector of the second bipolar transistor.