TWI822432B - Power converter and control method thereof - Google Patents

Abstract

A power converter includes first to fourth switches, a flying capacitor, an inductor, an output capacitor and a control circuit. The first to fourth switches are coupled in cascode and in sequence. The first switch is further used to receive an input voltage, and the fourth switch is further coupled to a ground terminal. The flying capacitor is coupled across the second switch and the third switch, the inductor is coupled to the second switch, the third switch and the output capacitor. The output capacitor is used to output an output voltage. When the input voltage is less than an input voltage threshold, the control circuit is used to switch the first to fourth switches according to a resonant frequency. When the input voltage exceeds the input voltage threshold, the control circuit is used to switch the first to fourth switches according to a regulated frequency exceeding the resonant frequency. If the flying capacitor is coupled to the inductor, the flying capacitor and the inductor can form a resonant circuit having the resonant frequency.

Description

Power converter and control method thereof

The present invention relates to electric energy conversion, in particular to a power converter and its control method.

The resonant switched-capacitor converter (RSCC) is a power converter that produces no or only a small amount of power consumption when transmitting power. It is commonly used in mobile electronic devices such as mobile phones and notebook computers. Used to provide power.

Resonant switched capacitor converters convert input voltage to output voltage with a fixed conversion ratio. When the input voltage is too large, the resonant switched capacitor converter still produces an excessive output voltage with a fixed conversion ratio, causing damage to the electronic device.

An embodiment of the present invention provides a power converter, which includes a first switch, a second switch, a third switch, a fourth switch, a flying capacitor, an inductor, an output capacitor and a control circuit. The first switch includes a control terminal, a first terminal for receiving the input voltage, and a second terminal. The second switch includes a control terminal and a first terminal coupled to the second terminal and the second terminal of the first switch. The third switch includes a control terminal and a first terminal coupled to the second terminal and the second terminal of the second switch. The fourth switch includes a control terminal, a first terminal coupled to the second terminal of the third switch, and a second terminal coupled to the ground terminal. The flying capacitor includes a first terminal coupled to the second terminal of the first switch, and a second terminal coupled to the second terminal of the third switch. The inductor includes a first terminal coupled to the second terminal of the second switch and the second terminal. The output capacitor includes a first terminal coupled to the second terminal of the inductor, used to output the output voltage, and the second terminal is coupled to the ground terminal. The control circuit is coupled to the first end of the first switch, the control end of the first switch, the control end of the second switch, the control end of the third switch and the control end of the fourth switch. The control circuit is used to switch the first switch, the second switch, the third switch and the fourth switch according to the resonant frequency when the input voltage is less than the input voltage critical value. When the input voltage exceeds the input voltage critical value, the control circuit Used to switch the first switch, the second switch, the third switch and the fourth switch according to the adjustment frequency exceeding the resonant frequency. If the flying capacitor is coupled to the inductor, the flying capacitor and the inductor will form a resonant circuit with a resonant frequency.

An embodiment of the present invention further provides a control method for a power converter. The power converter includes a first switch, a second switch, a third switch, a fourth switch, a flying capacitor, an inductor, an output capacitor and a control circuit. The first switch includes a control terminal, a first terminal for receiving the input voltage, and a second terminal. The second switch includes a control terminal and a first terminal coupled to the second terminal and the second terminal of the first switch. The third switch includes a control terminal and a first terminal coupled to the second terminal and the second terminal of the second switch. The fourth switch includes a control terminal, a first terminal coupled to the second terminal of the third switch, and a second terminal coupled to the ground terminal. The flying capacitor includes a first terminal coupled to the second terminal of the first switch, and a second terminal coupled to the second terminal of the third switch. The inductor includes a first terminal coupled to the second terminal of the second switch and the second terminal. The output capacitor includes a first terminal coupled to the second terminal of the inductor for outputting the output voltage, and a second terminal coupled to the ground terminal. The control circuit is coupled to the first end of the first switch, the control end of the first switch, the control end of the second switch, the control end of the third switch and the control end of the fourth switch. The control method includes: when the input voltage is less than the input voltage critical value, the control circuit switches the first switch, the second switch, the third switch and the fourth switch according to the resonant frequency; and when the input voltage exceeds the input voltage critical value, the control circuit switches according to the exceeding The adjustment frequency of the resonant frequency switches the first switch, the second switch, the third switch and the fourth switch. If the flying capacitor is coupled to the inductor, the flying capacitor and the inductor will form a resonant circuit with a resonant frequency.

1: Power converter

10,20,30,40,120: switch

50:Flying Capacitor

60:Inductor

70: Output capacitor

800:Control circuit

801: Signal generation circuit

802: Feedback circuit

803: Status detection circuit

804: Closed loop circuit

805,806,807,808: Phase circuit

80, 81, 85 and 86: Buffer

95,96,263,315,415:OR gate

111:Transistor

112:Current source

113 and 152: Capacitor

150: Error amplifier

155,210,220: Comparator

250:Zero Cross Detector

260,320,343,420,443: flip-flop

261,267,311,411: reverser,

265,330,345,430,445: Pulse generator

310,312,321,322,341,410,412,421,422,441: And gate

110,325,425: NOR gate

342,442:Non-and gate

200:Control method

S202 and S204: steps

CLP: closed loop signal

COMP: error amplification signal

IL: inductor current

P1,P2,PA,PB: phase signal

Pz1 to Pz3, Pfb1, Pfb2: pulse wave

RAMP: ramp signal

S1 to S4: switch signal

SDM: degaussing signal

SZ: zero cross signal

t1 to r9: time

TG1, TG2, TGA, TGB: trigger signal

Vcc: supply voltage

Vin: input voltage

VH: high voltage

VL: low voltage

Vo: output voltage

VR: reference voltage

VT: degaussing reference voltage

Vx: switching voltage

GND: ground voltage

Figure 1 is a schematic circuit diagram of a power converter in an embodiment of the present invention.

Figure 2 is a flow chart of the control method of the power converter in Figure 1.

Figure 3 is a waveform diagram of the power converter in Figure 1 in non-regulated mode.

Figure 4 is a waveform diagram of the power converter in Figure 1 in regulation mode.

Figure 5 is a schematic diagram of part of the control circuit in Figure 1.

Figure 6 is a schematic diagram of other parts of the control circuit in Figure 1.

Figure 7 is a waveform diagram of the circuit in Figure 6.

Figure 8 is a schematic diagram of other parts of the control circuit in Figure 1.

Figure 9 is a schematic diagram of other parts of the control circuit in Figure 1.

Figure 10 is a schematic diagram of other parts of the control circuit in Figure 1.

Figure 1 is a schematic circuit diagram of a power converter 1 in one embodiment of the present invention. The power converter 1 can step down the input voltage Vin to generate an output voltage Vo to the load. Both the input voltage Vin and the output voltage Vo can be DC voltages, and the output voltage Vo can be less than or equal to half of the input voltage Vin. The power converter 1 can operate in a non-regulated mode or a regulated mode. When the input voltage Vin is less than the input voltage threshold, the power converter 1 can operate in a non-regulated mode, and the output voltage Vo in the non-regulated mode can be a divided voltage of the input voltage Vin. For example, the output voltage Vo may be equal to half of the input voltage Vin, and the input voltage threshold may be 40V. When the input voltage Vin exceeds the input voltage critical value, the power converter 1 can operate in a regulation mode to regulate the output voltage Vo to be equal to or less than the output voltage upper limit value. In some embodiments, the output voltage upper limit value may be equal to half of the input voltage threshold value, for example, the input voltage threshold value may be 40V, and the output voltage upper limit value may be 20V. If the input voltage Vin is equal to 30V, then The output voltage Vo generated by the power converter 1 can be 15V; and if the input voltage Vin is equal to 60V, the power converter 1 can adjust the output voltage Vo to be equal to or less than 20V to avoid damage to the load and enhance system efficiency. In either the non-regulating mode or the regulating mode, the power converter 1 can operate in discontinuous conduction mode (DCM) but not in continuous conduction mode (CCM).

The power converter 1 may include switches 10 , 20 , 30 , 40 , a flying capacitor 50 , an inductor 60 , an output capacitor 70 and a control circuit 800 . The switch 10 includes a control terminal for receiving the switch signal S1, a first terminal and a second terminal. The switch 20 includes a control terminal for receiving the switch signal S2 and a first terminal coupled to the second terminal and the second terminal of the switch 10 . The switch 30 includes a control terminal for receiving the switch signal S3 and a first terminal coupled to the second terminal and the second terminal of the switch 20 . The switch 40 includes a control terminal for receiving the switch signal S4, a first terminal coupled to the second terminal of the switch 30, and a second terminal coupled to the ground terminal. The flying capacitor 50 includes a first terminal coupled to the second terminal of the switch 10 and a second terminal coupled to the second terminal of the switch 30 . The inductor 60 includes a first terminal coupled to the second terminal of the switch 20 and a second terminal. The output capacitor 70 includes a first terminal coupled to a second terminal of the inductor 60 and a second terminal coupled to the ground. The control circuit 800 may be coupled to the control end of the switch 10 , the control end of the switch 20 , the control end of the switch 30 and the control end of the switch 40 .

The first terminal of the switch 10 can receive the input voltage Vin, and the first terminal of the output capacitor 70 can output the output voltage Vo. The ground terminal can provide ground voltage GND, such as 0V. The second terminal of the switch 20 can provide the switching voltage Vx. The current flowing through the inductor 60 may be called the inductor current IL.

The control circuit 800 may receive the input voltage Vin and/or the output voltage Vo to generate switching signals S1 to S4 to switch the switches 10 , 20 , 30 and 40 . When the input voltage Vin is less than the input voltage threshold, the control circuit 800 can switch the switch 10 and the switch when the inductor current IL of the inductor 60 is 0 according to the resonant frequency. 20. Switch 30 and switch 40 to reduce power loss. When the input voltage Vin exceeds the input voltage threshold, the control circuit 800 can reduce the ON time of the switch 10 or the switch 20 and increase the simultaneous ON time of the switch 30 and the switch 40 to switch according to the adjustment frequency beyond the resonant frequency. Switches 10, 20, 30 and 40, thereby adjusting the output voltage Vo to be equal to or less than the upper limit of the output voltage. In some embodiments, when the input voltage Vin exceeds the input voltage threshold, the control circuit 800 can turn off the switch 10 or the switch 20 before the inductor current IL of the inductor 60 reaches 0 when magnetizing the inductor 60 . Then after turning off the switch 10 or the switch 20, the control circuit 800 can turn on the switch 30 and the switch 40 to demagnetize the inductor 60, and when demagnetizing the inductor 60, the control circuit 800 can increase the inductor current IL of the inductor 60. When reaching 0, switch 30 or switch 40 is turned off. In some embodiments, when the power converter 1 is in a light load state, the control circuit 800 may additionally increase the OFF time of the switches 10 and 20, as well as the switches 30 and 40.

Although in the embodiment, the power converter 1 compares the input voltage Vin and the input voltage threshold value to determine the operating mode of the power converter 1, those skilled in the art can also change the circuit settings of the power converter 1 and compare the output voltage Vo according to actual needs. and the upper limit of the output voltage to determine the operating mode of the power converter 1. For example, when the output voltage Vo is less than the upper limit of the output voltage, the power converter 1 can operate in the non-regulating mode; and when the output voltage Vo exceeds the upper limit of the output voltage, the power converter 1 can operate in the regulating mode.

Figure 2 is a flow chart of the control method 200 of the power converter 1. The control method 200 includes steps S202 and S204 for controlling the power converter 1 to operate in a non-regulated mode or a regulated mode. Any reasonable technical changes or step adjustments fall within the scope disclosed by the present invention. Steps S202 and S204 are explained as follows: Step S202: When the input voltage Vin is less than the input voltage threshold, the control circuit 800 follows Switches 10, 20, 30 and 40 are switched according to the resonant frequency; Step S204: When the input voltage Vin exceeds the input voltage threshold, the control circuit 800 switches switches 10, 20, 30 and 40 according to the adjustment frequency exceeding the resonant frequency.

In step S202 , the power converter 1 operates in the non-regulated mode, and the resonant frequency may be the resonant frequency of the resonant circuit formed by the flying capacitor 50 and the inductor 60 if the flying capacitor 50 is coupled to the inductor 60 . The switch signals S1 and S3 can be substantially the same, the switches 10 and 30 can be switched substantially synchronously, the switch signals S2 and S4 can be substantially the same, and the switches 20 and 40 can be switched substantially synchronously, as shown in Figure 3 . Figure 3 is a waveform diagram of the power converter 1 in the non-regulated mode, in which the horizontal axis is time and the vertical axis is voltage or current. The following describes the operation of the power converter 1 in the non-regulated mode with reference to Figure 1 and Figure 3 at the same time. In the non-regulating mode, the control circuit 800 can use the phase signal P1 to generate the switching signals S1 and S3, use the phase signal P2 to generate the switching signals S2 and S4, generate the zero-crossing signal SZ according to the inductor current IL, and switch the phase according to the zero-crossing signal SZ. Signals P1 and P2 are used to achieve zero-current switching (ZCS). The phase signal P1 and the switching signals S1 and S3 may be substantially the same, and the phase signal P2 and the switching signals S2 and S4 may be substantially the same. The generation method of the phase signals P1 and P2 will be described in subsequent paragraphs.

At time t1, the inductor current IL reaches 0A, triggering the pulse wave Pz1 on the zero-crossing signal SZ. At the same time, the pulse wave Pz1 triggers the phase signal P2 to switch from the high voltage VH to the low voltage VL, and the phase signal P1 is maintained at the low voltage VL. The low voltage VL may be the ground voltage GND. At time t2, the pulse wave Pz1 triggers the phase signal P1 to switch from the low voltage VL to the high voltage VH, the phase signal P2 is maintained at the low voltage VL, and the pulse wave Pz1 on the zero-crossing signal SZ ends. The pulse wave Pz1 may have a predetermined width, for example, the predetermined width is equal to (t2-t1).

Between time t2 and time t3, the phase signal P1 is maintained at the high voltage VH, the phase signal P2 is maintained at the low voltage VL, the inductor current IL oscillates at the resonant frequency, and the zero-crossing signal SZ is maintained at the low voltage. VL. The switching signals S1 and S3 (=phase signal P1) can be high voltage VH, switches 10 and 30 are turned on, and the switching signals S2 and S4 (=phase signal P2) can be low voltage VL, switches 20 and 40 are turned off, so that the flying capacitor The first terminal of the capacitor 50 receives the input voltage Vin via the switch 10 , and the second terminal of the flying capacitor 50 is coupled to the first terminal of the inductor 60 via the switch 30 . Therefore, the input voltage Vin charges the flying capacitor 50 and the output capacitor 70 and magnetizes the inductor 60. At this time, the flying capacitor 50 and the output capacitor 70 can form a voltage divider to generate the output voltage Vo, and the flying capacitor 50 and the inductor 60 can form a resonant circuit to make the inductor current IL oscillate at the resonant frequency. In some embodiments, the capacitance values of the flying capacitor 50 and the output capacitor 70 can be equal, so the cross voltages of the flying capacitor 50 and the output capacitor 70 are equal, and the switching voltage Vx and the output voltage Vo are both equal to half of the input voltage Vin.

At time t3, the inductor current IL reaches 0A, triggering the pulse wave Pz2 on the zero-crossing signal SZ. At the same time, the pulse wave Pz2 triggers the phase signal P1 to switch from the high voltage VH to the low voltage VL, and the phase signal P2 is maintained at the low voltage VL. At time t4, the pulse wave Pz2 triggers the phase signal P2 to switch from the low voltage VL to the high voltage VH, the phase signal P1 remains at the low voltage VL, and the pulse wave Pz2 on the zero-crossing signal SZ ends. The pulse wave Pz2 may have the same predetermined width as the pulse wave Pz1, for example, the predetermined width (t4-t3) of the pulse wave Pz2 is equal to the predetermined width (t2-t1) of the pulse wave Pz1.

Between time t4 and time t5, the phase signal P1 is maintained at the low voltage VL, the phase signal P2 is maintained at the high voltage VH, the inductor current IL oscillates at the resonant frequency, and the zero-crossing signal SZ is maintained at the low voltage VL. The switching signals S1 and S3 (= phase signal P1) can be low voltage VL, and the switches 10 and 30 are turned off, and the switching signals S2 and S4 can be high voltage VH, and the switches 20 and 40 are turned on, so that the first terminal of the flying capacitor 50 passes through The switch 20 is coupled to the first terminal of the inductor 60 , and the second terminal of the flying capacitor 50 is coupled to the ground via the switch 40 . The flying capacitor 50 can be used as a voltage source to charge the output capacitor 70 and excite the inductor 60. Therefore, the cross voltage of the flying capacitor 50 can be equal to the output voltage Vo. If the cross voltage of the flying capacitor 50 is equal to one of the input voltage Vin Half, then the output voltage Vo is also equal to half of the input voltage Vin. At the same time, the flying capacitor 50 and the inductor 60 can form a resonant circuit so that the inductor current IL oscillates at the resonant frequency.

At time t5, the inductor current IL reaches 0A, triggering the pulse wave Pz3 on the zero-crossing signal SZ. At the same time, the pulse wave Pz3 triggers the phase signal P2 to switch from the high voltage VH to the low voltage VL, and the phase signal P1 is maintained at the low voltage VL. At time t6, the pulse wave Pz3 triggers the phase signal P1 to switch from the low voltage VL to the high voltage VH, the phase signal P2 remains at the low voltage VL, and the pulse wave Pz3 on the zero-crossing signal SZ ends. The pulse wave Pz3 may have the same predetermined width as the pulse wave Pz1, for example, the predetermined width (t6-t5) of the pulse wave Pz1 is equal to the predetermined width (t2-t1) of the pulse wave Pz1.

Afterwards, if the input voltage Vin is less than the input voltage threshold, the power converter 1 will continue to switch the switches 10, 20, 30 and 40 according to the resonant frequency to repeat the waveform from time t2 to t6, thereby outputting the output voltage Vo to the load.

In step S204, the power converter 1 operates in the regulation mode, and the switching signals S1 to S4 can be different, as shown in Figure 4. Figure 4 is a waveform diagram of the power converter 1 in the regulation mode, in which the horizontal axis is time and the vertical axis is voltage or current. The following describes the operation of the power converter 1 in the regulation mode with reference to Figure 1 and Figure 4 at the same time. In the adjustment mode, the control circuit 800 can generate the switching signal S1 according to the phase signal P1, generate the switching signal S2 according to the phase signal P2, generate the switching signal S3 according to the phase signals P1, PA and PB, and generate the switching signal S3 according to the phase signals P1, PA and PB. Switch signal S4. The switching signal S1 can be substantially equal to the phase signal P1, the switching signal S2 can be substantially equal to the phase signal P2, the switching signal S3 can be substantially equal to the OR operation result of the phase signals P1, PA and PB, and the switching signal S4 can be substantially equal to the phase signal P1, PA and PB. The above is equal to the OR operation result of the phase signals P2, PA and PB. The generation method of the phase signals P1, P2, PA and PB will be explained in the subsequent paragraphs.

At time t1, the inductor current IL reaches 0A, the trigger phase signal PB switches from the high voltage VH to the low voltage VL and the trigger phase signal P1 switches from the low voltage VL to the high voltage VH. The phase signals PA and P2 remain at the low voltage VL, causing the switch Signal S1 switches from low voltage VL to high voltage VH, switching signal S2 remains at low voltage VL, switching signal S3 remains at high voltage VH, and switching signal S4 switches from high voltage VH to low voltage VL. Therefore, when inductor current IL reaches 0A Switch 40 will be turned off.

Between time t1 and time t2, the switching signals S1 and S3 are maintained at the high voltage VH, and the switching signals S2 and S4 are maintained at the low voltage VL, causing the switches 10 and 30 to be turned on, and the switches 20 and 40 to be turned off. The terminal receives the input voltage Vin through the switch 10 , and the second terminal of the flying capacitor 50 is coupled to the first terminal of the inductor 60 through the switch 30 . Therefore, the input voltage Vin charges the flying capacitor 50 and the output capacitor 70 and excites the inductor 60. At this time, the flying capacitor 50 and the inductor 60 can form a resonant circuit so that the inductor current IL starts to rise.

At time t2, the input voltage Vin exceeds the input voltage threshold, the trigger phase signal P1 switches from the high voltage VH to the low voltage VL and the trigger phase signal PA switches from the low voltage VL to the high voltage VH. The phase signals P2 and PB remain at the low voltage VL. , causing the switching signal S1 to switch from the high voltage VH to the low voltage VL, the switching signal S2 to maintain the low voltage VL, the switching signal S3 to maintain the high voltage VH, and the switching signal S4 to switch from the low voltage VL to the high voltage VH, so the control circuit 800 When the inductor 60 is excited, the switch 10 can be turned off before the inductor current IL of the inductor 60 reaches 0, thereby reducing the conduction time of the switch 10 .

Between time t2 and time t3, the switching signals S1 and S2 are maintained at the low voltage VL, and the switching signals S3 and S4 are maintained at the high voltage VH, causing the switches 10 and 20 to be turned off, the switches 30 and 40 to be turned on, and the first end of the inductor 60 is coupled to the ground via switches 30 and 40, so the inductor 60 will be demagnetized before the inductor current IL reaches It was pulled down to 0A before reaching the peak value. Since the inductor 60 is coupled to the ground, the decreasing speed of the inductor current IL will be much faster than the decreasing speed of the inductor current IL due to resonance in Figure 3, and the time required for the inductor 60 to be magnetized and demagnetized is shown in Figure 4. (=t3-t1) will be less than the time for one excitation and demagnetization of the inductor 60 in Figure 3 (=t3-t1), so the control circuit 800 will switch switches 10, 20, 30 and 40 according to the adjustment frequency that exceeds the resonant frequency. .

At time t3, the inductor current IL reaches 0A, the trigger phase signal PA switches from the high voltage VH to the low voltage VL and the trigger phase signal P2 switches from the low voltage VL to the high voltage VH. The phase signals PB and P1 remain at the low voltage VL, causing the switch The signal S1 is maintained at the low voltage VL, the switching signal S2 switches from the low voltage VL to the high voltage VH, the switching signal S3 switches from the high voltage VH to the low voltage VL, and the switching signal S4 is maintained at the high voltage VH. Therefore, when the inductor current IL reaches 0A Switch 30 will be turned off.

Between time t3 and time t4, the switching signals S2 and S4 are maintained at the high voltage VH, and the switching signals S1 and S3 are maintained at the low voltage VL, causing the switches 20 and 40 to be turned on, and the switches 10 and 30 to be turned off. The terminal is coupled to the first terminal of the inductor 60 via the switch 20 , and the second terminal of the flying capacitor 50 is coupled to the ground terminal via the switch 40 . The flying capacitor 50 can be used as a voltage source to charge the output capacitor 70 and excite the inductor 60. The flying capacitor 50 and the inductor 60 can form a resonant circuit to cause the inductor current IL to start to rise.

At time t4, the input voltage Vin exceeds the input voltage threshold, the trigger phase signal P2 switches from the high voltage VH to the low voltage VL and the trigger phase signal PB switches from the low voltage VL to the high voltage VH. The phase signals P1 and PA remain at the low voltage VL. , causing the switching signal S1 to maintain at the low voltage VL, the switching signal S2 to switch from the high voltage VH to the low voltage VL, the switching signal S3 to switch from the low voltage VL to the high voltage VH, and the switching signal S4 to maintain the high voltage VH, so the control circuit 800 When the inductor 60 is excited, the switch 20 can be turned off before the inductor current IL of the inductor 60 reaches 0, thereby reducing the conduction time of the switch 20 and exceeding the limit. The frequency switch 20 is used to adjust the resonant frequency.

Between time t4 and time t5, the switching signals S1 and S2 are maintained at the low voltage VL, and the switching signals S3 and S4 are maintained at the high voltage VH, causing the switches 10 and 20 to be turned off, the switches 30 and 40 to be turned on, and the first end of the inductor 60 It is coupled to the ground via switches 30 and 40, so the inductor 60 will be demagnetized, and the inductor current IL will be pulled down to 0A before it reaches the peak value. Since the inductor 60 is coupled to the ground, the decreasing speed of the inductor current IL will be much faster than the decreasing speed of the inductor current IL due to resonance in Figure 3, and the time required for the inductor 60 to be magnetized and demagnetized is shown in Figure 4. (=t5-t3) will be less than the time for one excitation and demagnetization of the inductor 60 in Figure 3 (=t5-t3), so the control circuit 800 will switch switches 10, 20, 30 and 40 according to the adjustment frequency that exceeds the resonant frequency. .

In some embodiments, when the power converter 1 is in a light load state, the control circuit 800 can increase the dead-time delay between the phase signals P1 and PA, PA and P2, P2 and PB, PB and P1. ), thereby increasing the off time (OFF time) of switches 10 and 20, switches 30 and 40, thereby achieving the purpose of power saving. When there is a space-time delay between the phase signals P1 and PA, PA and P2, P2 and PB, PB and P1, each pulse wave of the switching signals S3 and S4 in Figure 4 can be replaced by 3 sub-pulse waves. For example, the starting time of the first sub-pulse wave of the switching signal S3 can be later than the starting time of the original pulse wave of the switching signal S3 in Figure 4, and the end time of the third sub-pulse wave of the switching signal S3 can be later than that in Figure 4 At the end time of the original pulse wave of the switching signal S3, the pulse width of each sub-pulse wave is smaller than the pulse width of the original pulse wave of the switching signal S3 in Figure 4, and there may be a time interval between two adjacent sub-pulse waves. Similarly, the starting time of the first sub-pulse wave of the switching signal S4 may be later than the starting time of the original pulse wave of the switching signal S4 in Figure 4, and the end time of the third sub-pulse wave of the switching signal S4 may be later than the fourth The end time of the original pulse wave of the switching signal S4 in the figure. The pulse width of each sub-pulse wave is smaller than the pulse width of the original pulse wave of the switching signal S4 in the figure 4, and there may be a time interval between two adjacent sub-pulse waves. .

The waveforms from time t5 to t9 and thereafter are similar to those from time t1 to t5. For explanation, please refer to the previous paragraphs and will not be repeated here. If the input voltage Vin is higher, the control circuit 800 will turn off the switch 10 or 20 sooner, and switch the switches 10, 20, 30 and 40 at a faster resonant frequency, so that the output voltage Vo is equal to or less than the upper limit of the output voltage. value to achieve the effect of adjusting the output voltage Vo, avoiding damage to the load and enhancing system efficiency.

FIG. 5 is a schematic diagram of part of the control circuit 800 in FIG. 1 . The control circuit 800 may include a signal generating circuit 801. The signal generating circuit 801 can generate switching signals S1 to S4 according to the phase signals P1, P2, PA and PB. The signal generating circuit 801 may include buffers 80, 81, 85 and 86, and OR gates 95 and 96.

The buffer 80 includes an input terminal for receiving the phase signal P1 and an output terminal for outputting the switching signal S1. The phase signal P1 can generate the switching signal S1 after passing through the buffer 80 . Therefore, the switching signal S1 can be the waveform of the phase signal P1 after a period of delay.

The buffer 81 includes an input terminal for receiving the phase signal P2 and an output terminal for outputting the switching signal S2. The phase signal P2 can generate the switching signal S2 after passing through the buffer 81. Therefore, the switching signal S2 can be a delayed waveform of the phase signal P2.

The OR gate 95 includes a first input terminal for receiving the phase signal P1, a second input terminal for receiving the phase signal PA, a third input terminal for receiving the phase signal PB, and an output terminal for outputting the phase signal P1. The result of the OR operation of , PA and PB. When any one of the phase signals P1, PA and PB is the high voltage VH, the OR gate 95 will output the high voltage VH. When each of the phase signals P1, PA and PB is the low voltage VL, the OR gate 95 will output the low voltage VL. Buffer 85 includes input terminals for receiving The operation result of the OR gate 95 is received and the output terminal is used to output the switching signal S3. The operation result of the OR gate 95 can generate the switching signal S3 through the buffer 85. Therefore, the switching signal S3 can be the waveform of the operation result of the OR gate 95 after a delay.

The OR gate 96 includes a first input terminal for receiving the phase signal P2, a second input terminal for receiving the phase signal PA, a third input terminal for receiving the phase signal PB, and an output terminal for outputting the phase signal P2. The result of the OR operation of , PA and PB. When any one of the phase signals P2, PA and PB is the high voltage VH, the OR gate 95 will output the high voltage VH. When each of the phase signals P2, PA and PB is the low voltage VL, the OR gate 95 will output the low voltage VL. The buffer 86 includes an input terminal for receiving the operation result of the OR gate 96 and an output terminal for outputting the switching signal S4. The operation result of the OR gate 96 can generate the switching signal S4 through the buffer 86. Therefore, the switching signal S4 can be the waveform of the operation result of the OR gate 96 after a delay.

FIG. 6 is a schematic diagram of other parts of the control circuit 800 in FIG. 1 . The control circuit 800 may further include a feedback circuit 802 . The feedback circuit 802 can generate the feedback signal SFB to adjust the output voltage Vo. The feedback signal SFB can indicate that the input voltage Vin exceeds the input voltage threshold or the output voltage Vo exceeds the output voltage upper limit, and can be used to reset the phase signals P1 and/or P2 to the low voltage VL early, thereby reducing the number of switches 10 and/or 20 on time and increase the adjustment frequency. The feedback circuit 802 may include a NOR gate 110, a current source 112, a transistor 111, capacitors 113 and 152, resistors 114, 115, 116, 117 and 151, a switch 120, an error amplifier 150 and a comparator 155.

The NOR gate 110 includes a first input terminal for receiving the phase signal P1, a second input terminal for receiving the phase signal P2, and an output terminal for outputting the result of the OR operation of the phase signals P1 and P2. The current source 112 includes a first terminal coupled to the power supply terminal for receiving the power supply voltage Vcc, and a second terminal. Electricity The crystal 111 includes a control terminal coupled to the output terminal of the NOR gate 110 for receiving the operation result of the NOR gate 110, a first terminal coupled to the second terminal of the current source 112, and a second terminal coupled to the NOR gate 110. on the ground terminal. The capacitor 113 includes a first terminal coupled to the first terminal of the transistor 111 and a second terminal coupled to the ground. The NOR gate 110, the current source 112, the transistor 111 and the capacitor 113 can form a ramp circuit. When the phase signal P1 or the phase signal P2 is the high voltage VH, the ramp circuit can generate a gradually rising ramp signal RAMP. When the phase signal P1 and/or the phase signal P2 are both low voltage VL, the ramp circuit can reset the ramp signal RAMP to the ground voltage GND.

The resistor 114 includes a first terminal for receiving the output voltage Vo and a second terminal. The resistor 115 includes a first terminal coupled to a second terminal of the resistor 114 and a second terminal coupled to the ground. The resistor 116 includes a first terminal for receiving the reference voltage VR and a second terminal. The reference voltage VR can be set to 2V or other suitable values. The resistor 117 includes a first terminal coupled to the second terminal of the resistor 116 and a second terminal. The switch 120 includes a control terminal for receiving the closed-loop signal CLP, a first terminal coupled to the second terminal of the resistor 117, and a second terminal coupled to the ground terminal. The resistors 114 and 115 can form a voltage divider to generate a divided voltage according to the output voltage Vo. For example, the resistance value of the resistor 114 can be 9k ohms, and the resistance value of the resistor 115 can be 1k ohms, so that the voltage divider produces a voltage dividing ratio of 10:1. If the output voltage Vo is 20V, then the first voltage of the resistor 115 The terminal can generate 2V as a divided voltage of the output voltage Vo. The error amplifier 150 includes an inverting input terminal coupled to the second terminal of the resistor 114, a forward input terminal coupled to the second terminal of the resistor 116, and an output terminal. The resistor 151 includes a first terminal coupled to the output terminal of the error amplifier 150 and a second terminal. The capacitor 152 includes a first terminal coupled to a second terminal of the resistor 114 and a second terminal coupled to the ground. When the closed loop signal CLP is the low voltage VL, the switch 120 can be turned off, and the error amplifier 150 can compare the divided voltage of the output voltage Vo with the reference voltage VR to generate the error amplification signal COMP. The error amplification signal COMP can be a stable voltage level and is related to the output voltage Vo. If the divided voltage of the output voltage Vo exceeds the reference voltage VR, the error amplification signal COMP will decrease; if the divided voltage of the output voltage Vo is less than the reference voltage VR, the error amplification signal COMP will increase. For example, If the reference voltage VR is 2V and the divided voltage of the output voltage Vo is 2V, the error amplifier 150 can set the error amplification signal COMP to 3V; if the reference voltage VR is 2V and the divided voltage of the output voltage Vo is 2.2V, the error amplifier 150 150 can set the error amplification signal COMP to 2.8V; if the reference voltage VR is 2V and the divided voltage of the output voltage Vo is 1.8V, the error amplifier 150 can set the error amplification signal COMP to 3.2V.

The closed loop signal CLP can represent the operating mode of the power converter 1 . If the closed-loop signal CLP is the low voltage VL, the power converter 1 will operate in the non-regulating mode; if the closed-loop signal CLP is the high voltage VH, the power converter 1 will operate in the regulating mode. When the closed loop signal CLP is the high voltage VH, the switch 120 can be turned on, and the resistors 116 and 117 can form a voltage divider to generate a divided voltage according to the reference voltage VR. The error amplifier 150 can compare the divided voltage of the output voltage Vo and the divided voltage of the reference voltage VR to generate an amplified error amplification signal COMP. For example, the resistance value of the resistor 116 can be 1k ohm, and the resistance value of the resistor 117 can be 9k ohm, so that the voltage divider can produce a voltage dividing ratio of 10:9. If the reference voltage VR is 2V, then the resistance of the resistor 117 is One end can generate 1.8V as a divided voltage of the reference voltage VR, and the error amplifier 150 can reduce the level of the error amplification signal COMP when the divided voltage of the output voltage Vo exceeds 1.8V, and when the divided voltage of the output voltage Vo is less than 1.8V When raising the level of the error amplification signal COMP. The closed loop signal CLP can provide hysteresis control on the reference voltage VR. The resistor 151 and the capacitor 152 can form a low-pass filter for filtering the error amplification signal COMP. In some embodiments, the resistor 151 and the capacitor 152 can also be omitted and the error amplification signal COMP is directly input to the comparator 155 .

The comparator 155 includes a positive input terminal coupled to the first terminal of the capacitor 113, a reverse input terminal, a first terminal of the resistor 151, and an output terminal for outputting the feedback signal SFB. The comparator 155 can compare the ramp signal RAMP and the error amplification signal COMP. When the ramp signal RAMP is smaller than the error amplification signal COMP, the comparator 155 can set the feedback signal SFB to the low voltage VL. Once the ramp signal RAMP reaches the error amplification signal COMP, the comparator 155 can insert a predetermined width into the feedback signal SFB. positive pulse wave.

According to the previous paragraph, if the divided voltage of the output voltage Vo exceeds the reference voltage VR, the error amplification signal COMP will decrease, allowing the ramp signal RAMP to reach the error amplification signal COMP faster, thereby generating the feedback signal SFB faster. In addition, when the closed-loop signal CLP is a high voltage VH, the error amplification signal COMP will further decrease, allowing the ramp signal RAMP to reach the error amplification signal COMP faster, thereby generating the feedback signal SFB faster and more stably, thereby increasing the feedback signal SFB reliability.

Figure 7 is a waveform diagram of the feedback circuit 802, in which the horizontal axis is time and the vertical axis is voltage. The operation of the feedback circuit 802 is explained below with reference to Figure 7.

Between time t1 and t2, the phase signal P1 is a high voltage VH, and the trigger ramp signal RAMP begins to rise. At the same time, the phase signal P2 and the feedback signal SFB are maintained at a low voltage VL. At time t2, the ramp signal RAMP and the error amplification signal COMP are equal, triggering the pulse wave Pfb1 on the feedback signal SFB. The pulse wave Pfb1 triggers the phase signal P1 to be switched to the low voltage VL, and because the phase signals P1 and P2 are both low voltages VL, so the ramp signal RAMP is reset to the low voltage VL. At time t3, the pulse wave Pfb1 ends, and the phase signals P1 and P2 and the ramp signal RAMP are maintained at the low voltage VL. Between time t3 and t4, the phase signals P1 and P2, the ramp signal RAMP and the feedback signal SFB are all maintained at the low voltage VL.

Between time t4 and t5, the phase signal P2 is at the high voltage VH, and the trigger ramp signal RAMP begins to rise. At the same time, the phase signal P1 and the feedback signal SFB are maintained at the low voltage VL. At time t5, the ramp signal RAMP and the error amplification signal COMP are equal, triggering the pulse wave Pfb2 on the feedback signal SFB. The pulse wave Pfb2 triggers the phase signal P2 to be switched to the low voltage VL, and because the phase signals P1 and P2 are both low voltages VL, so the ramp signal RAMP is reset to the low voltage VL. At time t6, pulse wave Pfb2 ends beam, the phase signals P1 and P2 and the ramp signal RAMP are maintained at the low voltage VL.

The feedback circuit 802 may repeat the waveform from time t1 to t2 to generate the feedback signal SFB.

Figure 8 is a schematic diagram of other parts of the control circuit 800. The control circuit 800 may further include a state detection circuit 803 and a closed loop circuit 804. The state detection circuit 803 may generate a zero-crossing signal SZ and a degaussing signal SDM. The zero-crossing signal SZ can indicate that the voltage across the inductor 60 passes 0V, and the degaussing signal SDM can indicate that the switching voltage Vx (the voltage across the switches 30 and 40 ) exceeds the degaussing reference voltage VT. The closed-loop circuit 804 can generate a closed-loop signal CLP, and the closed-loop signal CLP can represent the operating mode of the power converter 1 . When the closed-loop signal CLP is a high voltage VH, it indicates that the power converter 1 is operating in the regulating mode, and when the closed-loop signal CLP is a low voltage VL, it indicates that the power converter 1 is operating in a non-regulating mode.

The state detection circuit 803 may include comparators 210 and 220, and a zero-crossing detector (ZCD) 250. The comparator 210 includes a forward input terminal for receiving the switching voltage Vx, a reverse input terminal for receiving the output voltage Vo, and an output terminal for outputting a comparison result of the switching voltage Vx and the output voltage Vo. The switching voltage Vx is the voltage at the first terminal of the inductor 60 , and the output voltage Vo is the voltage at the second terminal of the inductor 60 . When it is detected that the switching voltage Vx exceeds the output voltage Vo, the comparator 210 can output the high voltage VH as the comparison result; when it is detected that the switching voltage Vx is less than the output voltage Vo, the comparator 210 can output the low voltage VL as the comparison result. The zero-crossing detector 250 includes an input terminal for receiving the comparison result of the switching voltage Vx and the output voltage Vo, and an output terminal for outputting the zero-crossing signal SZ. When detecting that the two consecutive comparison results of the comparator 210 switch from the high voltage VH to the low voltage VL or from the low voltage VL to the high voltage VH, the zero-crossing detector 250 can generate a pulse with a predetermined width on the zero-crossing signal SZ. wave; when detecting that the two consecutive comparison results of the comparator 210 are both high voltage VH or both low voltage VL, the zero-crossing detector 250 can set the zero-crossing signal SZ to the low voltage VL.

The comparator 220 includes a forward input terminal for receiving the switching voltage Vx, a reverse input terminal for receiving the degaussing reference voltage VT, and an output terminal for outputting a comparison result of the switching voltage Vx and the degaussing reference voltage VT as a degaussing signal. SDM. The degaussing reference voltage VT can be set to 0V. The switching voltage Vx may be equal to the voltage across switches 30 and 40 . If the inductor 60 is completely demagnetized, the switching voltage Vx will reach a peak value. When the switching voltage Vx exceeds the degaussing reference voltage VT, the comparator 220 can set the degaussing signal SDM to a high voltage VH; when the switching voltage Vx is less than the degaussing reference voltage VT, the comparator 220 can set the degaussing signal SDM to a low voltage VL.

The closed loop circuit 804 may include inverters 261 and 267, a flip-flop 260, a pulse generator 265 and an OR gate 263. The inverter 261 includes an input terminal for receiving the zero-cross signal SZ and an output terminal for outputting an inverse signal of the zero-cross signal SZ. The OR gate 263 includes a first input terminal for receiving the phase signal P1, a second input terminal for receiving the phase signal P2, and an output terminal for outputting an OR operation result of the phase signals P1 and P2. The pulse generator 265 includes an input terminal for receiving the result of the OR operation of the output phase signals P1 and P2, and an output terminal for outputting the first pulse signal. The inverter 267 includes an input terminal for receiving the first pulse signal and an output terminal for outputting the first reset signal. The flip-flop 260 includes a data input terminal for receiving the reverse signal of the zero-crossing signal SZ, a clock terminal for receiving the feedback signal SFB, a reset terminal for receiving the first reset signal, and an output terminal for To output the closed loop signal CLP. The closed-loop signal CLP can be triggered by the feedback signal SFB and reset by the rising edge of the phase signal P1 or P2.

Figures 9 and 10 are schematic diagrams of other parts of the control circuit 800. FIG. 9 shows that the control circuit 800 may further include phase circuits 805 and 806, and FIG. 10 shows that the control circuit 800 may further include phase circuits 807 and 808. The phase circuit 805 can generate the phase signal P1 and the trigger signal TG1. The phase circuit 806 The phase signal PA and the trigger signal TGA can be generated. The phase circuit 807 can generate the phase signal P2 and the trigger signal TG2. The phase circuit 808 can generate the phase signal PB and the trigger signal TGB. When the closed loop signal CLP is low voltage VL (non-regulated mode), the phase circuits 805 and 807 will be enabled and the phase circuits 806 and 808 will be disabled. When the closed loop signal CLP is high voltage VH (regulation mode), the phase circuits 805 to 808 are all enabled.

The phase circuit 805 may include AND gates 310, 312, 321 and 322, an OR gate 315, a NOR gate 325, a flip-flop 320, a pulse generator 330 and an inverter 311. The AND gate 310 includes a first input terminal for receiving the trigger signal TGB, a second input terminal for receiving the closed loop signal CLP, and an output terminal for outputting the result of the AND operation of the trigger signal TGA and the closed loop signal CLP. . The inverter 311 includes an input terminal for receiving the closed-loop signal CLP and an output terminal for outputting an inverse signal of the closed-loop signal CLP. The AND gate 312 includes a first input terminal for receiving the reverse signal of the closed-loop signal CLP, a second input terminal for receiving the trigger signal TG2, and an output terminal for outputting the reverse signal and trigger of the closed-loop signal CLP. The result of the AND operation on signal TG2. The OR gate 315 includes a first input terminal for receiving the operation result of the AND gate 310, a second input terminal for receiving the operation result of the AND gate 312, and an output terminal for outputting the operation result of the OR operation. The AND gate 321 includes a first input terminal for receiving the phase signal P1, a second input terminal for receiving the zero-crossing signal SZ, and an output terminal for outputting the operation result of the AND operation of the phase signal P1 and the zero-crossing signal SZ. . The AND gate 322 includes a first input terminal for receiving the phase signal P1, a second input terminal for receiving the feedback signal SFB, and an output terminal for outputting the result of the AND operation of the phase signal P1 and the feedback signal SFB. The NOR gate 325 includes a first input terminal for receiving the operation result of the AND gate 321, a second input terminal for receiving the operation result of the AND gate 322, and an output terminal for outputting the operation result of the NOR operation. The flip-flop 320 includes a data input terminal for receiving the supply voltage Vcc, a clock terminal coupled to the output terminal of the OR gate 315 for receiving the operation result of the OR gate 315, and a reset terminal for receiving the NOR gate. The operation result and output terminal of 325 are used to output the phase signal P1, and the reverse output terminal is used to To output the reverse signal of the phase signal P1. The pulse generator 330 includes an input terminal for receiving the reverse signal of the phase signal P1 and an output terminal for outputting the trigger signal TG1.

The phase circuit 806 may include an AND gate 341 and a NAND gate 342, a flip-flop 343 and a pulse generator 345. The AND gate 341 includes a first input terminal for receiving the closed-loop signal CLP, a second input terminal for receiving the trigger signal TG1, and an output terminal for outputting the result of the AND operation of the closed-loop signal CLP and the trigger signal TG1. . The NAND gate 342 includes a first input terminal for receiving the degaussing signal SDM, a second input terminal for receiving the phase signal PA, and an output terminal for outputting the result of the NAND operation of the degaussing signal SDM and the phase signal PA. . The flip-flop 343 includes a data input terminal for receiving the supply voltage Vcc, a clock terminal for receiving the operation result of the AND gate 341, a reset terminal for receiving the operation result of the NAND gate 342, and an output terminal for receiving the operation result of the AND gate 341. The phase signal PA is output, and the reverse output terminal is used to output the reverse signal of the phase signal PA. The pulse generator 345 includes an input terminal for receiving the reverse signal of the phase signal PA, and an output terminal for outputting the trigger signal TGA.

When the closed loop signal CLP is the low voltage VL, the AND gate 310 will be disabled, the flip-flop 320 can be triggered by the trigger signal TG2 to generate the phase signal P1, and the phase signal P1 can be reset by the zero-crossing signal SZ. When the closed loop signal CLP is the high voltage VH, the AND gate 312 will be disabled, the flip-flop 320 can be triggered by the trigger signal TGB to generate the phase signal P1, and can reset the phase signal P1 by the zero-crossing signal SZ and/or the feedback signal SFB. . The pulse generator 330 may be used to generate a dead-time delay of the trigger signal TG1. The longer the space-time delay of the trigger signal TG1 is, the longer the start time of the phase signal P2/PA is delayed, increasing the space time between the end of the phase signal P1 and the start of the phase signal P2/PA.

When the closed loop signal CLP is the low voltage VL, the phase circuit 806 will be disabled. When the closed loop signal CLP is the high voltage VH, the phase circuit 806 will be enabled, and the flip-flop 343 can be triggered by the trigger signal TG1 The trigger generates the phase signal PA, and the phase signal PA can be reset by the degaussing signal SDM. The pulse generator 345 can be used to generate a space-time delay of the trigger signal TGA. The longer the space-time delay of the trigger signal TGA is, the more the start time of the phase signal P2 is delayed, increasing the space time between the end of the phase signal PA and the start of the phase signal P2.

The phase circuit 807 may include AND gates 410, 412, 421 and 422, an OR gate 415, a NOR gate 425, a flip-flop 420, a pulse generator 430 and an inverter 411. The AND gate 410 includes a first input terminal for receiving the trigger signal TGA, a second input terminal for receiving the closed loop signal CLP, and an output terminal for outputting the result of the AND operation of the trigger signal TGA and the closed loop signal CLP. . The inverter 411 includes an input terminal for receiving the closed-loop signal CLP and an output terminal for outputting an inverse signal of the closed-loop signal CLP. The AND gate 412 includes a first input terminal for receiving the reverse signal of the closed-loop signal CLP, a second input terminal for receiving the trigger signal TG1, and an output terminal for outputting the reverse signal and trigger of the closed-loop signal CLP. The result of the AND operation on signal TG1. The OR gate 415 includes a first input terminal for receiving the operation result of the AND gate 410, a second input terminal for receiving the operation result of the AND gate 412, and an output terminal for outputting the operation result of the OR operation. The AND gate 421 includes a first input terminal for receiving the phase signal P2, a second input terminal for receiving the zero-crossing signal SZ, and an output terminal for outputting the operation result of the AND operation of the phase signal P2 and the zero-crossing signal SZ. . The AND gate 422 includes a first input terminal for receiving the phase signal P2, a second input terminal for receiving the feedback signal SFB, and an output terminal for outputting the result of the AND operation of the phase signal P2 and the feedback signal SFB. The NOR gate 425 includes a first input terminal for receiving the operation result of the AND gate 421, a second input terminal for receiving the operation result of the AND gate 422, and an output terminal for outputting the operation result of the NOR operation. The flip-flop 420 includes a data input terminal for receiving the supply voltage Vcc, a clock terminal for receiving the operation result of the OR gate 415, a reset terminal for receiving the operation result of the NOR gate 425, and an output terminal for receiving the operation result of the NOR gate 425. The phase signal P2 is output, and the reverse output terminal is used to output the reverse signal of the phase signal P2. The pulse generator 430 includes an input terminal for receiving the reverse signal of the phase signal P2 and an output terminal for outputting Trigger signal TG2.

The phase circuit 808 may include an AND gate 441, a NAND gate 442, a flip-flop 443 and a pulse generator 445. The AND gate 441 includes a first input terminal for receiving the closed-loop signal CLP, a second input terminal for receiving the trigger signal TG2, and an output terminal for outputting the result of the AND operation of the closed-loop signal CLP and the trigger signal TG2. . The NAND gate 442 includes a first input terminal for receiving the degaussing signal SDM, a second input terminal for receiving the phase signal PB, and an output terminal for outputting the result of the NAND operation of the degaussing signal SDM and the phase signal PB. . The flip-flop 443 includes a data input terminal for receiving the supply voltage Vcc, a clock terminal for receiving the operation result of the AND gate 441, a reset terminal for receiving the operation result of the NAND gate 442, and an output terminal for receiving the operation result of the AND gate 441. The phase signal PB is output, and the reverse output terminal is used to output the reverse signal of the phase signal PB. The pulse generator 445 includes an input terminal for receiving the reverse signal of the phase signal PB, and an output terminal for outputting the trigger signal TGB.

When the closed loop signal CLP is the low voltage VL, the AND gate 410 will be disabled, the flip-flop 420 can be triggered by the trigger signal TG1 to generate the phase signal P2, and can reset the phase signal P2 by the zero-crossing signal SZ. When the closed loop signal CLP is the high voltage VH, the AND gate 412 will be disabled, the flip-flop 420 can be triggered by the trigger signal TGA to generate the phase signal P2, and can reset the phase signal P2 by the zero-crossing signal SZ and/or the feedback signal SFB. . The pulse generator 430 can be used to generate a space-time delay of the trigger signal TG2. The longer the space-time delay of the trigger signal TG2 is, the more the start time of the phase signal P1/PB is delayed, increasing the space time between the end of the phase signal P2 and the start of the phase signal P1/PB.

When the closed loop signal CLP is the low voltage VL, the phase circuit 808 will be disabled. When the closed loop signal CLP is the high voltage VH, the phase circuit 808 is enabled, the flip-flop 443 can be triggered by the trigger signal TG2 to generate the phase signal PB, and can be reset by the degaussing signal SDM. Pulse Generator 445 A space-time delay that can be used to generate the trigger signal TGB. The longer the space-time delay of the trigger signal TGB is, the more the start time of the phase signal PB is delayed, increasing the space time between the end of the phase signal PB and the start of the phase signal P1.

When the power converter 1 is in a light load state, the control circuit 800 can additionally set the pulse generators 330, 345, 430, and 445 to increase the space-time delays of the trigger signals TG1, TGA, TG2, and TGB, thereby increasing the number of switches 10 and 445. 20. The cut-off time (OFF time) of switch 30 and switch 40 to achieve the purpose of power saving.

The embodiments of Figures 1 to 10 are used to control the power converter 1 to operate in a non-regulated mode or a regulated mode to avoid damage to the load and enhance system efficiency.

The above are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the patentable scope of the present invention shall fall within the scope of the present invention.

1: Power converter

10, 20, 30 and 40: switch

50:Flying Capacitor

60:Inductor

70: Output capacitor

800:Control circuit

IL: inductor current

S1 to S4: switch signal

Vin: input voltage

Vo: output voltage

Vx: switching voltage

GND: ground voltage

Claims (26)

A power converter includes: a first switch including a control end and a first end for receiving an input voltage and a second end; a second switch including a control end and a first end, Coupled to the second terminal of the first switch and a second terminal; a third switch including a control terminal and a first terminal coupled to the second terminal of the second switch and a first terminal Two terminals; a fourth switch, including a control terminal, a first terminal, coupled to the second terminal of the third switch, and a second terminal, coupled to a ground terminal; a flying capacitor, including a A first terminal is coupled to the second terminal of the first switch, and a second terminal is coupled to the second terminal of the third switch; an inductor includes a first terminal coupled to the third switch. the second terminal of two switches, and a second terminal; an output capacitor, including a first terminal coupled to the second terminal of the inductor, for outputting an output voltage, and a second terminal coupled to at the ground terminal; and a control circuit coupled to the control terminal of the first switch, the control terminal of the second switch, the control terminal of the third switch and the control terminal of the fourth switch, for When the input voltage is less than an input voltage threshold, the first switch, the second switch, the third switch and the fourth switch are switched according to a resonant frequency. When the input voltage exceeds the input voltage threshold, The first switch, the second switch, the third switch and the fourth switch are switched according to an adjustment frequency exceeding the resonant frequency; if the flying capacitor is coupled to the inductor, the flying capacitor and the inductor will form A resonant circuit with this resonant frequency. The power converter of claim 1, wherein the output voltage is less than or equal to half of the input voltage. The power converter of claim 1, wherein when the input voltage is less than the input voltage threshold, the control circuit is further used to switch the first switch and the second switch when one of the inductor currents of the inductor is 0. , the third switch and the fourth switch. The power converter of claim 1, wherein when the input voltage exceeds the input voltage threshold, the control circuit is used to reduce the ON time of the first switch or the second switch. The power converter as claimed in claim 1, wherein when the power converter is in a light load state, the control circuit is additionally used to add the first switch, the second switch, the third switch and the fourth switch. The deadline (OFF time). The power converter of claim 1, wherein when the input voltage exceeds the input voltage threshold, the control circuit is further used to magnetize the inductor before an inductor current of the inductor reaches 0 Turn off the first switch or the second switch. The power converter of claim 6, wherein when the input voltage exceeds the input voltage threshold, the control circuit is further used to turn on the third switch and the second switch after turning off the first switch or the second switch. The fourth switch is used to demagnetize the inductor. The power converter as claimed in claim 7, wherein when the input voltage exceeds the input voltage When the critical value is reached, the control circuit is also used to demagnetize the inductor and turn off the third switch or the fourth switch when one of the inductor currents of the inductor reaches 0. The power converter of claim 1, wherein: when the first switch and the third switch are turned on, the input voltage charges the flying capacitor and the output capacitor through the inductor; and when the second switch and the When the fourth switch is turned on, the flying capacitor charges the output capacitor through the inductor. The power converter of claim 1, wherein: when the input voltage is less than the input voltage critical value, the output voltage is a divided voltage of the input voltage; and when the input voltage exceeds the input voltage critical value , the power converter operates in a regulation mode. The power converter of claim 1, wherein the power converter operates in discontinuous conduction mode (DCM). The power converter as claimed in claim 1, wherein the control circuit includes: a first phase circuit for controlling the power converter according to a third trigger signal, a fourth trigger signal, a closed loop signal, a zero-crossing signal and a feedback The signal generates a first phase signal and a first trigger signal; a second phase circuit, coupled to the first phase circuit, is used to generate a second phase signal based on the closed loop signal, the first trigger signal and a degaussing signal. phase signal and a second trigger signal; a third phase circuit, coupled to the second phase circuit, for based on the first trigger signal, the third Two trigger signals, the closed loop signal, the zero-crossing signal and the feedback signal generate a third phase signal and the third trigger signal; a fourth phase circuit coupled to the third phase circuit and the first phase circuit , used to generate a fourth phase signal and the fourth trigger signal based on the third trigger signal, the closed loop signal and the degaussing signal; a signal generation circuit coupled to the first phase circuit and the second phase circuit , the third phase circuit and the fourth phase circuit are used to generate a first switching signal, a second phase signal based on the first phase signal, the second phase signal, the third phase signal, and the fourth phase signal. switch signal, a third switch signal and a fourth switch signal. The first switch signal, the second switch signal, the third switch signal and the fourth switch signal are used to switch the first switch, the second switch respectively. switch, the third switch and the fourth switch; a feedback circuit coupled to the first phase circuit, the third phase circuit and the first end of the output capacitor for controlling the first phase signal, the The third phase signal, the output voltage, a reference voltage and the closed loop signal generate the feedback signal; a state detection circuit is coupled to the first end of the output capacitor and the first end of the inductor for The zero-crossing signal and the degaussing signal are generated according to the output voltage, a degaussing reference voltage and a switching voltage at the first end of the inductor; and a closed loop circuit coupled to the status detection circuit and the feedback circuit, The first phase circuit and the third phase circuit are used to generate the closed loop signal based on the zero cross signal, the feedback signal, the first phase signal and the third phase signal. The power converter of claim 12, wherein: the first phase circuit includes: a first AND gate, including: a first input terminal for receiving the fourth trigger signal; a second input terminal for receiving the closed loop signal; and an output terminal; a first inverter including: an input terminal for receiving the closed loop signal; and an output terminal for outputting a reverse signal of the closed loop signal; a second AND gate including: a first input terminal for receiving the reverse signal of the closed loop signal; a second input terminal for receiving the third trigger signal; and an output terminal; a first OR gate, including: a first input terminal coupled to the output terminal of the first AND gate; a second input terminal , coupled to the output end of the second AND gate; and an output end; a third AND gate, including: a first input end for receiving the first phase signal; a second input end for receiving the a zero-cross signal; and an output terminal; a fourth AND gate, including: a first input terminal for receiving the first phase signal; a second input terminal for receiving the feedback signal; and an output terminal; A first NOR gate includes: a first input terminal coupled to the output terminal of the third AND gate; a second input terminal, coupled to the output terminal of the fourth AND gate; and an output terminal; a first flip-flop, including: a data input terminal for receiving a supply voltage; a clock terminal, coupled to The output terminal of the first OR gate; a reset terminal coupled to the output terminal of the first NOR gate; an output terminal for outputting the first phase signal; and an inverting output terminal for to output a reverse signal of the first phase signal; and a first pulse generator including: an input terminal for receiving the reverse signal of the first phase signal; and an output terminal for outputting The first trigger signal; and the second phase circuit include: a fifth AND gate, including: a first input terminal for receiving the closed loop signal; a second input terminal for receiving the first trigger signal ; and an output terminal; a first NAND gate, including: a first input terminal for receiving the degaussing signal; a second input terminal for receiving the second phase signal; and an output terminal; a first Two flip-flops, including: a data input terminal for receiving the supply voltage; a clock terminal coupled to the output terminal of the fifth AND gate; a reset terminal coupled to the first NAND gate The output terminal; an output terminal for outputting the second phase signal; and a reverse output terminal for outputting a reverse signal of the second phase signal; and a second pulse generator including: an input terminal for to receive the reverse signal of the second phase signal; and an output terminal for outputting the second trigger signal. The power converter of claim 12, wherein: the third phase circuit includes: a first AND gate, including: a first input terminal for receiving the second trigger signal; a second input terminal for to receive the closed-loop signal; and an output terminal; a first inverter, including: an input terminal to receive the closed-loop signal; and an output terminal to output an inverted signal of the closed-loop signal ; A second AND gate, including: a first input terminal for receiving the reverse signal of the closed loop signal; a second input terminal for receiving the first trigger signal; and an output terminal; a first An OR gate, including: a first input terminal coupled to the output terminal of the first AND gate; a second input terminal coupled to the output terminal of the second AND gate; and an output terminal; a third AND gate ,Include: a first input terminal for receiving the third phase signal; a second input terminal for receiving the zero-crossing signal; and an output terminal; a fourth AND gate, including: a first input terminal for Receive the third phase signal; a second input terminal for receiving the feedback signal; and an output terminal; a first NOR gate, including: a first input terminal coupled to the output terminal of the third AND gate ; a second input terminal, coupled to the output terminal of the fourth AND gate; and an output terminal; a first flip-flop, including: a data input terminal for receiving a supply voltage; a clock terminal, coupled to at the output terminal of the first OR gate; a reset terminal coupled to the output terminal of the first NOR gate; an output terminal for outputting the third phase signal; and an inverting output terminal, for outputting a reverse signal of the third phase signal; and a first pulse generator, including: an input end for receiving the reverse signal of the third phase signal; and an output end for Output the third trigger signal; and the fourth phase circuit includes: a fifth AND gate, including: a first input terminal for receiving the closed loop signal; a second input terminal for receiving the third trigger signal signal; and An output terminal; a first NAND gate, including: a first input terminal for receiving the degaussing signal; a second input terminal for receiving the fourth phase signal; and an output terminal; a second positive The inverter includes: a data input terminal for receiving the supply voltage; a clock terminal coupled to the output terminal of the fifth AND gate; and a reset terminal coupled to the first NAND gate. an output terminal; an output terminal for outputting the fourth phase signal; and a reverse output terminal for outputting a reverse signal of the fourth phase signal; and a second pulse generator including: an input a terminal for receiving the reverse signal of the fourth phase signal; and an output terminal for outputting the fourth trigger signal. The power converter of claim 12, wherein: the signal generating circuit includes: a first buffer, including: an input terminal for receiving the first phase signal; and an output terminal for outputting the first phase signal. First switching signal: a second buffer, including: an input terminal for receiving the second phase signal: and an output terminal for outputting the second switching signal: A first OR gate, including: a first input terminal for receiving the first phase signal: a second input terminal for receiving the second phase signal: a third input terminal for receiving the fourth phase signal Phase signal: and an output terminal: a third buffer, including: an input terminal coupled to the output terminal of the first OR gate: and an output terminal for outputting the third switching signal: a second The OR gate includes: a first input terminal for receiving the third phase signal: a second input terminal for receiving the second phase signal: and a third input terminal for receiving the fourth phase signal: and an output terminal: and a fourth buffer, including: an input terminal coupled to the output terminal of the second OR gate; and an output terminal for outputting the fourth switching signal. The power converter of claim 12, wherein: the feedback circuit includes: a first NOR gate, including: a first input terminal for receiving the first phase signal: and a second input terminal for receiving the first phase signal. To receive the third phase signal: and an output terminal: a current source, including: a first terminal coupled to a power supply terminal for receiving a supply voltage; and a second terminal: a transistor, including: a control terminal coupled to the output terminal of the first NOR gate: a A first terminal coupled to the second terminal of the current source; and a second terminal coupled to a ground terminal; a first capacitor including: a first terminal coupled to the third terminal of the transistor. One end: and a second end, coupled to the ground end: a first resistor, including: a first end for receiving the output voltage: and a second end: a second resistor, including: a first One end, coupled to the second end of the first resistor: and a second end, coupled to the ground end: a third resistor, including: a first end for receiving the reference voltage: and a The second end: a fourth resistor, including: a first end, coupled to the second end of the third resistor: and a second end: a switch, including: a control end, for receiving the closed loop Signal: a first terminal coupled to the second terminal of the fourth resistor: and a second terminal coupled to the ground terminal: an error amplifier including: an inverting input terminal coupled to the second terminal of the first resistor: a forward input terminal coupled to the third resistor The second terminal: and an output terminal: a fifth resistor, including: a first terminal, coupled to the output terminal of the error amplifier: and a second terminal: a second capacitor, including: a first terminal, coupled to the second terminal of the fifth resistor; and a second terminal coupled to the ground terminal; and a comparator, including: a positive input terminal coupled to the first capacitor. The first terminal: an inverting input terminal, coupled to the first terminal of the fifth resistor: and an output terminal for outputting the feedback signal. The power converter of claim 12, wherein: the state detection circuit includes: a first comparator, including: a forward input terminal for receiving the switching voltage: and a reverse input terminal for receiving the output voltage: and an output terminal: a zero-crossing detector, including: an input terminal coupled to the output terminal of the first comparator; and an output terminal for outputting the zero-crossing signal; a second comparator including: a forward input terminal for receiving the switching voltage; a reverse input terminal for receiving the degaussing reference voltage; and an output The terminal is used to output the degaussing signal: and the closed loop circuit includes: a first inverter, including: an input terminal is used to receive the zero-crossing signal: and an output terminal is used to output the zero-crossing signal. A reverse signal: a first OR gate, including: a first input terminal for receiving the first phase signal: a second input terminal for receiving the third phase signal: and an output terminal: a The second pulse generator includes: an input terminal coupled to the output terminal of the first OR gate; and an output terminal for outputting a first pulse signal; a second inverter including: a An input terminal is used to receive the first pulse signal: and an output terminal is used to output a reset signal: and a flip-flop, including: a data input terminal is used to receive the reverse signal of the zero-crossing signal. : a clock terminal for receiving the feedback signal: a reset terminal for receiving the reset signal: and an output terminal for outputting the closed loop signal. A control method for a power converter. The power converter includes a first switch, a second switch, a third switch, a fourth switch, a flying capacitor, an inductor, an output capacitor and a control circuit. The first switch is A switch includes a control end, a first end for receiving an input voltage, and a second end. The second switch includes a control end, a first end, and is coupled to the second end of the first switch. terminal, and a second terminal, the third switch includes a control terminal, a first terminal coupled to the second terminal of the second switch, and a second terminal, the fourth switch includes a control terminal, A first terminal is coupled to the second terminal of the third switch, and a second terminal is coupled to a ground terminal. The flying capacitor includes a first terminal coupled to the third terminal of the first switch. Two terminals and a second terminal are coupled to the second terminal of the third switch. The inductor includes a first terminal coupled to the second terminal of the second switch and a second terminal. The output capacitor includes a first terminal coupled to the second terminal of the inductor for outputting an output voltage, and a second terminal coupled to the ground terminal, and the control circuit is coupled to the first switch. The first end, the control end of the first switch, the control end of the second switch, the control end of the third switch and the control end of the fourth switch, the control method includes: when the input When the voltage is less than an input voltage threshold, the control circuit switches the first switch, the second switch, the third switch and the fourth switch according to a resonant frequency; and when the input voltage exceeds the input voltage threshold, The control circuit switches the first switch, the second switch, the third switch and the fourth switch according to an adjustment frequency exceeding the resonant frequency; wherein if the flying capacitor is coupled to the inductor, then the flying capacitor and the The inductor forms a resonant circuit with this resonant frequency. The method of claim 18, wherein when the input voltage exceeds the input voltage critical When the value is , the control circuit switches the first switch, the second switch, the third switch and the fourth switch according to the adjustment frequency exceeding the resonant frequency, including: when the input voltage is less than the input voltage threshold, the The control circuit switches the first switch, the second switch, the third switch and the fourth switch when an inductor current of the inductor is 0. The method of claim 18, wherein when the input voltage exceeds the input voltage threshold, the control circuit switches the first switch, the second switch, the third switch and the third switch according to the adjustment frequency exceeding the resonant frequency. The fourth switch includes: when the input voltage exceeds the input voltage threshold, the control circuit reduces the ON time of the first switch or the second switch. The method of claim 18, wherein when the input voltage exceeds the input voltage threshold, the control circuit switches the first switch, the second switch, the third switch and the third switch according to the adjustment frequency exceeding the resonant frequency. The fourth switch includes: when the power converter is in a light load state, the control circuit increases the OFF time of the first switch, the second switch, the third switch and the fourth switch. The method of claim 18, wherein when the input voltage exceeds the input voltage threshold, the control circuit switches the first switch, the second switch, the third switch and the third switch according to the adjustment frequency exceeding the resonant frequency. The fourth switch includes: when the input voltage exceeds the input voltage threshold, the control circuit turns off the first switch or the second switch before an inductor current of the inductor reaches 0 when magnetizing the inductor. switch. The method of claim 22, wherein when the input voltage exceeds the input voltage threshold, the control circuit switches the first switch, the second switch, the third switch and the third switch according to the adjustment frequency exceeding the resonant frequency. The fourth switch also includes: when the input voltage exceeds the input voltage threshold, the control circuit turns on the third switch and the fourth switch after turning off the first switch or the second switch to perform operation on the inductor. Demagnetizing. The method of claim 23, wherein when the input voltage exceeds the input voltage threshold, the control circuit switches the first switch, the second switch, the third switch and the third switch according to the adjustment frequency exceeding the resonant frequency. The fourth switch further includes: when the input voltage exceeds the input voltage threshold, the control circuit turns off the third switch or the fourth switch when an inductor current of the inductor reaches 0 when degaussing the inductor. The method of claim 18, wherein when the input voltage exceeds the input voltage threshold, the control circuit switches the first switch, the second switch, the third switch and the third switch according to the adjustment frequency exceeding the resonant frequency. The fourth switch includes: when the first switch and the third switch are turned on, the input voltage charges the flying capacitor and the output capacitor through the inductor; and when the second switch and the fourth switch are turned on, the input voltage charges the flying capacitor and the output capacitor through the inductor. The flying capacitor charges the output capacitor via the inductor. The method of claim 18, wherein: when the input voltage is less than the input voltage threshold, the control circuit switches the first switch, the second switch, the third switch and the fourth switch according to the resonant frequency. Contains: when the input When the voltage is less than the input voltage threshold, the output voltage is a divided voltage of the input voltage; and when the input voltage exceeds the input voltage threshold, the control circuit switches the third adjustment frequency based on the adjustment frequency exceeding the resonant frequency. A switch, the second switch, the third switch and the fourth switch include: when the input voltage exceeds the input voltage threshold, the power converter operates in a regulation mode.

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