TWI822323B - Voltage gateration circuit and semiconductor memory device - Google Patents

Abstract

Providing a voltage generation circuit and a semiconductor memory device capable of reducing layout size and current consumption. A voltage generation circuit includes a plurality of voltage generation units that generate different output voltages based on the input voltage. Each of the voltage generators has a plurality of resistors connected in series to detect the output voltages. At least one resistor of the resistors is commonly provided among the plurality of voltage generation units.

Description

Voltage generating circuit and semiconductor memory device

The present invention relates to a voltage generating circuit and a semiconductor memory device.

In order to provide a power supply voltage to memory elements or circuits in a semiconductor memory device (such as a dynamic random access memory (DRAM), etc.), it is known (for example, Japanese Patent Application Laid-Open No. 5-74140) to generate a voltage based on an externally supplied voltage. Internal voltage stabilizing circuit (voltage generating section).

All memory elements or circuits in a semiconductor memory device are driven by multiple types of power supply voltages, rather than by a single type of voltage power supply. Therefore, in order to drive all the memory elements or circuits, it is necessary to provide a plurality of voltage generating units that generate different power supply voltages in the semiconductor memory device. At this time, since the number of different power supply voltages increases, the number of voltage generating parts provided in the semiconductor memory device increases. Therefore, the layout size occupied by each voltage generating part in the semiconductor memory device increases, and at the same time, in response to the number of voltage generating parts As the number increases, the current consumption of semiconductor memory devices may increase.

In view of the above problems, an object of the present invention is to provide a voltage generating circuit and a semiconductor memory device that can reduce layout size and current consumption.

The present invention provides a voltage generation circuit, including: a plurality of voltage generation parts that generate different output voltages based on an input voltage; wherein each of the voltage generation parts has a series of complex resistors for detecting the output voltage; At least one resistor among the resistors is provided in common between the voltage generating parts.

In addition, the present invention provides a semiconductor memory device including the voltage generating circuit of the above invention.

According to the invention, it is possible to reduce the layout size occupied by each voltage generating section and at the same time reduce the power consumption of the semiconductor memory device.

According to the voltage generation circuit and the semiconductor memory device of the present invention, layout size and current consumption can be reduced.

Hereinafter, the voltage generation circuit and the semiconductor memory device according to the embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, this embodiment is only an example, and the present invention is not limited thereto.

FIG. 1 is a block diagram showing an example of the configuration of the voltage generating circuit 10 of the semiconductor memory device according to the first embodiment of the present invention. The voltage generation circuit 10 is provided in a semiconductor memory device (eg, DRAM, etc.) and is configured to generate a power supply voltage for driving memory elements or circuits in the semiconductor memory device. In this embodiment, the voltage generation circuit 10 includes a first voltage generation part 11, a second voltage generation part 12, a third voltage generation part 13 and a control part 14 (shown in FIG. 2). In order to simplify the description here, other conventional structures of the semiconductor memory device (such as memory cell arrays or instruction decoders, etc.) are not shown.

In this embodiment, each of the first voltage generation part 11, the second voltage generation part 12, and the third voltage generation part 13 is configured to use the external voltage power supply VDD as an input voltage and generate different outputs based on the input voltage. Voltage V1, V2, V3 (for example: VDD>V1>V2>V3). Specifically, the first voltage generation unit 11 generates the output voltage V1, the second voltage generation unit 12 generates the output voltage V2, and the third voltage generation unit 13 generates the output voltage V3. Although the case where the external voltage power supply VDD is used as the input voltage is taken as an example here, the input voltage may also be other voltages other than the external voltage power supply VDD (for example, other voltages generated based on the external voltage power supply VDD).

The first voltage generating part 11 is a linear regulator (regulator), including: P-channel type metal oxide semi-field effect transistors (MOSFETs) 11a, 11b, 11c; an error amplifier 11d; and a series circuit for detecting the output voltage V1 Complex numbers (four in this embodiment) of resistors R1, R2, R3, R4.

The MOSFET 11a is provided between the input terminal of the first voltage generating section 11 (the terminal to which the external voltage power supply VDD is applied as the input voltage) and the input terminal of the MOSFET 11b (herein, the source), and is arranged so as to be controlled by a second control device to be described later. Signal EN1O is activated. In addition, the MOSFET 11a is an example of the "second switching part" of the present invention.

The MOSFET 11b is connected between the input terminal of the first voltage generating section 11 (through the MOSFET 11a) and the output terminal for outputting the output voltage V1, and is configured to be controlled by the error amplifier 11d. In addition, MOSFET 11b is an example of the "output driver" of the present invention.

MOSFET 11c is provided between the output terminal (here, the drain) of MOSFET 11b and the plurality of resistors R1, R2, R3, and R4, and is configured to be controlled by a first control signal EN1I described below. In addition, the MOSFET 11c is an example of the "first switching unit" of the present invention.

The error amplifier 11d is configured to compare a specific reference voltage VREF, and to compare the output voltage V1 between at least one resistor (here, resistor R4) among the plurality of resistors R1, R2, R3, R4 and other resistors (here, resistors R1, R4). R2, R3) divides the voltage VDET between them, and controls the MOSFET 11b based on the comparison result. In addition, the error amplifier 11d is an example of the "comparison part" of the present invention.

A plurality of resistors R1, R2, R3, R4 are connected between the output terminal (here the drain) of the MOSFET 11b (through the MOSFET 11c) and a low-voltage power supply lower than the external voltage power supply VDD. Here, at least one resistor (here, resistor R4) among the plurality of resistors R1, R2, R3, and R4 is connected between the other resistors (here, resistors R1, R2, and R3) and the low-voltage power supply, and the other resistors (here, resistors R4 R1, R2, R3) are connected between the output terminal (here the drain) of MOSFET 11b (through MOSFET 11c) and at least 1 resistor (resistor R4).

The source of MOSFET 11a is connected to the external voltage power supply VDD, and the drain of MOSFET 11a is connected to the source of MOSFET 11b. In addition, the second control signal EN1O is applied to the gate of MOSFET 11a. Furthermore, the drain of MOSFET 11b is connected to the source of MOSFET 11c, and the gate of MOSFET 11b is connected to the output terminal of error amplifier 11d. In addition, the drain terminal of the MOSFET 11c is connected to one end of the resistor R1, and the first control signal EN1I is applied to the gate terminal of the MOSFET 11c. A plurality of resistors R1, R2, R3, and R4 are connected in series between the drain of the MOSFET 11c and the low power supply voltage. In addition, a node between the resistor R3 and the resistor R4 is connected to one of the input terminals of the error amplifier 11d, and the reference voltage VREF is applied to the other input terminal of the error amplifier 11d.

The error amplifier 11d compares the voltage VDET input to one of the input terminals with the reference voltage VREF, and outputs the comparison result to the MOSFET 11b as a signal PGON. Here, when the voltage VDET < the reference voltage VREF, the error amplifier 11d generates the signal PGON and outputs it to the MOSFET 11b. The signal PGON causes the startup resistance of the MOSFET 11b to decrease (that is, the output voltage V1 increases). In addition, when voltage VDET>reference voltage VREF, error amplifier 11d generates signal PGON and outputs it to MOSFET 11b. This signal PGON increases the startup resistance of MOSFET 11b (that is, the output voltage V1 decreases).

The second voltage generating part 12 is a linear voltage regulator, including: P-type MOSFETs 12a, 12b, 12c; an error amplifier 11d; and a series of complex (three in this embodiment) resistors for detecting the output voltage V2. R2, R3, R4. That is, the second voltage generating section 12 and the first voltage generating section 11 share the error amplifier 11d and the complex resistors R2, R3, and R4.

MOSFET 12a is provided between the input terminal of the second voltage generating section 12 (the input terminal to which external voltage power supply VDD is applied as the input voltage) and the input terminal of MOSFET 12b (source here), and is arranged to be controlled by the second Signal EN2O is on. In addition, the MOSFET 12a is an example of the "second switching part" of the present invention.

The MOSFET 12b is connected between the input terminal of the second voltage generating section 12 (through the MOSFET 12a) and the output terminal for outputting the output voltage V2, and is configured to be controlled by the error amplifier 11d. In addition, MOSFET 12b is an example of the "output driver" of the present invention.

MOSFET 12c is provided between the output terminal (here, the drain) of MOSFET 12b and the plurality of resistors R2, R3, and R4, and is configured to be controlled by the first control signal EN2I. In addition, the MOSFET 12c is an example of the "first switching unit" of the present invention.

The error amplifier 11d is configured to compare a specific reference voltage VREF and to compare the output voltage V2 between at least one of the plurality of resistors R2, R3 and R4 (here the resistor R4) and the other resistor (here the resistors R2 and R3). The voltage VDET is divided between them, and the MOSFET 12b is controlled based on the comparison result.

The part about the complex resistors R2, R3, and R4 is as described above.

The source of MOSFET 12a is connected to the external voltage power supply VDD, and the drain of MOSFET 12a is connected to the source of MOSFET 12b. In addition, the second control signal EN2O is applied to the gate of MOSFET 12a. Furthermore, the drain of MOSFET 12b is connected to the source of MOSFET 12c, and the gate of MOSFET 12b is connected to the output terminal of error amplifier 11d. In addition, the drain terminal of the MOSFET 12c is connected to one end of the resistor R2, and the first control signal EN2I is applied to the gate terminal of the MOSFET 12c. Complex resistors R2, R3, and R4 are connected in series between the drain of MOSFET 12c and the low supply voltage.

The error amplifier 11d compares the voltage VDET input to one of the input terminals with the reference voltage VREF, and outputs the comparison result to the MOSFET 12b as a signal PGON. Here, when voltage VDET < reference voltage VREF, error amplifier 11d generates signal PGON and outputs it to MOSFET 12b. This signal PGON causes the startup resistance of MOSFET 12b to decrease (that is, the output voltage V2 increases). In addition, when voltage VDET>reference voltage VREF, error amplifier 11d generates signal PGON and outputs it to MOSFET 12b. This signal PGON causes the startup resistance of MOSFET 12b to increase (that is, the output voltage V2 decreases).

The third voltage generating part 13 is a linear voltage regulator, including: P-type MOSFETs 13a, 13b, 13c; an error amplifier 11d; and a series-connected complex number (two in this embodiment) resistors for detecting the output voltage V3. R3, R4. That is, the third voltage generating section 13 shares the error amplifier 11d and the complex resistors R3 and R4 with the first voltage generating section 11 and the second voltage generating section 12 .

MOSFET 13a is provided between the input terminal of the third voltage generating section 13 (the input terminal to which external voltage power supply VDD is applied as the input voltage) and the input terminal of MOSFET 13b (source here), and is arranged to be controlled by the second Signal EN3O is on. In addition, the MOSFET 13a is an example of the "second switching part" of the present invention.

The MOSFET 13b is connected between the input terminal of the third voltage generating section 13 (through the MOSFET 13a) and the output terminal for outputting the output voltage V3, and is configured to be controlled by the error amplifier 11d. In addition, MOSFET 13b is an example of the "output driver" of the present invention.

MOSFET 13c is provided between the output terminal (here, the drain) of MOSFET 13b and the plurality of resistors R3 and R4, and is configured to be controlled by the first control signal EN3I. In addition, MOSFET 13c is an example of the "first switching unit" of the present invention.

The error amplifier 11d is configured to compare a specific reference voltage VREF and divide the output voltage V3 between at least one of the plurality of resistors R3 and R4 (here the resistor R4) and the other resistor (here the resistor R3). voltage VDET, and controls the MOSFET 13b based on the comparison result.

The part about the complex resistors R3~R4 is as mentioned above.

The source of MOSFET 13a is connected to the external voltage power supply VDD, and the drain of MOSFET 13a is connected to the source of MOSFET 13b. In addition, the second control signal EN3O is applied to the gate of MOSFET 13a. Furthermore, the drain of MOSFET 13b is connected to the source of MOSFET 13c, and the gate of MOSFET 13b is connected to the output terminal of error amplifier 11d. In addition, the drain terminal of MOSFET 13c is connected to one end of resistor R3, and the first control signal EN3I is applied to the gate terminal of MOSFET 13c. The complex resistors R3~R4 are connected in series between the drain terminal of the MOSFET 13c and the low power supply voltage.

The error amplifier 11d compares the voltage VDET input to one of the input terminals with the reference voltage VREF, and outputs the comparison result to the MOSFET 13b as a signal PGON. Here, when voltage VDET < reference voltage VREF, error amplifier 11d generates signal PGON and outputs it to MOSFET 13b. This signal PGON causes the startup resistance of MOSFET 13b to decrease (that is, the output voltage V3 increases). In addition, when voltage VDET>reference voltage VREF, error amplifier 11d generates signal PGON and outputs it to MOSFET 13b. This signal PGON increases the startup resistance of MOSFET 13b (that is, the output voltage V3 decreases).

Next, the structure of the control unit 14 will be described with reference to FIG. 2 . The control unit 14 includes an oscillator 14a, a counter 14b, and a decoder 14c.

The oscillator 14a generates an oscillation signal OSC at specific intervals and outputs it to the counter 14b.

The counter 14b counts the pulses of the oscillation signal OSC output from the oscillator 14a, and outputs a signal CNTV showing the count value of the pulses to the decoder 14c. Here, each time the count value of the pulse reaches a specific value (for example, 5), it can be reset to the initial value (for example, 0). In addition, the counter 14b counts the pulses of the oscillation signal OSC output from the oscillator 14a, and outputs a signal CNTS indicating the count value of the pulses to the update control unit 15.

The decoder 14c generates the first control signals EN1I, EN2I, EN3I and the second control signals EN1O, EN2O, EN3O respectively based on the count value displayed by the signal CNTV, and converts the generated first control signals EN1I, EN2I, EN3I and the second control signal EN1O, EN2O, and EN3O are output to the first voltage generating unit 11, the second voltage generating unit 12, and the third voltage generating unit 13.

The update control unit 15 is configured to perform an update operation of the memory cells (omitted in the illustration) in the semiconductor memory device every time the count value displayed by the signal CNTS reaches a specific value.

Here, the control unit 14 can control and drive any one of the plural voltage generating units 11, 12, and 13 (for example, the first voltage generating unit 11). Therefore, the control unit 14 can cause only any one of the plurality of voltage generating units 11, 12, and 13 (for example, the first voltage generating unit 11) to generate an output voltage (for example, the output voltage V1).

For example, the decoder 14c of the control unit 14 may also activate the MOSFET 11c by outputting the low-level first control signal EN1I to the MOSFET 11c of the first voltage generating unit 11, and output the low-level second control signal EN1O to the MOSFET 11c. The MOSFET 11a of the first voltage generating section 11 activates the MOSFET 11a to drive the first voltage generating section 11. At this time, the control unit 14 may also turn off the MOSFETs 12c and 13c by outputting high-level first control signals EN2I and EN3I to the MOSFET 12c and the MOSFET 13c of the third voltage generation unit 12 and 13, respectively. The high-level second control signals EN2O and EN3O are output to the MOSFET 12a of the second voltage generating part 12 and the MOSFET 13a of the third voltage generating part 13. The MOSFETs 12a and 13a are turned off to stop driving the second voltage generating part 12 and the third voltage. Generation part 13.

In addition, the control unit 14 may switch the voltage generating units driven among the plural voltage generating units 11, 12, and 13 at each specific timing. Therefore, the voltage generating unit driven can be changed at each specific timing.

Furthermore, when the number of pulses of the clock signal reaches a specific value at a specific time, the control unit 14 may switch the driven voltage generating unit among the plural voltage generating units 11 , 12 , and 13 . Therefore, each time the number of pulses of the specific clock signal reaches a specific value, the driven voltage generating unit can be changed.

For example, the decoder 14c of the control unit 14 may switch the driven voltage generating unit each time the count value displayed by the signal CNTV increases by a specific value (for example, 2). For example, when the driven voltage generating unit is switched from the first voltage generating unit 11 to the second voltage generating unit 12, the decoder 14c can output the first control signal EN1I changed from a low level to a high level to the first voltage generating unit. The MOSFET 11c of the part 11 turns off the MOSFET 11c, and outputs the second control signal EN1O changed from the low level to the high level to the MOSFET 11a of the first voltage generating part 11 to turn off the MOSFET 11a to stop driving the first voltage generating part 11. In addition, the control unit 14 may also activate the MOSFET 12c by outputting the first control signal EN2I that changes from the high level to the low level to the MOSFET 12c of the second voltage generating unit 12, and changes the first control signal EN2I from the high level to the low level. The control signal EN2O is output to the MOSFET 12a of the second voltage generating part 12 to activate the MOSFET 12a to drive the second voltage generating part 12. In addition, for example, when the driven voltage generating unit is switched from the second voltage generating unit 12 to the third voltage generating unit 13 or the first voltage generating unit 11, the control unit 14 may control the MOSFETs 12a and 12 of the second voltage generating unit 12 to turn off. 12c, and start the MOSFET of the driven voltage generating part (MOSFET 13a, 13c or MOSFET 11a, 11c).

Furthermore, the control unit 14 may switch the voltage generating units driven among the plural voltage generating units 11, 12, and 13 in a specific order. Therefore, the driven voltage generating section can be changed in a specific order.

For example, the decoder 14c of the control unit 14 may switch the driven voltage generating unit according to a specific driving sequence (for example, repeating the sequence of the first voltage generating unit 11, the second voltage generating unit 12, and the third voltage generating unit 13). Here, the information about the driving sequence can be stored in, for example, a mode register (omitted in the figure) in the semiconductor memory device or a storage circuit provided in the decoder 14c. In addition, the information about the driving sequence can be changed at any time.

FIG. 3 is a timing chart showing an example of the operation of the voltage generating circuit 10 according to this embodiment. First, at time t1, when the decoder 14c of the control unit 14 receives the count value (here 0) displayed by the signal CNTV from the counter 14b, it generates the first control signal EN1I of low level and generates the first control signal EN1I of high level. 1 control signals EN2I, EN3I and 2nd control signals EN1O, EN2O, EN3O. Therefore, the MOSFET 11c of the first voltage generating unit 11 is turned on, and the other MOSFETs 11a, 12a, 12c, 13a, and 13c are turned off. Next, at time t2, when the decoder 14c of the control unit 14 receives the count value (here 1) displayed by the signal CNTV from the counter 14b, it generates the first control signal EN1I and the second control signal EN1O of low level, And generate high-level first control signals EN2I, EN3I and second control signals EN2O, EN3O. Therefore, the MOSFETs 11a and 11c of the first voltage generating unit 11 are activated to drive the first voltage generating unit 11. At this time, the error amplifier 11d reduces the startup resistance of the MOSFET 11b by generating the signal PGON based on the comparison result between the reference voltage VREF and the voltage VDET (here, VREF>VDET), so that the output voltage V1 rises to the target voltage.

Next, at time t3, when the decoder 14c of the control unit 14 receives the count value (here 2) displayed by the signal CNTV from the counter 14b, it generates the first control signal EN2I of low level and generates the first control signal EN2I of high level. 1 control signals EN1I, EN3I and 2nd control signals EN1O, EN2O, EN3O. Therefore, the MOSFET 12c of the second voltage generating unit 12 is turned on, and the other MOSFETs 11a, 11c, 12a, 13a, and 13c are turned off. Next, at time t4, when the decoder 14c of the control unit 14 receives the count value (here, 3) displayed by the signal CNTV from the counter 14b, it generates the first control signal EN2I and the second control signal EN2O of low level, And generate high-level first control signals EN1I, EN3I and second control signals EN1O, EN3O. Therefore, the MOSFETs 12a and 12c of the second voltage generating unit 12 are activated, and the second voltage generating unit 12 is driven. At this time, the error amplifier 11d reduces the startup resistance of the MOSFET 12b by generating the signal PGON based on the comparison result between the reference voltage VREF and the voltage VDET (here, VREF>VDET), so that the output voltage V2 rises to the target voltage.

Next, at time t5, when the decoder 14c of the control unit 14 receives the count value (here 4) displayed by the signal CNTV from the counter 14b, it generates the first control signal EN3I of low level and generates the first control signal EN3I of high level. 1 control signals EN1I, EN2I and 2nd control signals EN1O, EN2O, EN3O. Therefore, the MOSFET 13c of the third voltage generating unit 13 is turned on, and the other MOSFETs 11a, 11c, 12a, 12c, and 13a are turned off. Next, at time t6, when the decoder 14c of the control unit 14 receives the count value (here, 5) displayed by the signal CNTV from the counter 14b, it generates the first control signal EN3I and the second control signal EN3O of low level, And generate high-level first control signals EN1I, EN2I and second control signals EN1O, EN2O. Therefore, the MOSFETs 13a and 13c of the third voltage generating unit 13 are activated, and the third voltage generating unit 13 is driven. At this time, the error amplifier 11d reduces the startup resistance of the MOSFET 13b by generating the signal PGON based on the comparison result between the reference voltage VREF and the voltage VDET (here, VREF>VDET), so that the output voltage V3 rises to the target voltage.

In addition, after time t7, the operations from time t1 to time t6 are repeated.

In this way, the voltage generating units driven in the complex voltage generating units 11, 12, and 13 can be switched at each specific timing (here, each time the number of pulses of the clock signal reaches a specific value).

Here, the effect of reducing current consumption of the voltage generation circuit 10 according to this embodiment will be described. For example, when the reference voltage VREF is 0.8V, the resistance of resistor R1 is 200kΩ, the resistance of resistor R2 is 100kΩ, the resistance of resistor R3 is 200kΩ, and the resistance of resistor R4 is 800kΩ, the output voltages V1, V2, and V3 are calculated as follows.

V1=VREF×(R1+R2+R3+R4)/R4=1.3V

V2=VREF×(R2+R3+R4)/R4=1.1V

V3=VREF×(R3+R4)/R4=1.0V

In addition, when the current consumption of the error amplifier 11d is 1 μA and only the output voltage V1 is generated among the output voltages V1, V2, and V3, the current consumption (excluding the supply current) I of the voltage generation circuit 10 can be calculated as follows.

I=current consumption of the error amplifier 11d + current consumption of the resistor of the first voltage generating section 11=1μA+1.3/1300kΩ=2μA

On the other hand, for example, when the error amplifier 11d and the complex resistors R1, R2, R3, and R4 are provided independently of each other instead of sharing the error amplifier 11d, R2, R3, and R4 in each of the complex voltage generating units 11, 12, and 13, each of the voltage generating units 11, 12, and 13 One generates the output voltage V1, At V2 and V3, the total current consumption I′ of each voltage generating unit 11, 12, and 13 can be calculated as follows.

I′=current consumption of the error amplifier 11d of each voltage generating unit 11, 12, 13 + current consumption of the resistor of each voltage generating unit 11, 12, 13=1μA×3+1.3V/1300kΩ+1.1V/1100kΩ+1.0 V/1000kΩ=6μA

Therefore, compared with the case where each of the complex voltage generating sections 11, 12, 13 is provided with the error amplifier 11d and the complex resistors R1, R2, R3, R4 independently of each other instead of sharing them, the voltage generation according to this embodiment Circuit 10 can reduce current consumption to 1/3.

In addition, the driving stop period of each voltage generating unit 11, 12, 13 may be set in accordance with, for example, the load current or capacitance of the voltage generating unit. For example, when the load current I _OUT is 20 μA, the capacitance C _OUT is 2 nF, and the target value dV of the voltage drop during driving stop is 50 mV, the driving stop period dT_max can be calculated as follows.

dT_max=C _OUT ×dV/I _OUT =2nF×50mV/20μA=5μs

This means that when the drive stop period is shorter than 5 μs, the voltage drop during drive stop can be set to less than 50 mV.

In addition, in order to minimize noise (switching noise) caused by the voltage generating part of the switching drive, it is preferable to adjust the starting resistance of the MOSFET 11b, 12b, 13b of each voltage generating part 11, 12, 13 to be equal. . Here, since the load currents of the voltage generating units 11, 12, and 13 are different from each other depending on the level of the output voltage, for example, when the gate widths of the MOSFETs 11b, 12b, and 13b are linearly determined according to the load current, by corresponding Load current adjustment MOSFET 11b, 12b, 13b The size can be set to make the starting resistance equal. For example, when the load current of the first voltage generating part 11 is four times the load current of the second voltage generating part 12, the gate width of the MOSFET 11b of the first voltage generating part 11 can be adjusted to the size of the second voltage generating part. 12 is 4 times the gate width of MOSFET 12b. Therefore, noise (switching noise) caused by switching of the driven voltage generating section can be minimized.

As described above, in this embodiment, at least one resistor among the plurality of resistors R1, R2, R3, and R4 is provided in common between the plurality of voltage generating units 11, 12, and 13. In addition, the complex resistors R2, R3, and R4 are provided in common between the complex voltage generating units 11 and 12. Therefore, since at least one of the complex resistors included in each of the complex voltage generating sections 11 , 12 , 13 can be shared between the complex voltage generating sections 11 , 12 , 13 , and for example, the complex voltage generating sections 11 , 12 , 13, by setting independent resistors instead of sharing any resistor, the layout size occupied by each voltage generating section 11, 12, 13 can be reduced, and the current consumption of the semiconductor memory device can be reduced.

In addition, in this embodiment, the error amplifier 11d is provided in common between the complex voltage generating units 11, 12, and 13. Therefore, for example, since the complex voltage generating sections 11, 12, and 13 can share a single error amplifier 11d, the layout size occupied by each voltage generating section 11, 12, and 13 can be reduced, and the current consumption of the semiconductor memory device can be reduced.

Next, a second embodiment of the present invention will be described. At least one voltage generating unit 11 among the plural voltage generating units 11, 12, and 13 of the voltage generating circuit 10 is different from the first voltage generating unit 11 in that it includes a boosting circuit 11e that boosts an input voltage (external voltage power supply VDD) and generates an output voltage V1. 1 The embodiments are different. Configurations different from those of the first embodiment will be described below.

FIG. 4 shows a structural example of the voltage generating circuit 10 of the semiconductor memory device according to this embodiment. In this embodiment, the first voltage generating unit 11 is provided with a boosting circuit 11e instead of the MOSFET 11a.

The boosting circuit 11e is configured to boost the input voltage (external voltage power supply VDD) in response to the oscillation signal OSC output from the oscillator 14a of the control unit 14, and generate the output voltage V1. In this embodiment, the boost circuit 11e is configured to boost the input voltage when the second control signal EN1O is at a low level when the reference voltage VREF>voltage VDET. In addition, the boost circuit 11e may also be constructed using a conventional charge pump.

FIG. 5 is a timing chart of an example of the operation of the voltage generation circuit 10 according to this embodiment. First, at time t11, when the decoder 14c of the control unit 14 receives the count value (here 00) displayed by the signal CNTV from the counter 14b, it generates the first control signal EN1I of low level and generates the first control signal EN1I of high level. 1 control signals EN2I, EN3I and 2nd control signals EN1O, EN2O, EN3O. Therefore, the MOSFET 11c of the first voltage generating unit 11 is turned on, and the other MOSFETs 12a, 12c, 13a, and 13c are turned off. Next, at time t12, when the decoder 14c of the control unit 14 receives the count value (here, 02) displayed by the signal CNTV from the counter 14b, it generates the first control signal EN1I and the second control signal EN1O of low level, And generate high-level first control signals EN2I, EN3I and second control signals EN2O, EN3O. Therefore, while the boost circuit 11e of the first voltage generating unit 11 is driven, the MOSFET 11c is turned on and the first voltage generating unit 11 is driven. At this time, by the boost circuit 11e at time t13 and time t14 In response to the oscillation signal OSC, the boost input voltage (external voltage power supply VDD) is triggered (toggle), and the output voltage V1 rises to the target voltage. In addition, the voltage boosting circuit 11e stops the voltage boosting operation when the reference voltage VREF < voltage VDET at time t14. Afterwards, when the reference voltage VREF > the voltage VDET at time t15, the boost circuit 11e responds to the toggle of the oscillation signal OSC and restarts the boosting operation.

Next, at time t16, when the decoder 14c of the control unit 14 receives the count value (here, 08) displayed by the signal CNTV from the counter 14b, it generates the first control signal EN2I of low level, and generates the first control signal EN2I of high level. The first control signals EN1I, EN2I and the second control signals EN1O, EN2O, EN3O. In addition, the operation from time t16 to time t17 is the same as the operation from time t3 to time t5 shown in FIG. 3 .

Next, at time t17, when the decoder 14c of the control unit 14 receives the count value (0C here) displayed by the signal CNTV from the counter 14b, it generates the first control signal EN3I of low level and generates the first control signal EN3I of high level. The first control signals EN1I, EN2I and the second control signals EN1O, EN2O, EN3O. In addition, the operation from time t17 to time t18 is the same as the operation from time t5 to time t7 shown in FIG. 3 .

In addition, after time t18, the operations from time t11 to t17 are repeated.

As described above, according to the voltage generation circuit 10 and the semiconductor memory device of this embodiment, at least one voltage generation unit (the first voltage generation unit 11) among the plurality of voltage generation units 11, 12, and 13 can generate a voltage higher than the input voltage. (External voltage supply VDD) high output voltage V1.

In this embodiment, the case where the first voltage generating unit 11 includes the boosting circuit 11e is taken as an example, but it is not limited to this. The second voltage generating section 12 or the third voltage generating section The generating unit 13 may include a voltage boosting circuit instead of the first voltage generating unit 11, and the first voltage generating unit 11, the second voltage generating unit 12, and the third voltage generating unit 13 may all include a boosting circuit.

Each of the embodiments described above is described in order to make the present invention easier to understand, and the above description is not intended to limit the present invention. Therefore, each element disclosed in the above embodiments is intended to include all design changes or equivalents that fall within the technical scope of the present invention.

For example, in the first embodiment, the case where the driven voltage generating unit is switched every time the clock number of the oscillation signal OSC reaches a specific value (for example, 2) is taken as an example, but the present invention is not limited to this. For example, when it is desired to set the driving interval (voltage generation interval) of any one of the plurality of voltage generating units 11, 12, and 13 to be longer than that of the other voltage generating units, as shown in FIG. 6, by The first control signals EN1I, EN2I, and EN3I and the second control signals EN1O, EN2O, and EN3O are masked when they change to a low level, or they can maintain a high level (that is, maintaining the driving stop state of the corresponding voltage generating unit). Therefore, since the state in which the driving of the voltage generating section is stopped can be simply extended, the current consumption of the voltage generating circuit 10 can be reduced.

In addition, in each of the above embodiments, the case where the "output driver", "first switching part" and "second switching part" of the present invention are composed of P-channel MOSFETs is taken as an example, but the present invention is not limited to this. For example, the "output driver", "first switching part" and "second switching part" may be composed of N-channel MOSFETs, or may be composed of other transistors or switching elements.

Furthermore, in each of the above embodiments, although the first voltage generating unit 11. The case where the second voltage generating part 12 and the third voltage generating part 13 are linear voltage regulators is taken as an example, but the present invention is not limited thereto. For example, the first voltage generating unit 11, the second voltage generating unit 12, and the third voltage generating unit 13 may be other regulators such as switching regulators.

In addition, the configurations of the voltage generating circuit 10 and the components 11 to 14 shown in FIGS. 1 , 2 and 4 are only examples and may be appropriately changed, and a conventional configuration or other various configurations may be adopted.

10: Voltage generation circuit

11: 1st voltage generating section

11a, 11b, 11c: Metal Oxygen Semi-field Effect Transistor (MOSFET)

11d: Error amplifier

11e: Boost circuit

12: Second voltage generating section

12a, 12b, 12c: Metal-oxide semi-field effect transistor (MOSFET)

13: 3rd voltage generation section

13a, 13b, 13c: Metal-oxide semi-field effect transistor (MOSFET)

14:Control Department

14a:Oscillator

14b: Counter

14c: decoder

15:Update Control Department

CNTS, CNTV: signal

EN1I, EN2I, EN3I: 1st control signal

EN1O, EN2O, EN3O: second control signal

OSC: oscillation signal

PGON: signal

R1, R2, R3, R4: Resistors

V1, V2, V3: output voltage

VDD: external voltage power supply

VDET: voltage

VREF: reference voltage

FIG. 1 is a diagram showing a configuration example of a voltage generating circuit according to the first embodiment of the present invention. Figure 2 is a block diagram showing an example of the structure of the control unit. Figure 3 is a timing diagram of the time transition of signals in the voltage generating circuit. FIG. 4 is a diagram illustrating a configuration example of a voltage generating circuit according to the second embodiment of the present invention. Figure 5 is a timing diagram of the time transition of signals in the voltage generating circuit. FIG. 6 is a timing chart showing the time transition of signals in the voltage generating circuit according to the modified example.

10: Voltage generation circuit

11: 1st voltage generating section

11a, 11b, 11c: Metal Oxygen Semi-field Effect Transistor (MOSFET)

11d: Error amplifier

12: Second voltage generating section

12a, 12b, 12c: Metal-oxide semi-field effect transistor (MOSFET)

13: 3rd voltage generating section

13a, 13b, 13c: Metal-oxide semi-field effect transistor (MOSFET)

EN1I, EN2I, EN3I: 1st control signal

EN1O, EN2O, EN3O: second control signal

PGON: signal

R1, R2, R3, R4: Resistors

V1, V2, V3: output voltage

VDD: external voltage power supply

VREF: reference voltage

Claims (12)

A voltage generating circuit, including: a plurality of voltage generating parts that generate different output voltages based on an input voltage; and a control part that controls and drives any one of the voltage generating parts; wherein each of the voltage generating parts Or, it has a plurality of resistors connected in series for detecting the output voltage; at least one resistor among the resistors is commonly provided between the voltage generating parts. The voltage generation circuit of claim 1, wherein: each of the voltage generation parts includes: a comparison part that compares a specific reference voltage with a divided voltage, the divided voltage being the output voltage in the resistors. The voltage divided between the at least one resistor and other resistors among the resistors; wherein the comparison part is commonly provided between the voltage generating parts. The voltage generating circuit of claim 2, wherein: each of the voltage generating parts further includes: an output driver, connected between the input terminal for applying the input voltage and the output terminal for outputting the output voltage, and is driven by The comparison section controls. The voltage generating circuit of claim 3, wherein: the at least 1 resistor is connected between other resistors of the resistors and the low-voltage power supply; the other resistors of the resistors are connected between the output terminal of the output driver and the at least 1 resistor. between resistors. Such as the voltage generating circuit of claim 4, wherein: The specific reference voltage is applied to one of the input terminals of the comparison part; the other input terminal of the comparison part is connected to a node between the at least one resistor and other resistors among the resistors. In the voltage generating circuit of claim 4, a first switch portion turned on by a specific first control signal is provided between the output terminal of the output driver and the resistors. In the voltage generating circuit of claim 4, a second switch portion turned on by a specific second control signal is provided between the input terminal of each of the voltage generating portions and the input terminal of the output driver. In the voltage generating circuit of claim 1, at least one of the voltage generating parts includes a boost circuit that boosts the input voltage and generates the output voltage. In the voltage generating circuit of claim 1, the control unit switches the voltage generating unit driven among the voltage generating units at each specific timing. In the voltage generating circuit of claim 9, the control unit switches the voltage generating unit driven among the voltage generating units when the number of pulses of the specific clock signal reaches a specific value. In the voltage generating circuit of claim 1, the control unit switches the voltage generating unit driven among the voltage generating units in a specific order. A semiconductor memory device including the voltage generating circuit of any one of claims 1 to 11.

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