TWI822219B - Operation circuit having lower calibration time and calibration method thereof - Google Patents

Abstract

A calibration method for calibrating an operation circuit which has a variant offset and includes at least one comparator circuit having first variant offset. The calibration method configured to provide an adjustable offset to calibrate the variant offset includes: P100: reseting a test calibration deviation to an original value and configuring the operation circuit to a calibration mode, and then conducting an original calibration procedure according to the comparator circuit to decide an operating calibration code having N bits; P200: configuring the operation circuit to an operation mode, and then conducting a predetermined operation procedure according to the operating calibration code, wherein the operating calibration code corresponds to the adjustable offset; P300: conducting a less bit number calibration procedure according to the test calibration deviation and a test calibration code to renew the test calibration deviation or the operating calibration code, and then go back to P200.

Description

Operating circuit with low correction period and correction method therein

The present invention relates to an operating circuit, and in particular to an operating circuit with a low correction period. The invention also relates to a correction method with a low correction period.

Please refer to Figure 1A and Figure 1B. Figure 1A shows the relationship between the changing offset value of the comparison circuit and the temperature change. FIG. 1B shows a prior art operating circuit (operating circuit 1000) that can correct offset values. As shown in Figure 1A, due to the manufacturing process, there is a variable offset value (offset) between the actual comparator and the ideal comparator. In other words, the actual comparator is not ideal, and there is a variable offset between the actual comparator and the ideal comparator. There is a changing offset value. In addition, for example, as the ambient temperature changes or other environmental factors change, the above-mentioned variation offset value also changes accordingly. For example, when the temperature is Tp1, the corresponding variation offset value is Vv1, and when the temperature changes to Tp2, the variation offset value correspondingly changes to Vv2. As shown in FIG. 1B , in the operating circuit 1000 of the prior art, the comparison circuit 101 essentially includes an ideal comparator 11 and has a varying offset value Vv during a preset operating procedure. As mentioned above, the variable offset value Vv changes with the temperature change. Therefore, the offset adjustment circuit 21 generates the adjustment offset value Va according to the comparison result VO of the comparison circuit 101 and the correction signal Cen, thereby correcting the comparison circuit 101. Changing the offset value Vv makes the operation circuit 1000 closer to the ideal state.

Please refer to FIG. 1B and FIG. 1C at the same time. FIG. 1C shows an operation waveform and program diagram of one of the prior art. The operation circuit 1000 performs the correction process P101 in the period T11, and uses the binary search method to successively make the adjustment offset value Va approach the changing offset value Vv, and updates the adjustment offset value Va when the binary search method is completed to compensate for the changing offset. Shifting the value Vv enables the operation circuit 1000 to be as close as possible to the ideal comparator during the preset operation procedure. Then entering the default operation program P201 of the period T12, the operation circuit 1000 performs normal operation. At this time, the changing offset value Vv of the comparison circuit 101 is corrected with the adjusted offset value Va updated in the period T11, and then the correction is performed repeatedly and staggered Program P101 and one-time preset operation program P201. Since the variable offset value Vv changes with temperature, the operation circuit 1000 of the prior art needs to execute the correction process P101 at a fixed period in the default operation program P201, and each correction process P101 executes a complete binary search method, and The adjustment offset value Va is updated when the search is completed, thereby causing the adjustment offset value Va to be updated regularly to accurately correct the varying offset value Vv with temperature changes.

The disadvantage of the above-mentioned prior art is that in order to accurately correct the changing offset value of the comparison circuit, not only the preset operation program needs to be periodically interrupted to perform the correction process, but also each correction process needs to execute a complete binary search method, thus causing interruptions. The normal operation time is too long. In addition, even if the variation offset value does not change significantly, a complete binary search method still needs to be performed in the calibration procedure, which will also cause unnecessary power consumption and waste of time.

Compared with the above-mentioned prior art, the operation circuit of the present invention has the advantage of low correction period. When the changing offset value does not change significantly, it can not only greatly reduce the time that is interrupted and cannot operate normally, but also maintain the accuracy of correction. degree, reducing unnecessary power consumption and improving circuit operation efficiency.

From one of the viewpoints, the present invention provides a calibration method for calibrating an operating circuit, wherein the operating circuit has a variable offset value, the operating circuit includes at least one comparison circuit, wherein the calibration method is used to provide an operable offset value. Adjust the offset value to correct the changing offset value, wherein the changing offset value includes a first changing offset value of the comparison circuit, the correction method includes: P100: configure the operating circuit to a correction configuration, and Reset an adjustment parameter to an initial value, and perform an initial correction process based on a comparison result of the comparison circuit to determine an operation correction code with N bits, where N is a positive integer greater than or equal to 2; P200: Set the The operation circuit is configured in an operation configuration, and operates the operation circuit to perform a preset operation procedure according to the operation correction code, wherein the operation correction code corresponds to the adjustable offset value and is used to correct the preset operation procedure. Change the offset value; P300: Configure the operating circuit to the correction configuration, adjust a test correction code according to the adjustment parameter, and operate the operating circuit to perform a low-bit correction process according to the test correction code to update the adjustment parameter or update the operation correction code according to the updated adjustment parameter, wherein the test correction code is related to the operation correction code, and then returns to the program P200; wherein the low bit number correction program includes: configuring the operation circuit for the correction Configuration; and perform the sub-calibration program P305 at most M times or perform the sub-calibration program P306 at most M times, where M is a positive integer less than N; then return to program P200; where the sub-calibration program P305 is used to perform the operation Starting from the correction code, adjust a least significant bit of the test correction code with a single slope to determine whether to continue to adjust the test correction code or update the operation correction code; wherein the sub-correction program P306 is used to adjust the test correction code through a binary search method. One bit of the test correction code is used to determine whether to continue adjusting the test correction code or to update the operation correction code; wherein M in the low-bit number correction process is a fixed value or a variable value.

In a preferred embodiment, the operating circuit further includes an amplifying circuit coupled to the comparison circuit, wherein the varying offset value further includes a second varying offset value of the amplifying circuit.

In a preferred embodiment, the sub-correction procedure P305 includes: setting the test correction code to be equal to the operation correction code superimposed on the adjustment parameter; and determining whether the adjustment parameter is The initial value, where if the adjustment parameter is the initial value, the direction judgment step S310 is performed, otherwise the difference comparison step S320 is performed; wherein the direction judgment step S310 includes: providing the adjustable value corresponding to the operation circuit according to the test correction code. offset value; operate the comparison circuit according to the adjustable offset value to generate the comparison result; determine a correction direction according to the comparison result; and superimpose the adjustment parameter with a preset unit difference corresponding to the correction direction to Update the adjustment parameter; wherein the difference comparison step S320 includes: providing the adjustable offset value corresponding to the operation circuit according to the test correction code; operating the comparison circuit according to the adjustable offset value to generate the comparison result; and Determine the direction of the comparison result. If the comparison result corresponds to the correction direction, enter the correction code update step S323. Otherwise, enter the adjustment parameter update step S324. The correction code update step S323 includes: correcting the operation. The code superimposes the adjustment parameter to update the operation correction code; resets the adjustment parameter to the initial value; wherein the adjustment parameter update step S324 includes: superimposing the adjustment parameter with the unit difference to update the adjustment parameter; or wherein the The sub-correction procedure P306 includes: using the adjustment parameter to indicate a bit sequence of a current test bit of the test correction code; setting the current test bit of the test correction code to a consistent enable state, and the rest of the test correction code The lower significant bits are set to a non-enabled state; an adjustable offset value corresponding to the operation circuit is provided according to the test correction code; the comparison circuit is operated according to the adjustable offset value to generate the Comparison result; and judging the size of the adjustable offset value and the changing offset value, wherein if the comparison result indicates that the adjustable offset value is greater than the changing offset value of the operating circuit, the test correction code is The current test bit is set to the non-enabled state; it is determined whether the bit sequence is a least significant bit. If the adjustment parameter indicates that the least significant bit has been reached, the correction code update step S325 is performed. Otherwise, the adjustment parameter is entered. Update step S326; wherein the correction code update step S325 includes: updating the operation correction code according to the test correction code; resetting the adjustment parameter to the initial value; wherein the adjustment parameter update step S326 includes: subtracting 1 from the current adjustment parameter to update the tuning parameters.

In a preferred embodiment, the initial value of the adjustment parameter corresponding to the sub-correction procedure P305 is 0, and the initial value of the adjustment parameter corresponding to the sub-correction procedure P306 is N.

In a preferred embodiment, the correction code updating step S323 further includes: superimposing the operation correction code on the adjustment parameter according to the correction direction and subtracting a unit difference to update the operation correction code.

In a preferred embodiment, the process P300 includes: operating the comparison circuit to perform the low bit number correction process with 1 clock cycle, wherein the unit difference corresponds to a least significant bit corresponding to the correction direction ( least significant bit,LSB).

In a preferred embodiment, M equals 1.

In a preferred embodiment, the time length required for the M times of the sub-correction procedure P305 or the M times of the sub-correction procedure P306 is less than the time length required for the preset operation procedure.

In a preferred embodiment, the time length required for the M times of the sub-correction procedure P305 or the M times of the sub-correction procedure P306 is less than the time length required for the initial correction procedure.

In a preferred embodiment, the characteristic curve of the adjustable offset value corresponding to the operation correction code or the test correction code is a sub-radix-2 curve (sub-radix-2).

In a preferred embodiment, the initial calibration process includes: a sub-calibration process P306 that is continuously performed N times, where the initial value is N.

In a preferred embodiment, in the default operating program, the comparison circuit is used to compare an input signal with a reference threshold, or is used in an analog-to-digital converter.

From another point of view, the present invention also provides an operation circuit with a low correction period, wherein the operation circuit has a changing offset value, including: at least one comparison circuit for comparing a first input end of the comparison circuit A difference with a second input terminal of the comparison circuit generates a comparison result, wherein the variation offset value includes a first variation offset value of the comparison circuit; a an offset generation circuit, coupled to the comparison circuit, for generating an adjustable offset value according to an operation correction code having N bits to correct the varying offset value; an offset adjustment circuit, for The following steps generate the operation correction code to correct the changing offset value, and operate the operation circuit to perform a preset operation procedure according to the operation correction code: P100: configure the operation circuit to a correction configuration and reset an adjustment The parameters are set to an initial value, and an initial correction process is performed based on a comparison result of the comparison circuit to determine the operation correction code, where N is a positive integer greater than or equal to 2; P200: configure the operation circuit to an operation configuration, The operation circuit is operated according to the operation correction code to perform the preset operation program, wherein the operation correction code corresponds to the adjustable offset value and is used to correct the changing offset value in the preset operation program; P300: Set the The operation circuit is configured in the correction configuration, adjusts a test correction code according to the adjustment parameter, and operates the operation circuit to perform a low-bit correction process according to the test correction code to update the adjustment parameter or according to the updated adjustment parameter Update the operation correction code, wherein the test correction code is related to the operation correction code, and then return to the program P200; wherein the low-bit number correction process includes: configuring the operation circuit to the correction configuration; and performing up to M times The sub-correction procedure P305 or the sub-correction procedure P306 is performed at most M times, where M is a positive integer less than N; and then returns to the procedure P200; wherein the sub-correction procedure P305 is used to adjust the operation correction code with a single slope starting from the operation correction code. A least significant bit of the test correction code is used to determine whether to continue adjusting the test correction code or update the operation correction code; wherein the sub-correction program P306 is used to adjust a bit of the test correction code through a binary search method, using To determine to continue to adjust the test correction code or update the operation correction code; wherein M in the low-bit number correction procedure is a fixed value or a variable value.

In a preferred embodiment, in the preset operating program, the comparison circuit is used to compare an input signal with a reference threshold, and the comparison result corresponds to indicating an operating state of the operating circuit; or the operating circuit is an analog Digital converter, wherein in the default operation program, the amplifying circuit is used to amplify an analog signal and connect the first input end of the comparison circuit to the comparison circuit. The second input end of the circuit generates an amplified signal, and the comparison circuit is used to compare the amplified signal with an adjustable reference value to generate a digital output code corresponding to the analog signal.

In a preferred embodiment, the analog-to-digital converter includes a first digital-to-analog converter, and the first digital-to-analog converter is used to provide the adjustable reference value in the preset operating program, wherein the offset generating circuit A second digital-to-analog converter is composed of partial bits of the first digital-to-analog converter.

It will be easier to understand the purpose, technical content, characteristics and achieved effects of the present invention through detailed description of specific embodiments below.

11:Ideal comparator

100,101,105: Comparison circuit

1000: Operating circuit

20:Offset generation circuit

21:Offset adjustment circuit

200: Amplification circuit

2002, 2011, 2014: Operating circuit

30: Offset adjustment circuit

310,311: First digital to analog converter

320,321: Second digital to analog converter

40: Operation control circuit

50: Sampling and holding circuit

51,52: Sub-sampling sustain circuit

60:Ideal Amplifier

Calen: Correction enable signal

CCO: Operation correction code

CCT: test correction code

CDO: digital output code

Cen: correction signal

Ckcom: clock signal

CPO: Comparison results

M: positive integer

N: positive integer

N1~N4: nodes

Na: node

Nb: node

Ni1, Ni1a: first input terminal

Ni2, Ni2a: second input terminal

P100:Procedure

P200:Procedure

P201: Preset operating procedures

P300:Program

S001: Steps

S101: Calibration procedure

S200: Steps

S301, S302: steps

P305: Sub-calibration program

P306: Sub-calibration program

S307: Step

S310: Direction judgment step

S320: Difference comparison step

S321, S322: steps

S323: Correction code update steps

S324: Adjust parameter update steps

S325: Correction code update steps

S326: Adjust parameter update steps

S351, S352: steps

S361~S365: steps

SA: analog signal

SH: signal

Sw: switch

Sw1, Sw2: switch

T1~T10: time period

T11, T12: time period

Tp1, Tp2: temperature

Va: adjust offset value

Vcm: common mode voltage

VO:Compare results

Vosa: adjustable offset value

Vosv: change offset value

Vosv1: first change offset value

Vosv2: second change offset value

Vref: reference threshold

Vsns: input signal

Vv: variation offset value

Vv1, Vv2: changing offset value

X: unit difference

Y1, Y2: value of operation correction code

Z1, Z2: Value of operation correction code

Figure 1A shows a graph showing the changing offset value of the comparison circuit as a function of temperature.

FIG. 1B shows a prior art operating circuit capable of correcting offset values.

FIG. 1C shows an operation waveform and program diagram of one of the prior art.

FIG. 2 shows a schematic diagram of an operating circuit with a low correction period according to an embodiment of the present invention.

FIG. 3 shows a flow chart of the complete operating procedure in the operating circuit with low correction period of the present invention.

FIG. 4 shows a partially detailed flow chart corresponding to FIG. 3 .

FIG. 5 shows a complete operation sequence diagram of the operation circuit with low correction period of the present invention.

FIG. 6 shows the operation waveform and program diagram of a specific embodiment of the present invention in which the operation circuit with a low correction period performs correction using the sub-correction program P305.

FIG. 7A shows a flow chart corresponding to a specific embodiment of the sub-correction procedure P305 in FIG. 4 .

FIG. 7B shows a flow chart corresponding to another specific embodiment of the sub-correction program P305 in FIG. 4 .

FIG. 8 shows the operation waveform and program diagram of a specific embodiment of the present invention in which the operation circuit with a low correction period performs correction using the sub-correction program P305.

FIG. 9 shows the operation waveform and program diagram of a specific embodiment of the present invention in which the operation circuit with a low correction period performs correction using the sub-correction program P306.

FIG. 10A shows a flow chart corresponding to a specific embodiment of the sub-correction procedure P306 in FIG. 4 .

FIG. 10B shows a flow chart corresponding to another specific embodiment of the sub-correction procedure P306 in FIG. 4 .

FIG. 11 shows a schematic diagram of an operating circuit with a low correction period according to a specific embodiment of the present invention.

FIG. 12 shows operation waveforms and program diagrams corresponding to the embodiment of FIG. 11 .

FIG. 13 shows the characteristic curve of the adjustable offset value corresponding to the operation correction code or the test correction code of the operation circuit with a low correction period of the present invention.

FIG. 14 shows a schematic diagram of an operation circuit with a low correction period according to a specific embodiment of the present invention.

The diagrams in the present invention are schematic and are mainly intended to represent the coupling relationship between circuits and the relationship between signal waveforms. The circuits, signal waveforms and frequencies are not drawn to scale.

Please refer to FIG. 2. FIG. 2 shows a schematic diagram of an operating circuit with a low correction period (operating circuit 2002) according to an embodiment of the present invention. In one embodiment, operating circuit 2002 includes: at least A comparison circuit (comparison circuit 100 in the embodiment of FIG. 2 ), offset generation circuit 20 and offset adjustment circuit 30 . In one embodiment, the operating circuit 2002 has a variable offset value Vosv. In this embodiment, the variable offset value Vosv is the first variable offset value Vosv1 of the comparison circuit 100 . The equivalent circuit of the comparison circuit 100 includes the ideal comparator 12 and has a first variable offset value Vosv1. In this embodiment, in the operating configuration, the non-inverting input terminal of the ideal comparator 12 receives the first superposition result of the input signal Vsns and the first variable offset value Vosv1; the inverting input of the ideal comparator 12 The terminal receives the second superposition result after superposition of the reference threshold Vref and the adjustable offset value Vosa. That is to say, in this embodiment, in the operating configuration, the first input terminal Ni1 of the comparison circuit 100 receives the input signal Vsns; the second input terminal Ni2 of the comparison circuit 100 receives the reference threshold Vref and the adjustable offset value Vosa. The second superposition result after superposition. Therefore, in this embodiment, in the operating configuration, the ideal comparator 12 compares the first superposition result and the second superposition result, so that the comparison circuit 100 generates the comparison result CPO. The offset generation circuit 20 is coupled to the comparison circuit 100 and is used in the operation configuration to generate the adjustable offset value Vosa according to the N-bit operation correction code CCO to correct the varying offset value Vosv; and in the correction In the configuration, the adjustable offset value Vosa in the calibration configuration is generated according to the test correction code CCT with N bits to perform a low-bit number calibration process. The offset adjustment circuit 30 is coupled to the output end of the comparison circuit 100 and is used in the correction configuration to generate the operation correction code CCO according to the comparison result CPO.

It should be noted that the first variable offset value Vosv1 is the equivalent comprehensive variable offset value of the comparison circuit 100, which is not limited to being coupled to the non-inverting input end of the ideal comparator 12 as shown in FIG. 2 , can also be coupled to the inverting input end of the ideal comparator 12, and only need to adjust the first variable offset value Vosv1 accordingly; in addition, the offset generation circuit 20 and the offset adjustment circuit 30 are not limited to being coupled to the ideal comparator. The inverting input terminal of the ideal comparator 12 can also be coupled to the non-inverting input terminal of the ideal comparator 12, and only the adjustable offset value Vosa needs to be adjusted accordingly.

Please refer to FIG. 2 and FIG. 3 at the same time. FIG. 3 shows a flow chart of the complete operating procedure in the operating circuit with a low correction period of the present invention. In one embodiment, the offset adjustment circuit 30 is used to generate the operation correction code CCO (corresponding to the adjustable offset value Vosa) according to the correction enable signal Calen in the following steps to correct the varying offset value Vosv, and the operation circuit 2002 Perform the preset operation procedure according to the operation correction code CCO.

As shown in Figure 3, the first step is program P100, which is an initial calibration procedure. In the process P100, the operating circuit 2002 is first configured in the calibration configuration according to the calibration enable signal Calen, and the offset adjustment circuit 30 resets the adjustment parameters to Initial value (in one embodiment, the initial value may be 0 or N, which will be described in detail in subsequent embodiments). In the calibration configuration, the switch Sw is switched according to the calibration enable signal Calen to switch the first input terminal Ni1 is coupled to the node Nb, so that the first input terminal Ni1 and the second input terminal Ni2 of the comparison circuit 100 are coupled to each other, and then a sub-correction process (described in detail later) is performed according to the comparison result CPO of the comparison circuit 100 to determine the N-bit operation correction code CCO, where N is a positive integer greater than or equal to 2. As shown in Figure 2, in this embodiment, in the correction configuration, the non-inverting input terminal of the ideal comparator 12 receives the third superposition result of the reference threshold Vref and the first variable offset value Vosv1; the ideal comparison The inverting input terminal of the device 12 is the same as in the operating configuration, and still receives the second superposition result of the superposition of the reference threshold Vref and the adjustable offset value Vosa. That is to say, in this embodiment, in the correction configuration, the first input terminal Ni1 of the comparison circuit 100 receives the reference threshold Vref; the second input terminal Ni2 of the comparison circuit 100 receives the second superposition result. Therefore, in this embodiment, in the calibration configuration, the ideal comparator 12 compares the third superposition result with the second superposition result, so that the comparison circuit 100 generates the comparison result CPO.

It should be noted that, in the correction configuration shown in the embodiment of FIG. 2 , the first input terminal Ni1 and the second input terminal Ni2 are, for example, commonly coupled to the reference threshold Vref. According to the present invention, in the correction configuration, The first input terminal Ni1 and the second input terminal Ni2 can also be jointly coupled to other preset voltages, such as ground potential, etc., and are not limited to being jointly coupled to the reference threshold Vref.

Next, program P200 is entered, which is a default operation program. In program P200, the operation circuit 2002 is first configured into an operation configuration according to the correction enable signal Calen. In the operating configuration, the switch Sw is switched according to the correction enable signal Calen to couple the first input terminal Ni1 to the node Na, so that the first input terminal Ni1 and the second input terminal Ni2 of the comparison circuit 100 are respectively coupled to Inputting the signal Vsns and the reference threshold Vref, the operation circuit 2002 performs normal operation steps according to the operation correction code CCO. In the normal operation steps, the comparison circuit 100 generates the comparison result CPO according to the input signal Vsns, the reference threshold Vref and the adjustable offset value Vosa. , corresponding to the operating status of the schematic operation circuit 2002, such as but not limited to over-voltage protection, over-current protection, over-temperature protection, etc., where the operation correction code CCO corresponds to the adjustable offset value Vosa, which is used for normal operation steps. Medium correction variation offset value Vosv.

Next, the program P300 is entered, which is a low-bit correction program. In the program P300, the operation circuit 2002 is first configured in a calibration configuration according to the calibration enable signal Calen, and the switch Sw causes the first input of the comparison circuit 100 according to the calibration enable signal Calen. The terminal Ni1 is coupled to the node Nb, whereby the first input terminal Ni1 and the second input terminal Ni2 of the comparison circuit 100 are coupled to each other. At this time, the offset generation circuit 20 causes the operation circuit 2002 to perform operation according to the adjustment parameters and the test correction code CCT. The low bit number correction process P300 is to update the adjustment parameters or update the operation correction code CCO according to the updated adjustment parameters, where the test correction code CCT is related to the operation correction code CCO. In a preferred embodiment, the low bit number correction process P300 includes: causing the operating circuit 2002 to perform the low bit number correction process P300 in one clock cycle. Then return to the default operating procedure P200. The default operation program P200 and the low-bit correction program P300 are repeatedly and alternately executed, so that the operation circuit 2002 operates with a comparator close to an ideal state in the default operation program P200, and compared with the previous technology, the interruption of correction is significantly reduced. It can maintain the accuracy of calibration even when normal operation is not possible, reduce unnecessary power consumption, and improve the efficiency of operating circuits.

Please refer to FIG. 4 and FIG. 5 at the same time. FIG. 4 shows a partially detailed flow chart corresponding to FIG. 3 . FIG. 5 shows a complete operation sequence diagram of the operation circuit with low correction period of the present invention. As shown in FIG. 4 , in one embodiment, the initial calibration process P100 includes step S301 and N sub-calibration processes P306. In step S301, the operating circuit is configured as a correction configuration, and then enters the N sub-correction program P306, using the binary search method to adjust the test correction code CCT with N bits, so that the adjustable offset value Vosa successively approaches the changing offset value Vosv, The operation correction code CCO with N bits is completely determined and updated in the initial calibration procedure P100. In one embodiment, the default operation procedure P200 includes step S001 and step S200. In step S001, the operating circuit is configured as an operating configuration, and the adjustable offset value Vosa is controlled with the operating correction code CCO determined in the initial calibration procedure P100 to correct the changing offset value Vosv, and then the normal operation step of step S200 is entered. The details are detailed later. In one embodiment, the low bit number correction process P300 includes step S301 and step S302. In step S301, the operating circuit is configured in a correction configuration, and then step S302 is entered. From one point of view, the aforementioned binary search method can also be regarded as an N-bit operation that converts the analog variable offset value Vosv into digital by using the Successive Approximation Register Analog to Digital Conversion method. Correction code CCO.

Among them, in step S302 of the low bit number correction procedure P300, the sub-correction procedure P305 will be performed M times or the sub-correction procedure P306 will be performed M times, where M is a positive integer less than N, that is, the minimum value of M is 1, and the maximum value is N-1. Specifically, when entering step S302 from step S301, the sub-correction procedure P305 or sub-correction procedure P306 is first performed (for convenience of description, if it is only collectively referred to as the "sub-correction procedure" without specifically labeling P305 or P306, it refers to the sub-correction procedure. P305 or sub-calibration program P306). In one embodiment, after executing the sub-correction procedure, step S307 is then entered. In another embodiment, after executing the sub-correction procedure, the process returns to the default operation procedure P200. The relevant details will be described in detail later. In step S307, it is determined whether it is the M-th sub-correction program. When it is determined that it is the M-th sub-correction program, return to the default operation program P200; otherwise, return to the sub-correction program.

It should be noted in Figure 5 that in each step S302, M is a positive integer less than N, and N is a positive integer greater than or equal to 2. Therefore, M can be a positive integer greater than or equal to 1. In one embodiment, M is equal to 1. At this time, step S302 includes only one sub-correction procedure, and then enters the default operation procedure P200; in other embodiments, M is greater than 1, and at this time, step S302 includes M times (greater than (once) of the sub-calibration procedure, and then return to the default operation procedure P200.

From one point of view, according to the present invention, M sub-correction procedures are executed between any two preset operation procedures P200. In a preferred embodiment, multiple sub-correction procedures can be allocated in different steps S302, and the operation correction code CCO is determined and updated by combining the same or different M times of sub-correction procedures. In other words, the M value in step S302 of different low bit number correction procedures P300 may be a fixed value or a variable value.

For example, as shown in FIG. 5 , in one embodiment, step S302 in the first low-bit number correction process P300 includes M1 sub-correction processes, and in the second low-bit number correction process P300 Step S302 in program P300 includes M2 sub-correction procedures, in which M1 and M2 may be the same as each other or different values from each other.

Please continue to refer to Figures 4 and 5. After the initial calibration process P100 is completed, the default operation process P200 is then entered. Step S001 is first executed, that is, the operation circuit 2002 is configured as an operation configuration according to the calibration enable signal Calen, and then is executed. In step S200, the operation circuit 2002 performs normal operation steps according to the operation correction code CCO (step S200). In the normal operation steps, the comparison circuit 100 generates a comparison result CPO according to the input signal Vsns, the reference threshold Vref and the adjustable offset value Vosa. , corresponding to illustrate the operating state of the operating circuit 2002. After the default operation program P200 is completed, the low bit number correction program P300 is entered, including step S301 and step S302. In step S301, the operating circuit is configured in a correction configuration, and then step S302 is entered. In step S302, the sub-correction program P305 or the sub-correction program P306 is performed, and then step S307 is entered to determine whether it is the M-th sub-correction program. When it is determined that it is the M-th sub-correction program, the preset operation program P200 is then performed. ;no Then the sub-correction program P305 or the sub-correction program P306 is performed, and then step S307 is performed. In this way, the sub-correction program and step S307 are alternately repeated until the execution of the M sub-correction programs is completed, and the M-th sub-correction is determined by step S307. When the program is completed, proceed to the next preset operation program P200.

It should be noted that in the embodiment where M in each low-bit correction procedure P300 is 1, step S307 can be omitted. In other words, when the sub-correction procedure is completed, the next preset operation can be continued directly. Procedure P200.

It is worth noting that if the sub-correction procedure P305 is used in the low-bit correction procedure P300, the low-bit correction procedure P300 needs to be executed at least once and at most 2 ^N times to update the operation correction code CCO. If the sub-correction procedure P306 is used in the low-bit correction program P300, the low-bit correction program P300 needs to be executed at least 2 times and at most N times to update the operation correction code CCO. And each low-bit number correction program P300 and the default operation program P200 are executed in turn with each other.

In addition, if the sub-correction procedure P305 is used in the low-bit number correction procedure P300, through one or more steps S302, the sub-correction procedure S305 needs to be executed at least once and at most 2 ^N times to update the operation correction code CCO. On the other hand, if the sub-correction procedure P306 is used in the low-bit number correction procedure P300, through multiple steps S302, it is necessary to execute the sub-correction procedure P306 a total of N times to update the operation correction code CCO.

It should also be noted that in a preferred embodiment, the time length required for M times of sub-correction procedures P305 or M times of sub-correction procedures P306 is less than the time length required for the preset operation procedure P200, and/or The time length required for M times of sub-correction procedures P305 or M times of sub-correction procedures P306 is less than the time length required for N times of sub-correction procedures in the initial calibration procedure P100, thereby greatly reducing the correction period, and when changes Even if the offset value does not change significantly, the accuracy of the correction can be maintained.

Please refer to FIG. 6 . FIG. 6 shows the operation waveform and program diagram of a specific embodiment of the present invention in which the operation circuit with a low correction period performs correction using the sub-correction program P305. The embodiment of FIG. 6 is an embodiment in which M in each low-bit number correction process P300 is all 1. In this embodiment, step S307 can be omitted, as will be described in detail later. It should be noted that, for ease of understanding, each step S001 and step S301 are omitted in the program diagram in FIG. 6 .

In a specific embodiment, as shown in Figure 6, in the initial calibration process P100 of period T1, the operating circuit is first configured in the calibration configuration, and then the adjustment parameters are reset to the initial values. In a preferred embodiment, The initial value of the adjustment parameter corresponding to the sub-correction program P306 is N, which is used to indicate that the highest N-th bit of the test correction code CCT is in the enabled state (for example, 1), and the other bits are in the disabled state (for example, 1). is 0), use the binary search method to adjust the test correction code CCT with N bits, so that the adjustable offset value Vosa (marked with a solid line) successively approaches the changing offset value Vosv (marked with a long dotted line) to determine and update Operation correction code CCO with N bits. In this embodiment, at the end of the initial calibration procedure P100, the value of the initial operation correction code CCO is Z1, and then the default operation procedure P200 of period T2 is entered, and the operation circuit is operated according to the operation correction code CCO (Z1) determined in period T1. The operation procedure P200 is preset, and the variable offset value Vosv is corrected with the adjustable offset value Vosa corresponding to the operation correction code CCO (Z1).

After the default operation program P200 is completed, the low bit number correction program P300 is then entered. Please refer to Figures 2, 6, 7A and 7B at the same time. Figure 7A shows a flow chart corresponding to the sub-correction procedure P305 in Figure 4, and Figure 7B shows another flow chart corresponding to the sub-correction procedure P305 in Figure 4. Specific embodiment flow chart. In one embodiment, as shown in Figure 6, the sub-correction program P305 adjusts a least significant bit of the test correction code CCT with a single slope starting from the operation correction code CCO (Z1), and adjusts the least significant bit of the test correction code CCT according to the corresponding The adjustable offset value Vosa and the changing offset value Vosv determine to continue to adjust the test correction code CCT (for example, continue to add 1) or to update the operation correction code CCO. For example, starting from resetting the adjustment parameters to 0, before confirming and updating the operation correction code CCO, by adjusting For parameter adjustment, in each step S351 of setting the test correction code CCT, the test correction code CCT will increase by 1 or decrease by 1, depending on the correction direction judgment result. Specifically, as shown in Figure 7A and Figure 7B , sub-correction program P305 includes the following steps: First, step S351 is performed to set the test correction code CCT to be equal to the current operation correction code CCO superposition adjustment parameter. Then enter step S352 to determine whether it is a new calibration program, that is, determine whether the adjustment parameter is an initial value (in this embodiment, the initial value is 0, for example). If the adjustment parameter is an initial value, it indicates a new calibration program, and the direction judgment is entered. Step S310, otherwise it is not a new correction procedure and enters the difference comparison step S320.

The direction determination step S310 includes: providing the adjustable offset value Vosa corresponding to the operating circuit 2002 according to the test correction code CCT. In one embodiment, as shown in FIG. 2 , for example, providing the adjustable offset value Vosa to the third terminal of the operating circuit 2002. Two input terminals Ni2; operate the comparison circuit 100 according to the adjustable offset value Vosa to generate a comparison result CPO; determine the correction direction according to the comparison result CPO. In a specific embodiment, in the direction determination step S310, if the comparison result CPO indicates a change If the offset value Vosv is greater than the adjustable offset value Vosa, the correction direction is positive, otherwise the direction is negative; then the unit difference value X corresponding to the correction direction is determined; then the adjustment parameter is superimposed on the unit difference value X to update the adjustment parameter. In a preferred embodiment, the unit difference value , if the comparison result indicates that the correction direction is positive, the unit difference X is +LSB; if the comparison result indicates that the changing offset value Vosv is smaller than the adjustable offset value Vosa (the correction direction is negative), the unit difference X is - LSB. Next, in an embodiment in which M in each low-bit number correction process P300 is 1 (such as the embodiment in FIG. 6 ), as shown in FIG. 7A , step S307 can be omitted, that is, after the direction determination step S310 is completed, , directly enter the next preset operation program P200; in the embodiment where M in each low-bit number correction program P300 is not 1, as shown in Figure 7B, the direction judgment step S310 is executed. After the operation is completed, step S307 is entered to determine whether it is the M-th sub-correction program. When it is determined that it is the M-th sub-correction program, return to the default operation program P200, otherwise, return to the sub-correction program P305.

The difference comparison step S320 includes: step S321, step S322, step S323 and step S324. First, step S321 is performed: providing the adjustable offset value Vosa corresponding to the operating circuit 2002 according to the test correction code CCT. In one embodiment, as shown in FIG. 2, for example, the adjustable offset value Vosa is provided to the second terminal of the operating circuit 2002. Input terminal Ni2, and operate the comparison circuit 100 according to the adjustable offset value Vosa to generate the comparison result CPO; then execute step S322: determine whether the comparison result CPO turns, that is, determine the direction of the comparison result CPO, if the comparison result CPO corresponds to the correction The direction is reversed, indicating that the comparison result has turned. In other words, the current test correction code CCT after one or more adjustments has made the difference between the corresponding adjustable offset value Vosa and the changing offset value Vosv less than A unit difference After multiple adjustments, the difference between the adjustable offset value Vosa and the changing offset value Vosv corresponding to the current test correction code CCT is not less than a unit difference X. At this time, the adjustment parameter update step S324 will be entered to continue the update. Adjust the parameters and continue to adjust the test correction code CCT.

Specifically, in this embodiment, the correction code update step S323 includes: superimposing the operation correction code CCO with the adjustment parameters to update the operation correction code CCO, and resetting the adjustment parameters to the initial values. In addition, the updated operation correction code may be continued. In addition to performing correction in the default operation program P200, the CCO also indicates that the next low-bit correction process P300 will restart one or more low-bit correction processes P300 to reconfirm and update the next operation correction code CCO. As shown in FIG. 7A and FIG. 7B , after the correction code updating step S323 is completed, the process returns to the default operation program P200.

Specifically, in this embodiment, the adjustment parameter update step S324 includes: superimposing the adjustment parameter by the unit difference value One unit difference X. The adjustment parameter update step S324 is completed. Afterwards, in an embodiment in which M in each low-bit correction process P300 is 1 (such as the embodiment of FIG. 6 ), as shown in FIG. 7A , step S307 can be omitted, that is, the adjustment parameter update step S324 is completed. After that, directly enter the next preset operation program P200; in the embodiment where M in each low-bit number correction program P300 is not 1, as shown in Figure 7B, after the adjustment parameter update step S324 is completed, step S307 is entered. , determine whether it is the M-th sub-correction program. When it is determined that it is the M-th sub-correction program, return to the default operation program P200, otherwise, return to the sub-correction program P305.

Please continue to refer to FIG. 6 and FIG. 7A. In a specific embodiment, as shown in FIG. 6, in the sub-calibration program P305 of the period T3, after step S301 is configured as the calibration configuration (omitted in FIG. 6), the steps are firstly performed. S351, set the test correction code CCT to be equal to the operation correction code CCO (Z1) and superimpose the adjustment parameter. In this embodiment, the initial value of the adjustment parameter is 0, so the test correction code CCT is Z1+0, and then enter step S352 to determine Whether it is a new calibration program, at this time, because the adjustment parameter is the initial value 0, it indicates that it is a new calibration program, so the direction judgment step S310 is entered. In the direction determination step S310, the adjustable offset value Vosa corresponding to the operating circuit 2002 is provided according to the test correction code CCT (Z1+0), and the comparison circuit 100 generates a comparison result based on the adjustable offset value Vosa and the changing offset value Vosv. CPO, in this embodiment, since the adjustable offset value Vosa is lower than the variable offset value Vosv, the correction direction determined based on the comparison result CPO is positive, and the unit difference X determined based on the correction direction is, for example, +LSB, Then the adjustment parameter is superimposed with the unit difference X to update the adjustment parameter to 0+X. Next, in the embodiment of FIG. 6 and FIG. 7A , after the direction determination step S310 is completed, the system returns to the default operation program P200, that is, enters the default operation program P200 of the period T4 to operate the correction code CCO (not updated yet, still The adjustable offset value Vosa corresponding to Z1) corrects the changing offset value Vosv.

Next, in the sub-calibration program P305 of period T5, after step S301 is configured as the calibration configuration (omitted in Figure 6), step S351 is first entered. At this time, the adjustment parameter is X, so the test correction code CCT is set to Z1+ X, then in step S352, since the adjustment parameter is not the initial value 0, it is judged that it is not a new calibration procedure, and the difference comparison step S320 is entered. In the difference comparison step S320, first enter Step S321, provide the adjustable offset value Vosa corresponding to the operating circuit 2002 according to the test correction code CCT (Z1+X), and operate the comparison circuit 100 according to the adjustable offset value Vosa to generate the comparison result CPO, and then enter step S322 to determine The comparison result CPO is whether to turn. In this embodiment, the adjustable offset value Vosa is still lower than the variable offset value Vosv. The comparison result CPO corresponds to the correction direction and is in phase, that is, the comparison result CPO has not turned. Therefore, the adjustment parameter update step S324 is entered. . In the adjustment parameter updating step S324, the adjustment parameter is superimposed with the unit difference X, so the adjustment parameter is updated to 2X. Next, in the embodiment of FIG. 6 and FIG. 7A , after the adjustment parameter update step S324 is completed, the system returns to the default operation program P200, that is, enters the default operation program P200 of the period T6 to operate the correction code CCO (not yet updated, but still Correct the changing offset value Vosv for the adjustable offset value Vosa corresponding to Z1).

Next, in the sub-correction procedure P305 of the period T7, steps S301, step S351, step S352 and step S321 are all similar to the sub-correction procedure P305 of the period T5, and will not be described again here. Then enter step S322 to determine whether the comparison result CPO has turned. In this embodiment, the adjustable offset value Vosa is higher than the variable offset value Vosv. The comparison result CPO corresponds to the correction direction and is in reverse phase, that is, the comparison result CPO has turned. Therefore, Enter correction code update step S323. In the correction code update step S323, the operation correction code CCO is superimposed on the adjustment parameters to update the operation correction code CCO. In this embodiment, the operation correction code CCO is updated to Z1+2X (=Z2), and the adjustment parameters are reset to the initial value. Value 0. After the correction code update step S323 is completed, then return to the default operation program P200, that is, enter the default operation program P200 of period T8 to operate the adjustable offset value Vosa corresponding to the correction code CCO (updated to Z2) to correct changes. Offset value Vosv.

Please refer to FIG. 8. FIG. 8 shows an operation waveform and program diagram of a specific embodiment of the present invention in which the operation circuit with a low correction period performs correction using the sub-correction program P305. The operation waveform diagram and program diagram of Figure 8 are similar to the operation waveform diagram and program diagram of Figure 6. The difference is that in a preferred embodiment, the correction code update step S323 further includes: changing the operation correction code CCO according to the correction direction. The adjustment parameters are superimposed and one unit difference is deducted to update the operation correction code CCO. The specific implementation is shown in Figure 8. In this example, in the correction code update step S323 of the sub-correction program P305 in period T7, the operation correction code CCO is updated to Z1+2X-X=Z1+X=Z2, thereby making the changing offset value Vosv relatively stable, and the operation correction code CCO and the adjustable offset value Vosa can also be stable values instead of jittering values. If the operation correction code CCO is not updated to Z1+2X-X in the correction code update step S323 of the sub-correction program P305 in the period T7, the comparison result CPO will not end the correction process until it is judged as turning in the sub-correction program P305. Therefore, the This causes the operation correction code CCO to switch between Z1+2X and Z1+X after each correction procedure ends, thereby causing the adjustable offset value Vosa to change after each low-bit number correction procedure P300 ends, resulting in possible The offset value Vosa is jittering or unstable.

Please refer to FIG. 9 . FIG. 9 shows the operation waveform and program diagram of a specific embodiment of the present invention in which the operation circuit with a low correction period performs correction using the sub-correction procedure P306. The embodiment of FIG. 9 is an embodiment in which M in each low-bit number correction process P300 is all 1. In this embodiment, step S307 can be omitted, as will be described in detail later. It should be noted that, for ease of understanding, similar to FIG. 6 and FIG. 8 , each step S001 and step S301 are also omitted in the program diagram in FIG. 9 . In the embodiment of FIG. 9 , the initial calibration procedure P100 of period T1 and the preset operation procedure P200 of period T2 are similar to the embodiment of FIG. 6 . In the initial calibration procedure P100 of period T1 of FIG. 9 , the operating circuit is first configured as Calibrate the configuration, and then reset the adjustment parameters to the initial values. In a preferred embodiment, the initial value of the adjustment parameters corresponding to the sub-calibration procedure P306 is N, which is used to indicate the highest N-th bit of the test correction code CCT. is the enabled state (for example, 1), and other bits are in the disabled state (for example, 0). The test correction code CCT with N bits is adjusted using the binary search method, so that the adjustable offset value Vosa (realized by The changing offset value Vosv (marked by the long dashed line) is successively approximated to determine and update the operation correction code CCO with N bits. In this embodiment, at the end of the initial calibration procedure P100, the value of the initial operation correction code CCO is Y1, and then the default operation procedure P200 of the period T2 is entered, and the operation is performed according to the operation correction code CCO (Y1) determined in the period T1. The operation circuit performs the preset operation program P200, and corrects the variable offset value Vosv with the adjustable offset value Vosa corresponding to the operation correction code CCO (Y1).

After the default operation program P200 is completed, the low bit number correction program P300 is then entered. Please refer to Figure 2, Figure 9, Figure 10A and Figure 10B at the same time. Figure 10A shows a flow chart corresponding to the sub-correction procedure P306 in Figure 4, and Figure 10B shows another flow chart corresponding to the sub-correction procedure P306 in Figure 4. Specific embodiment flow chart. In one embodiment, as shown in FIG. 9 , the sub-correction process P306 uses the binary search method to sequentially decrease one bit from the highest bit (Nth bit) to the lowest bit (the first bit) in bit order. ), and sequentially adjust each bit of the test correction code CCT according to the adjustment parameters, and decide to continue to adjust the test correction code CCT or update the operation correction code CCO. Specifically, as shown in Figures 10A and 10B, the sub-correction program P306 includes the following steps: First, step S361 is entered to adjust the parameters to indicate the bit sequence of the current test bits of the test correction code CCT (in a specific embodiment, the current test bits start from the Nth bit of the highest bit in descending order). The lowest bit is the 1st bit), and then the current test bit of the test correction code CCT is set to the enabled state (in a specific embodiment, the enable state is 1), and the remaining lower bits of the test correction code CCT are The lower significant bits are set to the disabled state (for example, 0 in a specific embodiment), and the remaining higher significant bits of the test correction code CCT remain as they were since the last reset. The state after adjusting parameters.

Then step S362 is entered, and the adjustable offset value Vosa corresponding to the operating circuit 2002 is provided according to the test correction code CCT. In one embodiment, as shown in FIG. 2, for example, the adjustable offset value Vosa is provided to the second terminal of the operating circuit 2002. The input terminal Ni2 then operates the comparison circuit 100 according to the adjustable offset value Vosa to generate the comparison result CPO.

Then step S363 is entered to determine whether the adjustable offset value Vosa is greater than the changing offset value Vosv. If the comparison result CPO indicates that the adjustable offset value Vosa is greater than the changing offset value Vosv of the operating circuit 2002, then step S364 is entered to correct the test. The current test bit of code CCT is set to a non-enabled state. If the comparison result CPO indicates that the adjustable offset value Vosa is less than the changing offset of the operating circuit 2002 By shifting the value Vosv, the current test bit of the test correction code CCT is kept in the enabled state, step S364 is skipped, and the next step (S365) is entered directly.

After the end of step S364, or after the judgment result of step S363 is no, step S365 is then entered to judge whether the bit sequence of the current test bit of the test correction code CCT is the least significant bit. If the adjustment parameter indicates that the bit sequence has been If it is the least significant bit (for example, the first bit has been reached in a specific embodiment), the correction code update step S325 is performed; otherwise, the adjustment parameter update step S326 is performed.

Specifically, in this embodiment, the correction code update step S325 includes: updating the operation correction code CCO according to the test correction code CCT, and resetting the adjustment parameters to the initial value (for example, N). In addition, the updated operation correction can be continued. In addition to correcting the code CCO in the default operation program P200, it also indicates that the next low-end correction process P300 will restart one or more low-end correction procedures P300 to reconfirm and update the next operation correction code CCO. As shown in FIG. 10A and FIG. 10B , after the correction code updating step S325 is completed, the process returns to the default operation program P200.

Specifically, in this embodiment, the adjustment parameter updating step S326 includes: decrementing the current adjustment parameter by 1 to update the adjustment parameter. The value of the adjustment parameter indicates the bit sequence to be corrected next in the test correction code CCT. After the adjustment parameter update step S326 is completed, in an embodiment in which M in each low-bit correction process P300 is 1 (such as the embodiment of FIG. 9 ), as shown in FIG. 10A , step S307 can be omitted, that is, the adjustment After the parameter update step S326 is completed, the next preset operation program P200 is entered directly; in an embodiment in which M in each low-bit number correction program P300 is not 1, as shown in FIG. 10B , the adjustment parameter update step S326 is executed. After completion, step S307 is entered to determine whether it is the M-th sub-correction program. When it is determined that it is the M-th sub-correction program, return to the default operation program P200; otherwise, return to the sub-correction program P306.

Please continue to refer to FIG. 9 and FIG. 10A. In a specific embodiment, as shown in FIG. 9, in the sub-calibration process P306 of period T3, after step S301 is configured as the calibration configuration (omitted in FIG. 9), First, step S361 is entered to adjust the parameters to indicate the bit sequence of the current test bits of the test correction code CCT. In this embodiment, the initial value of the adjustment parameters is N during the period T3, so the test correction code CCT bits need to be corrected. The order is the Nth bit, then set the current test bit (Nth bit) of the test correction code CCT to the enabled state (for example, set to 1), and set the remaining lower significant bits of the test correction code CCT Set to a disabled state (e.g. set to 0). Then step S362 is entered, the adjustable offset value Vosa corresponding to the operation circuit 2002 is provided according to the test correction code CCT, and then the comparison circuit 100 is operated according to the adjustable offset value Vosa to generate the comparison result CPO. Then enter step S363 to determine whether the adjustable offset value Vosa is greater than the changing offset value Vosv. In this specific embodiment, the comparison result CPO indicates that the adjustable offset value Vosa is greater than the changing offset value Vosv of the operating circuit 2002, so step 1 is entered. S364: Set the current test bit of the test correction code CCT to a non-enabled state (for example, set to 0). Then step S365 is entered to determine whether the bit sequence of the current test bit of the test correction code CCT is the least significant bit. In this embodiment, it is the Nth bit, not the least significant bit. Therefore, the adjustment parameter update step S326 is entered. The adjustment parameter N is decreased by 1 to indicate that the value of the next bit sequence (N-1th bit) of the test correction code CCT needs to be corrected, and the adjustment parameter is updated to N-1. Next, in the embodiments of FIG. 9 and FIG. 10A , after the adjustment parameter update step S326 is completed, the system returns to the default operation program P200, that is, enters the default operation program P200 of period T4 to operate the correction code CCO (not yet updated, but still Correct the changing offset value Vosv for the adjustable offset value Vosa corresponding to Y1).

Then, in the sub-correction program P306 of period T5, after step S301 is configured as the correction configuration (omitted in Figure 9), step S361 is first entered to adjust the parameter N-1 to indicate that the test correction code CCT is the N-1th bit , then set the current test bit (N-1th bit) of the test correction code CCT to the enabled state (for example, set to 1), and set the remaining lower significant bits of the test correction code CCT to non-enabled The state (for example, is set to 0), and according to the above, the Nth bit of the test correction code CCT is in a non-enabled state (for example, is 0). Then step S362 is entered, the adjustable offset value Vosa corresponding to the operating circuit 2002 is provided according to the test correction code CCT, and then the comparison circuit 100 is operated according to the adjustable offset value Vosa to generate a ratio. Compare the results to CPO. Then enter step S363 to determine whether the adjustable offset value Vosa is greater than the changing offset value Vosv. In this specific embodiment, the comparison result CPO indicates that the adjustable offset value Vosa is less than the changing offset value Vosv of the operating circuit 2002, so the test is maintained. The N-1th bit of the correction code CCT is in the enabled state (for example, set to 1), and step S364 is skipped, and step S365 is entered to determine whether the bit sequence of the current test bit of the test correction code CCT is the least significant bit. The bit in this embodiment is the N-1th bit, not the least significant bit. Therefore, the adjustment parameter update step S326 is entered, and the adjustment parameter N-1 is decreased by 1 to indicate the next bit sequence (Nth bit) of the test correction code CCT. -2 bits) needs to be corrected, and the adjustment parameter is updated to N-2. Next, in the embodiments of FIG. 9 and FIG. 10A , after the adjustment parameter update step S326 is completed, the system returns to the default operation program P200, that is, enters the default operation program P200 of period T6 to operate the correction code CCO (not yet updated, but still Correct the changing offset value Vosv for the adjustable offset value Vosa corresponding to Y1).

Then, as shown in Figure 9, the process similar to the period T3 to the period T4, or the process similar to the period T5 to the period T6 is continuously repeated, and the operation correction is updated when the adjustable offset value Vosa approaches the changing offset value Vosv. Code CCO. In a specific embodiment, when in step S365 of the sub-correction procedure P306, it is determined that the bit sequence of the current test bit of the test correction code CCT has become the least significant bit, for example, the sub-correction procedure P306 of the period T9 in Figure 9, When the bit sequence is the least significant bit (for example, the 1st bit), the correction code update step S325 is entered, the operation correction code CCO is updated to Y2 according to the test correction code CCT, and the adjustment parameters are reset to the initial value N. After the correction code update step S325 is completed, then return to the default operation program P200, that is, enter the default operation program P200 of the period T10 to operate the adjustable offset value Vosa corresponding to the correction code CCO (updated to Y2) to correct changes. Offset value Vosv.

Please refer to FIG. 11 , which shows a schematic diagram of an operation circuit with a low correction period (operation circuit 2011 ) according to a specific embodiment of the present invention. In a specific embodiment, the operation circuit 2011 is a switched capacitor analog-to-digital converter. The operation circuit 2011 includes a comparison circuit 105 and an amplification circuit. 200. The first digital-to-analog converter 310, the second digital-to-analog converter 320, the offset adjustment circuit 30 and the operation control circuit 40. In this embodiment, the operating circuit 2011 has a varying offset value Vosv, where the varying offset value Vosv includes the first varying offset value Vosv1 of the comparison circuit 105 and the second varying offset value Vosv2 of the amplifying circuit 200 . In one embodiment, as shown in FIG. 11 , the amplifying circuit 200 is coupled to the comparison circuit 105 via a first digital-to-analog converter 310 and a second digital-to-analog converter 320 . The equivalent circuit of the amplifying circuit 200 includes an ideal amplifier 60 , and has a second variable offset value Vosv2. The amplifying circuit 200 also includes a sampling and holding circuit 50. The sampling and holding circuit 50 includes a sub-sampling holding circuit 51 and a sub-sampling holding circuit 52. The sub-sampling holding circuit 51 and the sub-sampling holding circuit 52 are used for The positive sub-output signal and the negative sub-output signal generated by the ideal amplifier 60 are sampled and maintained according to the signal SH. In this embodiment, the first digital-to-analog converter 310 and the second digital-to-analog converter 320 are switched capacitor digital-to-analog converters, and the second digital-to-analog converter 320 is used as an offset generating circuit.

Please refer to FIG. 11 and FIG. 12 at the same time. FIG. 12 shows the operation waveform and program diagram corresponding to the embodiment of FIG. 11 . In one embodiment, in the default operation program P200, the switch Sw1 controls the first input terminal Ni1a of the amplifier circuit 200 to be coupled to the node N1, and the switch Sw2 controls the second input terminal Ni2a of the amplifier circuit 200 to be coupled to the node N2. At this time, the amplifier circuit 200 is used to amplify the analog signal SA and generate an amplified signal at the first input terminal Ni1 of the comparison circuit 105 and the second input terminal Ni2 of the comparison circuit. The operation control circuit 40 operates according to the clock signal Ckcom and the correction enable signal Calen. The first digital-to-analog converter 310 is controlled to generate an adjustable reference value, and the comparison circuit 105 is used to compare the amplified signal with the adjustable reference value, for example, using a successive approximation register type analog-to-digital conversion method to generate a digital signal corresponding to the analog signal SA. Output code CDO. In one embodiment, in the low bit number correction process P300, the switch Sw1 controls the first input terminal Ni1a of the amplifier circuit 200 to be coupled to the node N3, and the switch Sw2 controls the second input terminal Ni2a of the amplifier circuit 200 to be coupled to the node N4. , so that the two input terminals of the amplifier circuit 200 are commonly coupled to the common mode voltage Vcm. At this time, the offset adjustment circuit 30 adjusts the clock signal Ckcom and The enable signal Calen is corrected to control the second digital-to-analog converter 320 to generate an adjustable offset value to correct the varying offset value Vosv of the operating circuit 2011 in the default operating procedure P200.

Please refer to FIG. 13. FIG. 13 shows a characteristic curve of the adjustable offset value of the operating circuit with a low correction period of the present invention corresponding to the operating correction code or the test correction code. In a preferred embodiment, as shown in Figure 13, the characteristic curve of the adjustable offset value Vosa used to correct the varying offset value Vosv of the present invention corresponding to the operation correction code CCO or the test correction code CCT is sub-radix 2. The curve (sub-radix-2) enables the operation correction code or measurement correction code to be searched within the preset error range marked in Figure 13.

Please refer to FIG. 14. FIG. 14 shows a schematic diagram of an operation circuit with a low correction period (operation circuit 2014) according to a specific embodiment of the present invention. The operation circuit 2014 of FIG. 14 is similar to the operation circuit 2011 of FIG. 11 . In one embodiment, in the default operation program P200 , in the operation circuit 2014 , the operation control circuit 40 adjusts the offset generated by the offset adjustment circuit 30 As a result, the clock signal Ckcom and the correction enable signal Calen control the first digital-to-analog converter 311 to provide an adjustable reference value. In this embodiment, the offset generating circuit includes some bits of the first digital-to-analog converter 311 The second digital-to-analog converter 321 is composed of elements.

It should be noted that the adjustable offset value Vosa, the variable offset value Vosv, the first variable offset value Vosv1, and the second variable offset value Vosv2 in the above embodiments are all offset voltages, but are not limited to offset voltages. , in other embodiments, it can also be an offset current.

The present invention has been described above with reference to the preferred embodiments. However, the above description is only to make it easy for those familiar with the art to understand the content of the present invention, and is not intended to limit the scope of rights of the present invention. The various embodiments described are not limited to single application, but can also be used in combination. For example, two or more embodiments can be used in combination, and part of the components in one embodiment can also be used to replace those in another embodiment. Corresponding components. In addition, under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. For example, the so-called "basic "Processing or computing or producing an output result based on a certain signal" is not limited to based on the signal itself, but also includes, when necessary, voltage and current conversion, current to voltage conversion, and/or ratio conversion of the signal, and then based on the conversion The final signal is processed or calculated to produce an output result. It can be seen from this that under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. There are many combinations, and they are not listed here. Accordingly, the scope of the present invention is intended to cover the above and all other equivalent changes.

Calen: Correction enable signal

CCO: Operation correction code

CCT: test correction code

P100:Procedure

P200:Procedure

P305: Sub-calibration program

T1~T8: time period

Vosa: adjustable offset value

Vosv: change offset value

X: unit difference

Z1, Z2: Value of operation correction code

Claims (26)

A correction method for correcting an operating circuit, wherein the operating circuit has a changing offset value, the operating circuit includes at least one comparison circuit, wherein the correction method is used to provide an adjustable offset value to correct the changing offset value, wherein the changing offset value includes a first changing offset value of the comparison circuit, and the correction method includes: P100: configure the operating circuit into a correction configuration and reset an adjustment parameter to an initial value, An initial correction process is performed based on a comparison result of the comparison circuit to determine an operation correction code with N bits, where N is a positive integer greater than or equal to 2; P200: configure the operation circuit to an operation configuration, according to The operation correction code operates the operation circuit to perform a preset operation program, wherein the operation correction code corresponds to the adjustable offset value and is used to correct the changing offset value in the preset operation program; P300: change the operation The circuit is configured in the correction configuration, adjusts a test correction code according to the adjustment parameter, and operates the operation circuit according to the test correction code to perform a low-bit correction process to update the adjustment parameter or update according to the updated adjustment parameter. The operation correction code, wherein the test correction code is related to the operation correction code, then returns to the program P200; wherein the low-bit number correction process includes: configuring the operation circuit to the correction configuration; and performing sub-steps up to M times. Calibration procedure P305 or sub-correction procedure P306 performed at most M times, where M is a positive integer less than N; then return to procedure P200; wherein the sub-correction procedure P305 is used to adjust the test with a single slope starting from the operation correction code A least significant bit of the correction code, used to determine whether to continue adjusting the test correction code or to update the operation correction code; The sub-correction program P306 is used to adjust one bit of the test correction code through a binary search method to determine whether to continue to adjust the test correction code or update the operation correction code; where M in the low-bit correction program is A fixed value, or a variable value. The correction method of claim 1, wherein the operating circuit further includes an amplifying circuit coupled to the comparison circuit, and the varying offset value further includes a second varying offset value of the amplifying circuit. The correction method as described in claim 1, wherein the sub-correction procedure P305 includes: setting the test correction code to be equal to the operation correction code superimposed on the adjustment parameter; and determining whether the adjustment parameter is the initial value, wherein if the adjustment The parameter is the initial value, and the direction judgment step S310 is performed; otherwise, the difference comparison step S320 is performed; wherein the direction judgment step S310 includes: providing the adjustable offset value corresponding to the operating circuit according to the test correction code; The offset value operates the comparison circuit to generate the comparison result; determines a correction direction according to the comparison result; and superimposes the adjustment parameter with a preset unit difference corresponding to the correction direction to update the adjustment parameter; wherein the difference The value comparison step S320 includes: providing the adjustable offset value corresponding to the operation circuit according to the test correction code; operating the comparison circuit according to the adjustable offset value to generate the comparison result; and determining the direction of the comparison result, where If the comparison result corresponding to the correction direction is inverted, enter the correction code update step S323, otherwise enter the adjustment parameter update step S324; wherein the correction code update step S323 includes: superimposing the operation correction code on the adjustment parameter to update the Operation correction code; Reset the adjustment parameter to the initial value; wherein the adjustment parameter update step S324 includes: superimposing the adjustment parameter with the unit difference to update the adjustment parameter; or wherein the sub-correction procedure P306 includes: indicating the adjustment parameter with the adjustment parameter Test the bit sequence of a current test bit of the test correction code; set the current test bit of the test correction code to a consistent state, and set the remaining lower significant bits of the test correction code to a non-enabled state; providing an adjustable offset value corresponding to the operation circuit according to the test correction code; operating the comparison circuit according to the adjustable offset value to generate the comparison result; and judging the difference between the adjustable offset value and The size of the changing offset value, if the comparison result indicates that the adjustable offset value is greater than the changing offset value of the operating circuit, the current test bit of the test correction code is set to the non-enabled state; judging Whether the bit sequence is a least significant bit, where if the adjustment parameter indicates that the least significant bit has been reached, the correction code update step S325 is performed, otherwise the adjustment parameter update step S326 is entered; wherein the correction code update step S325 includes : Update the operation correction code according to the test correction code; reset the adjustment parameter to the initial value; wherein the adjustment parameter update step S326 includes: decrementing the current adjustment parameter by 1 to update the adjustment parameter. The correction method as described in claim 3, wherein the initial value of the adjustment parameter corresponding to the sub-correction procedure P305 is 0, and the initial value of the adjustment parameter corresponding to the sub-correction procedure P306 is N. The correction method of claim 3, wherein the correction code updating step S323 further includes: superimposing the operation correction code on the adjustment parameter according to the correction direction and deducting a unit difference to update the operation correction code. The correction method as described in claim 3, wherein the process P300 includes: operating the comparison circuit to perform the low-bit number correction process with 1 clock cycle, wherein the unit difference corresponds to a least significant value corresponding to the correction direction. Bit (least significant bit, LSB). The correction method as described in claim 1, wherein M is equal to 1. The correction method as described in claim 1, wherein the time length required for the M times of the sub-correction procedure P305 or the M times of the sub-correction procedure P306 is less than the time length required for the preset operation procedure. The correction method as described in claim 1, wherein the time length required for the M times of the sub-correction procedure P305 or the M times of the sub-correction procedure P306 is less than the time length required for the initial correction procedure. The correction method as claimed in claim 1, wherein the characteristic curve of the adjustable offset value corresponding to the operation correction code or the test correction code is a sub-radix-2 curve (sub-radix-2). The correction method as described in claim 1, wherein the initial correction procedure includes: a sub-correction procedure P306 that is continuously performed N times, wherein the initial value of the adjustment parameter corresponding to the sub-correction procedure P306 is N. The correction method as claimed in claim 1, wherein in the default operation program, the comparison circuit is used to compare an input signal with a reference threshold, or is used in an analog-to-digital converter. An operating circuit with a low correction period, wherein the operating circuit has a varying offset value, including: At least one comparison circuit for comparing a difference between a first input terminal of the comparison circuit and a second input terminal of the comparison circuit to generate a comparison result, wherein the variation offset value includes a first variation of the comparison circuit Offset value; an offset generation circuit, coupled to the comparison circuit, used to generate an adjustable offset value according to an operation correction code having N bits to correct the varying offset value; an offset adjustment The circuit is used to generate the operation correction code to correct the changing offset value according to the following steps, and operate the operation circuit to perform a preset operation procedure according to the operation correction code: P100: Configure the operation circuit into a correction configuration, And reset an adjustment parameter to an initial value, and perform an initial correction process based on a comparison result of the comparison circuit to determine the operation correction code, where N is a positive integer greater than or equal to 2; P200: Configure the operation circuit as An operation configuration, operating the operation circuit according to the operation correction code to perform the preset operation procedure, wherein the operation correction code corresponds to the adjustable offset value and is used to correct the changing offset value in the preset operation procedure ;P300: Configure the operation circuit to the correction configuration, adjust a test correction code according to the adjustment parameter, and operate the operation circuit to perform a low-bit correction program according to the test correction code to update the adjustment parameter or according to the required The updated adjustment parameter updates the operation correction code, wherein the test correction code is related to the operation correction code, and then returns to the process P200; wherein the low bit number correction process includes: configuring the operation circuit to the correction configuration; and Perform the sub-correction procedure P305 at most M times or perform the sub-correction procedure P306 at most M times, where M is a positive integer less than N; then return to procedure P200; The sub-correction program P305 is used to adjust a least significant bit of the test correction code with a single slope starting from the operation correction code to determine whether to continue to adjust the test correction code or update the operation correction code; wherein the sub-correction Program P306 is used to adjust one bit of the test correction code through a binary search method to determine whether to continue to adjust the test correction code or update the operation correction code; where M in the low-bit correction program is a fixed value, or a variable value. The operating circuit of claim 13 further includes an amplifying circuit coupled to the comparison circuit, wherein the varying offset value further includes a second varying offset value of the amplifying circuit. The operation circuit as described in claim 14, wherein in the preset operation program, the comparison circuit is used to compare an input signal with a reference threshold, and the comparison result correspondingly indicates an operation state of the operation circuit; or the operation circuit is an analog-to-digital converter, wherein in the default operation program, the amplifying circuit is used to amplify an analog signal and generate an amplified signal at the first input terminal of the comparison circuit and the second input terminal of the comparison circuit , the comparison circuit is used to compare the amplified signal with an adjustable reference value to generate a digital output code corresponding to the analog signal. The operating circuit of claim 15, wherein the analog-to-digital converter includes a first digital-to-analog converter, the first digital-to-analog converter is used to provide the adjustable reference value in the preset operating program, wherein the bias The shift generating circuit includes a second digital-to-analog converter composed of partial bits of the first digital-to-analog converter. The operation circuit as described in claim 13, wherein the sub-correction program P305 includes: setting the test correction code to be equal to the operation correction code superimposed on the adjustment parameter; and determining whether the adjustment parameter is the initial value, wherein if the adjustment The parameter is the initial value, and the direction judgment step S310 is performed; otherwise, the difference comparison step S320 is performed; the direction judgment step S310 includes: Provide the adjustable offset value corresponding to the operation circuit according to the test correction code; operate the comparison circuit according to the adjustable offset value to generate the comparison result; determine a correction direction according to the comparison result; and superimpose the adjustment parameters A preset unit difference corresponding to the correction direction is used to update the adjustment parameter; wherein the difference comparison step S320 includes: providing the adjustable offset value corresponding to the operating circuit according to the test correction code; according to the adjustable The offset value operates the comparison circuit to generate the comparison result; and determines the direction of the comparison result, where if the comparison result corresponds to the correction direction and is inverted, enter the correction code update step S323, otherwise enter the adjustment parameter update step S324. ; wherein the correction code update step S323 includes: superimposing the operation correction code on the adjustment parameter to update the operation correction code; resetting the adjustment parameter to the initial value; wherein the adjustment parameter update step S324 includes: superimposing the adjustment parameter The unit difference is used to update the adjustment parameter; or the sub-correction process P306 includes: using the adjustment parameter to indicate a bit sequence of a current test bit of the test correction code; changing the current test bit sequence of the test correction code. bits are set to an enabled state, and the remaining lower significant bits of the test correction code are set to a non-enabled state; an adjustable offset value corresponding to the operating circuit is provided according to the test correction code; The comparison circuit is operated according to the adjustable offset value to generate the comparison result; and Determine the size of the adjustable offset value and the changing offset value, wherein if the comparison result indicates that the adjustable offset value is greater than the changing offset value (present offset) of the operating circuit, the test correction code is The current test bit is set to the non-enabled state; it is determined whether the bit sequence is a least significant bit. If the adjustment parameter indicates that the least significant bit has been reached, the correction code update step S325 is performed. Otherwise, the adjustment parameter is entered. Update step S326; wherein the correction code update step S325 includes: updating the operation correction code according to the test correction code; resetting the adjustment parameter to the initial value; wherein the adjustment parameter update step S326 includes: subtracting 1 from the current adjustment parameter to update the tuning parameters. The operating circuit of claim 17, wherein the initial value of the adjustment parameter corresponding to the sub-correction procedure P305 is 0, and the initial value of the adjustment parameter corresponding to the sub-correction procedure P306 is N. The operation circuit of claim 17, wherein the correction code updating step S323 further includes: superimposing the operation correction code on the adjustment parameter according to the correction direction and subtracting a unit difference to update the operation correction code. The operation circuit as described in claim 17, wherein the process P300 includes: operating the comparison circuit to perform the low-bit number correction process with 1 clock cycle, wherein the unit difference corresponds to a least significant value corresponding to the correction direction. Bit (least significant bit, LSB). The operating circuit as claimed in claim 13, wherein M is equal to 1. The operation circuit as described in claim 13, wherein the time length required for the M times of the sub-correction procedure P305 or the M times of the sub-correction procedure P306 is less than the time length required for the preset operation procedure. The operation circuit as described in claim 13, wherein the time length required for the M times of the sub-correction process P305 or the M times of the sub-correction process P306 is less than the time length required for the initial correction process. The operating circuit of claim 13, wherein the adjustable offset value corresponds to a characteristic curve of the operating correction code or the test correction code that is a sub-radix-2 curve. The operating circuit as claimed in claim 13, wherein the initial correction procedure includes: a sub-correction procedure P306 that is continuously performed N times, wherein the initial value is N. The operation circuit of claim 13, wherein in the default operation program, the comparison circuit is used to compare an input signal with a reference threshold, or is used in an analog-to-digital converter.

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