TWI820769B - Apparatus, method, system and medium for measuring pulse signal width - Google Patents

Abstract

An apparatus, method, system and medium are provided. The apparatus includes: a buffer chain, including N first buffers connected end to end, N first AND gates with one input connected to a pulse signal and the other input connected to an output of a corresponding first buffer, and N flip-flops coupled with outputs of respective first AND gates; a path time delay adjustment circuit, with an input receiving a pulse signal, and an output connected to an input terminal of the first buffer; a control apparatus, controlling the time delay produced by the adjustment circuit to be reduced by at least one step from a preset time delay during each adjustment until an output of a P ^thflip-flop flips; a measuring device measuring the pulse signal’s width according to an output of each flip-flop, the time delay of each first buffer and the time delay of the adjustment circuit.

Description

Pulse signal width measurement device, method, system and medium

The present invention relates to the field of integrated circuits, and more specifically, to a pulse signal width measurement device, method, system and medium for measuring the delay of a critical path.

Modern integrated circuits are affected by process deviations during the manufacturing process, resulting in performance differences between different finished products. For example, some integrated circuits can operate at a frequency of 3GHz, while some can only operate at 2.8GHz. . Integrated circuit operating speed is often determined by critical path delays within the chip. The critical path is generally a batch of paths with the longest delay within the integrated circuit. In order to perform performance calibration of integrated circuits, the delay of the critical path of the integrated circuit can be directly measured during factory measurements. The measurement can use a time-to-digit conversion circuit.

In addition, during the operation of the integrated circuit, due to the influence of aging, temperature, and supply voltage, the delay of the internal path of the integrated circuit will also fluctuate, which may cause the delay of some critical paths in the integrated circuit to exceed clock cycles, causing errors in integrated circuit operation.

Therefore, it is necessary to accurately measure the delay of certain critical paths in integrated circuits.

According to one aspect of the present invention, a pulse signal width measuring device is provided, including: a buffer link, including N first buffers, one input end connected to the pulse signal and the other input end connected to the output of the corresponding first buffer. N first AND gates, and corresponding N flip-flops coupled to the output terminals of each first AND gate, and the respective output terminals of the N first buffers are connected to the input terminals of the next first buffer. are connected, where N is a positive integer greater than 1; a path delay adjustment circuit, wherein an input end of the path delay adjustment circuit receives a pulse signal, and an output end of the path delay adjustment circuit is connected to the buffer link The input end of the first buffer; the control device controls the delay generated by the path delay adjustment circuit according to the preset adjustment step during each adjustment to reduce the delay from the preset delay by at least one preset adjustment step until The output of the P-th flip-flop changes, where P is a positive integer and less than or equal to N; the measuring device is connected to the output end of each flip-flop and the control device, and is at least based on the result output by the output end of each flip-flop and each The width of the pulse signal is measured by the delay of the first buffer and the delay of the path delay adjustment circuit just before the output of the P-th flip-flop changes.

According to another aspect of the present invention, a pulse signal width measurement method using a pulse signal width measurement device is provided, wherein the pulse signal width measurement device includes: a buffer link, including N first buffers, an input end connected to the pulse signal and another input terminal connected to N first AND gates corresponding to the outputs of the first buffers and corresponding N flip-flops coupled to the output terminals of each first AND gate, and the N first buffers Each output end of the buffer is connected to the input end of the next first buffer, where N is a positive integer greater than 1; a path delay adjustment circuit, wherein the input end of the path delay adjustment circuit receives a pulse signal, and the The output end of the path delay adjustment circuit is connected to the input end of the first buffer in the buffer chain; wherein the pulse signal width measurement method includes: controlling the path according to a preset adjustment step during each adjustment The delay generated by the delay adjustment circuit is reduced from the preset delay by at least one preset adjustment step until the output of the P-th flip-flop changes, where P is a positive integer and less than or equal to N; at least according to the output of each flip-flop. The width of the pulse signal is measured as a result of the delay of each first buffer and the delay of the path delay adjustment circuit just before the output of the P-th flip-flop changes.

According to another aspect of the present invention, a computer system is provided, including: a processor; and a memory coupled to the processor and storing computer-executable instructions therein for performing a pulse signal width measurement method when executed by the processor.

According to another aspect of the present invention, a computer-readable medium is provided on which a computer program is stored, wherein the pulse signal width measurement method is implemented when the program is executed by a processor.

All aspects of the present invention adopt a path delay adjustment circuit, which greatly improves the measurement accuracy; the measurement structure is converted into a ring oscillator measurement, which enables more accurate measurement and reduces the impact of factors such as process deviation, aging, wiring, etc. on the accuracy of the measurement structure. Error effects; the signal latch circuit is used to generate the clock signal of the flip-flop to avoid the metastable phenomenon of the flip-flop; the measurement accuracy is high; compared with the use of digital analog conversion circuits, resistors and capacitors, etc., this structure can use pure digital structures ( For example, multiplexers, logic circuits and latch structures, etc.) can be realized by using components in the standard device library, and can be directly synthesized, which is extremely friendly to the integrated circuit design process; this structure is resistant to aging interference, even if the circuit is due to aging As a result, the delay is increased and the measurement accuracy is less affected; this structure only requires a very small area overhead and has little impact on the original integrated circuit design.

Reference will now be made in detail to the specific embodiments of the invention, examples of which are illustrated in the accompanying drawings. Although the present invention will be described in conjunction with specific embodiments, it will be understood that there is no intention to limit the invention to the described embodiments. On the contrary, the intention is to cover alterations, modifications and equivalents included within the spirit and scope of the invention as defined by the appended claims. It should be noted that the method steps described here can be implemented by any functional block or functional arrangement, and any functional block or functional arrangement can be implemented as a physical entity or a logical entity, or a combination of both.

In traditional technology, a time-to-digital conversion circuit can be used to measure the delay of the critical path and determine the status of the integrated circuit, such as whether it is in a state of excessive aging, insufficient supply voltage, etc.

Time-to-digital conversion circuits are also widely used in measuring the time interval between two signals, such as ultrasonic flowmeters, high-energy physics and nuclear physics, various handheld/airborne or fixed-working high-precision laser rangefinders, lidar, and laser scanning. Instruments and other fields.

Usually the critical path delay or the time interval between two signals to be measured by the time-to-digital conversion circuit is several ns or even hundreds of ps. During measurement, the critical path delay or the time interval of two signals is first converted into a pulse signal. The width of the pulse signal is the critical path delay or the time interval of the two signals. Time-to-digital conversion circuits generally measure the number of signals passing through logic gate circuits, and their accuracy depends on the delay of the unit logic gate circuit.

However, the design structure of the existing technology is complex, and the accuracy depends on the delay of the buffer. There is a problem of insufficient accuracy. At the same time, due to aging and other effects, the delay of the buffer will change, resulting in inaccurate measurement; path delay measurement requires It takes a long time, which affects the normal operation of the critical path; some designs use analog circuits, which are complex designs and difficult to implement in advanced processes.

The solution of the present invention further improves the measurement accuracy of pulse width through the path delay adjustment scheme, which can reach 25% of the delay of a single buffer; further, by converting the measurement structure into a ring oscillator, it reduces factors such as aging and wiring. The impact of the error on the measurement accuracy of the present invention; the present invention can complete the measurement of the critical path delay in only 4 clock cycles at the fastest, and has little impact on the critical path; and the present invention can be implemented using pure digital circuits to achieve Convenient and easy to integrate.

Figure 1 shows an overall block diagram of a time-to-digit conversion circuit 100 according to an embodiment of the present invention.

As shown in Figure 1, the time-digit conversion circuit 100 designed in the present invention mainly includes three parts: a pulse signal conversion device 101, a pulse signal width measurement device 102 and a control device 103. The pulse signal conversion device 101 mainly converts the object to be measured (for example, the time delay of the critical path, or the time interval to be measured between two signals, etc.) into a pulse signal. The width of the pulse signal is the value of the object to be measured (i.e., time). interval). The pulse signal width measuring device is used to measure the width of the pulse signal output by the pulse signal converting device 101. The control device is used to control the operation of the pulse signal converting device 101 and the pulse signal width measuring device.

Figure 2A shows a circuit and waveform schematic for converting critical path delays into pulse signals.

The same signal is used to pass through two paths (one path has the delay of the critical path, and one path does not have the delay) and then input a mutually exclusive OR gate to obtain a pulse signal with the delay of the critical path as the width.

Specifically, usually, the starting point of the path is, for example, the output signal of a flip-flop, and the output obtained by passing the output signal of the flip-flop through the critical path and the output of the flip-flop directly passing through the wire (that is, it is still the input signal to the critical path) are simultaneously Enter a two-port exclusive OR gate. Because there is a delay in the critical path, there is a delay difference between the two signals input to the mutex OR gate. According to the characteristics of the mutually exclusive OR gate, when there is a difference between the two input signals (for example, the high-level output of the flip-flop output passes through the critical path and the output is still low-level (because the high-level level is still in the critical path at this time) has not finished), and the direct output of the flip-flop is high) will cause the mutex or gate output to be high, otherwise, when both input signals are high (i.e., the flip-flop output is high) After completing the critical path and outputting a high level, the direct output of the flip-flop is still a high level) or a low level (for example, there is no signal input), the output of the mutually exclusive OR gate is a low level.

Specifically, Figure 2B shows a schematic waveform diagram of the critical path delay converted into a pulse signal. By configuring the trigger at the starting point of the critical path, the input of the critical path is a rising edge signal, and the output of the critical path is a rising edge signal that delays the duration of the critical path. After the two signals pass through a mutually exclusive OR gate , a pulse signal with a width of the critical path delay can be output. That is, the pulse signal is the output of a mutually exclusive OR gate obtained by using the signal at the starting point of the critical path of the integrated circuit through the critical path and the signal at the starting point as two inputs of the mutually exclusive OR gate.

Here, using a mutually exclusive OR gate to obtain the above-mentioned specific output is only an example. Other circuits that can obtain the above-mentioned specific output after receiving the above two inputs are also included in the present disclosure and will not be described again here.

In addition to measuring the critical path delay, the above method can be used to obtain a pulse signal with a width of the critical path delay. For measuring the delay difference between the rising edges of the two signals to be measured, the above method can also be used to convert the width of the pulse signal. .

FIG. 3A shows a circuit and waveform schematic diagram for converting the delay difference of two rising signals into pulse signals. The difference in delay between the rising edges of the two signals to be measured is the width of the converted pulse signal. Figure 3B shows a schematic waveform diagram of two rising signal delay differences converted into pulse signals. After the two signals pass through the mutually exclusive OR gate, a pulse signal with a width equal to the delay difference between the rising edge of the signal to be measured can be output.

Of course, each of the above examples uses the rising edge as the starting point of the delay difference, but in the actual circuit, the falling edge can also be used as the starting point of the delay difference, and output a width equal to the arrival of the falling edge of the signal to be measured. For pulse signals with different time delays, correspondingly, mutually exclusive OR gates must also be converted into other gates to achieve the above conversion.

Figure 4 shows a block diagram of one embodiment of a pulse signal width measuring device 400 according to an embodiment of the present invention.

The pulse signal width measuring device 400 includes: a buffer link 401, including N first buffers 4011, one input terminal connected to the pulse signal and the other input terminal connected to the output of the corresponding first buffer 4011. gate 4012, and corresponding N flip-flops 4013 (flip-flop 1 to flip-flop N) coupled to the output of each first and gate 4012, and the respective outputs of the N first buffers 4011 are coupled to the next The input end of a buffer 4011 is connected, where N is a positive integer greater than 1; the path delay adjustment circuit 402, where the input end of the path delay adjustment circuit 402 receives the pulse signal, and the output end of the path delay adjustment circuit 402 is connected to the input end of the first buffer 4011 in the buffer chain 401; the control device 403 controls the delay generated by the path delay adjustment circuit 402 according to the preset adjustment step size during each adjustment to reduce the delay generated by the preset delay by at least A preset adjustment step until the output of the P-th flip-flop 4013 changes, where P is a positive integer and less than or equal to N; the measuring device 404 is connected to the output end of each flip-flop 4013 and the control device 403, and according to each trigger The high-precision width of the pulse signal is measured by using the output result of the output terminal of the buffer 4013, the delay of each first buffer 4011, and the delay of the path delay adjustment circuit 402 just before the output of the P-th flip-flop 4013 changes.

In this way, the solution of adding the path delay adjustment circuit 402 improves the measurement accuracy to the preset adjustment step of the path delay adjustment circuit 402.

FIG. 5 shows a block diagram of another embodiment of a pulse signal width measuring device 500 according to an embodiment of the present invention. The same parts in Figure 5 as in Figure 4 are identified with the same reference numerals. Figure 5 will also be described in detail later.

Next, the structure and operation of each device in Figure 4 will be described with reference to other figures.

FIG. 6 shows each first buffer 4011 and the first AND gate 4012 in the buffer chain 401 when an example pulse signal waveform is input and the path delay adjustment circuit 402 is not considered according to an embodiment of the present invention. The output waveform diagram.

As shown in Figure 6, when a pulse signal to be measured with a width to be measured is input, after the delay of the first first buffer 4011, the output of the first first buffer 4011 is as shown in Figure 6 Waveforms with the same width, and then after the delay of the second first buffer 4011, the output of the second first buffer 4011 is as shown in Figure 6, and so on, it can be seen that each first buffer 4011 The output waveform is the same as the pulse signal to be measured, except that the output of each first buffer 4011 will further delay the pulse signal to be measured by the delay of the first buffer 4011.

After adding the first AND gate 4012 so that the pulse signal to be measured performs an AND operation with the output of the first buffer 4011, when the pulse signal to be measured is at a high level, the output of the first AND gate 4012 and is connected to the first AND gate 4012 The output signal of the first buffer 4011 is the same, that is, when the pulse signal to be measured is a high level and the output signal of the first buffer 4011 input to the first AND gate 4012 is also a high level, the first AND gate 4012 The output is a high level; otherwise the first AND gate 4012 always outputs a low level. Therefore, combined with the waveform of the pulse signal in Figure 6, the output signal of the first first AND gate 4012 is as shown in Figure 6, the output signal of the second first AND gate 4012 is as shown in Figure 6, and so on, until The output of the mth first AND gate 4012 has a high level, but the output of the m+1th first AND gate 4012 does not have a high level, where m is a positive integer.

Under the control of the first AND gate 4012 for signal propagation control, the rising edge of the pulse signal to be measured can only propagate through m first buffers 4011 within the time corresponding to the width of the pulse signal, where m <= N, so that these m The first AND gate 4012 for signal propagation control connected to the first buffer 4011 can output a pulse signal, as shown in FIG. 6 . By recording the number of first AND gates 4012 that output excessively high level pulse signals, the width of the pulse signals measured by the same number of first buffers 4011 can be recorded, that is, the number multiplied by the delay of the first buffers 4011 .

Of course, this measurement result is rough, because as long as the width of the pulse signal is less than one delay of the first buffer 4011 than the total delay of the m-1 first buffer 4011, then the rising edge of the pulse signal to be measured will The signal width will propagate through m first buffers 4011 within a time period corresponding to the signal width. It is not accurate as to how much the width of the pulse signal is greater than the total delay of the m-1th first buffer 4011. According to an embodiment of the present invention, the width of the pulse signal can be further accurately measured later through the path delay adjustment circuit 402 .

The following describes the specific high-precision measurement operations and functions of the path delay adjustment circuit 402 according to the embodiment of the present invention.

In traditional technology, there is no path delay adjustment circuit 402, only the first buffer 4011 and the first AND gate 4012. If the buffer link 401 is simply used for measurement, the measurement resolution of the pulse signal is equal to the buffer. Delay of a single buffer on link 401. That is, it is known that the delay of the first buffer 4011 is about 5 ps. As shown in Figure 6, the output of the m-th first AND gate 4012 has a high level, and the output of the m+1-th first AND gate 4012 If there is no high level, the width of the roughly measured pulse signal is m×5ps. But in fact, the width of the pulse signal may be between (m-1)×5 ps to m×5ps, because as long as the width of the pulse signal is more than the delay of m-1 first buffers 4011, and is more than m+1 The delay of the mth first buffer 4011 is small, so the output of the first AND gate 4012 of the mth first buffer 4011 will be a high-level pulse. Therefore, the measurement accuracy using the buffer link 401 alone is insufficient. In actual experiments, if the pulse signal width to be measured is 300ps, the measurement error corresponding to the 5ps delay buffer is 1.67%, which will face the problem of insufficient accuracy.

Therefore, the present invention further introduces a path delay adjustment circuit 402, then the output waveforms of each first buffer 4011 and the first AND gate 4012 are different from Figure 6, but you can refer to Figure 6, that is, the first first buffer The waveform output by 4011 is further delayed by the delay itself of the path delay adjustment circuit 402 on the basis of Figure 6 (note that the delay of the path delay adjustment circuit 402 is not shown in Figure 6), and the subsequent first buffer 4011 is also To delay further. Then, this path delay adjustment circuit 402 is controlled by the control device 403, and can gradually reduce the overall delay of the path delay adjustment circuit 402 in very small steps.

Assume that the delay delay of the first buffer 4011 in the buffer link 401 is 5ps, the preset delay of the path delay adjustment circuit 402 is initially 10ps, and the preset adjustment step is 1ps. Assume that the actual width of the pulse signal to be measured is is 58ps. Here, the preset adjustment step size is usually smaller than a delay of the first buffer 4011, so as to further refine the delay of the first buffer 4011. During the initial measurement, if the results show that the output of the first 10 first flip-flops 4013 changes from low level to high level, it can be inferred that the rough width of the pulse signal to be measured is (10ps+10×5 ps)=60ps, Compared with the actual pulse signal width, the difference is large and the accuracy is not enough.

At this time, the delay of the path delay adjustment circuit 402 can be gradually reduced through a preset adjustment step of, for example, 1 ps. When the delay of the path delay adjustment circuit 402 is reduced to 8 ps, the measurement results show the first 10 flip-flops 4013 The output is still high level, then it is estimated that the width of the pulse signal to be measured is 68ps at this time; continue to reduce the delay of the path delay adjustment circuit 402, when the delay of the path delay adjustment circuit 402 is reduced to 7ps, measure The result shows that the output of the 11th flip-flop 4013 changes from low level to high level, that is, the measurement result has changed, indicating that the adjustment is excessive. The last measurement result should prevail, that is, the output of the 11th flip-flop 4013 changes from The delay of the path delay adjustment circuit 402 before the low level changes to the high level is subject to 8ps. Therefore, the measurement results show that the high-precision width of the pulse signal to be measured is (8ps+10×5 ps)=58ps. Compared with the traditional technology that only uses the first buffer 4011 and the first AND gate 4012 for measurement, the accuracy is improved. to 1ps fineness instead of the 5ps fineness of the first buffer 4011.

Therefore, the solution of adding the path delay adjustment circuit 402 according to the embodiment of the present invention improves the measurement accuracy to the precision of the preset adjustment step of the path delay adjustment circuit 402 .

In this way, through the buffer link 401 with this structure, according to the diagram of FIG. 6, it can be intuitively known that the width of the pulse signal has gone through the delay of the path delay adjustment circuit 402 and the delay of several first buffers 4011. Delay to measure the high-precision width of the pulse signal to be measured.

Of course, only this structure of the first buffer 4011 and the first AND gate 4012 directly connected to the clock input port of the flip-flop 4013 may cause the flip-flop 4013 to perform data sampling when the first AND gate 4012 outputs a high level, then There is a possibility that the output high-level pulse width of the first AND gate 4012 is too narrow, resulting in failure to meet the timing requirements of the flip-flop 4013, resulting in sampling failure or metastable state.

Therefore, another embodiment of the present invention introduces a signal latch circuit (refer to FIGS. 5 and 7 ). When the high-level pulse width generated by the first AND gate 4012 used for signal propagation control is narrow, the signal latch circuit also It can stably change the output from low level to high level, providing a stable rising edge sampling signal for the flip-flop 4013 clock port.

Figure 7 shows a schematic circuit diagram of a signal latch circuit 700 according to an embodiment of the invention.

For the m-th first AND gate 4012 (m is a positive integer, and can be any integer from 1 to N), a signal latch circuit 700 composed of an OR gate 701 and a second AND gate 702 is added (as shown in the figure 7), the OR gate 701 and the second AND gate 702 each have two inputs and one output port. One input of the OR gate 701 is the output of the mth first AND gate 4012 for signal propagation control, and the other input of the OR gate 701 is the output of the second AND gate 702 in the signal latch circuit 700. The output port is connected to an input port of the second AND gate 702 in the signal latch circuit 700, and at the same time, as the output of the signal latch circuit 700, is connected to the clock signal input port of the m-th first flip-flop 4013. Another input signal of the second AND gate 702 in the signal latch circuit 700 is the reset signal of the signal latch circuit 700, which is controlled by the control device 403 and is at a low level during reset.

Combined with Figure 5, the working mode of the signal latch circuit 700 is as follows: 1) Before the measurement starts, the control device 403 sets the reset signal of the signal latch circuit 700 to a low level. At the same time, since it is not in the measurement state, the pulse signal width measurement device 500 The input of is always at a low level, so that the output of the first AND gate 4012 used for signal propagation control is at a low level. Therefore, the output of the signal latch circuit 700 also remains at a low level; 2) The signal latch circuit 700 re- After setting, the control device 403 sets the reset signal of the signal latch circuit 700 to a high level. At this time, the signal latch circuit 700 can be used to capture the high level output of the first AND gate 4012 for signal propagation control; 3 ) Once the output of the first AND gate 4012 used for signal propagation control changes from low level to high level, then the output of the OR gate 701 is a high level, so the output of the second AND gate 702 is a high level, or gate The output of 701 is still high even after the output of the first AND gate 4012 becomes low because one input of the OR gate 701 (ie, the output of the second AND gate 702) is high. That is to say, the output of the OR gate 701 is converted from the original low level to a high level, and the signal latch circuit 700 will latch this high level value, and generate a rising edge signal at the clock port of the flip-flop 4013, Perform trigger 4013 data sampling. Of course, the flip-flop 4013 will also be reset before measurement, so that the output is low; during the measurement process, the data port D of the flip-flop 4013 remains high. Once the clock port connected to the OR gate 701 has ( The rising edge signal output by the OR gate 701 is sampled, and the output of the output terminal Q of the flip-flop 4013 changes from a low level to a high level.

Through the signal latch circuit 700, even when the high-level pulse width generated by the first AND gate 4012 used for signal propagation control is narrow, the signal latch circuit 700 can latch the high-level level, which is the flip-flop 4013. The clock port provides a stable rising edge sampling signal to meet the trigger 4013 timing requirements and eliminate the phenomenon of sampling failure or metastability.

Next, a specific circuit embodiment of the path delay adjustment circuit 402 is introduced.

FIG. 8A shows a circuit diagram of one embodiment of a path delay adjustment circuit 402 according to an embodiment of the present invention.

In this embodiment, the path delay adjustment circuit 402 includes M first multiplexers (multiplexers, MUX) 801, M is a positive integer, and the input terminal of each first multiplexer 801 is different from the buffering time by at least The two second buffers 802 are connected, and during each adjustment, the control device 403 inputs respective path delay adjustment signals to the strobe signal terminal of each first multiplexer 801 to gate at least two second buffers 802 . One of the buffers 802 is used to control the delay generated by the path delay adjustment circuit 402 to be reduced by at least one preset adjustment step from the preset delay. The control device 403 can input respective path delay adjustment signals to each first multiplexer 801 to adjust the delay caused by the second buffer 802 that each first multiplexer 801 passes through.

For example, there are a total of five first multiplexers 801, and the input end of each first multiplexer 801 is connected to two second buffers 802 with different buffering times (for example, buffering 1ps, 2ps, etc.), also That is, each first multiplexer 801 can result in a delay of 1 ps or 2 ps, depending on which second buffer 802 is demultiplexed. If the initial delay is 10ps, then the five first multiplexers 801 are all selected to the second buffer 802 with a delay of 2ps. Assume that the preset adjustment step is 1 ps. If you want to control the delay generated by the path delay adjustment circuit 402 to be reduced from the preset delay by a preset adjustment step, that is, 1 ps, you can control a first multiplexer 801 to By selecting the second buffer 802 with a delay of 1 ps instead of the second buffer 802 with a delay of 2 ps, the total delay of the entire five first multiplexers 801 can be reduced to 9 ps. By analogy, if there are other numbers of first multiplexers 801 and other cache times and other preset adjustment steps, the adjustment can be performed as above.

FIG. 8B shows a circuit diagram of another embodiment of the path delay adjustment circuit 402 according to an embodiment of the present invention.

In this embodiment, the path delay adjustment circuit 402 includes a first multiplexer 801', the first multiplexer 801' has a plurality of input terminals, each input terminal is different from the total buffering time by at least 2 A second buffer group 802' is connected. The difference in buffering time here can be achieved by using different numbers of second buffers in the second buffer group 802'. And during each adjustment, the control device 403 inputs a path delay adjustment signal to the strobe signal terminal of the first multiplexer 801' to select one of the at least two second buffer groups 802'. , to control the delay generated by the path delay adjustment circuit 402 to be reduced by at least one preset adjustment step from the preset delay. The control device 403 can be used to input respective path delay adjustment signals to the first multiplexer 801' to respectively adjust the delay caused by the second buffer passed by the first multiplexer 801'.

For example, the delay of each buffer is 1ps, there are 5 second buffer groups 802' in total, the first second buffer group 802' includes 5 buffers, and the second second buffer group 802' includes 4 buffer, and so on. Assume that the preset adjustment step is 1ps. If you want to control the delay generated by the path delay adjustment circuit 402 to be reduced from the preset delay of 5ps by a preset adjustment step, that is, 1ps, you can control the first multiplexer 801' The second second buffer group 802' is selected to achieve a latency of 4ps. Other delays can be deduced in the same way.

Of course, FIG. 8A and FIG. 8B only show two example embodiments of the path delay adjustment circuit 402, but the present invention is not limited thereto. As long as the circuit structure can satisfy the effect of adjusting the delay, it is included in the present disclosure. .

The above is used to adjust the delay more finely through the path delay adjustment circuit 402, so that it stops before the adjustment reaches the critical point, that is, exceeds the critical point (for example, the delay of the path delay adjustment circuit 402 is 7ps), then the Pth first The output of the latch connected to the first AND gate 4012 of the buffer 4011 flips (from low level to high level), and then adjusts back (for example, the delay of the path delay adjustment circuit 402 is 8ps), so that The latch connected to the first AND gate 4012 of the P-th first buffer 4011 returns to the low level, that is, the delay of the fixed path delay adjustment circuit 402 is 8 ps, which is the optimal delay. In this way, the measuring device 404 measures the high-precision width of the pulse signal through the following steps: adding the total delay of the first (P-1) first buffer 4011 to the path delay before the output of the P-th flip-flop 4013 changes. The delay of the circuit 402 is adjusted to obtain the high-precision width of the pulse signal. In this example, assuming P=11, the calculated high-precision width of the pulse signal is (10×5 ps+8ps)=58ps.

Of course, the above measurement example is based on the known delays of the first buffer 4011 and the second buffer 802. However, it should be noted that due to the influence of wafer manufacturing process deviations, even if the same buffer configuration is selected during design After the buffer link 401 and the chip are manufactured, there may be differences in the buffer delays in the same buffer link 401. In addition, factors such as aging and temperature may also affect the buffer delay. Latency may also change over time, so the actual latency of the buffer may differ from the measured value and therefore cannot be directly accumulated from the known value of the design. At the same time, in order for the first AND gate 4012 used for signal propagation control to output a high-level signal, the high-level coincidence time of the two input signals must be maintained to exceed a minimum threshold time. This leads to the possibility that there may still be problems measured using the above method. Error, this error includes the minimum threshold time mentioned above.

In order to eliminate errors caused by the first AND gate 4012 and wiring used for signal propagation control, the clock signal with a known width can be measured before the actual measurement, and the difference between the measurement result and the known width of the clock signal can be obtained. The difference is the above error. The pulse width of the signal to be measured is the difference between the actual measurement result and the error, and the random error can be the adjustment step of the path delay adjustment circuit 402 . This is because the pulse width of the signal to be measured is the rough delay of the N buffers plus the delay adjusted by the path delay adjustment circuit 402. Assuming that the adjustment step of the path delay adjustment circuit 402 is 7ps, then the value to be measured The pulse width of the signal is usually between the rough delay of N buffers plus 7ps*j and the rough delay of N buffers plus 7ps*(j+1) (7ps*j and 7ps*(j+ 1) is the delay of the path delay adjustment circuit 402 obtained by two adjacent adjustments). The pulse width of the signal under test may be very close to (the rough delay of N buffers plus 7ps*j)), or it may be very close to (the rough delay of N buffers plus 7ps*(j+1)) Close, so the error in the worst case is 7 ps (ie, the adjustment step size of the path delay adjustment circuit 402).

The following solution of the present invention can further solve the above problems, achieve the above effects, and further improve the accuracy of measurement.

In one embodiment, in order to eliminate the difference between the designed and actual buffer delays and eliminate the delay effects caused by wiring, the design introduces a second multiplexer.

Referring to FIG. 5 , the pulse signal width measuring device 404 also includes a second multiplexer 501 , a plurality of odd-numbered reverse gates 502 , a counter 503 and a timer 504 . FIG. 5 exemplarily shows that each group of odd-numbered reverse gates 502 only includes one reverse gate (a circle represents the "reverse" operation). However, in order to achieve ring oscillation, each group of odd-numbered anti-gates 502 may actually include other numbers of anti-gates. For example, each group of odd-numbered anti-gates 502 may include three anti-gates, which is not limited here. Of course, the number of reverse gates in each group is preferably the same, so that the circuit delays or errors caused by these groups of reverse gates are basically the same.

The multiple input terminals of the second multiplexer 501 respectively receive the output signals of the output terminals of the N first buffers 4011 through multiple sets of odd-numbered reverse gates 502 and receive pulse signals and clock signals with predetermined pulse widths. The second The output end of the multiplexer 501 is connected to the path delay adjustment circuit 402, the output end of the path delay adjustment circuit 402 is also connected to the counter 503, and the counter 503 is also connected to the timer 504.

The measurement process of the pulse signal width measuring device 500 that adds a second multiplexer 501, multiple groups of odd-numbered reverse gates 502, a counter 503 and a timer 504 is as follows:

In order to measure the above-mentioned errors caused by the actual delay, threshold time and wiring of the buffer, the control device 403 outputs a ring oscillator switching signal to the strobe signal terminal of the second multiplexer 501 to use a known pulse width. clock signal to measure the error:

First, in the high-precision measurement step:

The second multiplexer 501 is controlled to select a clock signal with a predetermined pulse width. The measurement device 404 adjusts the path delay through the path delay adjustment circuit 402 and the control device 403, and controls the path according to the preset adjustment step during each adjustment. The delay generated by the delay adjustment circuit 402 is reduced from the preset delay by at least one preset adjustment step until the output of the Q-th flip-flop 4013 changes, and the delay of the path delay adjustment circuit 402 is fixed at the Q-th trigger. The output of controller 4013 changes to the state before it changes, where Q is a positive integer and less than or equal to N.

At this time, the state just before the output of the Q-th flip-flop 4013 changes, that is, the first first buffer 4011 to the first first AND gate 4012 corresponding to the (Q-1)-th first buffer 4011 The output of the (Q-1) first AND gate 4012 is a high level, and the output of the other first AND gates 4012 is a low level.

This step is to fix the most appropriate delay of the path delay adjustment circuit 402 to obtain a high-precision measurement result of the pulse width. However, the above-mentioned errors due to the actual delay, threshold time, and routing of the buffer still exist in this measurement.

Next, in the calibration step:

The control device 403 controls the second multiplexer 501 to select the output of the Q-1 first buffer 4011, and uses the timer 504 to perform ring oscillation counting using the counter 503 within a predetermined time to measure the band error of the clock signal. width, and the difference between the predetermined pulse width and the width with error is taken as the error.

Here, since the second multiplexer 501 gates the output of the Q-1 first buffer 4011, the output passes through the odd number of reverse gates 502, the path delay adjustment circuit 402, and the first first buffer. 4011 to the Q-1 first buffer 4011, which forms an odd-numbered reverse gate 502, a path delay adjustment circuit 402, and the 1st first buffer 4011 to the Q-1 first buffer. ring oscillator of the 4011.

In one example, the pulse signal width measuring device 404 adjusts the path delay adjustment circuit 402. For example, the result shows that the delay of the path delay adjustment circuit 402 is 8 ps, and the outputs of the AND gates of the first 10 flip-flops 4013 change from low to low. level changes to a high level. If the delay of the path delay adjustment circuit 402 is 7ps and the output of the AND gate of the 11th flip-flop 4013 changes from a low level to a high level, the control device 403 will adjust the second The multiplexer 501 selects the output signal of the 10th flip-flop 4013. In this way, the pulse signal width measuring device 404 is configured as a ring oscillator including an odd number of reverse gates 502, a path delay adjustment circuit 402, and the first to tenth first buffers 4011 to 4011.

Then, using the timer 504 to count ring oscillations using the counter 503 within a predetermined timing to measure the width of the clock signal with an error includes dividing the predetermined timing by the count of ring oscillations by the counter 503 within the predetermined timing to measure the clock signal. The width of the band error.

In one example, when the timer 504 is used to set a predetermined timing, such as 1 μs, and within the predetermined timing, the counter 503 counts oscillations 10,000 times, then the pulse signal width measuring device 500 measures the width with error of the clock signal to be 0.1 ns. In this way, by using the counter 503 and the timer 504 to count and measure the ring oscillator, the accurate time delay with error of the pulse signal width to be measured can be obtained. However, assuming that the predetermined pulse width of the input clock signal is 1/12ns, the difference between the predetermined pulse width 1/12ns and the width with error 1/10ns is regarded as the error, that is, 1/10ns-1/12ns≈0.0167ns .

In this way, the pulse signal width measuring device 500 is configured as a ring oscillator for accurate measurement. Through the embodiment of the present invention, the actual delay, threshold time and wiring of the entire pulse signal width measuring device 500 caused by the buffer are obtained. Error can effectively resist the change in buffer link 401 delay caused by aging and reduce the impact of aging on measurement accuracy.

Next, the practical measurement of any pulse signal with high accuracy and error-free width is introduced.

In high-precision and error-free measurement mode:

The control device 403 controls the second multiplexer 501 to select the pulse signal to be measured, and the measuring device 404 obtains the error-width of the pulse signal to be measured through high-precision mode and calibration steps. From the error-band width of the pulse signal to be measured, The error is subtracted from the width to obtain the high accuracy of the pulse signal and the error-free width.

Specifically, for the pulse signal to be measured, the measurement after high-precision mode and calibration steps includes: First, in the high-precision measurement step:

The second multiplexer 501 is controlled to select the pulse signal to be measured. The measurement device 404 adjusts the path delay through the path delay adjustment circuit 402 and the control device 403, and controls the path delay adjustment according to the preset adjustment step during each adjustment. The delay generated by the circuit 402 is reduced by at least one preset adjustment step from the preset delay until the output of the Q-th flip-flop 4013 changes, fixing the delay of the path delay adjustment circuit 402 at just the Q-th flip-flop 4013 The state before the output changes, where Q is a positive integer less than or equal to N.

Next, in the calibration step:

The control device 403 controls the second multiplexer 501 to select the output of the Q-1 first buffer 4011, and uses the timer 504 to perform ring oscillation counting using the counter 503 within a predetermined time to measure the pulse signal to be measured. Width with error.

Next, subtract the error from the error-bearing width of the pulse signal to be measured to obtain the high-precision and error-free width of the pulse signal including:

In the error removal step:

The control device 403 subtracts the error previously calculated using a clock signal of a predetermined width from the error-bearing width of the pulse signal to be measured to obtain a high-precision and error-free width of the pulse signal.

It should be noted that in order to reduce the interference of wiring on delay measurement, it may be required that the wiring distance from each first buffer 4011 to the second multiplexer 501 is equal during wiring.

In summary, the measurement process of the time-to-digit conversion circuit proposed by various embodiments of the present invention is as follows:

1) Calibrate first, input the clock signal with known pulse width to the pulse signal width measurement device, adjust the path delay adjustment circuit until the output of the flip-flop changes, obtain the high-precision value of the clock pulse signal, and then control The device converts the pulse signal width measurement device into a ring oscillator by controlling the multiplexer, uses counters and timers to accurately measure the width of the clock pulse signal to be measured, and compares it with the known pulse width value of the clock signal to obtain the current pulse width measurement device. Structural measurement errors.

2) Use the pulse conversion device to convert the signal of the critical path to be measured or the two time intervals to be measured into the pulse signal to be measured, and input it to the pulse signal width measuring device for measurement. The actual high value is obtained by removing the error from the measurement result. Accurate and error-free measurement results.

When various embodiments of the present invention are used for critical path delay measurement, since there is more than one critical path in the integrated circuit, a time-to-digital conversion circuit designed by the present invention can be placed in each area where the critical path exists, such as As shown in Figure 9. Figure 9 shows a schematic diagram in which a time-to-digital conversion circuit designed according to the present invention is placed in each area where a critical path exists. If there are multiple critical paths in a certain area at the same time, these critical paths can share a time-digit conversion circuit, and the outputs of different critical paths only need to be input to the time-digit conversion circuit through a multiplexer.

Each embodiment of the present invention adopts a path delay adjustment circuit, which greatly improves the measurement accuracy; the measurement structure is converted into a ring oscillator measurement, which enables more accurate measurement and reduces the impact of factors such as process deviation, aging, wiring, etc. on the accuracy of the measurement structure. Error effects; a signal latch circuit is used to generate the clock signal of the flip-flop to avoid metastable phenomena in the flip-flop; the measurement accuracy is high, and the random measurement error is less than 1 ps under the 12nm process; compared with the use of digital analog conversion circuits and resistors Capacitors, etc., this structure uses pure digital structures (such as multiplexers, logic circuits and latch structures, etc.), which can be realized using components in the standard device library, can be directly synthesized, and is very friendly to the integrated circuit design process. ; This structure is resistant to aging interference. Even if the delay of the circuit increases due to aging, the measurement accuracy is less affected; this structure only requires a very small area overhead and has little impact on the original integrated circuit design.

FIG. 10 shows a flow chart of a pulse signal width measurement method 1000 of a pulse signal width measurement device according to an embodiment of the present invention.

In the pulse signal width measurement method 1000 of the pulse signal width measurement device, the pulse signal width measurement device includes: a buffer link including N first buffers, one input end is connected to the pulse signal, and the other input end is connected to the corresponding first buffer. N first AND gates at the output of a buffer, and corresponding N flip-flops coupled to the output terminals of each first AND gate, and the respective output terminals of the N first buffers are coupled to the next first buffer The input end of the path delay adjustment circuit is connected to the input end of the device, where N is a positive integer greater than 1; the path delay adjustment circuit, where the input end of the path delay adjustment circuit receives the pulse signal, and the output end of the path delay adjustment circuit is connected to the buffer link the input of the first buffer.

The pulse signal width measurement method includes: step 1001, during each adjustment, the delay generated by the path delay adjustment circuit is controlled according to the preset adjustment step size and is reduced from the preset time delay by at least one preset adjustment step size until the P-th flip-flop The output changes, where P is a positive integer and less than or equal to N; step 1002, at least according to the results output by the output terminals of each flip-flop and the delay of each first buffer, just before the output of the P-th flip-flop changes The path delay adjusts the delay of the circuit to measure the width of the pulse signal.

In this way, the solution of adding a path delay adjustment circuit and performing specific adjustments improves the measurement accuracy to the preset adjustment step of the path delay adjustment circuit.

In one embodiment, the path delay adjustment circuit includes M first multiplexers, M is a positive integer, and the input end of each first multiplexer is connected to at least 2 second buffers with different buffering times. , and the step 1001 of reducing the delay generated by the path delay adjustment circuit from the preset delay by at least one preset adjustment step according to the preset adjustment step size during each adjustment includes: during each adjustment, A strobe signal terminal of a multiplexer inputs respective path delay adjustment signals to strobe at least one of the two second buffers to control the delay generated by the path delay adjustment circuit to reduce by at least one preset delay from the preset delay Adjust the step size.

In one embodiment, the path delay adjustment circuit includes a first multiplexer, and the input end of the first multiplexer is connected to at least two second buffer groups with different total buffering times. The step 1001 of reducing the delay generated by the path delay adjustment circuit by controlling the path delay adjustment circuit according to the preset adjustment step size from the preset delay time by at least one preset adjustment step size at each adjustment time includes: at each adjustment time, The path delay adjustment signal is input to the strobe signal terminal of the device to gate one of the at least two second buffer groups to control the delay generated by the path delay adjustment circuit to be reduced by at least one preset delay from the preset delay. Set the adjustment step size.

In this way, through different embodiments of the path delay adjustment circuit, different The delay adjustment method is used to reduce the delay generated by the control path delay adjustment circuit from the preset delay by at least one preset adjustment step.

In one embodiment, the pulse signal width measuring device further includes a second multiplexer, multiple groups of odd-numbered anti-gates, counters and timers, wherein multiple input terminals of the second multiplexer pass through multiple groups respectively. An odd number of reverse gates receive output signals from the output terminals of the N buffers and receive pulse signals and clock signals with a predetermined pulse width. The output terminal of the second multiplexer is connected to the path delay adjustment circuit, and the output of the path delay adjustment circuit The terminal is also connected to the counter, and the counter is also connected to the timer.

In one embodiment, the method further includes: outputting a ring oscillator switching signal to the strobe signal terminal of the second multiplexer to:

In the high-precision measurement step: control the second multiplexer to gate a clock signal with a predetermined pulse width, and control the delay generated by the path delay adjustment circuit according to the preset adjustment step to reduce from the preset delay at each adjustment At least one preset adjustment step until the output of the Q-th flip-flop changes, fixing the delay of the path delay adjustment circuit at the state just before the output of the Q-th flip-flop changes, where Q is a positive integer and less than or equal to N,

During the calibration step:

Control the second multiplexer to select the output of the Q-1 first buffer, use a timer to perform ring oscillation counting within a predetermined time, and use a counter to measure the width of the clock signal with error, and convert the predetermined pulse The difference between the width and the width with error is taken as the error;

Among them, the width of the pulse signal is measured at least based on the output result of the output terminal of each flip-flop, the delay of each first buffer, and the delay of the path delay adjustment circuit just before the output of the P-th flip-flop changes. Step 1002 includes:

In high-precision and error-free measurement mode:

Control the second multiplexer strobe pulse signal, and obtain the width with error of the pulse signal to be measured through high-precision mode and calibration steps. Subtract the error from the width with error of the pulse signal to be measured to obtain the pulse signal. High precision and error-free width.

In one embodiment, the second multiplexer strobe pulse signal is controlled, and the measuring device undergoes measurement in a high-precision mode and a calibration step to obtain the width of the pulse signal to be measured with error, from the width of the pulse signal to be measured with error. The steps to subtract the error from the width to obtain the high accuracy of the pulse signal and the error-free width include:

In the high-precision measurement step: the second multiplexer is controlled to select the pulse signal to be measured, and the measurement device adjusts the path delay through the path delay adjustment circuit and the control device, and controls the path according to the preset adjustment step during each adjustment. The delay generated by the delay adjustment circuit is reduced from the preset delay by at least one preset adjustment step until the output of the Q-th flip-flop changes, and the delay of the path delay adjustment circuit is fixed at the output of the Q-th flip-flop. Change the previous state, where Q is a positive integer and less than or equal to N;

In the calibration step: the control device controls the second multiplexer to select the output of the Q-1 first buffer, and uses a timer to perform ring oscillation counting within a predetermined time using a counter to measure the pulse signal to be measured. Width with error;

In the error removal step:

The control device subtracts the error previously calculated by the clock signal of a predetermined width from the error-bearing width of the pulse signal to be measured to obtain a high-precision and error-free width of the pulse signal.

In this way, the pulse signal width measurement device is configured as a ring oscillator for accurate measurement. Through the embodiment of the present invention, the error caused by the actual delay, threshold time and wiring of the buffer of the entire pulse signal width measurement device is obtained. It can effectively resist changes in buffer link delay caused by aging and reduce the impact of aging on measurement accuracy.

In one embodiment, the step of using a timer to count ring oscillations with a counter within a predetermined timing to measure the width of the clock signal with an error includes: dividing the predetermined timing by the count of ring oscillations by the counter within the predetermined timing. Measure the width of the clock signal with error.

In one embodiment, the pulse is measured based on at least the result of the output of each flip-flop and the delay of each first buffer and the delay of the path delay adjustment circuit just before the output of the P-th flip-flop changes. The signal width step 1002 includes: adding the total delay of the first (P-1) first buffer to the delay of the path delay adjustment circuit before the output of the P-th flip-flop changes to obtain the high value of the pulse signal. Precision width.

In one embodiment, the pulse signal width measuring device further includes: N signal latch circuits, wherein each buffer is connected to the clock input end of the corresponding flip-flop through its respective signal latch circuit, wherein the input of each flip-flop terminal receives a high level, wherein each signal latch circuit includes: a first AND gate, whose first input terminal is connected to the output terminal of the corresponding buffer, and whose second input terminal receives the pulse signal; or gate, whose The first input terminal is connected to the output terminal of the first AND gate, and its output terminal is connected to the clock input terminal of the corresponding flip-flop; the output terminal of the second AND gate is connected to the second input terminal of the OR gate, and its output terminal is connected to the second input terminal of the OR gate. The first input terminal is connected to the output terminal of the OR gate, and the second input terminal receives the reset signal of the signal latch circuit, which is at a low level during reset.

In one embodiment, the pulse signal is a mutually exclusive OR gate obtained by using the signal at the starting point of the critical path of the integrated circuit through the critical path and the signal at the starting point as two inputs of the mutually exclusive OR gate. output.

In summary, the measurement process of the time-to-digit conversion circuit proposed by various embodiments of the present invention is as follows:

1) Calibrate first, input the clock signal with known pulse width to the pulse signal width measurement device, adjust the path delay adjustment circuit until the output of the flip-flop changes, obtain the high-precision value of the clock pulse signal, and then control The device converts the pulse signal width measurement device into a ring oscillator by controlling the multiplexer, uses counters and timers to accurately measure the width of the clock pulse signal to be measured, and compares it with the known pulse width value of the clock signal to obtain the current pulse width measurement device. Structural measurement errors.

2) Use the pulse conversion device to convert the signal of the critical path to be measured or the two time intervals to be measured into the pulse signal to be measured, and input it to the pulse signal width measuring device for measurement. The actual high value is obtained by removing the error from the measurement result. Accurate and error-free measurement results.

Each embodiment of the present invention adopts a path delay adjustment circuit, which greatly improves the measurement accuracy; the measurement structure is converted into a ring oscillator measurement, which enables more accurate measurement and reduces the impact of factors such as process deviation, aging, wiring, etc. on the accuracy of the measurement structure. Error effects; a signal latch circuit is used to generate the clock signal of the flip-flop to avoid metastable phenomena in the flip-flop; the measurement accuracy is high, and the random measurement error is less than 1 ps under the 12nm process; compared with the use of digital analog conversion circuits and resistors Capacitors, etc., this structure uses pure digital structures (such as multiplexers, logic circuits and latch structures, etc.), which can be realized using components in the standard device library, can be directly synthesized, and is very friendly to the integrated circuit design process. ; This structure is resistant to aging interference. Even if the delay of the circuit increases due to aging, the measurement accuracy is less affected; this structure only requires a very small area overhead and has little impact on the original integrated circuit design.

Figure 11 illustrates a block diagram of an exemplary computer system suitable for implementing embodiments of the invention.

The computer system may include a processor (H1); a memory (H2) coupled to the processor (H1) and storing therein computer-executable instructions for performing various methods of embodiments of the invention when executed by the processor steps.

The processor (H1) may include but is not limited to, for example, one or more processors or microprocessors.

Storage (H2) may include, but is not limited to, for example, random access memory (RAM), read only memory (ROM), flash memory, EPROM memory, EEPROM memory, scratchpad, computer storage media ( For example, hard disk, floppy disk, solid state disk, removable disk, CD-ROM, DVD-ROM, Blu-ray disk, etc.).

In addition, the computer system may also include a data bus (H3), an input/output (I/O) bus (H4), a monitor (H5), and input/output devices (H6) (e.g., keyboard, mouse , speakers, etc.) etc.

The processor (H1) can communicate with external devices (H5, H6, etc.) via the I/O bus (H4) via a wired or wireless network (not shown).

The memory (H2) may also store at least one computer-executable instruction for performing various functions and/or method steps in the embodiments described in the present technology when executed by the processor (H1).

In one embodiment, the at least one computer-executable instruction can also be compiled into or constitute a software product, in which one or more computer-executable instructions are executed by a processor to perform various functions in the embodiments described in the present technology. and/or method steps.

Figure 12 shows a schematic diagram of a non-transitory computer-readable storage medium according to an embodiment of the present disclosure.

As shown in Figure 12, instructions are stored on the computer-readable storage medium 1220, such as computer-readable instructions 1210. When the computer readable instructions 1210 are executed by the processor, the supply voltage detection method described with reference to the above figures may be performed. Computer-readable storage media includes, but is not limited to, volatile storage and/or non-volatile storage, for example. Volatile storage may include, for example, random access memory (RAM) and/or cache memory (cache), etc. Anti-volatile storage may include, for example, read-only memory (ROM), hard disk, flash memory, etc. For example, the computer-readable storage medium 1220 can be connected to a computing device such as a computer, and then, when the computing device runs the computer-readable instructions 1210 stored on the computer-readable storage medium 1220, the above methods can be performed.

Of course, the above-mentioned specific embodiments are only examples and not limitations, and those skilled in the art can combine and combine some steps and devices from the above-mentioned separately described embodiments according to the concept of the present invention to achieve the effects of the present invention. Embodiments that are combined and combined are also included in the present invention, and such combinations and combinations are not described one by one here.

Note that the advantages, advantages, effects, etc. mentioned in this disclosure are only examples rather than limitations, and it cannot be considered that these advantages, advantages, effects, etc. are necessary for each embodiment of the present invention. In addition, the specific details disclosed above are only for the purpose of illustration and to facilitate understanding, and are not limiting. The above details do not limit the present invention to the fact that the invention must be implemented using the above specific details.

The block diagrams of the components, devices, equipment, and systems involved in the present disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these elements, devices, equipment, systems may be connected, arranged, and configured in any manner. Words such as "includes," "includes," "having," etc. are open-ended terms that mean "including, but not limited to," and may be used interchangeably therewith. As used herein, the words "or" and "and" refer to the words "and/or" and are used interchangeably therewith, unless the context clearly dictates otherwise. As used herein, the word "such as" refers to the phrase "such as, but not limited to," and may be used interchangeably therewith.

The step flow diagrams and method descriptions above in this disclosure are intended to be illustrative examples only and are not intended to require or imply that the steps of various embodiments must be performed in the order presented. As those skilled in the art will recognize, the sequence of steps in the above embodiments may be performed in any order. Words such as "thereafter," "then," "next," and the like are not intended to limit the order of the steps; these words are merely used to guide the reader through the description of these methods. Furthermore, any reference to an element in the singular, such as using the articles "a," "an," or "the," is not to be construed as limiting the element to the singular.

In addition, the steps and devices in each embodiment in this article are not limited to implementation in a certain embodiment. In fact, some of the relevant steps and some of the devices in each embodiment in this article can be combined according to the concept of the present invention. New embodiments are contemplated and are included within the scope of the present invention.

Each operation of the method described above can be performed by any appropriate means capable of performing the corresponding function. This means may include various hardware and/or software components and/or modules, including but not limited to hardware circuits, application specific integrated circuits (ASICs) or processors.

A general purpose processor, digital signal processor (DSP), ASIC, field programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or electronic device designed to perform the functions described herein may be utilized. Each illustrated logic block, module, and circuit is implemented or described as crystal logic, discrete hardware components, or any combination thereof. A general purpose processor may be a microprocessor, but alternatively the processor may be any commercially available processor, controller, microcontroller or state machine. A processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, a microprocessor cooperating with a DSP core, or any other such configuration.

The steps of the method or algorithm described in conjunction with the present disclosure may be embedded directly in hardware, in a software module executed by a processor, or in a combination of the two. Software modules may exist in any form of tangible storage medium. Some examples of storage media that can be used include random access memory (RAM), read only memory (ROM), flash memory, EPROM memory, EEPROM memory, scratchpad, hard disk, removable disk, CD-ROM etc. The storage medium can be coupled to the processor so that the processor can read information from and write information to the storage medium. In the alternative, the storage medium may be integral with the processor. A software module can be a single instruction or many instructions, and can be distributed over several different code segments, between different programs, and across multiple storage media.

The methods disclosed herein include acts for implementing the described methods. Methods and/or acts may be interchanged with each other without departing from the scope of the claimed claims. In other words, unless a specific order of actions is specified, the order and/or use of specific actions may be modified without departing from the scope of the claimed claims.

The above functions can be implemented by hardware, software, firmware or any combination thereof. If implemented in software, functions can be stored as instructions on a tangible computer-readable medium. Storage media can be any available physical media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage elements or may be used to carry or store instructions or data structures in the form of desired Any other tangible medium that contains program code and can be accessed by a computer. As used herein, disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where discs typically reproduce data magnetically, while discs typically reproduce data magnetically. Use lasers to optically reproduce data.

Therefore, the computer program product can perform the operations given here. For example, such a computer program product may be a computer-readable tangible medium having instructions tangibly stored (and/or encoded) thereon, the instructions executable by a processor to perform the operations described herein. Computer program products may include packaging materials.

Software or instructions may also be transmitted over a transmission medium. For example, the Software may be transmitted from a website, server, or other remote source using a transmission medium such as coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology such as infrared, radio, or microwave.

In addition, modules and/or other appropriate means for performing the methods and techniques described herein may be downloaded and/or otherwise obtained by user terminals and/or base stations as appropriate. For example, such a device may be coupled to a server to facilitate the transfer of means for performing the methods described herein. Alternatively, the various methods described herein may be provided via storage means (e.g., RAM, ROM, physical storage media such as CD or floppy disk, etc.) so that the user terminal and/or the base station can be coupled to or to the device. Provides various methods for obtaining parts when storing them. Additionally, any other suitable technology for providing the methods and techniques described herein to a device may be utilized.

Other examples and implementations are within the scope and spirit of the disclosure and appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination of these. Features that implement the functionality may also be physically located in various locations, including being distributed so that portions of the functionality are implemented at different physical locations. Furthermore, as used herein, including as used within the scope of the claim, the use of "or" in a list of items beginning with "at least one" indicates a discrete list, such that, for example, "at least one of A, B, or C "An enumeration means A or B or C, or AB or AC or BC, or ABC (that is, A and B and C). Furthermore, the word "exemplary" does not mean that the described example is preferred or better than other examples.

Various changes, substitutions and alterations to the technology described herein may be made without departing from the teachings defined by the appended claims. Furthermore, the scope of the claims of the present disclosure is not limited to the specific aspects of the process, machine, manufacture, composition of events, means, methods and acts described above. A currently existing or later developed process, machine, manufacture, composition of events, means, method or act may be utilized that performs substantially the same function or achieves substantially the same results as described herein. Accordingly, the scope of the appended claims includes within its scope such processes, machines, manufactures, compositions of events, means, methods or acts.

The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the invention. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the invention. Thus, the present invention is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

The foregoing description has been presented for the purposes of illustration and description. Furthermore, this description is not intended to limit embodiments of the invention to the form disclosed herein. Although various example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

100: Time-digital conversion circuit 101: Pulse signal conversion device 102, 500: Pulse signal width measurement device 401: buffer link 402: Path delay adjustment circuit 103, 403: Control device 404: Measuring device 4011, 802: buffer 4012, 702: and gate 4013:Trigger 700: Signal latch circuit 701:OR gate 801, 801’: multiplexer 802’: Buffer group 1000: Pulse signal width measurement method 1001, 1002: steps 1210:Command 1220: Computer readable storage media H1: Processor H2: Storage H3: Data bus H4:Bus H5, H6: External equipment

In order to more clearly explain the embodiments of the present disclosure or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are only for the purpose of explaining the embodiments or the technical solutions in the prior art. For some disclosed embodiments, those of ordinary skill in the art can also obtain other drawings based on these drawings without exerting creative efforts. Figure 1 shows an overall block diagram of a time-to-digital conversion circuit according to an embodiment of the present invention. Figure 2A shows a circuit and waveform schematic for converting critical path delays into pulse signals. Figure 2B shows a schematic waveform diagram of the critical path delay converted into a pulse signal. FIG. 3A shows a circuit and waveform schematic diagram for converting the delay difference of two rising signals into pulse signals. Figure 3B shows a schematic waveform diagram of two rising signal delay differences converted into pulse signals. FIG. 4 shows a block diagram of an embodiment of a pulse signal width measuring device according to an embodiment of the present invention. FIG. 5 shows a block diagram of another embodiment of a pulse signal width measuring device according to an embodiment of the present invention. 6 shows an output waveform diagram of each first buffer and the first AND gate in the buffer chain when the pulse signal waveform of the example is input and the path delay adjustment circuit is not considered according to an embodiment of the present invention. . Figure 7 shows a schematic circuit diagram of a signal latch circuit according to an embodiment of the present invention. FIG. 8A shows a circuit diagram of an embodiment of a path delay adjustment circuit according to an embodiment of the present invention. FIG. 8B shows a circuit diagram of another embodiment of a path delay adjustment circuit according to an embodiment of the present invention. FIG. 9 shows a schematic diagram of placing a time-to-digital conversion circuit designed according to the present invention in each area where a critical path exists, according to an embodiment of the present invention. FIG. 10 shows a flow chart of a pulse signal width measurement method of a pulse signal width measurement device according to an embodiment of the present invention. Figure 11 illustrates a block diagram of an exemplary computer system suitable for implementing embodiments of the invention. Figure 12 shows a schematic diagram of a non-transitory computer-readable storage medium according to an embodiment of the present disclosure.

401: buffer link

402: Path delay adjustment circuit

403:Control device

404: Measuring device

4011:Buffer

4012: and gate

4013:Trigger

Claims (20)

A pulse signal width measuring device, including: a buffer link, including N first buffers, one input terminal connected to the pulse signal and the other input terminal connected to the output of the corresponding first buffer, and N first AND gates, and There are corresponding N flip-flops coupled to the output terminals of each first AND gate, and the respective output terminals of the N first buffers are connected to the input terminals of the next first buffer, where N is greater than 1 a positive integer; a path delay adjustment circuit, wherein an input end of the path delay adjustment circuit receives a pulse signal, and an output end of the path delay adjustment circuit is connected to the input of the first buffer in the buffer chain end; a control device that controls the delay generated by the path delay adjustment circuit according to the preset adjustment step during each adjustment to reduce the delay generated by the preset delay by at least one preset adjustment step until the output of the P-th flip-flop changes , where P is a positive integer and less than or equal to N; the measuring device is connected to the output end of each flip-flop and the control device, and is at least based on the result output by the output end of each flip-flop and the delay of each first buffer, The width of the pulse signal is measured by adjusting the delay of the path delay circuit just before the output of the P-th flip-flop changes. The device according to claim 1, wherein the path delay adjustment circuit includes M first multiplexers, M is a positive integer, and the input end of each first multiplexer is different from the buffering time by at least 2 are connected to the second buffers, and during each adjustment, the control device inputs respective path delay adjustment signals to the strobe signal terminals of each first multiplexer to strobe the to One of the two second buffers is used to control the delay generated by the path delay adjustment circuit to be reduced from the preset delay by at least one preset adjustment step. The device according to claim 1, wherein the path delay adjustment circuit includes a first multiplexer, and at least two second input terminals of the first multiplexer are different from the total buffering time. The buffer groups are connected, and during each adjustment, the control device inputs a path delay adjustment signal to the strobe signal terminal of the first multiplexer to gate the at least two second buffer groups. A second buffer group is provided to control the delay generated by the path delay adjustment circuit to be reduced from the preset delay by at least one preset adjustment step. The device according to claim 1, further comprising a second multiplexer, a plurality of odd-numbered reverse gates, a counter and a timer, wherein multiple input terminals of the second multiplexer pass through the plurality of groups respectively. An odd number of reverse gates receive output signals from the output terminals of the N buffers and receive the pulse signal and a clock signal with a predetermined pulse width. The output terminal of the second multiplexer is connected to the path delay adjustment circuit. , the output end of the path delay adjustment circuit is also connected to the counter, and the counter is also connected to the timer. The device of claim 4, wherein the control device outputs a ring oscillator switching signal to the strobe signal terminal of the second multiplexer to: in the high-precision measurement step mode: The second multiplexer is controlled to gate the clock signal with a predetermined pulse width, and the measuring device adjusts the delay according to the preset during each adjustment through the path delay adjustment circuit and the control device. The step size controls the delay generated by the path delay adjustment circuit to be reduced by at least one preset adjustment step from the preset delay until the output of the Qth flip-flop changes, and the delay of the path delay adjustment circuit is fixed at the current value. The state before the output of the Q-th flip-flop changes, where Q is a positive integer and less than or equal to N, in the calibration step: control the second multiplexer to gate the Q-1 first buffer The output of the clock signal is measured by using the timer to perform ring oscillation counting with a counter within a predetermined timing, and the difference between the predetermined pulse width and the width with error is calculated. As an error; in the high-precision and error-free measurement mode: control the second multiplexer to gate the pulse signal, and the measurement device undergoes measurement in the high-precision mode and calibration steps to obtain the pulse to be measured The error is subtracted from the error-bearing width of the signal to be measured to obtain the high-precision and error-free width of the pulse signal, wherein the timer is used to use the counter within the predetermined timing. Performing ring oscillation counting to measure the error-bearing width of the clock signal includes dividing a predetermined timing by the count of ring oscillations by a counter within the predetermined timing to measure the error-bearing width of the clock signal. The device according to claim 5, wherein the second multiplexer is controlled to gate the pulse signal, and the measuring device undergoes measurement in the high-precision mode and calibration steps to obtain the band of the pulse signal to be measured. The width of the error, subtracting the error from the width of the pulse signal to be measured with error, to obtain the high accuracy of the pulse signal and the error-free width includes: in the high-precision measurement step: controlling the selection of the second multiplexer Through the pulse signal to be measured, the measuring device adjusts the delay generated by the path delay adjustment circuit and the control device according to the preset adjustment step size during each adjustment. Reduce at least one preset adjustment step from the preset delay until the output of the Q-th flip-flop changes, and fix the delay of the path delay adjustment circuit at the state just before the output of the Q-th flip-flop changes, Where Q is a positive integer and less than or equal to N; in the calibration step: the control device controls the second multiplexer to select the output of the Q-1 first buffer, and uses the timer to A counter is used to perform ring oscillation counting to measure the error-bearing width of the pulse signal to be measured; in the error removal step: the control device subtracts the clock signal that has previously passed the predetermined width from the error-bearing width of the pulse signal to be measured. Calculate the error to obtain the high accuracy of the pulse signal and the error-free width. The device according to claim 1, wherein, The measuring device measures the high-precision width of the pulse signal through the following steps: adding the total delay of the first (P-1) first buffer before the output of the P-th flip-flop changes. The path delay adjusts the delay of the circuit to obtain the high-precision width of the pulse signal. The device as described in claim 1, further comprising: N signal latch circuits, wherein each buffer is connected to the clock input end of the corresponding flip-flop through its respective signal latch circuit, wherein the input end of each flip-flop receives High level, wherein each signal latch circuit includes: a first AND gate, whose first input terminal is connected to the output terminal of the corresponding buffer, and whose second input terminal receives the pulse signal; or gate, whose first The input terminal is connected to the output terminal of the first AND gate, and its output terminal is connected to the clock input terminal of the corresponding flip-flop; the output terminal of the second AND gate is connected to the second input terminal of the OR gate. , its first input terminal is connected to the output terminal of the OR gate, and its second input terminal receives the reset signal of the signal latch circuit, which is at a low level during reset. The device according to claim 1, wherein the pulse signal is a signal obtained by passing a starting point signal of a critical path of the integrated circuit through the critical path and a signal of the starting point as a mutually exclusive OR gate The output of the mutually exclusive OR gate is obtained from the two inputs. A pulse signal width measurement method of a pulse signal width measurement device, wherein the pulse signal width measurement device includes: a buffer link, including N first buffers, one input end is connected to the pulse signal, and the other input end is connected to the corresponding first buffer. N first AND gates at the output of a buffer, and corresponding N flip-flops coupled to the output terminals of each first AND gate, and the respective output terminals of the N first buffers are coupled to the next The input end of a buffer is connected, where N is a positive integer greater than 1; a path delay adjustment circuit, wherein the input end of the path delay adjustment circuit receives a pulse signal, and the output end of the path delay adjustment circuit is connected to the input end of the first buffer in the buffer chain; wherein the pulse signal width measurement method includes: controlling the delay generated by the path delay adjustment circuit according to the preset adjustment step size during each adjustment from the preset Assume that the time delay is reduced by at least one preset adjustment step until the output of the P-th flip-flop changes, where P is a positive integer and less than or equal to N; at least according to the results output by the output terminals of each flip-flop and each first buffer The width of the pulse signal is measured by the delay of the path delay adjustment circuit just before the output of the P-th flip-flop changes. The method of claim 10, wherein the path delay adjustment circuit includes M first multiplexers, M is a positive integer, and the input end of each first multiplexer is different from the buffering time by at least 2 connected to a second buffer, and The step of controlling the delay generated by the path delay adjustment circuit to reduce the delay by at least one preset adjustment step from the preset delay according to the preset adjustment step during each adjustment includes: during each adjustment, The strobe signal terminal of the multiplexer inputs respective path delay adjustment signals to strobe one of the at least two second buffers to control the delay generated by the path delay adjustment circuit to be reduced from the preset delay by at least A preset adjustment step size. The method of claim 10, wherein the path delay adjustment circuit includes a first multiplexer, and at least two second input terminals of the first multiplexer are different from the total buffering time. The buffer group is connected, and the step of controlling the delay generated by the path delay adjustment circuit to reduce the delay by at least one preset adjustment step from the preset delay according to the preset adjustment step during each adjustment includes: When , a path delay adjustment signal is input to the strobe signal terminal of the first multiplexer to gate one of the at least two second buffer groups to control the path delay. The delay generated by the adjustment circuit is reduced by at least one preset adjustment step from the preset time delay. The method according to claim 10, wherein the pulse signal width measuring device further includes a second multiplexer, a plurality of odd-numbered reverse gates, counters and timers, wherein the multiplexers of the second multiplexer The input terminals respectively receive the output signals of the output terminals of the N buffers through the plurality of odd-numbered reverse gates and receive the pulse signal and the clock signal with a predetermined pulse width, The output end of the second multiplexer is connected to the path delay adjustment circuit, the output end of the path delay adjustment circuit is also connected to the counter, and the counter is also connected to the timer. The method according to claim 13, further comprising: outputting a ring oscillator switching signal to the strobe signal terminal of the second multiplexer to: in the high-precision measurement step: control the second multiplexer The clock signal with the predetermined pulse width is gated by the device, and the delay generated by the path delay adjustment circuit is controlled according to the preset adjustment step during each adjustment, and the delay generated by the path delay adjustment circuit is reduced from the preset delay by at least one preset adjustment step until The output of the Q-th flip-flop changes, and the delay of the path delay adjustment circuit is fixed at the state just before the output of the Q-th flip-flop changes, where Q is a positive integer and less than or equal to N, in the calibration step: Control the second multiplexer to select the output of the Q-1th first buffer, and use the timer to perform ring oscillation counting with a counter within a predetermined time to measure the bandwidth of the clock signal. The width of the error, and the difference between the predetermined pulse width and the width with error is used as the error; wherein, at least according to the results output by the output terminals of each flip-flop and the delay of each first buffer, just The step of measuring the width of the pulse signal by changing the delay of the path delay adjustment circuit before the output of the P-th flip-flop changes: in the high-precision and error-free measurement mode: The second multiplexer is controlled to select the pulse signal, and the error-bearing width of the pulse signal to be measured is obtained through the measurement of the high-precision mode and the calibration step, and the error-bearing width of the pulse signal to be measured is reduced from The error is removed to obtain high accuracy and error-free width of the pulse signal, wherein the timer is used to perform ring oscillation counting using a counter within a predetermined timing to measure the width of the clock signal with error. The step includes: dividing the predetermined timing by the count of the ring oscillation by the counter within the predetermined timing to measure the width with error of the clock signal. The method of claim 14, wherein the second multiplexer is controlled to gate the pulse signal, and the measurement device undergoes measurement in the high-precision mode and calibration steps to obtain the band of the pulse signal to be measured. The error width is subtracted from the error-bearing width of the pulse signal to be measured. The step of obtaining the high accuracy of the pulse signal and the error-free width includes: in the high-precision measurement step: controlling the second multiplexing The pulse signal to be measured is gated by the device, and the measurement device adjusts the delay through the path delay adjustment circuit and the control device, and controls the path delay adjustment circuit to generate the output according to the preset adjustment step during each adjustment. The delay is reduced from the preset delay by at least one preset adjustment step until the output of the Q-th flip-flop changes, and the delay of the path delay adjustment circuit is fixed at the time just before the output of the Q-th flip-flop changes. state, where Q is a positive integer and less than or equal to N; in the calibration step: the control device controls the second multiplexer to gate the output of the Q-1 first buffer, and uses the timer to Usage plan within scheduled time The counter performs ring oscillation counting to measure the error-bearing width of the pulse signal to be measured; in the error removal step: the control device subtracts the previously calculated clock signal with a predetermined width from the error-bearing width of the pulse signal to be measured. Error, the high accuracy of the pulse signal and the error-free width are obtained. The method of claim 10, wherein the path delay adjustment just before the output of the P-th flip-flop is changed is at least based on the result output by the output terminal of each flip-flop and the delay of each first buffer. The step of measuring the width of the pulse signal according to the delay of the circuit includes: adding the total delay of the first (P-1) first buffer to the delay before the output of the P-th flip-flop changes. The path delay adjusts the delay of the circuit to obtain the high-precision width of the pulse signal. The method of claim 10, wherein the pulse signal width measuring device further includes: N signal latch circuits, wherein each buffer is connected to the clock input end of the corresponding flip-flop through its respective signal latch circuit. , wherein the input end of each flip-flop receives a high level, wherein each signal latch circuit includes: a first AND gate, the first input end of which is connected to the output end of the corresponding buffer, and the second input end of which receives pulse signal; An OR gate, the first input end of which is connected to the output end of the first AND gate, and the output end of which is connected to the clock input end of the corresponding flip-flop; the second AND gate, the output end of which is connected to the output end of the OR gate The second input terminal is connected, the first input terminal is connected to the output terminal of the OR gate, and the second input terminal receives the reset signal of the signal latch circuit, which is at a low level during reset. The method of claim 10, wherein the pulse signal is a signal obtained by passing a starting point signal of a critical path of the integrated circuit through the critical path and a signal of the starting point as a mutually exclusive OR gate The output of the mutually exclusive OR gate is obtained from the two inputs. A computer system includes: a processor; a storage coupled to the processor and storing computer-executable instructions therein for performing the method described in any one of claims 10-18 when executed by the processor. A computer-readable medium on which a computer program is stored, wherein when the program is executed by a processor, the method described in any one of claims 10-18 is implemented.