TWI820473B - Method and apparatuse and computer program product for handling sudden power off recovery - Google Patents

Abstract

A method for handling sudden power off recovery (SPOR), performed by a processing unit of an electronic device, includes: driving a flash interface to program data sent by a host into pseudo single level cell (pSLC) blocks through multiple channels in a SLC mode after detecting that SPO happens in the electronic device, thereby enabling dynamic random access memory (DRAM) data to be programmed into the pSLC blocks in as short time as possible.

Description

Instantaneous power outage recovery processing methods and devices and computer program products

The present invention relates to a data storage device, and in particular, to a data access control method and computer program product of a flash memory device.

Flash memory devices are generally divided into NOR flash memory devices and NAND flash memory devices. The NOR flash memory device is a random access device. The host device (Host) can provide any address for accessing the NOR flash memory device on the address pin and obtain the data pin of the NOR flash memory device in real time. Get the data stored at this address. In contrast, NAND flash memory devices do not have random access, but sequential access. NAND flash memory devices cannot access any random address like NOR flash memory devices. Instead, the master device needs to write a sequence of Bytes values to the NAND flash memory device to define the request. The type of command (such as read, write, erase, etc.), and the address used for this command. The address can point to a page (the smallest block of data for a write operation in a flash memory device) or a block (the smallest block of data for an erase operation in a flash memory device).

Since a momentary power outage caused by nature or man-made may cause the data stored in the volatile dynamic random access memory to be lost, the embodiment of the present invention proposes a momentary power outage recovery processing method and device as well as a computer program product, using NAND fast Flash memory to solve the problems mentioned above.

In view of this, how to alleviate or eliminate the deficiencies in the above-mentioned related fields remains to be solved. problem.

The present invention proposes an instantaneous power outage recovery processing method. The method is executed by a processing unit of an electronic device and includes the following steps: determining whether power is generated based on the information carried in one or more host write commands sent by the main device to the electronic device. It can only maintain operation in seconds after a momentary power outage; after detecting a momentary power outage of the electronic device, the driver flash memory interface writes the data transmitted by the host device into multiple channels through multiple channels in single-layer unit mode. pseudo-single-layer unit blocks of logical unit numbers, wherein these pseudo-single-layer unit blocks are retained without writing data during normal operation until an instantaneous power outage is detected; and when the When the master device issues a command to instruct the pruning of the pseudo-single-layer cell blocks, or when it detects that the pseudo-single-layer cell blocks have been read by the master device, the flash memory interface is driven to erase all pseudo-single-layer cell blocks. Memory unit of unit block.

The present invention also provides a computer program product, which includes program code that can implement the above method and is used for loading and executing by a processing unit.

The present invention proposes an instant power-off recovery processing device, which at least includes a processing unit for implementing the above method when loading and executing relevant firmware or software instructions.

One of the advantages of the above embodiment is that through the arrangement of pseudo-single-layer unit blocks and the data writing of multi-channel single-layer unit mode, the data of the dynamic random access memory can be written into the pseudo-simulator in the shortest possible time. Single storey unit block.

Other advantages of the present invention will be explained in more detail in conjunction with the following description and drawings.

100:System architecture

110: Main device

130:Controller

131: Processing unit

135: Main device interface

137: Static random access memory

139:Flash memory interface

150:Dynamic Random Access Memory

170:LUN

170#0~170#8:LUN

170#0-0~170#8-0: normal block

170#0-1~170#8-1: Pseudo single-layer unit block

CH#0~CH#2: input and output channels

CE#0~CE#2: Chip enable control signal

310~370: Logical section

LBA#0~LBA#36863: logical block address

S510~S560: Method steps

610: Logic-Entity Table

630: Entity location information

630-0: (entity) block number

630-1: (entity) page number

630-2: (entity) plane number

630-3: Logic unit number and input and output channel number

650:Physical block

655:Entity area

S710~S730: Method steps

FIG. 1 is a schematic system architecture diagram of a flash memory device according to an embodiment of the present invention.

Figure 2 is a schematic diagram of the connection between the flash memory interface and the logical unit number (Logical Unit Number LUN).

Figure 3 is a schematic diagram of a logical section according to an embodiment of the present invention.

Figure 4 is a schematic diagram of physical block partitioning of LUN according to an embodiment of the present invention.

FIG. 5 is a flow chart of a method for instantaneous power outage recovery processing according to an embodiment of the present invention.

Figure 6 is a logical-to-physical L2P table according to an embodiment of the present invention. Table) and the corresponding diagram of the entity position.

FIG. 7 is a flow chart of a method for instantaneous power outage recovery processing according to an embodiment of the present invention.

The following description is a preferred implementation manner for completing the invention, and its purpose is to describe the basic spirit of the invention, but is not intended to limit the invention. For the actual invention, reference must be made to the following claims.

It must be understood that the words "including" and "include" used in this specification are used to indicate the existence of specific technical features, numerical values, method steps, work processes, components and/or components, but do not exclude the possibility of adding further technical features, values, method steps, processes, components, components, or any combination of the above.

Words such as "first", "second", and "third" used in the claims are used to modify the elements in the claims, and are not used to indicate a priority, precedence relationship, or a single element. Prior to another element, or the chronological order in which method steps are performed, it is only used to distinguish elements with the same name.

It must be understood that when an element is described as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, and intervening elements may be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements could be interpreted in a similar fashion, such as "between" versus "directly between," or "adjacent" versus "directly adjacent," etc.

Refer to Figure 1. The system architecture 100 includes a main device 110, a controller 130, a dynamic random access memory 150 (Dynamic Random Access Memory DRAM), and a logical unit number (Logical Unit Number LUN) 170. This system architecture 100 can be implemented in servers, personal computers, laptop computers (Laptop PC), tablet computers, mobile phones, digital cameras, digital video cameras and other electronic products. The controller 130 is an Application-Specific Integrated Circuit ASIC used to control data access of the LUN 170 and may include a processing unit 131, a main device interface 135 and a flash memory interface. 139. The storage space provided by LUN 170 (such as 16, 32, and 64Gigabytes GBs) can be used as storage space for boot disk and cache data. The memory cells in LUN 170 can be triple level cells (Triple Level Cells, TLCs) or quad-level cells (Quad-Level Cells QLCs). When the memory unit is TLC and can record 8 states, a physical word line can include page P#0 (can be called the lowest bit page, Most Significant Bit MSB page), page P#1 (can be called the middle Bit page, CSB, Center Significant Bit page) and page P#2 (can be called the Least Significant Bit LSB page). When the memory unit is QLC and can record 16 states, in addition to the MSB, CSB and LSB pages, it also includes the TSB (can be called the top bit, TSB, Top Significant Bit) page. Static Random Access Memory (Static Random Access Memory SRAM) 137 can be used to cache data required by the processing unit 131 during execution, such as variables, data tables, etc. The processing unit 131 can communicate with the NAND flash memory 170 through the flash memory interface 139, for example, open NAND flash (Open NAND Flash Interface ONFI), double data rate switch (DDR Toggle) or other interfaces can be used.

The controller 130 includes a processing unit 131 that communicates with the host device 110 through a host device interface 135 . The main device interface 135 can be universal flash storage (Universal Flash Storage UFS), fast non-volatile memory (Non-Volatile Memory Express NVMe), universal serial bus (Universal Serial Bus, USB), advanced technology attachment (advanced technology attachment (ATA), serial advanced technology attachment (SATA), peripheral component interconnect express (PCI-E) or other interfaces. Either the main device 110 or the processing unit 131 may be implemented in a variety of ways, such as using general-purpose hardware (eg, a single processor, a multi-processor with parallel processing capabilities, or other processors with computing capabilities), and When executing firmware or software instructions (Instructions), the functions described later are provided. A multiprocessor is a single computing element that can be equipped with two or more independent processors (also called multi-core) to read and execute Program instructions.

Referring to Figure 2, the flash memory interface 139 may include three I/O channels (hereinafter referred to as channels) CH#0 to CH#2. Each channel is connected to three LUNs. For example, channel CH#0 is connected to LUN 170#. 0 to 170#2, channel CH#1 connects LUN 170#3 to 170#5, and so on. In other words, multiple LUNs can share a channel. For example, the processing unit 131 can drive the flash memory interface 139 to issue the enable signal CE#0 to enable LUNs 170#0, 170#3, and 170#6, and then read user data from the enabled LUNs in a parallel manner, or Write user data to enabled LUN.

The storage space in the data storage device can be logically divided into multiple partitions (Partitions) to store different types of data. Each partition uses a continuous logical address, such as a logical block address (Logical Block Address, LBA) to distinguish. For example, each LBA can be associated with data of 512 bytes, 4KB, 16KB, etc. In the following description, 4KB will be used as an example, but it is not limited to this. Referring to Figure 3, the first section 310 may include 6GB of space, with addresses ranging from LBA#0 to LBA#1,572,863, used to correspond to user data (referred to as data) of the main device 110, such as operating system-related program codes. . The second section 330 may include 2GB of space, with addresses ranging from LBA#1,572,864 to LBA#2,097,151, used to correspond to data of the main device 110, such as application-related program codes. The third section 350 may include 5GB of space, with addresses ranging from LBA#2,097,152 to LBA#3,407,871, used to correspond to data of the main device 110, such as cache data generated by the main device 110 when it is running. The dynamic random access memory 150 stores data required by the main device 110 during operation, such as variables, data tables, thread content (Thread Context), etc. In order to prevent the data stored in the dynamic random access memory 150 from being lost due to a momentary power outage, when the main device 110 detects a momentary power outage, it immediately requests the data storage device to transfer the data stored in the dynamic random access memory 150 through the host device. Device interface 135 writes to LUN 170. In order to achieve this purpose, the data storage device can be set up with a fourth section 370, including 5GB of space, with addresses ranging from LBA#3,407,872 to LBA#4,718,591, for corresponding dynamic random access memory The data stored in body 150. The size of the fourth section 370 may be a fixed value, such as 5GB, or may be equal to the size of the DRAM 150 . Afterwards, when the system recovers, the main device 110 can request the data storage device to provide the data of the fourth section 370 . In this way, the main device 110 can quickly retrieve the data originally stored in the dynamic random access memory 150 .

Referring to Figure 4, the physical blocks (Physical Blocks) of each LUN in the data storage device can be divided into normal blocks (Normal Blocks) and pseudo single-layer unit blocks (pseudo SLC, pSLC Blocks) according to different operating purposes or programming methods. ). Referring to Figure 4, for example, the physical blocks in LUN 170#0 can be configured to include 800 general blocks 170#0-0 and 400 pSLC blocks 170#0-1, and the physical blocks in LUN 170#1 can be configured to include 800 general blocks 170#1-0 and 400 pSLC blocks 170#1-1, and so on. The processing unit 131 preferably records the configuration information of the physical blocks and pseudo-single-layer unit blocks in LUNs 170#0 to 170#8 in the static random access memory 137. The general block is used to provide storage space in the first section 310, the second section 330, and the third section 350 to store data written by the host device during normal operation, such as operating system and application files. Since the memory cells in each LUN are TLC or QLC, the processing unit 131 can drive the flash memory interface 139 to use multi-stage programming methods, such as coarse (Foggy) programming and fine (Fine) programming to write data into the memory cells of general blocks.

On the other hand, the pseudo-single-level unit block such as cache data provides the storage space of the fourth section 370, so the pSLC block is retained without writing data during normal operation. When the processing unit 131 detects that a momentary power outage occurs, it writes the data stored in the dynamic random access memory 150 to the pSLC block according to the request of the main device 110 . After detecting a momentary power outage, the power from the host device 110 can usually only maintain the operation of the data storage device for a few seconds (for example, 1 to 5 seconds). Therefore, the data storage device needs to use this time to convert the dynamic random access memory into The data stored in 150 is written to LUN 170. If there is data occupying the memory unit in the pSLC block during normal operation, the processing unit 131 also needs to spend time moving the data stored in the pSLC block to the general block, and then perform erasure operations, etc. Waiting, not only takes time, but also consumes the remaining power, and the data of the dynamic random access memory 150 cannot be written into the pSLC block within the allowed time. The processing unit 131 adopts a single level cell (Single Level Cells, SLC) mode and an interleave page programming (Interleave Page Programming) method, and writes the data of the dynamic random access memory 150 into the memory in the pSLC block through all channels. unit, that is, writing the data of the dynamic random access memory 150 to the pSLC block of the data storage device in the fastest way, for example, writing the data to the data storage device at a data transfer rate of 300MB/s or higher. in the pSLC block. Although the embodiment describes three channels, each channel is connected to three LUNs as an example, those skilled in the art can modify the NAND flash memory architecture to include more or less channels and LUNs, and the invention should not be limited thereby. .

Referring to the flow chart of the data programming method shown in FIG. 5 , it is executed by the processing unit 131 when loading relevant software or firmware code. In step S510, the processing unit 131 detects whether there is a power outage interruption event. If so, step S520 is executed. If not, step S540 is executed.

In step S520, the processing unit 131 uses multi-channel and interleaved page programming to write data from the master device 110 into the pSLC block, where the pSLC block is a physical block that uses the SLC mode for data programming.

In step S530, the processing unit 131 updates a logical-to-Physical (L2P) mapping table according to the data stored in the pSLC block, where the L2P mapping table is preferably stored in the SRAM 137.

In step S540, the processing unit 131 writes data from the master device 110 into the general block using multi-channel and interleaved page programming.

In step S550, the processing unit 131 updates the logical-to-physical L2P mapping table according to the data stored in the general block.

In step S560, the processing unit 131 writes the updated L2P mapping table into the general block, wherein the processing unit 131 preferably writes the updated L2P mapping table into the general block in SLC mode.

Afterwards, when the power of the main device 110 is restored, the data storage device uploads the data stored in the pSLC block to the dynamic random access memory 150 according to the request of the main device 110. Afterwards, the processing unit 131 can erase the pSLC block. When a power outage interrupt event occurs again, the processing unit 131 can write data into the pSLC block again.

In order to record the correspondence between the logical location (managed by the host device 110) and the physical location (managed by the controller 130), the controller 130 can maintain an L2P mapping table in the SRAM 137, and store the actual data of each logical address in sequence. The information stored in which physical address allows the controller 130 to quickly find the corresponding physical address when processing a read or write command about a specific logical address. In addition, since the size of the SRAM 137 is limited, the L2P mapping table can be divided into a plurality of sub-tables, and the controller 130 uploads the sub-tables to the SRAM 137 in turn. Referring to FIG. 6 , for example, the sub-table 610 preferably stores the physical address information corresponding to each logical address in order. The space required for subtable 610 is preferably proportional to the total number of logical addresses. The logical address can be represented by LBA. Each LBA corresponds to a fixed-size logical block, such as 512B or 4KB, and the data of this LBA is stored in the physical address of LUN 170. The sub-table 610 stores the physical address information from LBA#26624 to LBA#27647 in sequence. The physical address information 630 includes, for example, four bytes, wherein the byte 630-0 records the (physical) block number, the byte 630-1 records the page number and offset (offset); the byte 630 -2 records the plane number, and byte 630-3 records the logical unit number, input and output channel number, etc. For example, physical address information 630 corresponding to LBA #26626 may point to a region 655 in block 650.

In some embodiments of step S510, the processing unit 131 may detect whether each command issued from the main device 110 is an immediate standby command (STANDBY IMMEDIATE command). For the content of the immediate standby command, please refer to ATA Command Set-4 (ATA Command Set). -4, ACS-4) specifications in Section 7.48. Although the immediate standby command originally instructs the main device 110 to enter the standby mode, the main device 110 and the controller 130 can agree that when the main device 110 detects a momentary power outage, an immediate standby command is issued to instruct the data storage device to enter standby mode. The processing unit 131 writes subsequently transmitted data into the LUN 170 at the fastest speed. Although the embodiment takes the immediate standby command as an example, the main device 110 can use other commands to instruct the processing unit 131 to achieve the same technical effect.

In other embodiments of step S510, the processing unit 131 may observe the host write commands (Host Write Commands) in the command queue (Command Queue) to determine whether a momentary power outage occurs in the electronic device. Compared with application scenarios where a mass storage device (Mass Storage) provides more than 100GB of storage space, when the main device 110 uses the LUN 170 as a boot disk and cache data storage space, under normal operation, the main device 110 It is rare to issue long data write commands. Therefore, when the processing unit 131 finds a long data write command followed by a continuous write command in the command queue, it can be determined that the electronic device is likely to experience a momentary power outage. The master device command usually contains the parameters of the starting logical address and length. The long data write command can refer to the length of the master device write command exceeding a preset threshold (such as 1MB), and the continuous write command can refer to the master device. The starting logical address in the write command is the address next to the ending logical address of the previous master write command in the command queue.

In some other embodiments of step S510, the processing unit 131 may observe whether the starting logical address of the master device write command in the command queue falls into a preset range to determine whether a momentary power outage occurs in the electronic device. For example, referring to FIG. 3 , when it is found that the starting logical address of any master device write command is between LBA#3407872 and LBA#4718591, the processing unit 131 determines that an instantaneous power outage is likely to occur in the electronic device.

In step S520, the processing unit 131 may first issue an SLC mode enable command (SLC MODE ENABLE Command) through the flash memory interface 139, and then issue a series of program page commands (PROGRAM PAGE Commands) to write data into the preconfigured pSLC block. Data writing in SLC mode means that the flash memory interface 139 programs each memory cell in the pSLC block to be in one of two states, rather than one of eight or sixteen states. Those skilled in the art will understand that the data writing speed in the SLC mode is better than the data writing speed in the TLC or QLC mode using coarse-fine technology.

In the preferred embodiment of step S520, the processing unit 131 can drive the flash memory interface to write data in a staggered page programming manner. Taking channel CH#0 in Figure 4 as an example, the flash memory interface 139 can send an enable signal CE#0 to enable LUN 170#0 and transmits data to The pSLC block 170#0-1 then sends an instruction to the pSLC block 170#0-1 to start programming the memory cells therein after the data transmission is completed. During the actual programming of the memory unit in pSLC block 170#0-1, the flash memory interface 139 can send out the enable signal CE#1 to enable LUN 170#1 and transmit data to pSLC block 170#1-1 through channel CH#0. And so on.

In the preferred embodiment of step S520, the processing unit 131 can drive the flash memory interface 139 to write the data transmitted by the host device 110 through all channels.

Referring to the method flow chart shown in FIG. 7 , the method is executed by the processing unit 131 when loading relevant software or firmware code. After detecting that the electronic device has completed the instantaneous power-off recovery (step S710), the processing unit 131 drives the flash memory interface 170 to erase the memory units of all pSLC blocks in the LUN 170, leaving the pSLC blocks in a ready state for possible next occurrences. Instantaneous power-off operation (step S730).

The processing unit 131 may check the content of each data set management command (DATA SET MANAGEMENT command) issued from the host device 110 to determine whether to instruct pSLC blocks to be trimmed. The content of the data set management command may refer to ATA Command Set-4 (ATA Command Set-4 ACS-4) Specifications in Section 7.6. The data set management command may include parameters such as LBA and trim bit (Trim Bit). The processing unit 131 may refer to the information in the L2P mapping table to determine whether the LBA in the data set management command is associated with a pSLC block and the trim bit is set to “1” ". If yes, the processing unit 131 determines that the electronic device has completed the instantaneous power-off recovery. Although the embodiment takes the data set management command as an example, the main device 110 can use other commands to instruct the processing unit 131 to achieve the same technical effect.

In other embodiments of step S710, the processing unit 131 may record the execution of host read commands (Host Read Commands) to determine whether the electronic device has completed instantaneous power-off recovery. The processing unit 131 may record the execution of each master read command associated with the pSLC block with reference to the contents of the L2P mapping table. When all the LBA data corresponding to the pSLC block in the L2P mapping table have been read by the host device 110, the processing unit 131 determines that the electronic device has completed instantaneous power-off recovery.

All or part of the steps in the method of the present invention can be implemented by computer programs, such as The computer's operating system, drivers for specific hardware in the computer, or software applications. In addition, it can also be implemented in other types of programs as shown above. Those with ordinary skill in the art can write the methods of the embodiments of the present invention into computer programs, which will not be described again for the sake of simplicity. The computer program implemented according to the method of the embodiment of the present invention can be stored in an appropriate computer-readable data carrier, such as DVD, CD-ROM, USB disk, hard disk, or can be placed in a computer program that can be accessed through a network (such as the Internet). route, or other appropriate vehicle).

Although Figure 1 contains the above-described components, it does not rule out the use of other additional components to achieve better technical effects without violating the spirit of the invention. In addition, although the flowcharts of Figures 5 and 7 are executed in a specified order, those skilled in the art can modify the order of these steps without violating the spirit of the invention and achieving the same effect. Therefore, The present invention is not limited to the use of only the sequence described above. In addition, those skilled in the art can also integrate several steps into one step, or in addition to these steps, perform more steps sequentially or in parallel, and the invention is not limited thereby.

Although the present invention is described using the above embodiments, it should be noted that these descriptions are not intended to limit the present invention. On the contrary, this invention covers modifications and similar arrangements which will be obvious to one skilled in the art. Therefore, the scope of the claims of the application must be interpreted in the broadest manner to include all obvious modifications and similar arrangements.

S510~S560: Method steps

Claims (9)

An instant power outage recovery processing method, executed by a processing unit in an electronic device, includes: judging whether the power can only be maintained based on the information carried in one or more host write commands issued by a host device to the electronic device. Momentary power outage after operation in seconds; when a long data write command is found in a command queue followed by a continuous write command, or a starting logical address of a host write command falls into a default interval, it is determined that the electronic device has experienced a momentary power outage; after detecting that the electronic device has experienced a momentary power outage, it drives a flash memory interface to write the data transmitted by the host device into multiple channels through multiple channels in a single-layer unit mode. pseudo-single-layer unit blocks of logical unit numbers, wherein these pseudo-single-layer unit blocks are retained during normal operation without writing data until an instantaneous power outage is detected; when the main device restores power and then record the execution of a master device read command, wherein the master device issues the master device read command to request data to be read from the pseudo single-layer unit blocks; and when the pseudo single-layer units are detected When all the blocks have been read by the host device, it is determined that the host device has completed the instantaneous power-off recovery operation, and drives the flash memory interface to erase all memory cells of the pseudo-single-layer unit block. The instant power-off recovery processing method as described in claim 1, wherein each physical block in each logical unit number is divided into a general block or the pseudo-single-layer unit block, and the memory in the pseudo-single-layer unit block The cell is a three-level cell or a four-level cell, and data writing in the single-level cell mode programs each memory cell in each of the pseudo-single-level cell blocks to become one of two states. The instant power outage recovery processing method described in claim 2 includes: after detecting that the electronic device has experienced an instant power outage, driving the flash memory interface to restore the main device to the main device. The transmitted data is written into the pseudo-single-layer unit block of the logical unit numbers in a staggered page programming manner. The instantaneous power-off recovery processing method described in claim 1 includes: after detecting that the host device has completed the instantaneous power-off recovery, driving the flash memory interface to erase all the memory cells of the pseudo-single-layer unit blocks. A computer program product, including a program code for instant power outage recovery processing, wherein when a processing unit in an electronic device loads and executes the above program code, the implementation is as described in any one of claims 1 to 4. The instant power outage recovery processing method described above. An instant power-off recovery processing device includes: a main device interface; a flash memory interface; and a processing unit, coupled to the main device interface and the flash memory interface, according to a main device sending a message to the instant power outage through the main device interface. One or more host write commands of the call reply processing device use the information carried in the write command to determine whether power is generated and can only maintain operation in seconds before a momentary power outage; when a long data write command is found in a command queue Then a continuous write command is issued, or a starting logical address of a host write command is found in the command queue to fall into a preset range, it is determined that an instantaneous power outage has occurred in the instantaneous power-off recovery processing; upon detection After a momentary power outage occurs in the instantaneous power-off recovery processing device, the flash memory interface is driven to write the data transmitted by the main device through the main device interface into a single-layer unit mode through multiple channels and into multiple logical unit numbers. Hierarchical unit blocks, in which these pseudo-single-layer unit blocks are retained without writing data during normal operation until a momentary power outage is detected; when the main device restores power, a main device read is recorded Execution of the fetch command, in which the master device issues the master device read command to request data to be read from the pseudo-single-layer unit blocks; and when it is detected that the pseudo-single-layer unit blocks have been read by the master device When reading, it is determined that the host device has completed the instantaneous power-off recovery operation, and drives the flash memory interface to erase all the memory cells of the pseudo-single-layer unit block. The instant power-off recovery processing device as described in claim 6, wherein each physical block in each logical unit number is divided into a general block or the pseudo-single-layer unit block, and the memory in the pseudo-single-layer unit block The cell is a three-level cell or a four-level cell, and data writing in the single-level cell mode programs each memory cell in each of the pseudo-single-level cell blocks to become one of two states. The instant power outage recovery processing device as described in claim 7, wherein the processing unit detects that the electronic device has an instant power outage and drives the flash memory interface to write the data transmitted by the host device into the flash memory interface in a staggered page programming manner. These pseudo-single-layer unit blocks have certain logical unit numbers. The instantaneous power-off recovery processing device as described in claim 6, wherein the processing unit drives the flash memory interface to erase all memory cells of the pseudo-single-layer unit block after detecting that the host device has completed instantaneous power-off recovery.

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