TWI819446B - Single-layer semiconductor grinding tape and manufacturing method thereof - Google Patents
Single-layer semiconductor grinding tape and manufacturing method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims description 46
- 229920006254 polymer film Polymers 0.000 claims abstract description 68
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- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000005498 polishing Methods 0.000 claims description 55
- 239000000203 mixture Substances 0.000 claims description 31
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- FACXGONDLDSNOE-UHFFFAOYSA-N buta-1,3-diene;styrene Chemical compound C=CC=C.C=CC1=CC=CC=C1.C=CC1=CC=CC=C1 FACXGONDLDSNOE-UHFFFAOYSA-N 0.000 claims description 2
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Abstract
Description
本揭露係有關於一種半導體研磨膠帶,特別是一種單層半導體研磨膠帶。本揭露還涉及此半導體研磨膠帶的製造方法。The present disclosure relates to a semiconductor polishing tape, particularly a single-layer semiconductor polishing tape. The present disclosure also relates to a manufacturing method of the semiconductor polishing tape.
一般而言,現有的半導體研磨膠帶為多層結構,其外層為黏著層,內層為塗佈層,大多應用塗佈方式製成。因此,現有的半導體研磨膠帶的製程較為複雜,故成本也較高。Generally speaking, existing semiconductor polishing tapes have a multi-layer structure. The outer layer is an adhesive layer and the inner layer is a coating layer. Most of them are made by coating. Therefore, the manufacturing process of the existing semiconductor polishing tape is relatively complicated, so the cost is also high.
另外,製成研磨膠帶的過程中,也常遇到厚膜平整度較差的疑慮,若使用平整度較差的研磨膠帶附著於晶片進行切割時,易造成較大的晶片厚度誤差,進而影響晶片的效能。In addition, in the process of making abrasive tapes, concerns about poor flatness of thick films are often encountered. If abrasive tapes with poor flatness are used to attach to wafers for cutting, it will easily cause large wafer thickness errors, thereby affecting the quality of the wafers. efficacy.
近年來,晶片的厚度不斷的下降,過往可被接受的誤差範圍,已在本體的厚度下降過程中,逐漸失去了優勢,反而造成了影響效能的關鍵。以成捲式塗佈技術為例,首先將一捲基材(如PP、PET、PI、銅箔等),經過塗佈裝置將塗料披覆於基材之上,再經過乾燥過程將溶劑移除,最後收捲成卷,即為成品或半成品用。由於塗佈的過程中,較難以控制其平整度,進而形成些許的厚度誤差。又,以熱乾燥、紫外光、或者紅外光乾燥的過程中去除溶劑時,亦擴大了原塗佈時形成的誤差。In recent years, the thickness of the wafer has continued to decrease. The acceptable error range in the past has gradually lost its advantage in the process of decreasing the thickness of the body, and has become the key to affecting performance. Taking roll coating technology as an example, firstly, a roll of substrate (such as PP, PET, PI, copper foil, etc.) is coated on the substrate through a coating device, and then the solvent is transferred through the drying process. In addition, it is finally rolled into rolls, which are finished products or semi-finished products. During the coating process, it is difficult to control the flatness, resulting in slight thickness errors. In addition, when the solvent is removed during heat drying, ultraviolet light, or infrared light drying, the error caused during the original coating is also amplified.
根據本揭露之一實施例,提出一種單層半導體研磨膠帶,其包含基材及高分子膜。高分子膜設置於基材上,高分子膜包含高分子聚合物材料。其中,高分子膜在第一溫度區間時呈軟化狀態且具有第一黏著度,而高分子膜在第二溫度區間時呈硬化狀態且具有第二黏著度,第一溫度區間大於第二溫度區間,且第一黏著度大於第二黏著度;其中,該第一溫度區間為50˚C~80˚C,該第二溫度區間為20˚C~25˚C,該第一黏著度為400g/inch -800g/inch,而第二黏著度為20g/inch -150g/inch。According to an embodiment of the present disclosure, a single-layer semiconductor polishing tape is provided, which includes a base material and a polymer film. The polymer film is arranged on the base material, and the polymer film contains high molecular polymer material. Wherein, the polymer film is in a softened state and has a first degree of adhesion in the first temperature range, and the polymer film is in a hardened state and has a second degree of adhesion in the second temperature range, and the first temperature range is greater than the second temperature range. , and the first viscosity is greater than the second viscosity; wherein, the first temperature range is 50˚C~80˚C, the second temperature range is 20˚C~25˚C, and the first viscosity is 400g/ inch -800g/inch, while the second adhesion is 20g/inch -150g/inch.
較佳地,該第二黏著度為20g/inch -90g/inch。Preferably, the second adhesion degree is 20g/inch-90g/inch.
根據本揭露之另一實施例,提出一種單層半導體研磨膠帶的製造方法,其以一製造系統執行,此製造系統包含押出機、衣架型膜頭及整平機,押出機包含入料口、本體、螺桿、加熱器及出料口,入料口及出料口分別設置於本體的二端,螺桿設置於本體內部,而加熱器與本體連接,衣架型膜頭呈漸寬延伸,並與押出機的出料口連接,整平機設置於衣架型膜頭之一側,單層半導體研磨膠帶的製造方法包含下列步驟:將高分子聚合物材料混合產生混合物;將混合物置入押出機的入料口,並透過押出機的加熱器及螺桿對混合物進行加熱及壓縮;透過押出機的出料口將經過加熱及壓縮的混合物輸送至衣架型膜頭;經由衣架型膜頭將混合物擠出形成高分子膜,並進行淋膜使高分子膜附著於基材上;以及透過整平機對附著於基材上的高分子膜進行整平。According to another embodiment of the present disclosure, a method for manufacturing a single-layer semiconductor polishing tape is proposed, which is executed with a manufacturing system. The manufacturing system includes an extruder, a hanger-type film head and a leveling machine. The extruder includes an inlet, The body, the screw, the heater and the discharge port. The feed port and the discharge port are respectively set at both ends of the body. The screw is set inside the body, and the heater is connected to the body. The hanger-type film head extends gradually wider, and Connected to the discharge port of the extruder, the leveling machine is installed on one side of the hanger-type film head. The manufacturing method of the single-layer semiconductor grinding tape includes the following steps: mix the high molecular polymer materials to produce a mixture; put the mixture into the extruder The inlet of the extruder is used to heat and compress the mixture through the heater and screw of the extruder; the heated and compressed mixture is transported to the hanger-type membrane head through the outlet of the extruder; the mixture is extruded through the hanger-type membrane head. Forming a polymer film and laminating it to make the polymer film adhere to the base material; and leveling the polymer film attached to the base material through a leveling machine.
承上所述,依本發明之單層半導體研磨膠帶及其製造方法,其可具有一或多個下述優點:Based on the above, the single-layer semiconductor polishing tape and its manufacturing method according to the present invention may have one or more of the following advantages:
(1)本揭露的一實施例中,單層半導體研磨膠帶為單層結構,故其基材上可僅具有單層的高分子膜,因此單層半導體研磨膠帶的製程能夠大幅簡化,故製造成本可進一步降低。(1) In one embodiment of the present disclosure, the single-layer semiconductor polishing tape has a single-layer structure, so the base material can only have a single-layer polymer film. Therefore, the manufacturing process of the single-layer semiconductor polishing tape can be greatly simplified, so the manufacturing Costs can be further reduced.
(2)本揭露的一實施例中,單層半導體研磨膠帶採用的高分子膜具有特殊的成份比例,使此高分子膜在不同的溫度範圍下具有不同的硬度及黏著度,故可同時提供良好的緩衝功能及黏著功能,且又可以很容易地由晶圓上撕除(2) In one embodiment of the present disclosure, the polymer film used in the single-layer semiconductor polishing tape has a special composition ratio, so that the polymer film has different hardness and adhesion in different temperature ranges, so it can be provided at the same time Good cushioning and adhesion functions, and can be easily removed from the wafer
(3)本揭露的一實施例中,單層半導體研磨膠帶採用的製造方法能有效地使高分子膜的厚度均勻及且具有更佳的表面平整度,故能滿足晶圓研磨製程的需求,應用上更為廣泛。(3) In one embodiment of the present disclosure, the single-layer semiconductor polishing tape adopts a manufacturing method that can effectively make the thickness of the polymer film uniform and have better surface flatness, so it can meet the needs of the wafer polishing process. More widely used.
(4)本揭露的一實施例中,單層半導體研磨膠帶採用的製造方法能有效地使高分子膜的製造公差降低,使生產的單層半導體研磨膠帶的品質更佳,以符合實際應用上的需求。(4) In one embodiment of the present disclosure, the single-layer semiconductor polishing tape adopts a manufacturing method that can effectively reduce the manufacturing tolerance of the polymer film, so that the quality of the single-layer semiconductor polishing tape produced is better, so as to meet the practical application requirements. needs.
以下將參照相關圖式,說明依本揭露之單層半導體研磨膠帶及其製造方法之實施例,為了清楚與方便圖式說明之故,圖式中的各部件在尺寸與比例上可能會被誇大或縮小地呈現。在以下描述及/或申請專利範圍中,當提及元件「連接」或「耦合」至另一元件時,其可直接連接或耦合至該另一元件或可存在介入元件;而當提及元件「直接連接」或「直接耦合」至另一元件時,不存在介入元件,用於描述元件或層之間之關係之其他字詞應以相同方式解釋。為使便於理解,下述實施例中之相同元件係以相同之符號標示來說明。The following will describe embodiments of the single-layer semiconductor polishing tape and its manufacturing method according to the present disclosure with reference to the relevant drawings. For the sake of clarity and convenience of illustration, the size and proportion of each component in the drawings may be exaggerated. or presented in reduced form. In the following description and/or patent claims, when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present; and when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present; When a component is "directly connected" or "directly coupled" to another component, there are no intervening components present, and other words used to describe the relationship between components or layers should be interpreted in a like manner. To facilitate understanding, the same components in the following embodiments are labeled with the same symbols for description.
請參閱第1圖,其係為本揭露之一實施例之單層半導體研磨膠帶之結構圖。如圖所示,單層半導體研磨膠帶1包含基材11及高分子膜12。Please refer to Figure 1, which is a structural diagram of a single-layer semiconductor polishing tape according to an embodiment of the present disclosure. As shown in the figure, the single-layer
在一實施例中,基材11可為聚烯烴(PO)、聚氯乙烯(PVC)或聚對苯二甲酸乙二酯(PET)等材料製成。In one embodiment, the
高分子膜12設置於基材11上,高分子膜12包含高分子聚合物材料及黏著賦予劑。在一實施例中,高分子聚合物材料可包苯乙烯-異戊二烯-苯乙烯熱塑性嵌段共聚物(SIS)、苯乙烯-丁二烯-苯乙烯熱塑性嵌段共聚物(SBS)、聚烯彈性體(POE)、聚氨酯(PU)及乙烯-醋酸乙烯酯共聚物(EVA)之一或其組合。在一實施例中,黏著賦予劑可包含松香、石油樹脂、乙烯-醋酸乙烯酯共聚物及乙烯丙烯酸(EAA)之一或其組合。例如,在本實施例中,該高分子聚合物材料包含乙烯-醋酸乙烯酯共聚物及聚烯彈性體,而黏著賦予劑為石油樹脂;其中,乙烯-醋酸乙烯酯共聚物的含量為50%-87%,聚烯彈性體的含量為10%-47%,石油樹脂的含量為3%-10%。The
較佳地,於本發明之另一實施例中,高分子膜12可只包含高分子聚合物材料及黏著賦予劑,但不包含石油樹脂;其中高分子聚合物材料包含乙烯-醋酸乙烯酯共聚物及聚烯彈性體,乙烯-醋酸乙烯酯共聚物的含量為50%-87%,而該聚烯彈性體的含量為10%-50%。Preferably, in another embodiment of the present invention, the
高分子膜12在第一溫度區間時呈軟化狀態且具有第一黏著度,而在第二溫度區間時呈硬化狀態且具有第二黏著度;第一溫度區間大於第二溫度區間,且第一黏著度大於第二黏著度。例如,第一溫度區間可為50˚C~80˚C,第二溫度區間可為20˚C~25˚C(室溫);第一黏著度可為400g/inch -800g/inch ,而第二黏著度可為10g/inch -150g/inch ;較佳地,第二黏著度為20g/inch -150g/inch 。The
例如,在一實施例中,高分子膜12包含高分子聚合物材料及黏著賦予劑。高分子聚合物材料包含乙烯-醋酸乙烯酯共聚物及聚烯彈性體,而黏著賦予劑為石油樹脂。乙烯-醋酸乙烯酯共聚物的含量為80%,聚烯彈性體的含量為17%,石油樹脂的含量為3%。製成的高分子膜12在60˚C(第一溫度區間)的第一黏著度為510g/inch,而在25˚C(第二溫度區間)的第二黏著度可為45g/inch。For example, in one embodiment, the
例如,在另一實施例中,高分子膜12包含高分子聚合物材料及黏著賦予劑。高分子聚合物材料包含乙烯-醋酸乙烯酯共聚物及聚烯彈性體,而黏著賦予劑為石油樹脂。乙烯-醋酸乙烯酯共聚物的含量為70%,聚烯彈性體的含量為30%,石油樹脂的含量為0%。製成的高分子膜12在60˚C(第一溫度區間)的第一黏著度為600g/inch,而在25˚C(第二溫度區間)的第二黏著度可為10g/inch。For example, in another embodiment, the
例如,在又一實施例中,高分子膜12包含高分子聚合物材料及黏著賦予劑。高分子聚合物材料包含乙烯-醋酸乙烯酯共聚物及聚烯彈性體,而黏著賦予劑為石油樹脂。乙烯-醋酸乙烯酯共聚物的含量為60%,聚烯彈性體的含量為33%,石油樹脂的含量為7%。製成的高分子膜12在60˚C(第一溫度區間)的第一黏著度為450g/inch,而在25˚C(第二溫度區間)的第二黏著度可為100g/inch。For example, in yet another embodiment, the
因此,高分子膜12在第一溫度區間時的軟化狀態的流變性可提供足夠的熱黏著性及且對晶圓上的凹凸點有良好的包覆性,使其可以有效地提供緩衝及黏著功能。另外,此時高分子膜12的硬度可在60-80(SHELLA)間,故為彈性良好的彈性體,極適合用於做為研磨緩衝材料。相反的,高分子膜12在第二溫度區間時,即可回復至低黏力的硬化狀態,在此狀態下,高分子膜12可以很容易由晶圓撕除。Therefore, the rheology of the
當然,本實施例僅用於舉例說明而非限制本揭露的範圍,根據本實施例的單層半導體研磨膠帶1而進行的等效修改或變更仍應包含在本發明的專利範圍內。Of course, this embodiment is only for illustration and does not limit the scope of the present disclosure. Equivalent modifications or changes made according to the single-layer
請參閱第2圖及第3圖,其係為本揭露之一實施例之單層半導體研磨膠帶之製造系統的第一示意圖及第二示意圖。如圖所示,製造系統2包含押出機21、衣架型膜頭22及整平機23。Please refer to Figures 2 and 3, which are first schematic diagrams and second schematic diagrams of a single-layer semiconductor polishing tape manufacturing system according to an embodiment of the present disclosure. As shown in the figure, the
押出機21包含入料口211、本體212、螺桿213、加熱器214及出料口215。入料口211及出料口215分別設置於本體212的二端。螺桿213設置於本體212內部。加熱器214與本體212連接。衣架型膜頭22呈漸寬延伸,其中較窄的一端與押出機21的出料口215連接,而較寬的一端則朝向整平機23。整平機23設置於衣架型膜頭22之一側。The extruder 21 includes an inlet 211, a body 212, a screw 213, a heater 214 and an outlet 215. The material inlet 211 and the material outlet 215 are respectively provided at two ends of the body 212. The screw 213 is arranged inside the body 212. The heater 214 is connected to the body 212 . The hanger-
首先,將高分子聚合物材料及黏著賦予劑透過前述的比例混合產生混合物。如前述,舉例而言,高分子聚合物材料可包含乙烯-醋酸乙烯酯共聚物及聚烯彈性體,其中乙烯-醋酸乙烯酯共聚物的含量為50%-87%,聚烯彈性體的含量為10%-47%,而石油樹脂的含量為3%-10%。First, the high molecular polymer material and the adhesion-imparting agent are mixed in the aforementioned ratio to produce a mixture. As mentioned above, for example, the high molecular polymer material may include ethylene-vinyl acetate copolymer and polyethylene elastomer, wherein the content of ethylene-vinyl acetate copolymer is 50%-87%, and the content of polyethylene elastomer The content of petroleum resin is 10%-47%, while the content of petroleum resin is 3%-10%.
較佳地,於本發明之另一實施例中,也可不加入黏著賦予劑;其中高分子聚合物材料包含乙烯-醋酸乙烯酯共聚物及聚烯彈性體,乙烯-醋酸乙烯酯共聚物的含量為50%-87%,而該聚烯彈性體的含量為10%-50%。Preferably, in another embodiment of the present invention, no adhesion-imparting agent may be added; wherein the polymer material includes ethylene-vinyl acetate copolymer and polyolefin elastomer, and the content of ethylene-vinyl acetate copolymer is It is 50%-87%, and the content of the polyethylene elastomer is 10%-50%.
然後,將混合物置入押出機21的入料口211,押出機21的螺桿213則轉動以對混合物進行壓縮;另外,押出機21的加熱器214則會在壓縮的同時進行加熱。Then, the mixture is put into the inlet 211 of the extruder 21, and the screw 213 of the extruder 21 rotates to compress the mixture; in addition, the heater 214 of the extruder 21 heats while compressing.
接著,在完成壓縮及加熱後,混合物經由押出機21的出料口215輸送至衣架型膜頭22,透過衣架型膜頭22將混合物擠出形成高分子膜12,並進行淋膜使高分子膜12附著於基材11。Then, after completing the compression and heating, the mixture is transported to the hanger-
最後,將附著有高分子膜12的基材11輸送至整平機23,並透過整平機23進行整平。Finally, the
於本發明之另一實施例中,衣架型膜頭22將混合物擠出形成高分子膜12後,藉由厚度偵測裝置偵測高分子膜12之膜厚,即時回饋給單層半導體研磨膠帶之製造系統,藉此以即時調整衣架型膜頭22之間隙,可更近一步達到均勻膜厚並減少公差之功效 ;其中,厚度偵測裝置可為傳統探頭裝置或紅外線偵測裝置,其偵測膜厚方式可為單點或多點偵測,也可以平行衣架型膜頭22出口方向進行反復式掃描,但不以此為限。In another embodiment of the present invention, after the hanger-
由上述可知,本實施例採用特殊的製造系統,其整合了押出機21、衣架型膜頭22及整平機23,且透過特殊的製程以製作單層半導體研磨膠帶1,不需要經由塗佈步驟,故單層半導體研磨膠帶1的高分子膜12的厚度均勻(高分子膜的厚度約在40um-500um之間)及且具有更佳的表面平整度,且能大幅地降低高分子膜12的製造公差(小於±5um)。As can be seen from the above, this embodiment adopts a special manufacturing system, which integrates the extruder 21, the hanger-
當然,本實施例僅用於舉例說明而非限制本揭露的範圍,根據本實施例的單層半導體研磨膠帶1的製造系統而進行的等效修改或變更仍應包含在本發明的專利範圍內。Of course, this embodiment is only for illustration and does not limit the scope of the present disclosure. Equivalent modifications or changes made according to the manufacturing system of the single-layer
值得一提的是,現有的半導體研磨膠帶為多層結構,其外層為黏著層,內層為塗佈層,大多應用塗佈方式製成。因此,現有的半導體研磨膠帶的製程較為複雜,故成本也較高。相反的,根據本揭露的實施例,單層半導體研磨膠帶為單層結構,故其基材上可僅具有單層的高分子膜,因此單層半導體研磨膠帶的製程能夠大幅簡化,故製造成本可進一步降低。It is worth mentioning that existing semiconductor polishing tapes have a multi-layer structure, with the outer layer being an adhesive layer and the inner layer being a coating layer. Most of them are made by coating. Therefore, the manufacturing process of the existing semiconductor polishing tape is relatively complicated, so the cost is also high. On the contrary, according to the embodiments of the present disclosure, the single-layer semiconductor polishing tape has a single-layer structure, so the base material can only have a single layer of polymer film. Therefore, the manufacturing process of the single-layer semiconductor polishing tape can be greatly simplified, so the manufacturing cost is reduced. can be further reduced.
又,根據本揭露的實施例,單層半導體研磨膠帶採用的高分子膜具有特殊的成份比例,使此高分子膜在不同的溫度範圍下具有不同的硬度及黏著度,故可同時提供良好的緩衝功能及黏著功能,且又可以很容易地由晶圓上撕除。In addition, according to embodiments of the present disclosure, the polymer film used in the single-layer semiconductor polishing tape has a special composition ratio, so that the polymer film has different hardness and adhesion in different temperature ranges, so it can provide good It has buffering function and adhesive function, and can be easily removed from the wafer.
此外,現有製成研磨膠帶的製程常遇到厚膜平整度較差的疑慮,若使用平整度較差的研磨膠帶附著於晶片進行切割時,易造成較大的晶片厚度誤差,進而影響晶片的效能。相反的,根據本揭露的實施例,單層半導體研磨膠帶採用的製造方法能有效地使高分子膜的厚度均勻及且具有更佳的表面平整度,故能滿足晶圓研磨製程的需求,應用上更為廣泛。In addition, existing processes for making abrasive tapes often encounter concerns about poor flatness of thick films. If abrasive tapes with poor flatness are used to attach to wafers for cutting, it will easily cause large wafer thickness errors, thereby affecting the performance of the wafers. On the contrary, according to the embodiments of the present disclosure, the single-layer semiconductor polishing tape adopts a manufacturing method that can effectively make the thickness of the polymer film uniform and have better surface flatness, so it can meet the needs of the wafer polishing process. Application more widely.
另外,現有製成研磨膠帶的製程需要經過塗佈步驟,故容易形成較大的公差。相反的,根據本揭露的實施例,單層半導體研磨膠帶採用的製造方法能有效地使高分子膜的製造公差降低,使生產的單層半導體研磨膠帶的品質更佳,以符合實際應用上的需求。In addition, the existing process for making abrasive tape requires a coating step, so it is easy to create large tolerances. On the contrary, according to the embodiments of the present disclosure, the manufacturing method adopted by the single-layer semiconductor polishing tape can effectively reduce the manufacturing tolerance of the polymer film, so that the quality of the single-layer semiconductor polishing tape produced is better, so as to meet the requirements of practical applications. need.
請參閱第4圖,其係為本揭露之一實施例之單層半導體研磨膠帶的製造方法的流程圖。如圖所示,本實施例之單層半導體研磨膠帶的製造方法包含下列步驟:Please refer to FIG. 4 , which is a flow chart of a manufacturing method of a single-layer semiconductor polishing tape according to an embodiment of the present disclosure. As shown in the figure, the manufacturing method of the single-layer semiconductor polishing tape of this embodiment includes the following steps:
步驟S41:將高分子聚合物材料混合產生混合物。在此步驟中,高分子聚合物材料及黏著賦予劑以特定的比例混合產生混合物,此加工過後能達到適當的特性,以應用於半導體研磨膠帶。Step S41: Mix high molecular polymer materials to produce a mixture. In this step, the high molecular polymer material and the adhesion imparting agent are mixed in a specific ratio to produce a mixture, which can achieve appropriate properties after processing for application in semiconductor polishing tape.
步驟S42:將混合物置入押出機的入料口,並透過押出機的加熱器及螺桿對混合物進行加熱及壓縮。在此步驟中,將混合物置入押出機21的入料口211;同時,押出機21的螺桿213轉動對混合物進行壓縮;另外,押出機21的加熱器214則在壓縮的同時進行加熱。Step S42: Place the mixture into the inlet of the extruder, and heat and compress the mixture through the heater and screw of the extruder. In this step, the mixture is placed into the inlet 211 of the extruder 21; at the same time, the screw 213 of the extruder 21 rotates to compress the mixture; in addition, the heater 214 of the extruder 21 heats while compressing.
步驟S43:透過押出機的出料口將經過加熱及壓縮的混合物輸送至衣架型膜頭。在此步驟中,將完成壓縮及加熱後的混合物經由押出機21的出料口215輸送至衣架型膜頭22。Step S43: Transport the heated and compressed mixture to the hanger-type film head through the discharge port of the extruder. In this step, the compressed and heated mixture is transported to the hanger-
步驟S44:經由衣架型膜頭將混合物擠出形成高分子膜,並進行淋膜使高分子膜附著於基材上。在此步驟中,透過具有漸寬延伸結構的衣架型膜頭22將完成壓縮及加熱後的混合物擠出形成高分子膜12,再進行淋膜步驟,使高分子膜12附著於基材11上。Step S44: Extrude the mixture through a hanger-type film head to form a polymer film, and laminate the polymer film to adhere to the substrate. In this step, the compressed and heated mixture is extruded through a hanger-
步驟S45:透過整平機對附著於基材上的高分子膜進行整平。在此步驟中,以整平機23對基材11上的高分子膜12進行整平,以確保高分子膜的厚度均勻及且具高表面平整度。Step S45: Use a leveling machine to level the polymer film attached to the base material. In this step, a leveling
當然,本實施例僅用於舉例說明而非限制本揭露的範圍,根據本實施例的單層半導體研磨膠帶的製造方法而進行的等效修改或變更仍應包含在本發明的專利範圍內。Of course, this embodiment is only for illustration and does not limit the scope of the present disclosure. Equivalent modifications or changes based on the manufacturing method of the single-layer semiconductor polishing tape of this embodiment should still be included in the patent scope of the present invention.
儘管本揭露描述的方法的步驟以特定順序示出和描述,但是每個方法的操作順序可以改變,也可以相反的順序執行某些步驟,或者某些步驟也與其他步驟同時執行。在另一個實施例中,不同步驟可以間歇和/或交替的方式實施。Although the steps of the methods described in this disclosure are shown and described in a specific order, the order of operations of each method may be changed, some steps may be performed in reverse order, or some steps may be performed concurrently with other steps. In another embodiment, the different steps may be performed in an intermittent and/or alternating manner.
綜上所述,根據本揭露的實施例,單層半導體研磨膠帶為單層結構,故其基材上可僅具有單層的高分子膜,因此單層半導體研磨膠帶的製程能夠大幅簡化,故製造成本可進一步降低。In summary, according to the embodiments of the present disclosure, the single-layer semiconductor polishing tape has a single-layer structure, so the base material can only have a single layer of polymer film. Therefore, the manufacturing process of the single-layer semiconductor polishing tape can be greatly simplified. Manufacturing costs can be further reduced.
又,根據本揭露的實施例,單層半導體研磨膠帶採用的高分子膜具有特殊的成份比例,使此高分子膜在不同的溫度範圍下具有不同的硬度及黏著度,故可同時提供良好的緩衝功能及黏著功能,且又可以很容易地由晶圓上撕除。In addition, according to embodiments of the present disclosure, the polymer film used in the single-layer semiconductor polishing tape has a special composition ratio, so that the polymer film has different hardness and adhesion in different temperature ranges, so it can provide good It has buffering function and adhesive function, and can be easily removed from the wafer.
此外,根據本揭露的實施例,單層半導體研磨膠帶採用的製造方法能有效地使高分子膜的厚度均勻及且具有更佳的表面平整度,故能滿足晶圓研磨製程的需求,應用上更為廣泛。In addition, according to embodiments of the present disclosure, the single-layer semiconductor polishing tape adopts a manufacturing method that can effectively make the thickness of the polymer film uniform and have better surface flatness, so it can meet the needs of the wafer polishing process. More extensive.
另外,根據本揭露的實施例,單層半導體研磨膠帶採用的製造方法能有效地使高分子膜的製造公差降低,使生產的單層半導體研磨膠帶的品質更佳,以符合實際應用上的需求。In addition, according to embodiments of the present disclosure, the manufacturing method used for the single-layer semiconductor polishing tape can effectively reduce the manufacturing tolerance of the polymer film, so that the quality of the single-layer semiconductor polishing tape produced is better, so as to meet the needs of practical applications. .
可見本揭露在突破先前之技術下,確實已達到所欲增進之功效,且也非熟悉該項技藝者所易於思及,其所具之進步性、實用性,顯已符合專利之申請要件,爰依法提出專利申請,懇請 貴局核准本件發明專利申請案,以勵創作,至感德便。It can be seen that this disclosure has indeed achieved the desired improvement effect by breaking through the previous technology, and it is not easily imagined by those familiar with the technology. Its progress and practicality clearly meet the requirements for patent application. I have filed a patent application in accordance with the law, and I sincerely request your office to approve this application for an invention patent to encourage creation, and I would like to express my gratitude to you.
以上所述僅為舉例性,而非為限制性者。其它任何未脫離本揭露之精神與範疇,而對其進行之等效修改或變更,均應該包含於後附之申請專利範圍中。The above is only illustrative and not restrictive. Any other equivalent modifications or changes that do not depart from the spirit and scope of this disclosure should be included in the appended patent application scope.
1:單層半導體研磨膠帶 11:基材 12:高分子膜 2:製造系統 21:押出機 211:入料口 212:本體 213:螺桿 214:加熱器 215:出料口 22:衣架型膜頭 23:整平機 S41-S45:步驟流程 1:Single layer semiconductor polishing tape 11:Substrate 12:Polymer membrane 2: Manufacturing system 21:Extrusion machine 211:Inlet port 212:Ontology 213:Screw 214:Heater 215: Discharge port 22: Hanger type membrane head 23: Leveling machine S41-S45: step process
第1圖係為本揭露之一實施例之單層半導體研磨膠帶之結構圖。 第2圖 係為本揭露之一實施例之單層半導體研磨膠帶之製造系統的第一示意圖。 第3圖 係為本揭露之一實施例之單層半導體研磨膠帶之製造系統的第二示意圖。 第4圖 係為本揭露之一實施例之單層半導體研磨膠帶的製造方法的流程圖。 Figure 1 is a structural diagram of a single-layer semiconductor polishing tape according to an embodiment of the present disclosure. Figure 2 is a first schematic diagram of a manufacturing system for a single-layer semiconductor polishing tape according to an embodiment of the present disclosure. Figure 3 is a second schematic diagram of a manufacturing system for a single-layer semiconductor polishing tape according to an embodiment of the present disclosure. FIG. 4 is a flow chart of a manufacturing method of a single-layer semiconductor polishing tape according to an embodiment of the present disclosure.
1:單層半導體研磨膠帶 1:Single layer semiconductor polishing tape
11:基材 11:Substrate
12:高分子膜 12:Polymer membrane
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| CN101896567B (en) * | 2008-02-05 | 2014-04-30 | 三井-杜邦聚合化学株式会社 | Adhesive resin composition and adhesive film or sheet |
| TWM627340U (en) * | 2021-12-28 | 2022-05-21 | 許滄益 | Single-layer semiconductor abrasive tape and manufacturing system thereof |
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| CN101896567B (en) * | 2008-02-05 | 2014-04-30 | 三井-杜邦聚合化学株式会社 | Adhesive resin composition and adhesive film or sheet |
| TWM627340U (en) * | 2021-12-28 | 2022-05-21 | 許滄益 | Single-layer semiconductor abrasive tape and manufacturing system thereof |
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