TWI819071B - Apparatus for and method of providing high precision delays in a lithography system - Google Patents

Abstract

Methods of and apparatus for controlling pulses in a laser system include controlling the relative timing of trigger pulses in a multi-chamber laser system to control a delay in the respective firing of the multiple chambers including the use of a combination of a field programmable gate array and programmable delay circuits.

Description

Devices and methods for providing high-precision delay in lithography systems

The subject matter disclosed herein relates to the control of light sources such as lasers used in integrated circuit photolithography manufacturing processes.

One system for generating laser radiation at frequencies suitable for semiconductor photolithography (deep ultraviolet (DUV) wavelengths) involves the use of a master oscillator power amplifier (MOPA) dual gas discharge chamber configuration. Managing the relative timing of pulses (excitation) in the master oscillator (MO) section of the MOPA relative to pulses (excitation) in the power amplifier (PA) section of the MOPA is required to achieve laser dose stability. Similar master oscillator seeds that provide other amplifier configurations such as power oscillators ("PO") to the laser system may also be used. However, for the sake of brevity, unless otherwise expressly indicated, the term MOPA or the terms MO and PA, respectively, shall be interpreted to mean any such multi-chamber laser system, such as a dual-chamber laser system, e.g. including an oscillator Seed pulse generation section, which optimizes the beam parameter quality, followed by amplification of the seed pulse by an amplifier section that receives any kind of seed pulse, examples of which are mentioned above, this amplifier section is used for the amplification function and for this amplification The process is adjusted so that the specific beam quality parameters optimized in the master oscillator section remain approximately constant.

The use of extreme ultraviolet ("EUV") light in photolithography processes, such as electromagnetic radiation (sometimes also called soft x-rays) with a wavelength of about 50 nm or less and including light with a wavelength of about 13.5 nm , to create extremely small features on substrates such as silicon wafers. Although it is understood that radiation described using the term "light" may not be in the visible portion of the spectrum, that term will be used here and elsewhere herein. The method used to generate EUV light involves converting the target material from a liquid to a plasma state. The target material preferably includes at least one element having one or more emission lines in the EUV range, such as xenon, lithium or tin. In one such method, often referred to as laser-produced plasma ("LPP"), the desired plasma can be generated by irradiating a target material having the desired line-emitting element with a laser beam. Managing the relative timing of pulses in EUV systems is also required to achieve dose stability.

There is a need to provide alternatives to existing devices or methods for managing relative pulse timing in such systems.

The following presents a simplified summary of one or more embodiments in order to provide a basic understanding of the invention. This summary is not an extensive overview of all contemplated embodiments and is intended to neither identify key or critical elements of all embodiments nor delineate the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later.

According to an aspect of an embodiment, a laser system is disclosed herein, which includes: a field programmable gate array configured to generate a first digital signal and a logical inversion of the first digital signal. a second digital signal, the first digital signal transitions from a first logic level to a second logic level for a plurality of clock cycles; a first programmable delay circuit configured to receive the a digital signal configured to delay propagation of the first digital signal by a first delay, thereby producing a delayed first digital signal; a second programmable delay circuit configured to receive the second digital signal a signal and configured to have a propagation delay of the second digital signal greater than the first delay, thereby producing a delayed second digital signal; and a first logic circuit configured to receive the a delayed first digital signal and the delayed second digital signal, and configured to be generated if and only when the first digital signal and the delayed second digital signal are both at the second logic level One pulse.

According to an aspect of an embodiment, a laser system is also disclosed herein, including: a module configured to supply a first pulse having a first duration and a second pulse having a second duration. a second pulse, wherein a start of the first pulse is separated in time from a start of the second pulse by a delay interval, the module comprising: a field programmable gate array configured to generate: a first A digital signal that transitions from a first logic level to a second logic level at a time t ₁ for a plurality of clock cycles; a second digital signal that is one of the logic levels of the first digital signal Conversely; a third digital signal that transitions from the first logic level to the second logic level at a time _t2 later than _t1 for a plurality of clock cycles; and a fourth digital signal, a logical inversion of the third digital signal; a first programmable delay circuit configured to receive the first digital signal and configured to delay propagation of the first digital signal by a first delay, A delayed first digital signal is thereby generated; a second programmable delay circuit configured to receive the second digital signal and configured to have a propagation delay of the second digital signal greater than one of the first delays a second delay, thereby generating a delayed second digital signal; a first logic circuit configured to receive the delayed first digital signal and the delayed second digital signal, and configured to when and The first pulse is generated only when both the first digital signal and the delayed second digital signal are at the second logic level; a third programmable delay circuit configured to receive the third digital signal signal and configured to delay propagation of the third digital signal by a third delay, thereby producing a delayed third digital signal; a fourth programmable delay circuit configured to receive the fourth digital signal and a fourth delay configured to have a propagation delay of the fourth digital signal greater than the third delay, thereby generating a delayed fourth digital signal; and a second logic circuit configured to receive the delayed The third digital signal and the delayed fourth digital signal are configured to, after the first pulse ceases, if and only if both the delayed third digital signal and the delayed fourth digital signal are The second pulse is generated when the second logic bit is present.

The laser system may be a system for generating deep ultraviolet radiation, and further comprising: a first trigger circuit configured to receive the first pulse and to cause a first chamber of the laser to respond to the and a second trigger circuit configured to receive the second pulse and to cause a second chamber of the laser to be excited in response to the second pulse.

The laser system may be a system for generating far ultraviolet radiation, and further comprising: a first trigger circuit configured to receive the first pulse and for causing a first laser pulse in response to the first and a second trigger circuit configured to receive the second pulse and to cause a second laser pulse to be excited in response to the second pulse.

The laser system may include: a first laser chamber configured to receive a first laser chamber excitation pulse based on the first pulse; and a second laser chamber configured to receive a first laser chamber excitation pulse based on the first pulse. The second pulse receives a second laser chamber excitation pulse.

According to an aspect of an embodiment, a method of generating a trigger pulse for a laser system is also disclosed. The method includes: generating a first digital signal and a logical inversion of the first digital signal. A second digital signal, the first digital signal transitions from a first logic level to a second logic level for a plurality of clock cycles; propagation of the first digital signal is delayed by a first delay, thereby generating a Delaying the first digital signal; applying a second delay greater than the propagation delay of the second digital signal to the first delay, thereby generating a delayed second digital signal; and if and only if the first digital signal and the first delay are A pulse is generated when both delayed second digital signals are at the second logic level.

According to an aspect of an embodiment, a method of generating a trigger pulse for a laser system is also disclosed. The method includes: generating a first digital signal and a logical inversion of the first digital signal. A second digital signal, the first digital signal transitions from a first logic level to a second logic level at a time t ₁ for a plurality of clock cycles; propagation of the first digital signal is delayed by a a delay, thereby producing a delayed first digital signal; a second delay that is greater than the propagation delay of the second digital signal greater than the first delay, thereby producing a delayed second digital signal; and if and only if the third digital signal is A first pulse is generated when both a digital signal and the delayed second digital signal are at the second logic level; a third digital signal and a fourth digital bit that is the logical inversion of the third digital signal are generated. signal, the third digital signal transitions from the first logic level to the second logic level at a time t ₂ later than t ₁ for a plurality of clock cycles; propagation delay of the third digital signal a third delay, thereby generating a delayed third digital signal; a fourth delay of a propagation delay of the fourth digital signal greater than the third delay, thereby generating a delayed fourth digital signal; and stopping the third delay After a pulse, a second pulse is generated when and only when both the delayed third digital signal and the delayed fourth digital signal are at the second logic level.

The method may further include supplying the first pulse as a trigger signal to a power inverter of a first chamber of a multi-chamber laser and supplying the second pulse as a trigger signal to a multi-chamber laser. A power commutator step for a second laser chamber.

The steps of generating the first digital signal, the second digital signal, the third digital signal and the fourth digital signal may be performed by a field programmable gate array.

The method may further include the steps of supplying the first pulse as a trigger signal to excite a first pulse at a target material and supplying the second pulse as a trigger signal to excite a second pulse at the target material. The first pulse can be a pre-pulse and the second pulse can be a main pulse.

The step of delaying the first digital signal may be performed by a first programmable delay circuit.

The step of delaying the second digital signal may be performed by a second programmable delay circuit.

The step of delaying the third digital signal may be performed by a third programmable delay circuit.

The step of delaying the fourth digital signal may be performed by a fourth programmable delay circuit.

Other features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. It should be noted that this invention is not limited to the specific embodiments described herein. Such embodiments are presented herein for illustrative purposes only. Additional embodiments will be apparent to those skilled in the relevant art based on the teachings contained herein.

Various embodiments are now described with reference to the drawings, wherein like reference numbers are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more embodiments. It may be apparent, however, in some or all instances that any of the embodiments described below may be practiced without the specific design details described below. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate description of one or more embodiments. A simplified summary of one or more embodiments is presented below in order to provide a basic understanding of the embodiments. This summary is not an extensive overview of all contemplated embodiments and is intended to neither identify key or critical elements of all embodiments nor delineate the scope of any or all embodiments.

The described embodiments, and references in this specification to "one embodiment," "an embodiment," "an example embodiment," etc., indicate that the described embodiment may include a particular feature, structure, or characteristic, but each Embodiments may not necessarily include this particular feature, structure or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Additionally, when a particular feature, structure, or characteristic is described in connection with an embodiment, it should be understood that it will be within the skill of those skilled in the art to implement the feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

Embodiments of the present invention may be implemented in hardware, firmware, software, or any combination thereof. Embodiments of the invention may also be implemented as instructions stored on a machine-readable medium, which may be read and executed by one or more processors. Machine-readable media may include any mechanism for storing or transmitting information in a form readable by a machine (eg, a computing device). For example, machine-readable media may include read-only memory (ROM); random-access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustic, or other forms Propagated signals (such as carrier waves, infrared signals, digital signals, etc.); and others. In addition, firmware, software, routines, and instructions may be described herein as performing certain actions. However, it should be understood that such descriptions are for convenience only and that such actions are actually caused by a computing device, processor, controller, or other device executing firmware, software, routines, instructions, or the like.

Before describing such embodiments in greater detail, it is instructive to present an example environment in which embodiments of the invention may be implemented. Although the following examples are based on a DUV system, those skilled in the art will understand that the subject matter disclosed herein may also be applied to other laser systems, such as systems used to generate EUV radiation.

Referring to FIG. 1 , photolithography system 100 includes illumination system 105 . As described more fully below, the illumination system 105 includes a light source that generates a pulsed beam 110 and directs it to a photolithography exposure device or scanner 115 that patterns the microelectronic features. on the wafer 120. Wafer 120 is placed on a wafer stage 125 that is constructed to hold wafer 120 and is connected to a positioner configured to accurately position wafer 120 according to certain parameters.

In the example of Figure 1, photolithography system 100 uses a light beam 110 having a wavelength in the deep ultraviolet (DUV) range, such as having a wavelength of 248 nanometers (nm) or 193 nm. The size of the microelectronic features patterned on wafer 120 depends on the wavelength of beam 110, with lower wavelengths resulting in smaller minimum feature sizes. When the wavelength of the beam 110 is 248 nm or 193 nm, the minimum size of the microelectronic features may be, for example, 50 nm or less. The bandwidth of beam 110 may be the actual instantaneous bandwidth of its spectrum (or emission spectrum), which contains information about how the light energy of beam 110 is distributed across different wavelengths. The scanner 115 includes an optical arrangement having, for example, one or more condenser lenses, a reticle, and an objective lens arrangement. The mask may move along one or more directions, such as along the optical axis of the beam 110 or in a plane perpendicular to the optical axis. The objective configuration includes a projection lens and enables image transfer from the reticle to the photoresist on wafer 120 . The illumination system 105 adjusts the range of angles at which the light beam 110 irradiates the photomask. Illumination system 105 also uniformizes the intensity distribution of beam 110 across the reticle (makes the intensity distribution uniform).

The scanner 115 may include a lithography controller 130, an air conditioning device, and a power supply for various electrical components, among other features. Lithography controller 130 controls how layers are printed on wafer 120 . Lithography controller 130 includes memory that stores information such as process recipes. The process sequence or recipe determines the exposure length on the wafer 120, the photomask used, and other factors that affect exposure. During lithography, multiple pulses of light beam 110 illuminate the same area of wafer 120 to constitute an illumination dose.

The photolithography system 100 also preferably includes a control system 135 . Generally speaking, the control system 135 includes one or more of digital electronic circuit systems, computer hardware, firmware, and software. The control system 135 also includes memory, which may be read-only memory and/or random access memory. Storage devices suitable for tangibly embodying computer program instructions and data include all forms of non-volatile memory, including (by way of example) semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks, such as internal hard drives. and removable disks; magneto-optical disks; and CD-ROM disks.

Control system 135 may also include one or more input devices (such as keyboards, touch screens, microphones, mice, handheld input devices, etc.) and one or more output devices (such as speakers or monitors). The control system 135 also includes one or more programmable processors and one or more computer program products tangibly embodied in a machine-readable storage device for execution by the one or more programmable processors. One or more programmable processors can each execute a program of instructions to perform a desired function by operating on input data and producing appropriate output. Typically, a processor receives instructions and data from memory. Any of the foregoing may be supplemented by, or incorporated into, specially designed Application Special Integrated Circuits (ASICs). Control system 135 may be centralized or partially or completely distributed throughout photolithography system 100 .

Referring to FIG. 2 , an exemplary illumination system 105 is a pulsed multi-chamber laser source that generates a pulsed laser beam as beam 110 . 2 depicts one particular set of components and optical paths strictly for the purpose of generally facilitating description of the broad principles of the invention, and it will be apparent to those of ordinary skill in the art that the principles of the invention may be advantageously applied to other devices having Components and configurations of lasers.

Figure 2 illustratively and in a block diagram shows a gas discharge laser system according to an embodiment of certain aspects of the disclosed subject matter. The gas discharge laser system may include, for example, a solid state or gas discharge seed laser system 140, a power amplification ("PA") stage such as a power ring amplifier ("PRA") stage 145, relay optics 150, and the laser system Output subsystem 160. The seed system 140 may include, for example, a master oscillator ("MO") chamber 165, in which discharges between electrodes (not shown) may cause laser gas discharges in the laser gas to generate a population of inverted high-energy molecules. , for example, including Ar, Kr or known in.

The seed laser system 140 may also include a master oscillator output coupler ("MO OC") 175, which may include a partial mirror that together with a reflection grating (not shown) in the LNM 170 forms an oscillator cavity. In the oscillator cavity, the seed laser 140 oscillates to form a seed laser output pulse, that is, a master oscillator (“MO”). The system may also include a line center analysis module ("LAM") 180. The LAM 180 can include an etalon spectrometer for fine wavelength measurements as well as a coarser resolution grating spectrometer. MO wavefront engineering box ("WEB") 185 may be used to redirect the output of MO seed laser system 140 to amplification stage 145, and may include, for example, a beam expander having, for example, a multi-channel beam expander (not shown) and For example, coherence busting in the form of optical delay paths (not shown).

The amplifying electrode 145 may include, for example, a laser chamber 200, which may also be an oscillator, which may be formed, for example, by seed beam injection and outcoupling optics (not shown). The seed beam injection and outcoupling optics may The gain medium incorporated into the PRA WEB 210 and may be redirected by the beam inverter 220 back through the chamber 200 . PRA WEB 210 may incorporate a partially reflective input/output coupler (not shown) and a maximum reflective mirror for the nominal operating wavelength (e.g., at approximately 193 nm for an ArF system), and one or more mirrors.

A bandwidth analysis module ("BAM") 230 at the output of the amplification stage 145 may receive the pulsed output laser beam from the amplification stage and pick up a portion of the beam for metrological purposes, such as to measure the output bandwidth. and pulse energy. The pulsed laser output beam is then passed through the optical pulse stretcher ("OPuS") 240 and the output combined automatic shutter metrology module ("CASMM") 250, which may also be the location of the pulse energy meter. One purpose of OPuS 240 may be, for example, to convert a single output laser pulse into a pulse train. Secondary pulses generated from the original single output pulse may be delayed relative to each other. By distributing the original laser pulse energy into secondary pulse trains, the effective pulse length of the laser can be extended while the peak pulse intensity is reduced. OPuS 240 can therefore receive the laser beam from PRA WEB 210 via BAM 230 and direct the output of OPuS 240 to CASMM 250.

MO and PA delay commands may be used to indicate to TEM 310 how long after a reference trigger signal (eg, trigger signal T from the consumer interface) to send respective trigger signals to respective pulse power systems 315 . There can be one pulsed power system for each of MO and PA or PRA.

In EUV light sources, EUV can be generated by preparing a target distribution from flying metal droplets via a laser pre-pulse and then heating the target distribution to a plasma state using a second laser pulse. The prepulse laser hits the droplet to modify the distribution of the target material, and the main pulse laser hits the target to heat it to a plasma that emits EUV. In some systems, the pre-pulse and main heating pulse are provided by the same laser system, and in other systems, there are two separate lasers. In some cases, the reflection of the main pulse from the formed target is used for diagnosis of the formed target or target site. It is important to "aim" the flying droplets to within a few microns to achieve efficient operation of the light source with minimal fragmentation.

Figure 3 is a non-scale schematic diagram of an EUV system 260 using both pre-pulses and main pulses. EUV system 260 includes a radiation source 265 capable of generating a pre-pulse 267 and a subsequent main pulse 268, among other features. Prepulses 267 and main pulses 268 propagate into a chamber 285 including a collector mirror 287 where they impact a quantity of target material 290 at an irradiation site 295. In the example shown, the target material 290 is initially in the form of a stream of droplets released by a target material dispenser 292, which in this example is a droplet generator. In this form, target material 290 may be ionized by the main pulse. Alternatively, the target material 290 may be ionized preconditioned with a prepulse, which may, for example, change the geometric distribution of the target material 290 . Therefore, it may be necessary both to accurately hit the target material 290 with the prepulse 267 to ensure that the target material 290 is in the desired form (disk, cloud, etc.), and to accurately hit the target with the main pulse to enable EUV. Efficient generation of radiation. All such operations occur under the control of control circuits

Several systems have been used in the past to accurately impact target materials with pre- or main pulses, including using reflected light from the operating pulse or using a second laser or light source to illuminate the droplet. For example, U.S. Patent No. 7,372,056 entitled "LPP EUV Plasma Source Material Target Delivery System" issued on May 13, 2008 (hereby incorporated by reference in its entirety) This article) discloses the use of a droplet detection radiation source and a droplet radiation detector that detects droplet detection radiation reflected from droplets of a target material.

4 is a functional block diagram of a circuit system that may be used to control the relative timing of the excitation of pulses (eg, MO chamber 165 and PRA chamber 200 in a DUV system or pre-pulse and main pulse in an EUV system). Figure 4 shows a firing control circuit (FCC) 300 that can send MO and PA delay commands from the energy and timing controller 305 to the timing and energy module (TEM) 310. TEM 310 may further send MO and PA commutator trigger signals to pulsed power system 315 to initiate discharge of a charging capacitor (not shown) via solid state switching elements (not shown) in pulsed power system 315. The respective trigger signals produce the resulting gas discharges due to the electrical energy provided to the respective counter electrodes through the laser gas medium between the electrodes in each of the respective MO and PA. In EUV systems, modules such as TEM can be used to, for example, control the relative timing of the excitation of pre-pulses and main pulses.

The main function of TEM 310 is to generate high-precision delayed pulses. TEMs such as the TEM 310 can be used in both DUV systems and EUV systems. The principles disclosed here apply to both DUV systems and EUV systems. In a DUV system, the TEM generates two pulses, one for the master oscillator (MO) and one for the power amplifier (PA). The current specifications for these two pulses are: 1- Pulse duration for MO and PA = 500 ns 2- The maximum delay from the reference trigger signal to the MO commutator trigger signal = 27 us 3- The maximum delay from the reference trigger signal to the PA commutator trigger signal = 27 us 4- Delay resolution for both MO trigger signal and PA trigger signal <250 ps 5- Used for delay jitter of both MO trigger signal and PA trigger signal <250 ps

According to one aspect of the embodiment, a circuit system including a field programmable gate array (FPGA) and a programmable delay chip (PDC) is used to generate the necessary high-precision delay. These devices used in isolation from each other have limitations. For example, FPGAs typically cannot generate subnanosecond logic. The PDC has a fixed propagation delay to its first tap and a very small delay range. However, combining these two technologies allows to overcome these limitations.

Figure 5 shows an example of a circuit combining FPGA 400 and PDCs 410, 415, 420 and 425. In more detail, the FPGA 400 receives the pulse data command and inputs the trigger signal A. As a result, the circuit system 440 within the FPGA 400 generates four signals b1, b2, b3 and b4 under the control of the oscillator 445. The first signal b1 is applied to the programmable delay circuit 410, which delays the propagation of the first signal b1. The second signal b2 is inverted by the inverter 450 and supplied to the programmable delay circuit 415 , which delays the propagation of the second signal b2 by a second delay that is greater than the first delay. The magnitude of the magnitude. The outputs of programmable delay circuit 410 and programmable delay circuit 415 are applied to logic circuit 430, which may be an AND gate, for example. The obtained signal P1 is used, for example, as a trigger signal for one chamber of a multi-chamber laser.

The third signal b3 is applied to the programmable delay circuit 420, which delays the propagation of the third signal b3. The fourth signal b4 is inverted by the inverter 450 and supplied to the programmable delay circuit 425 , which causes the propagation delay of the fourth signal b4 to be greater than that imposed by the programmable delay circuit 420 . The delay of the magnitude of the delay on the three signals. The outputs of programmable delay circuit 420 and programmable delay circuit 425 are applied to logic circuit 435, which may be an AND gate, for example. The obtained signal P2 is used, for example, as a trigger signal for the second chamber of a multi-chamber laser.

Programmable delay circuits 410, 415, 420, and 425 are programmed by programming module 460, which may be part of FPGA 400, for example.

An example of an FPGA suitable for use as the FPGA 400 is the Xilinx Kintex 7 FPGA (Speedgrade-3). This FPGA is limited to a maximum clock frequency of 800 MHz (1.25 ns). An example of a PDC suitable for use as PDCs 410, 415, 420 and 425 is the ON Semiconductor programmable delay chip MC100EP196BMNG with a total available delay between 2.5 ns and 13 ns (in 10 ps increments).

In the configuration of Figure 5, FPGA 400 is used to generate coarse delays (which also makes microsecond and millisecond delays possible). PDCs 410, 415, 420 and 425 are used to generate fine (10 ps increments) delays. In the above example, the phase locked loop (PLL) in FPGA 400 is used to generate a 400 MHz clock (2.5 ns period). This 2.5 ns period matches the delay of the first tap of PDC 410, 415, 420 and 425, so Makes it possible to have a continuous range of delays. In this case, the coarse delay resolution is 2.5 ns and the fine delay resolution is 10 ps, which is calculated by:

Figure 6 shows the generation of two 1 ns wide pulses with 1 ns separation. One nanosecond is used as a basis for Figure 5 to illustrate the diagram, but it will be apparent to those skilled in the art that the same relative timing can be used in the circuit shown in Figure 4 to produce picosecond resolution timing. As shown in Figure 5, the top signal labeled "1 ns period" is the clock signal. The next signal further down the graph is labeled "b1" and is the first signal described above. As can be seen, signal b1 changes from the first logic level to the second logic level on the rising edge of the clock, and then changes from the second logic level to the first logic level after several clock cycles. .

The next signal marked "~b2" below is the logical inverse of signal b1. The next signal labeled "b1_Delayed_2ns" below is the signal b1 that is delayed by two clock cycles. The next signal marked "~b2_Delayed_3ns" below is the signal ~b2 that is delayed by three clock cycles. The next signal marked "Pulse 1_1ns" below is the result of the AND operation of "b1_Delayed_2ns" and "~b2_Delayed_3ns". This produces a pulse that lasts for one clock cycle.

The next signal further down the diagram is labeled b3 and is the third signal described above. As can be seen, signal b3 changes from the first logic level to the second logic level on the rising edge of the clock, and then changes from the second logic level to the first logic level after several clock cycles. .

The next signal marked "~b4" below is the logical inverse of signal b4. The next signal labeled "b3_Delayed_2ns" below is the signal b3 that is delayed by two clock cycles. The next signal marked "~b4_Delayed_3ns" below is the signal ~b4 that is delayed by three clock cycles. The next signal marked "Pulse 2_1ns" below is the result of the AND operation of "b3_Delayed_2ns" and "~b4_Delayed_3ns". This operation produces a pulse that lasts for one clock cycle and is delayed by one clock cycle from the first pulse. The relative timing of transitions in signal b1 and signal b3 determines the amount of delay between pulse 1 and pulse 2.

Jitter in digital systems is caused by instabilities in the oscillator electronics. For this reason, the use of any PPL/DCM/MMCM inside the FPGA should be avoided when using an FPGA, which may suffer from jitter in the range of approximately 50 to 100 ps. Depending on the design requirements, an oscillator with appropriate frequency stability can be selected. An example of such an oscillator is the Abracon LLC ASGTX-D-400.000MHZ-1) which has a maximum jitter of 1.8 ps. Both analog and digital technologies suffer from jitter due to thermal noise and external interference from power and ground.

The above description includes examples of various embodiments. Of course, it is not possible to describe every conceivable combination of components or methods for the purpose of describing the foregoing embodiments, but one of ordinary skill in the art will recognize that many other combinations and permutations of the various embodiments are possible. The described embodiments are therefore intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the appended claims. Furthermore, to the extent that the term "includes" is used in the embodiments or claims, the term is intended to include in a manner similar to the way the term "includes" is interpreted when "includes" is used as a transition word in the claims. sexual. Furthermore, although elements of the described aspects and/or embodiments may be described or claimed in the singular, the plural is encompassed unless the singular limitation is expressly stated. Additionally, unless otherwise stated, all or part of any aspect and/or embodiment may be utilized in combination with all or part of any other aspect and/or embodiment.

Other aspects of the invention are set forth in the following numbered items. 1. A laser system including: A field programmable gate array configured to generate a first digital signal and a second digital signal that is a logical inversion of the first digital signal, the first digital signal being generated from a clock cycle for a plurality of clock cycles The first logic level changes to a second logic level; a first programmable delay circuit configured to receive the first digital signal and configured to delay propagation of the first digital signal by a first delay, thereby producing a delayed first digital signal; a second programmable delay circuit configured to receive the second digital signal and configured to delay the propagation of the second digital signal by a second delay greater than the first delay, thereby producing a delayed third two-digit signal; and A first logic circuit configured to receive the delayed first digital signal and the delayed second digital signal, and configured to receive the delayed first digital signal and the delayed second digital signal if and only if the first digital signal and the delayed second digital signal A pulse is generated when both digital signals are in the second logic bit. 2. A laser system including: A module configured to supply a first pulse having a first duration and a second pulse having a second duration, wherein a start of the first pulse and a start of the second pulse Separated in time by a delay interval, this module contains: A field programmable gate array configured to generate: a first digital signal that transitions from a first logic level to a second logic level at a time t1 for a plurality of clock cycles; a a second digital signal that is a logical inversion of the first digital signal; a third digital signal that transitions from the first logic level to the first logic level at a time t2 later than t1 for a plurality of clock cycles. a second logic level; and a fourth digital signal that is the logical inversion of the third digital signal, a first programmable delay circuit configured to receive the first digital signal and configured to delay propagation of the first digital signal by a first delay, thereby producing a delayed first digital signal, a second programmable delay circuit configured to receive the second digital signal and configured to delay the propagation of the second digital signal by a second delay greater than the first delay, thereby producing a delayed third Two-digit signal, A first logic circuit configured to receive the delayed first digital signal and the delayed second digital signal, and configured to receive the delayed first digital signal and the delayed second digital signal if and only if the first digital signal and the delayed second digital signal The first pulse is generated when both digital signals are in the second logic bit, a third programmable delay circuit configured to receive the third digital signal and configured to delay propagation of the third digital signal by a third delay, thereby producing a delayed third digital signal, a fourth programmable delay circuit configured to receive the fourth digital signal and configured to propagate the fourth digital signal with a fourth delay greater than the third delay, thereby producing a delayed third four digital signals, and a second logic circuit configured to receive the delayed third digital signal and the delayed fourth digital signal and configured to, after the first pulse ceases, if and only if the delayed third digital signal The second pulse is generated when both the third digital signal and the delayed fourth digital signal are at the second logic level. 3. The laser system of item 2, wherein the laser system is a system for generating deep ultraviolet radiation and further includes: a first trigger circuit configured to receive the first pulse and to cause a first chamber of the laser to fire in response to the first pulse; and A second trigger circuit configured to receive the second pulse and to cause a second chamber of the laser to fire in response to the second pulse. 4. The laser system of item 2, wherein the laser system is a system for generating far-ultraviolet radiation and further includes: a first trigger circuit configured to receive the first pulse and for causing a first laser pulse to fire in response to the first pulse; and A second trigger circuit configured to receive the second pulse and to cause a second laser pulse to fire in response to the second pulse. 5. For example, the laser system in item 2 further includes: a first laser chamber configured to receive a first laser chamber excitation pulse based on the first pulse, and A second laser chamber configured to receive a second laser chamber excitation pulse based on the second pulse. 6. A method of generating a trigger pulse for a laser system, the method comprising: Generating a first digital signal and a second digital signal that is a logical inversion of the first digital signal, the first digital signal transitions from a first logic level to a second logic bit for a plurality of clock cycles Accurate; Delay the propagation of the first digital signal by a first delay, thereby generating a delayed first digital signal; Apply a second delay greater than the propagation delay of the second digital signal to the first delay, thereby generating a delayed second digital signal; and A pulse is generated when and only when both the first digital signal and the delayed second digital signal are at the second logic level. 7. A method of generating a trigger pulse for a laser system, the method comprising: Generate a first digital signal and a second digital signal that is a logical inversion of the first digital signal. The first digital signal transitions from a first logic level to a logic level at a time t1 for a plurality of clock cycles. a second logic level; Delay the propagation of the first digital signal by a first delay, thereby generating a delayed first digital signal; applying a second delay greater than the propagation delay of the second digital signal to the first delay, thereby generating a delayed second digital signal; A first pulse is generated when and only when both the first digital signal and the delayed second digital signal are at the second logic level; Generating a third digital signal and a fourth digital signal that is a logical inversion of the third digital signal, the third digital signal is derived from the first logical signal at a time t2 later than t1 for a plurality of clock cycles. level transition to the second logic level, Delay the propagation of the third digital signal by a third delay, thereby generating a delayed third digital signal, The propagation delay of the fourth digital signal is greater than the third delay by a fourth delay, thereby generating a delayed fourth digital signal, and After stopping the first pulse, a second pulse is generated if and only when both the delayed third digital signal and the delayed fourth digital signal are at the second logic level. 8. The method of Item 7 further includes: supplying the first pulse as a trigger signal to a power commutator of a first chamber of a multi-chamber laser; and The second pulse is supplied as a trigger signal to a power inverter of a second chamber of a multi-chamber laser. 9. The method of Item 7, wherein the steps of generating the first digital signal, the second digital signal, the third digital signal and the fourth digital signal are performed by a field programmable gate array. 10. The method of item 7 further includes the following steps: supplying the first pulse as a trigger signal to excite a first pulse at a target material; and The second pulse is supplied as a trigger signal to excite a second pulse at the target material. 11. The method of item 7, wherein the first pulse is a pre-pulse and the second pulse is a main pulse. 12. The method of clause 7, wherein the step of delaying the first digital signal is performed by a first programmable delay circuit. 13. The method of clause 7, wherein the step of delaying the second digital signal is performed by a second programmable delay circuit. 14. The method of clause 7, wherein the step of delaying the third digital signal is performed by a third programmable delay circuit. 15. The method of Item 7, wherein the step of delaying the fourth digital signal is performed by a fourth programmable delay circuit.

100:Light lithography system 105:Lighting system 110: Pulse beam 115: Photolithography exposure device or scanner 120:wafer 125:Wafer table 130:Micro shadow controller 135:Control system 140:Solid state or gas discharge seed laser system 145: Power ring amplifier (“PRA”) stage/amplification stage 150:Relay optics 160: Laser system output subsystem 165: Master Oscillator (“MO”) Chamber 170: Line Narrowing Module (“LNM”) 175: Master Oscillator Output Coupler ("MO OC") 180: Line Center Analysis Module ("LAM") 185:MO wavefront engineering box ("WEB") 200:PRA chamber/laser chamber 210:PRA WEB 220:Beam inverter 230: Bandwidth Analysis Module (“BAM”) 240: Optical Pulse Stretcher ("OPuS") 250: Output Combined Automatic Shade Metrology Module ("CASMM") 260:EUV system 265: Radiation source 267: Prepulse 268: Main pulse 285: Chamber 287: Collector mirror 290:Target material 292:Target material dispenser 295:Irradiation site 300: Excitation control circuit (FCC) 305: Energy and timing controller 310: Timing and Energy Module (TEM) 315: Pulse power system 400:FPGA 410: Programmable delay circuit 415: Programmable delay circuit 420: Programmable delay circuit 425: Programmable delay circuit 430:Logic circuit 435:Logic circuit 440:Circuit system 445:Oscillator 450:Inverter 460:Stylized Module A: Input trigger signal b1: first signal b1_Delayed_2ns: signal b2: second signal ~b2: signal ~b2_Delayed_3ns: signal b3: The third signal b3_Delayed_2ns: signal b4: The fourth signal ~b4: signal ~b4_Delayed_3ns: signal P1: Resulting signal P2: Resulting signal Pulse 1_1ns: signal Pulse 2_1ns: signal T: trigger signal

The accompanying drawings, which are incorporated in and form part of this specification, illustrate the invention and, together with the description, further serve to explain the principles of the invention and to enable those skilled in the art to make and use the invention.

Figure 1 shows a schematic, not to scale, view of a general broad concept of a photolithography system in accordance with aspects of the disclosed subject matter.

2 shows a schematic, not to scale, view of a general broad concept of an illumination system for generating deep ultraviolet radiation, in accordance with aspects of the disclosed subject matter.

3 shows a schematic, not to scale, view of a general broad concept of an illumination system for generating far ultraviolet radiation in accordance with aspects of the disclosed subject matter.

Figure 4 is a functional block diagram of a circuit system for generating delayed pulses.

5 is a functional block diagram of a circuit system for generating delayed pulses, according to one aspect of the embodiment.

6 is a timing diagram illustrating signal levels and timing of an example of an operating mode of the circuit system of FIG. 4 according to an aspect of an embodiment.

Features and advantages of the present invention will become more apparent from the embodiments set forth below in conjunction with the drawings in which similar reference characters consistently identify corresponding elements. In the drawings, similar reference numbers generally indicate identical, functionally similar, and/or structurally similar elements.

400:FPGA

410: Programmable delay circuit

415: Programmable delay circuit

420: Programmable delay circuit

425: Programmable delay circuit

430:Logic circuit

435:Logic circuit

440:Circuit system

445:Oscillator

450:Inverter

460:Stylized Module

A: Input trigger signal

b1: first signal

b2: second signal

b3: The third signal

b4: The fourth signal

P1: Resulting signal

P2: Resulting signal

Claims (15)

A laser system comprising: a field programmable gate array configured to generate a first digital signal and a first logical inverse of the first digital signal. Two digital signals, the first digital signal transitions from a first logic level to a second logic level for a plurality of clock cycles; a first programmable delay circuit configured to receive the first digital signal a signal and configured to delay propagation of the first digital signal by a first delay, thereby producing a delayed first digital signal; a second programmable delay circuit configured to receive the second digital signal and a second delay configured to have a propagation delay of the second digital signal greater than the first delay, thereby generating a delayed second digital signal; and a first logic circuit configured to receive the delayed The first digital signal and the delayed second digital signal are configured to generate a pulse if and only when the first digital signal and the delayed second digital signal are both at the second logic level. . A laser system comprising: a module configured to supply a first pulse having a first duration and a second pulse having a second duration, wherein one of the first pulses begins Separated in time from the onset of one of the second pulses by a delay interval, the module includes: a programmable gate array configured to generate: a first digital signal that is generated for a plurality of clock cycles; A transition from a first logic level to a second logic level at time t ₁ ; a second digital signal, which is a logical inversion of the first digital signal; a third digital signal, which is for a plurality of times pulse cycle to transition from the first logic level to the second logic level at a time _t2 later than t1; and a _fourth digital signal that is the logical inversion of the third digital signal, a A first programmable delay circuit configured to receive the first digital signal and configured to delay propagation of the first digital signal by a first delay, thereby producing a delayed first digital signal, a second Programmable delay circuit configured to receive the second digital signal and configured to delay the propagation of the second digital signal by a second delay greater than the first delay, thereby generating a delayed second digital signal , a first logic circuit configured to receive the delayed first digital signal and the delayed second digital signal, and configured to receive the delayed first digital signal and the delayed second digital signal if and only if the first digital signal and the delayed third digital signal The first pulse is generated when two digital signals are both in the second logic bit, and a third programmable delay circuit is configured to receive the third digital signal and is configured to convert the third digital signal to a propagation delay, a third delay thereby producing a delayed third digital signal, a fourth programmable delay circuit configured to receive the fourth digital signal and configured to delay propagation of the fourth digital signal a fourth delay greater than the third delay, thereby generating a delayed fourth digital signal, and a second logic circuit configured to receive the delayed third digital signal and the delayed fourth digital signal And configured to generate the second pulse after the first pulse stops when and only when both the delayed third digital signal and the delayed fourth digital signal are at the second logic level. The laser system of claim 2, wherein the laser system is a system for generating deep ultraviolet radiation and further includes: a first trigger circuit configured to receive the first pulse and to cause the laser to a first chamber energized in response to the first pulse; and a second trigger circuit configured to receive the second pulse and to cause a second chamber of the laser to ignite in response to the second pulse. inspire. The laser system of claim 2, wherein the laser system is a system for generating far-ultraviolet radiation and further includes: a first trigger circuit configured to receive the first pulse and to cause a first a laser pulse is excited in response to the first pulse; and a second trigger circuit configured to receive the second pulse and for causing a second laser pulse to be excited in response to the second pulse. The laser system of claim 2, further comprising: a first laser chamber configured to receive a first laser chamber excitation pulse based on the first pulse, and a second laser chamber , which is configured to receive a second laser chamber excitation pulse based on the second pulse. A method of generating trigger pulses for a laser system, the method comprising: Generating a first digital signal and a second digital signal that is a logical inversion of the first digital signal, the first digital signal transitions from a first logic level to a second logic bit for a plurality of clock cycles accurate; delay the propagation of the first digital signal by a first delay, thereby producing a delayed first digital signal; delay the propagation of the second digital signal by a second delay greater than the first delay, thereby producing a delayed the second digital signal; and generate a pulse when and only when both the first digital signal and the delayed second digital signal are at the second logic level. A method for generating a trigger pulse for a laser system. The method includes: generating a first digital signal and a second digital signal that is a logical inversion of the first digital signal. The first digital signal is for a plurality of The clock cycle changes from a first logic level to a second logic level at a time _t1 ; delaying the propagation of the first digital signal by a first delay, thereby generating a delayed first digital signal; The propagation delay of the second digital signal is greater than the first delay by a second delay, thereby generating a delayed second digital signal; if and only if both the first digital signal and the delayed second digital signal A first pulse is generated in time at the second logic bit; a third digital signal and a fourth digital signal that is a logical inversion of the third digital signal are generated, and the third digital signal is generated for a plurality of clock cycles. Transitioning from the first logic level to the second logic level at a time t ₂ later than t ₁ delays the propagation of the third digital signal by a third delay, thereby generating a delayed third digital signal , the propagation delay of the fourth digital signal is greater than the fourth delay of the third delay, thereby generating a delayed fourth digital signal, and after stopping the first pulse, if and only if the delayed third A second pulse is generated when both the digital signal and the delayed fourth digital signal are in the second logic bit. The method of claim 7, further comprising: supplying the first pulse as a trigger signal to a power inverter of a first chamber of a multi-chamber laser; and using the second pulse as a trigger The signal is supplied to a power commutator of a second chamber of a multi-chamber laser. The method of claim 7, wherein the step of generating the first digital signal, the second digital signal, the third digital signal and the fourth digital signal is performed by a field programmable gate array. The method of claim 7, further comprising the steps of: supplying the first pulse as a trigger signal to excite a first pulse at a target material; and supplying the second pulse as a trigger signal to excite a target material at the target material. A second pulse is excited. The method of claim 7, wherein the first pulse is a pre-pulse and the second pulse is a main pulse. The method of claim 7, wherein the step of delaying the first digital signal is performed by a first programmable delay circuit. The method of claim 7, wherein the step of delaying the second digital signal is performed by a second programmable delay circuit. The method of claim 7, wherein the step of delaying the third digital signal is performed by a third programmable delay circuit. The method of claim 7, wherein the step of delaying the fourth digital signal is performed by a fourth programmable delay circuit.