TWI818834B - Microcontroller and serial peripheral interface system using the same - Google Patents

Abstract

A microcontroller and a serial peripheral interface (SPI) system using the same are provided. The SPI system includes a master device and at least one slave device. The slave device is coupled to the master device and configured to communicate with the master device through the SPI. The master device sends one or more of a preset clock signal, an output data signal, and a slave select signal as a clock setting request. The slave device identifies the clock setting request based on the received signal and sends a clock setting data indicating a clock phase and a clock polarity of the slave device in response to the clock setting request. The master device receives the clock setting data and sets the operation mode of the master device to match the clock phase and the clock polarity of the slave device according to the clock setting data.

Description

Microcontrollers and serial peripheral interface systems using them

The present invention relates to a serial peripheral interface communication technology, and in particular to a microcontroller and a serial peripheral interface system using the same.

Serial Peripheral Interface (SPI) is a full-duplex synchronous communication interface that mainly uses four-wire serial transmission. In a master-slave SPI system, the SPI master device can communicate with the SPI slave device through the SPI port to interactively transmit data. Because SPI has the advantages of simple operation and high data transmission rate, it is widely used in the design of devices such as microcontrollers or other radio frequency chips.

Since the devices that implement SPI slave devices may be manufactured by different manufacturers, or the set SPI timing/working modes are different due to differences in models, when setting up an SPI system, designers must individually address the specifications of the SPI slave device. Confirm, and then set the working mode of the SPI master device to be consistent with the SPI slave device. This makes the SPI system settings complex, and because each setting requires manual confirmation of the SPI timing/working mode, the risk of human setting errors is difficult to eliminate.

The present disclosure proposes a microcontroller and a serial peripheral interface system using the microcontroller, which can reduce the complexity of setting the SPI system and avoid the possibility of human setting errors.

The present disclosure provides a microcontroller that is suitable as a master device to communicate with slave devices. The microcontroller includes processing circuitry and SPI circuitry. The SPI circuit is coupled to the processing circuit and used to transmit data generated by the processing circuit to the slave device, or transmit data received from the slave device to the processing circuit. In the initialization setting mode, the SPI circuit sends one or more of the preset clock signal, the output data signal and the chip select signal as a clock setting request, receives the clock configuration data in response to the clock setting request, and based on The clock configuration data sets the clock polarity and clock phase of the serial peripheral interface circuit.

The present disclosure provides a microcontroller that is suitable as a slave device to communicate with a master device. The microcontroller includes processing circuitry and SPI circuitry. The SPI circuit is coupled to the processing circuit and is used to transmit data received from the host device to the processing circuit, or to transmit data generated by the processing circuit to the host device. In the initialization setting mode, the SPI circuit identifies a clock setting request based on one or more of the received preset clock signal, input data signal and chip select signal, and sends clock configuration data in response to the clock setting request. , where the clock configuration data indicates the clock polarity and clock phase of the sequence peripheral interface circuit.

The present disclosure provides an SPI system, including a master device and at least one slave device. The slave device is coupled to the master device and used to communicate with the master device through SPI. In the initialization setting mode, the master device sends one or more of a preset clock signal, an output data signal, and a chip select signal as a clock setting request. The slave device recognizes a clock setting request based on the received signal and sends clock configuration data indicating a clock phase and a clock polarity of the slave device in response to the clock setting request. The master device receives the clock configuration data, and sets the master device to conform to the clock phase and clock polarity of the slave device according to the clock configuration data.

Based on the above, the microcontroller of the present disclosure and the SPI system using it can enable the SPI master device to actively detect and obtain the clock polarity and clock phase of the SPI slave device during the initialization setting, and automatically The operating mode is set to be consistent with the SPI slave device. In this way, users no longer need to individually confirm the specifications of the SPI slave device and then manually set the SPI master device, thus avoiding the possibility of human setting errors.

The present disclosure proposes a new microcontroller and a serial peripheral interface system using the microcontroller to solve the problems mentioned in the background art. In order to make the features and advantages of the present disclosure more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. The following description contains specific information related to the exemplary embodiments of the present disclosure. The drawings and accompanying detailed description in this disclosure are merely exemplary embodiments. However, the present disclosure is not limited to these exemplary embodiments. Other variations and embodiments of the present disclosure will occur to those skilled in the art. Unless otherwise stated, the same or corresponding elements in the drawings may be designated by the same or corresponding reference numerals. Furthermore, the drawings and illustrations in the present disclosure are generally not to scale and are not intended to correspond to actual relative sizes.

FIG. 1 is a schematic diagram of a serial peripheral interface system according to an embodiment of the present disclosure. Referring to FIG. 1 , the Serial Peripheral Interface (SPI) system 10 of this embodiment includes an SPI master device 100 and n SPI slave devices 200_1 to 200_n, where n is greater than or equal to 1.

In this embodiment, the SPI master device 100 and the n SPI slave devices 200_1 ~ 200_n communicate through a 4-wire serial port of SPI to interactively transmit data, wherein the 4-wire serial port includes a clock port SCLK , master in and slave out port MOSI, master in and slave out port MISO and slave select port SS.

Specifically, the clock port SCLK, the master-in slave-in port MOSI, and the master-in slave port MISO of the SPI master device 100 are respectively coupled to the corresponding ports of each SPI slave device 200_1~200_n, and the SPI master device The clock port SCLK of 100 and the master input and slave input port MOSI will be used as signal output ports to transmit signals to each SPI slave device 200_1~200_n. The clock connection port SCLK is used to transmit the clock signal CLK to the SPI slave devices 200_1~200_n, so that the SPI slave devices 200_1~200_n can use the clock signal CLK as the communication clock. The master-output-slave-input port MOSI is an interface used to transmit data from the SPI master device 100 to the SPI slave devices 200_1~200_n.

The master-input-slave-output port MISO of the SPI master device 100 will be used as a signal input port to receive signals sent by the SPI slave devices 200_1~200_n. The master-input-slave-output port MISO is used to connect the SPI slave devices 200_1~200_n. The data is transmitted to the interface of the SPI master device 100 .

In addition, according to the setting of the number of slave devices 200_1 ~ 200_n in the system SPI, the SPI master device 100 may have slave select connection ports SS1 ~ SSn corresponding to the number of slave devices 200_1 ~ 200_n, wherein the slave select connection port SS1 of the SPI master device 100 ~SSn will be coupled to the slave select ports SS1~SSn of the slave devices 200_1~200_n respectively. In other words, each SPI slave device 200_1~200_n only has one slave selection port SS1~SSn connected to the corresponding slave selection port SS1~SSn on the SPI master device 100, or it can be said that under the setting of SPI slave mode , each slave device 200_1~200_n will have only one corresponding slave-side selection port SS1~SSn enabled. The slave select ports SS1~SSn of the SPI master device 100 are used as signal output ports to transmit enable signals to the corresponding SPI slave devices 200_1~200_n. The SPI slave devices 200_1~200_n that receive the enable signals will be enabled. for data transmission; otherwise, the SPI slave devices 200_1~200_n that have not received the enable signal will be disabled.

The SPI connection port in this embodiment is a 4-wire serial connection port as an example, but the disclosure is not limited to this. In some embodiments, if the SPI system 10 is configured in a one-to-one configuration (ie, n=1), the slave selection ports SS1~SSn may be omitted or disabled, and the SPI ports at this time may be 3-wire Serial port.

In this embodiment, the SPI master device 100 can be implemented using a microcontroller (hereinafter referred to as the microcontroller 100 ) as shown in Figure 2 , where Figure 2 shows a microcontroller as an SPI master device according to an embodiment of the present disclosure. schematic diagram.

Referring to FIG. 2 , the microcontroller 100 includes a processing circuit 110 , an SPI circuit 120 and a bus control circuit 130 . The processing circuit 110 is, for example, a central processing unit (CPU), which is used to process data access and operations. The SPI circuit 120 is coupled to the processing circuit 110 through the bus control circuit 130. The data generated by the processing circuit 110 will be transmitted to the SPI circuit 120 through the bus control circuit 130. The SPI circuit 120 will transmit the data through the master and slave according to its transmission format. Input port MOSI is transmitted to the outside. On the contrary, the data received by the SPI circuit 120 from the main input and output port MISO will be further transmitted to the processing circuit 110 through the bus control circuit 130 . The bus control circuit 130 may be, for example, an Advanced Peripheral Bus (APB) control circuit, but the disclosure is not limited thereto.

Specifically, when configuring the SPI system (eg 10), the microcontroller 100 will be controlled to enter an initialization setting mode. In the initialization setting mode, the SPI circuit 120 is set to the master mode, so that the clock port SCLK, the master-out slave-in port MOSI, and the slave-side selection port SS are set as signal output ports, and the master-input-slave-out connection Port MISO is set as the signal output port. At this time, the clock signal CLK generated by the SPI circuit 120 will pass through the clock connection port SCLK, the output data signal DOUTm of the microcontroller 100 will be output through the master output and slave input connection port MOSI, and the chip select signal SEL will be connected through the slave end selection Port SS output. In addition, the input data signal DINm received from the outside will be received through the master input and slave output port MISO.

After completing the setting of the host mode, the SPI circuit 120 will further send the clock signal CLK with a specific signal format, the output data signal DOUTm or the chip select signal SEL in the initialization setting mode, or combine the above signals in a specific timing sequence. as a clock setting request. The specific signal format and/or signal combination can be recognized by the SPI slave device, and then it is determined that the clock setting request is received.

For example, the specific signal format may be an output data signal DOUTm having a specific value, and the specific value may be easily identifiable two-tuple data, such as (0x00, 0xFF). In some embodiments, the specific signal format may also be a clock signal CLK with alternating frequency. The signal combination may be, for example, a clock signal CLK of a specific frequency and an output data signal DOUTm having a specific value.

In other words, the SPI circuit 120 may send one or more of the clock signal CLK, the output data signal DOUTm, and the chip select signal SEL as the clock setting request with specific signal characteristics that are easily recognized by the SPI slave device.

It should be noted here that in the initialization setting mode, since the microcontroller 100 as the SPI master device has not yet confirmed the working mode of the paired SPI slave device, the clock signal CLK sent at this time is a default clock signal. .

Next, the SPI circuit 120 receives the input data signal DINm sent by the SPI slave device in response to the clock setting request, where the input data signal DINm includes clock configuration data (ie, operating mode setting) of the SPI slave device. After the SPI circuit 120 identifies the clock configuration data from the input data signal DINm, it can set its clock polarity and clock phase according to the clock configuration data, so that the microcontroller 100 and the SPI slave device work in the same manner. mode communication, the initialization setting of the microcontroller 100 is completed.

In some embodiments, the SPI circuit 120 may include a control logic unit (not shown) for generating the clock signal CLK and the chip select signal SEL, a shift register (not shown) for accessing data, and Output input buffer unit (not shown). The control logic unit may also be used to perform the above-mentioned control on sending a clock setting request and set the clock polarity and clock phase of the SPI circuit according to the clock configuration data.

On the other hand, the SPI slave devices 200_1~200_n can be implemented using a microcontroller (hereinafter referred to as the microcontroller 200) as shown in Figure 3, where Figure 3 shows a microcontroller as an SPI slave device according to an embodiment of the present disclosure. schematic diagram.

Referring to Figure 3, the microcontroller 200 includes a processing circuit 210, an SPI circuit 220 and a bus control circuit 230. The microcontroller 200 as an SPI slave device and the above-mentioned microcontroller 100 as an SPI master device are in hardware configuration and The functions are roughly the same, and the only difference is that the SPI circuit 220 of the microcontroller 200 is set to work in slave mode. Therefore, the description of the processing circuit 210, the SPI circuit 220 and the bus control circuit 230 can refer to the above-mentioned embodiment of FIG. 2, and will not be described again here.

Specifically, when configuring the SPI system (eg 10), the microcontroller 200 will be controlled to enter an initialization setting mode. In the initialization setting mode, the SPI circuit 220 is set to the slave mode, so that the clock port SCLK, the master-out slave-in port MOSI, and the slave-side selection port SS are set as signal input ports, and the master-in slave-out port Port MISO is set as the signal input port. At this time, the SPI circuit 220 will receive the clock signal CLK through the clock connection port SCLK, the input data signal DINs (ie, the output data signal DOUTm of the SPI master device) will be received through the master output and slave input connection port MOSI, and the chip select signal SEL Will be received through the slave selected port SS. In addition, the output data signal DOUTs of the microcontroller 200 (ie, the input data signal DINm of the SPI master device) will be output through the master-out slave-in port MISO.

After completing the slave mode setting, the SPI circuit 220 will further identify the clock setting request according to one or more of the received clock signal, input data signal and chip select signal in the initialization setting mode, and determine When receiving the clock setting request, an output data signal DOUTs containing clock configuration data is sent, wherein the clock configuration data indicates the clock polarity and clock phase of the SPI circuit 220. This completes the initialization setting of the microcontroller 200. .

More specifically, when configuring the SPI system 10, the working modes of the SPI master device 100 and the SPI slave devices 200_1~200_n need to be set to be consistent, so that the signals between the SPI master device 100 and the SPI slave devices 200_1~200_n follow Sampling and output are performed at the same timing. The working mode can be divided into four different working modes according to the timing configuration and sampling selection of the clock signal CLK, as shown in Figure 4. Figure 4 shows the serial peripheral interface system in different working modes according to an embodiment of the present disclosure. Schematic diagram of clock configuration in mode.

Please refer to Figure 4. The four different working modes (Mode 0~Mode 3) are mainly defined according to clock polarity CPOL and clock phase CPHA.

Looking at the clock polarity CPOL, depending on the level at which the clock signal CLK is maintained in the idle state, the clock polarity CPOL can have two states: maintained at a low level in the idle state (CPOL=0) and idle. It remains at a high level (CPOL=1).

Looking at the clock phase CPHA, depending on the selection of the sampling time point, the clock phase CPHA can have two states, namely sampling at the first edge/odd edge of the clock signal CLK transition (CPHA=0) and at The second edge/even edge of the clock signal CLK transition is sampled (CPHA=1).

Under the above setting combination, four different working modes will be generated, namely: the clock signal CLK is maintained at a low level when idle, and the transmitted data is sampled/latched on the rising edge of the clock signal CLK ( Mode 0 - CPOL=0, CPHA=0); the clock signal CLK is maintained at a low level when idle, and the transmission data is sampled/latched on the falling edge of the clock signal CLK (Mode 1 - CPOL=0, CPHA =1); the clock signal CLK remains at a high level when idle, and the transmitted data is sampled/latched on the falling edge of the clock signal CLK (Mode 3 - CPOL=1, CPHA=0); and the clock signal CLK remains at a high level when idle, and the transmitted data is sampled/latched on the rising edge of the clock signal CLK (Mode 4 - CPOL=1, CPHA=1).

Since the SPI slave devices 200_1~200_n generally only support a single working mode, the SPI master device 100 in the SPI system 10 needs to be set in accordance with the working modes of the SPI slave devices 200_1~200_n, so that the SPI master device 100 and the SPI slave device 200_1 The working mode of ~200_n is consistent.

In this embodiment, through the operation configuration of the above-mentioned microcontrollers 100 and 200 in the initialization setting mode, the SPI master device can actively detect and obtain the clock polarity CPOL and clock phase CPHA of the SPI slave device, and will work Mode is set to be consistent with the SPI slave device. In this way, users no longer need to individually confirm the specifications of the SPI slave device and then manually set the SPI master device, thus avoiding the possibility of human setting errors.

The above embodiments of FIG. 2 and FIG. 3 respectively illustrate the operating configurations of the microcontrollers 100 and 200 in the initialization setting mode from the perspective of the microcontroller 100 as an SPI master device and the microcontroller 200 as an SPI slave device. Figure 5 below further illustrates the above-mentioned initialization setting step flow from the perspective of the overall SPI system. Figure 5 is a step flow chart of the initialization setting method of the serial peripheral interface system according to an embodiment of the present disclosure.

Please refer to Figure 1 and Figure 5 at the same time. When the SPI system enters the initialization setting mode, the SPI master device 100 will send one or more of the preset clock signal, output data signal and chip select signal as a clock setting request (step S110).

When the SPI slave devices 200_1 ~ 200_n receive the signal sent by the SPI master device, the SPI slave device 200_1 ~ 200_n will identify the clock setting request according to the received signal (step S120).

When the SPI slave devices 200_1 ~ 200_n recognize the clock setting request from the received signal, the SPI slave devices 200_1 ~ 200_n will further respond to the clock setting request and send a clock signal including the clock through the master-input-slave-out port MISO. A data signal of configuration data (step S130), wherein the clock configuration data indicates settings of clock phases and clock polarities of the slave devices 200_1~200_n.

When the SPI master device 100 receives the data signal sent by the SPI slave devices 200_1~200_n, the SPI master device 100 will identify the clock configuration data therefrom (step S140), and use the SPI master device 100 according to the identified clock configuration data. Set to match the clock polarity CPOL and clock phase CPHA of the SPI slave devices 200_1 to 200_n (step S150).

In order to explain the above-mentioned initialization setting process of the SPI system 10 in more detail, two different specific implementation examples are listed below for description.

Please refer to FIGS. 6 and 7 . FIG. 6 is an interaction flow chart during initialization of the serial peripheral interface system according to the exemplary embodiment of FIG. 5 , and FIG. 7 is an interactive flow chart of the serial peripheral interface system according to the embodiment of FIG. 6 . Signal timing diagram.

In the SPI system of this embodiment, a one-to-one configuration architecture is used for description, but the disclosure is not limited to this. In addition, the SPI master device 100 of this embodiment is, for example, preset to perform signal transmission in mode 0 (CPOL=0, CPHA=0), so the preset clock signal CLK is low level in the idle state and outputs a data signal. DOUTm is sampled on the rising edge of the preset clock signal CLK. The SPI slave device 200 in this embodiment is configured to perform signal transmission in mode 3 (CPOL=1, CPHA=1) as an example.

First, during initialization setting, the SPI master device 100 sends the preset clock signal CLK and the output data signal DOUTm including the polarity setting request SRPOL to the SPI slave device 200 (step S210m).

The polarity setting request SRPOL may be expressed in a specific data format, such as two-bit data DT1 and DT2. As shown in time frame F1 of FIG. 7 , the two-bit data DT1 and DT2 sent by the SPI master device 100 are, for example, (0x00, 0xFF).

When the SPI slave device 200 receives the output data signal DOUTm sent by the SPI master device 100, the SPI slave device 200 will recognize based on the two-bit data DT1 and DT2 that the signal sent by the SPI master device 100 is a polarity setting request SRPOL ( Step S210s), and in response to the polarity setting request SRPOL, an output data signal DOUTs with a high level H or a low level L is issued to indicate the setting value of the clock polarity CPOL (step S220s).

In this embodiment, since the SPI slave device 200 is configured to operate in mode 3, the SPI slave device 200 will send a high level H indicating that the clock polarity CPOL setting value is 1 to the SPI master device 100 in step S220s. .

In addition, it should be noted that although in the current state, the working modes of the SPI master device 100 and the SPI slave device 200 are different, so that the SPI slave device 200 may have errors in sampling and outputting the received output data signal DOUTm, but because The byte data DT1 and DT2 used to identify the polarity setting request SRPOL have easily identifiable numerical differences. Therefore, even if the SPI slave device 200 samples the received signal at a different time point than the SPI master device 100, it will not cause the SPI slave device 100 to fail. The device 200 cannot recognize the polarity setting request SRPOL.

When the SPI master device 100 receives the output data signal DOUTs sent by the SPI slave device 200, as shown in time frame F2 of FIG. 7, the SPI master device 100 will identify the SPI slave device 200 based on the output data signal DOUTs of the high level H. The set value of clock polarity CPOL is 1 (step S220m). On the other hand, the SPI master device 100 further sends the output data signal DOUTm including the phase setting request SRPHA to the SPI slave device 200 (step S230m).

The phase setting request SRPHA may be expressed in a specific data format that is different from the polarity setting request SRPOL, such as two-bit data DT3 and DT4. As shown in time frame F2 of FIG. 7 , the two-bit tuple data DT3 and DT4 sent by the SPI master device 100 are, for example, (0xFF, 0x00).

When the SPI slave device 200 receives the output data signal DOUTm sent by the SPI master device 100, the SPI slave device 200 will recognize based on the two-bit data DT3 and DT4 that the signal sent by the SPI master device 100 is a phase setting request SRPHA ( Step S230s), and in response to the phase setting request SRPHA, an output data signal DOUTs of high level H or low level L is issued to indicate the setting value of the clock phase CPHA (step S240s).

In this embodiment, since the SPI slave device 200 is configured to operate in mode 3, the SPI slave device 200 will send a high level H indicating that the clock polarity CPOL setting value is 1 to the SPI master device 100 in step S240s. .

Next, when the SPI master device 100 receives the output data signal DOUTs sent by the SPI slave device 200 again, as shown in time frame F3 of FIG. 7 , the SPI master device 100 will identify the SPI based on the output data signal DOUTs of the high level H. The set value of the clock phase CPHA of the slave device 200 is 1 (step S240m). Thereby, the SPI master device 100 can adjust the working mode of the SPI master device 100 from the default mode 0 to mode 3 according to the received clock polarity CPOL and clock phase CPHA information, and complete the initialization setting (step S250m ).

Incidentally, since the SPI master device 100 has completed sending the clock setting request in the initialization setting mode in time frame F3, it can repeatedly send the clock setting request, send redundant data or not send data, as shown in FIG. 7 is shown as an example of sending redundant data, but this disclosure is not limited to this.

In other words, in the example embodiments of FIG. 6 and FIG. 7 , the clock setting request sent by the SPI master device 100 can be divided into a polarity setting request SRPOL and a phase setting request SRPHA. The SPI circuit of the SPI master device 100 sends the output data signal DOUTm with the first data format (DT1=0x00, DT2=0xFF) as the polarity setting request SRPOL in step S210m, and sends the second data with the second data format in step S230m. The output data signal DOUTm in the format (DT3=0xFF, DT4=0x00) is used as the phase setting request SRPHA.

Among them, in order to make the polarity setting request SRPOL and the phase setting request SRPHA easy to identify, this embodiment uses the data DT1 to DT4 with the most significant signal difference as the data format of the identification request. For example, the 16 bits corresponding to the two-bit tuple data DT1 and DT2 in time frame F1 are (0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1 , 1), and the 16 bits corresponding to the two-bit tuple data DT3 and DT4 in time frame F2 are (1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 , 0, 0, 0), this can maximize the bit difference between different setting requests, that is, each bit in the first data format and the second data format is different, so that the SPI slave device 200 The polarity setting request SRPOL and the phase setting request SRPHA can be easily identified.

In the above exemplary embodiment, although the polarity setting request SRPOL and the phase setting request SRPHA are implemented using two-bit tuple data DT1 to DT4 respectively, the present disclosure is not limited thereto. In some embodiments, the polarity setting request SRPOL/phase setting request SRPHA can also be represented by one byte data. For example, the polarity setting request SRPOL can be set to 0x0F (0000_1111), and the phase setting request SRPHA can be set to 0xF0 (1111_0000). In other words, the first data format and the second data format can each be implemented using a data format of at least one byte or more.

In addition, the values used in the above-mentioned two-tuple data DT1 ~ DT4 are only illustrative examples. In practical applications, any value/data format that can be recognized by the SPI slave device 200 can be used as the polarity setting in this embodiment. Request SRPOL and phase setting request SRPHA.

Please refer to FIGS. 8 and 9 . FIG. 8 is an interactive flow chart during initialization of the serial peripheral interface system according to another exemplary embodiment of FIG. 5 , and FIG. 9 is an interactive flow chart of the serial peripheral interface system according to the embodiment of FIG. 8 . Signal timing diagram.

The SPI system in this embodiment is also described using a one-to-one configuration architecture, but the disclosure is not limited to this. In addition, similar to the above exemplary embodiment, the SPI master device 100 of this embodiment is also preset to perform signal transmission in mode 0 (CPOL=0, CPHA=0), and the SPI slave device 200 is configured to perform signal transmission in mode 3 (CPOL =1, CPHA=1) for signal transmission as an example.

First, during initialization setting, the SPI master device 100 sends the preset clock signal CLK and the output data signal DOUTm including the clock setting request SRCLK to the SPI slave device 200 (step S310m).

The clock setting request SRCLK may be expressed in a specific data format, such as two-bit data DT1 and DT2. As shown in time frame F1 of FIG. 9 , the two-bit data DT1 and DT2 sent by the SPI master device 100 are, for example, (0x00, 0xFF).

When the SPI slave device 200 receives the output data signal DOUTm sent by the SPI master device 100, the SPI slave device 200 will recognize based on the two-bit data DT1 and DT2 that the signal sent by the SPI master device 100 is a clock setting request SRCLK ( Step S310s), and in response to the polarity setting request SRPOL, an output data signal DOUTs including the clock configuration data of the SPI slave device 200 is sent to the SPI master device 100 (step S220s).

In this embodiment, the clock configuration data may be a data signal with a specific data format, which may be, for example, two-byte data DT3 and DT4, where the first byte data DT3 and the second byte data DT4 can indicate the setting values of clock polarity CPOL and clock phase CPHA respectively. For example, the first tuple data DT3 is 0x00 to indicate that the clock polarity CPOL is set to 0, and the first tuple data DT3 is 0xFF to indicate that the clock polarity CPOL is set to 1; similarly, the first tuple data DT3 is 0xFF. The two-byte data DT4 is 0x00 to indicate that the clock phase CPHA is set to 0, and the second byte data DT4 is 0xFF to indicate that the clock phase CPHA is set to 1. In other words, in the clock configuration data composed of the two-bit tuple data DT3 and DT4, some of the bits (ie, the first bit of the tuple data DT3) can be identified as the polarity configuration data, while the other part of the bits (ie, the first bit of the tuple data DT3) can be identified as the polarity configuration data. That is, the second byte data DT4) can be identified as phase configuration data.

Thereby, the two-bit data DT3 and DT4 can be used to contain the working mode information of the SPI slave device 200 .

Next, when the SPI master device 100 receives the output data signal DOUTs sent by the SPI slave device 200, as shown in time frame F2 of FIG. 9, the SPI master device 100 will identify the SPI slave device 200 based on the first bit of tuple data DT3. The set value of the clock polarity CPOL is 1, and the set value of the clock phase CPHA of the SPI slave device 200 is identified as 1 based on the second byte data DT4 (step S320m). Therefore, the SPI master device 100 can adjust the working mode of the SPI master device 100 from the default mode 0 to mode 3 according to the received clock polarity CPOL and clock phase CPHA information, and complete the initialization setting (step S330m). .

Incidentally, since the SPI master device 100 has completed sending the clock setting request in the initialization setting mode in time frame F2, it can repeatedly send the clock setting request SRCLK, send redundant data or not send data. FIG. 9 shows an example of repeatedly sending the clock setting request SRCLK represented by byte data DT1 and DT2, but the disclosure is not limited to this.

Compared with the aforementioned embodiments of FIG. 6 and FIG. 7 , this embodiment allows the SPI slave device 200 to return an output data signal including clock polarity and clock phase information at one time, so that the initialization setting process can be Further simplification.

To sum up, the microcontroller and the SPI system using it can enable the SPI master device to actively detect and obtain the clock polarity and clock phase of the SPI slave device during the initialization setting, and automatically work Mode is set to be consistent with the SPI slave device. In this way, users no longer need to individually confirm the specifications of the SPI slave device and then manually set the SPI master device, thus avoiding the possibility of human setting errors.

10:SPI system 100:SPI master/microcontroller 110, 210: Processing circuit 120, 220: SPI circuit 130, 230: Bus control circuit 200, 200_1~200_n: SPI slave device/microcontroller CLK: clock signal CPOL: clock polarity CPHA: clock phase DOUTm, DOUTs: output data signal DINm, DINs: input data signal DT1~DT4: byte data DUMMY: redundant data F1, F2, F3: time frame MOSI: master out and slave in port MISO: master input slave output port SCLK: Clock port SS, SS1~SSn: Slave port selection SEL: chip select signal S110~S150: Steps of initialization setting method of SPI system S210m~S250m, S310m~S330m: Steps of initialization setting method of SPI master device S210s~S240s, S310s~S320s: Steps of initialization setting method of SPI slave device

FIG. 1 is a schematic diagram of a serial peripheral interface system according to an embodiment of the present disclosure; FIG. 2 is a schematic diagram of a microcontroller serving as an SPI master device according to an embodiment of the present disclosure; FIG. 3 is a schematic diagram of a microcontroller serving as an SPI slave device according to an embodiment of the present disclosure; FIG. 4 is a schematic diagram of the clock configuration of the serial peripheral interface system in different operating modes according to an embodiment of the present disclosure; FIG. 5 is a step flow chart of an initialization setting method of the serial peripheral interface system according to an embodiment of the present disclosure; Figure 6 is an interaction flow chart during initialization of the serial peripheral interface system according to the exemplary embodiment of Figure 5; Figure 7 is a signal timing diagram of the serial peripheral interface system according to the embodiment of Figure 6; Figure 8 is an interaction flow chart during initialization of the serial peripheral interface system according to another exemplary embodiment of Figure 5; and FIG. 9 is a signal timing diagram of the serial peripheral interface system according to the embodiment of FIG. 8 .

S110~S150: Steps of initialization setting method of serial peripheral interface system

Claims (10)

A microcontroller, suitable as a master device to communicate with a slave device, the microcontroller includes: a processing circuit; and a serial peripheral interface (Serial Peripheral Interface) circuit coupled to the processing circuit for transmitting data generated by the processing circuit to the slave device, or transmitting data received from the slave device to the processing circuit, Wherein, in an initialization setting mode, the serial peripheral interface circuit sends one or more of a preset clock signal, an output data signal and a chip select signal as a clock setting request, and receives a response to the clock setting request. A clock configuration data, and a clock polarity and a clock phase of the sequence peripheral interface circuit are set according to the clock configuration data. The microcontroller of claim 1, wherein the clock setting request includes a polarity setting request and a phase setting request, and the serial peripheral interface circuit sends the output data signal having a first data format as the polarity setting request, and send the output data signal having a second data format as the phase setting request. The microcontroller as claimed in claim 2, wherein the first data format and the second data format respectively include at least one bit of tuple data, and each bit in the first data format and the second data format is Are not the same. The microcontroller of claim 2, wherein the serial peripheral interface circuit sets the clock polarity based on the clock configuration data responsive to the polarity setting request, and based on the clock configuration data responsive to the phase setting request Set this clock phase. The microcontroller of claim 1, wherein the clock configuration data includes at least one byte of data, and the serial peripheral interface circuit identifies part of the bits of the clock configuration data as a polarity configuration data, and converts the Another part of the clock configuration data is identified as a phase configuration data. The microcontroller of claim 5, wherein the serial peripheral interface circuit sets the clock polarity according to the polarity configuration data, and sets the clock phase according to the phase configuration data. A microcontroller, suitable as a slave device to communicate with a master device, the microcontroller includes: a processing circuit; and a sequence of peripheral interface circuits coupled to the processing circuit for transmitting data received from the host device to the processing circuit, or transmitting data generated by the processing circuit to the host device, Wherein, in an initialization setting mode, the serial peripheral interface circuit recognizes a clock setting request according to one or more of a received preset clock signal, an input data signal and a chip select signal, and responds to the clock setting request. The setup request sends a clock configuration data, The clock configuration data indicates a clock polarity and a clock phase of the sequence peripheral interface circuit. A microcontroller as claimed in claim 7, wherein: When the serial peripheral interface circuit receives the input data signal having a first data format, the serial peripheral interface circuit sends the clock configuration data indicating the clock polarity; and When the serial peripheral interface circuit receives the input data signal having a second data format, the serial peripheral interface circuit sends the clock configuration data indicating the clock phase. The microcontroller of claim 7, wherein when the serial peripheral interface circuit recognizes the clock setting request, the serial peripheral interface circuit sends the clock configuration data including at least one byte of data, wherein the clock Part of the bits in the clock configuration data indicates the clock polarity, and another part of the bits in the clock configuration data indicates the clock phase. A serial peripheral interface system, including: a master device; and at least one slave device coupled to the master device and configured to communicate with the master device through a serial peripheral interface, Wherein, in an initialization setting mode, the master device sends one or more of a preset clock signal, an output data signal and a chip select signal as a clock setting request, wherein the slave device identifies the clock setting request according to the received signal, and sends a clock configuration data indicating a clock phase and a clock polarity of the slave device in response to the clock setting request, Wherein, the master device receives the clock configuration data, and sets the master device to conform to the clock phase and the clock polarity of the slave device according to the clock configuration data.

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