TWI818249B - Deep trench capacitor and method thereof - Google Patents

Abstract

A deep trench capacitor including a substrate, a first electrode, a liner layer, a second electrode, and a dielectric layer is provided. There is a deep trench in the substrate. The first electrode is a continuous structure disposed on a bottom surface of the deep trench, a sidewall of the deep trench, and a top surface of the substrate. The liner layer is disposed between the first electrode and the substrate. The second electrode is disposed on the first electrode. A portion of the second electrode is located in the deep trench. The dielectric layer is disposed between the second electrode and the first electrode.

Description

Deep trench capacitor and manufacturing method thereof

The present invention relates to a capacitor and a manufacturing method thereof, and in particular to a deep trench capacitor and a manufacturing method thereof.

Currently, in the manufacturing process of deep trench capacitors, an ion implantation process is used to dope the substrate to form the lower electrode of the capacitor. However, using the above-mentioned ion implantation process to form the lower electrode will create a depletion area and cause damage or change to the wafer surface lattice structure, thereby reducing the product quality and performance of deep trench capacitors. In addition, the low-angle ion implantation process is prone to uneven implantation at the bottom of the deep trench, resulting in uneven resistance of the lower electrode, thereby reducing the product quality and performance of the deep trench capacitor.

The present invention provides a deep trench capacitor and a manufacturing method thereof, which can effectively improve product quality and performance.

The invention proposes a deep trench capacitor, which includes a substrate, a first electrode, lining layer, second electrode and dielectric layer. Has deep trenches in the base. The first electrode is a continuous structure disposed on the bottom surface of the deep trench, the sidewalls of the deep trench and the top surface of the substrate. The lining layer is disposed between the first electrode and the substrate. The second electrode is disposed on the first electrode. Part of the second electrode is located in the deep trench. The dielectric layer is disposed between the second electrode and the first electrode.

According to an embodiment of the present invention, in the above-mentioned deep trench capacitor, the first electrode can continuously extend from the bottom surface of the deep trench to the sidewalls of the deep trench and the top surface of the substrate, and can cover the entire bottom surface of the deep trench and the top surface of the substrate. Entire side walls.

According to an embodiment of the present invention, in the above-mentioned deep trench capacitor, the material of the first electrode and the material of the second electrode may be doped polycrystalline silicon, metal, conductive metal compound, or a combination thereof.

According to an embodiment of the present invention, in the above-mentioned deep trench capacitor, the doping concentration of the doped polycrystalline silicon is, for example, 1×10 ¹⁶ ions/cm ³ to 1×10 ²¹ ions/cm 3 .

According to an embodiment of the present invention, in the above-mentioned deep trench capacitor, part of the first electrode is not covered by the second electrode.

The invention proposes a manufacturing method of a deep trench capacitor, which includes the following steps. Deep trenches are formed in the substrate. A first electrode is formed on the bottom surface of the deep trench, the sidewalls of the deep trench and the top surface of the substrate. The first electrode is a continuous structure. An inner lining layer is formed between the first electrode and the substrate. A second electrode is formed on the first electrode. Part of the second electrode is located in the deep trench. A dielectric layer is formed between the second electrode and the first electrode.

According to an embodiment of the present invention, in the above deep trench capacitor In the manufacturing method, the method of forming the first electrode, the lining layer, the second electrode and the dielectric layer may include the following steps. A layer of lining material is formed on the substrate. The lining material layer may be located on the bottom surface of the deep trench, the side walls of the deep trench, and the top surface of the substrate. A first electrode material layer is formed on the lining material layer. A layer of dielectric material is formed on the first electrode material layer. A second electrode material layer is formed on the dielectric material layer. The second electrode material layer, the dielectric material layer, the first electrode material layer and the lining material layer are patterned respectively to form the second electrode, the dielectric layer, the first electrode and the lining layer.

According to an embodiment of the present invention, in the above method for manufacturing a deep trench capacitor, the material of the first electrode material layer and the material of the second electrode material layer may be doped polycrystalline silicon, metal, conductive metal compound or other materials. combination.

According to an embodiment of the present invention, the manufacturing method of the deep trench capacitor may further include the following steps. An annealing process is performed on the first electrode material layer made of doped polycrystalline silicon.

According to an embodiment of the present invention, the manufacturing method of the deep trench capacitor may further include the following steps. A tempering process is performed on the second electrode material layer made of doped polycrystalline silicon.

Based on the above, in the deep trench capacitor and the manufacturing method thereof proposed by the present invention, the first electrode is a continuous structure provided on the bottom surface of the deep trench, the sidewalls of the deep trench and the top surface of the substrate. Therefore, the first electrode can replace the electrode formed by doping the substrate using an ion implantation process in the prior art, thereby avoiding the occurrence of depletion areas, damage to the lattice structure of the wafer surface or damage to the wafer surface caused by the above-mentioned ion implantation process. changes and uneven resistance problems, which can effectively improve the product quality and quality of deep trench capacitors. Performance (e.g., component speed).

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings.

10: Deep trench capacitor

100:Base

102: Lining material layer

102a: Inner lining

104,108: Electrode material layer

104a,108a:Electrode

106:Dielectric material layer

106a: Dielectric layer

110,112: Patterned photoresist layer

BS: Bottom

SW: side wall

T: deep trench

TS: top surface

1A to 1E are cross-sectional views of the manufacturing process of a deep trench capacitor according to an embodiment of the present invention.

1A to 1E are cross-sectional views of the manufacturing process of a deep trench capacitor according to an embodiment of the present invention.

Referring to FIG. 1A , a deep trench T is formed in the substrate 100 . The substrate 100 may be a semiconductor substrate, such as a silicon substrate. The number of deep trenches T may be one or more. In this embodiment, although the number of deep trenches is multiple, the invention is not limited thereto. In addition, the formation method of the deep trench T is, for example, patterning the substrate 100 through a photolithography process and an etching process. That is, part of the substrate 100 can be removed through a photolithography process and an etching process to form the deep trench T.

Referring to FIG. 1B , a lining material layer 102 can be formed on the substrate 100 . For example, the layer of lining material 102 may be conformally formed on the substrate 100 . The lining material layer 102 may be located on the bottom surface BS of the deep trench T, the sidewall SW of the deep trench T, and the top surface TS of the substrate 100 . The material of the lining material layer 102 is, for example, an oxide (e.g., oxide silicon) or nitride (e.g., silicon nitride). The formation method of the lining material layer 102 is, for example, thermal oxidation, thermal nitridation or chemical vapor deposition.

Next, an electrode material layer 104 may be formed on the lining material layer 102 . For example, the electrode material layer 104 may be conformally formed on the liner material layer 102 . The material of the electrode material layer 104 may be doped polysilicon, metal, conductive metal compound, or a combination thereof. The doping concentration of doped polycrystalline silicon is, for example, 1×10 ¹⁶ ions/cubic centimeter to 1×10 ²¹ ions/cubic centimeter, depending on the doping elements and requirements. The metal is, for example, tungsten (W), aluminum (Al), copper (Cu) or cobalt (Co). The conductive metal compound is, for example, titanium nitride (TiN), titanium silicide (TiSi ₂ ), cobalt silicide (CoSi ₂ ), nickel silicide (NiSi) or tungsten silicide (WSi ₂ ). The formation method of the electrode material layer 104 is, for example, chemical vapor deposition or physical vapor deposition. In some embodiments, when the material of the electrode material layer 104 is doped polysilicon, a tempering process can be further performed on the electrode material layer 104 of doped polysilicon, thereby releasing stress to prevent the substrate 100 from being bend. In some embodiments, when the material of the electrode material layer 104 is doped polycrystalline silicon, after the electrode material layer 104 is formed, a metal silicide layer (such as a cobalt silicide layer or a nickel silicide layer) may be formed on the electrode material layer 104 ). The metal silicide layer can be formed by a self-aligned silicide (salicide) process. In some embodiments, when the material of the electrode material layer 104 is tungsten, before forming the electrode material layer 104 , a barrier layer (not shown) may be formed on the lining material layer 102 , and then the electrode material layer 104 formed on the barrier layer. The material of the barrier layer is, for example, titanium (Ti), titanium nitride or a combination thereof.

A layer of dielectric material 106 may then be formed on the layer of electrode material 104 . For example, dielectric material layer 106 may be conformally formed on electrode material layer 104 . The material of the dielectric material layer 106 is, for example, an oxide (eg, silicon oxide), a nitride (eg, silicon nitride), a high-k material (eg, hafnium oxide (HfO ₂ ), oxide Titanium (TiO ₂ ), aluminum oxide (Al ₂ O ₃ ) or zirconium oxide (ZrO ₂ )) or combinations thereof. The dielectric material layer 106 is formed by, for example, chemical vapor deposition.

Next, an electrode material layer 108 may be formed on the dielectric material layer 106 . The electrode material layer 108 may fill the deep trench T. The material of the electrode material layer 108 may be doped polysilicon, metal, conductive metal compound, or a combination thereof. The doping concentration of doped polycrystalline silicon is, for example, 1×10 ¹⁶ ions/cubic centimeter to 1×10 ²¹ ions/cubic centimeter, depending on the doping elements and requirements. Metals are, for example, tungsten, aluminum, copper or cobalt. The conductive metal compound is, for example, titanium nitride, titanium silicide, cobalt silicide, nickel silicide or tungsten silicide. The formation method of the electrode material layer 108 is, for example, chemical vapor deposition or physical vapor deposition. In some embodiments, when the material of the electrode material layer 108 is doped polysilicon, a tempering process can be further performed on the electrode material layer 108 of doped polysilicon, thereby releasing stress to prevent the substrate 100 from bending. In some embodiments, when the material of the electrode material layer 108 is doped polycrystalline silicon, after the electrode material layer 108 is formed, a metal silicide layer (such as a cobalt silicide layer or a nickel silicide layer) may be formed on the electrode material layer 108 ). The metal silicide layer can be formed by a self-aligned silicide process. In some embodiments, when the material of the electrode material layer 108 is tungsten, before forming the electrode material layer 108 , a barrier layer (not shown) may be formed on the dielectric material layer 106 , and then the electrode material layer 108 formed on the barrier layer. The material of the barrier layer is, for example, titanium, titanium nitride or a combination thereof.

In addition, the electrode material layer 108 and the electrode material layer 104 may be the same material or different materials. In some embodiments, when the material of the electrode material layer 104 is doped When polycrystalline silicon is used, the material of the electrode material layer 104 may be doped polycrystalline silicon, metal or a conductive metal compound. In some embodiments, when the material of the electrode material layer 104 is a metal or a conductive metal compound, the material of the electrode material layer 104 may be a metal or a conductive metal compound.

Afterwards, a patterned photoresist layer 110 may be formed on the electrode material layer 108 . The patterned photoresist layer 110 may expose part of the electrode material layer 108 . The patterned photoresist layer 110 can be formed by a photolithography process.

Referring to FIG. 1C , the patterned photoresist layer 110 can be used as a mask to remove part of the electrode material layer 108 and part of the dielectric material layer 106 , thereby patterning the electrode material layer 108 and the dielectric material layer 106 respectively. , to form the electrode 108a and the dielectric layer 106a. In some embodiments, electrode 108a may serve as the upper electrode of the capacitor. The method for removing part of the electrode material layer 108 and part of the dielectric material layer 106 is, for example, dry etching.

Next, the patterned photoresist layer 110 is removed. The method for removing the patterned photoresist layer 110 is, for example, dry stripping or wet stripping.

Referring to FIG. 1D, a patterned photoresist layer 112 can be formed on the electrode material layer 104 and the electrode 108a. The patterned photoresist layer 112 may expose part of the electrode material layer 104 . The patterned photoresist layer 112 can be formed by a photolithography process.

Referring to FIG. 1E , the patterned photoresist layer 112 can be used as a mask to remove part of the electrode material layer 104 and part of the lining material layer 102 , thereby patterning the electrode material layer 104 and the lining material layer 102 respectively. , to form the electrode 104a and the lining layer 102a. Part of the electrode 104a is not covered by the electrode 108a, thereby facilitating subsequent In the subsequent process, a contact window for electrically connecting to the electrode 104a is formed. In some embodiments, electrode 104a may serve as the lower electrode of the capacitor. The method for removing part of the electrode material layer 104 and part of the lining material layer 102 is, for example, dry etching.

In addition, through the above method, the electrode 104a can be formed on the bottom surface BS of the deep trench T, the sidewall SW of the deep trench T and the top surface TS of the substrate 100, and the lining layer 102a can be formed between the electrode 104a and the substrate 100. Electrode 108a is formed on electrode 104a, and dielectric layer 106a may be formed between electrode 108a and electrode 104a. The electrode 104a is a continuous structure, that is, the electrode 104a does not have parts that are separated from each other. Part of the electrode 108a is located in the deep trench T.

Next, the patterned photoresist layer 112 is removed. The method for removing the patterned photoresist layer 112 is, for example, a dry stripping method or a wet stripping method.

Hereinafter, the deep trench capacitor 10 of this embodiment will be described with reference to FIG. 1E . In addition, although the method for forming the deep trench capacitor 10 is described by taking the above method as an example, the present invention is not limited thereto.

Referring to FIG. 1E , the deep trench capacitor 10 includes a substrate 100, an electrode 104a, a lining layer 102a, an electrode 108a and a dielectric layer 106a. There is a deep trench T in the substrate 100 . The electrode 104 a is a continuous structure provided on the bottom surface BS of the deep trench T, the sidewall SW of the deep trench T, and the top surface TS of the substrate 100 . For example, the electrode 104a may continuously extend from the bottom surface BS of the deep trench T to the sidewall SW of the deep trench T and the top surface TS of the substrate 100, and may cover the entire bottom surface BS and the entire sidewall SW of the deep trench T. The lining layer 102a is disposed between the electrode 104a and the substrate 100, thereby preventing leakage current. Electrode 108a is provided on electrode 104a. Part of the electrode 108a is located in the deep trench T. In some embodiments, portions of electrode 104a are not covered by electrode 108a. Electrode 108a and electrode 104a may be of the same material or different materials. The material of the electrode 104a and the material of the electrode 108a may respectively be doped polycrystalline silicon, metal, conductive metal compound, or a combination thereof. The doping concentration of doped polycrystalline silicon is, for example, 1×10 ¹⁶ ions/cubic centimeter to 1×10 ²¹ ions/cubic centimeter, depending on the doping elements and requirements. Dielectric layer 106a is disposed between electrode 108a and electrode 104a.

In some embodiments, when the material of the electrode 104a is doped polycrystalline silicon, a metal silicide layer may be further provided on the electrode 104a. In some embodiments, when the material of the electrode 104a is tungsten, a barrier layer (not shown) may be further provided between the electrode 104a and the lining layer 102a. In some embodiments, when the material of the electrode 108a is doped polycrystalline silicon, a metal silicide layer may be further provided on the electrode 108a. In some embodiments, when the material of the electrode 108a is tungsten, a barrier layer (not shown) may be further provided between the electrode 108a and the dielectric layer 106a.

In addition, the materials, formation methods and functions of each component in the deep trench capacitor 10 have been described in detail in the above embodiments and will not be described again.

Based on the above embodiments, it can be seen that in the deep trench capacitor 10 and the manufacturing method thereof, the electrode 104 a is a continuous structure provided on the bottom surface BS of the deep trench T, the sidewall SW of the deep trench T and the top surface TS of the substrate 100 . Therefore, the electrode 104a can replace the electrode formed by doping the substrate using an ion implantation process in the prior art, thereby avoiding the depletion region and damage or change of the wafer surface lattice structure caused by the above ion implantation process. As well as the problem of uneven resistance values, the product quality and performance (such as component speed) of the deep trench capacitor 10 can be effectively improved.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.

10: Deep trench capacitor

100:Base

102a: Inner lining

104a,108a:Electrode

106a: Dielectric layer

BS: Bottom

SW: side wall

T: deep trench

TS: top surface

Claims (10)

A deep trench capacitor, including: a substrate having a deep trench in the substrate; a first electrode, wherein the first electrode is disposed on the bottom surface of the deep trench, the sidewall of the deep trench and the substrate a continuous structure on the top surface of the in a deep trench; and a dielectric layer disposed between the second electrode and the first electrode, wherein the lowest electrode among all electrodes of the deep trench capacitor is the first electrode. The deep trench capacitor of claim 1, wherein the first electrode continuously extends from the bottom surface of the deep trench to the sidewalls of the deep trench and the top surface of the substrate, and covers the The entire bottom surface and the entire side walls. The deep trench capacitor according to claim 1, wherein the material of the first electrode and the material of the second electrode respectively include doped polycrystalline silicon, metal, conductive metal compound or a combination thereof. The deep trench capacitor according to claim 3, wherein the doping concentration of the doped polycrystalline silicon is 1×10 ¹⁶ ions/cubic centimeter to 1×10 ²¹ ions/cubic centimeter. The deep trench capacitor of claim 1, wherein part of the first electrode is not covered by the second electrode. A method of manufacturing a deep trench capacitor, including: Forming a deep trench in the substrate; forming a first electrode on the bottom surface of the deep trench, the sidewalls of the deep trench, and the top surface of the substrate, wherein the first electrode is a continuous structure; on the first electrode forming a lining layer between the substrate and the first electrode; forming a second electrode on the first electrode, with part of the second electrode located in the deep trench; and between the second electrode and the first electrode. A dielectric layer is formed between the electrodes, wherein the lowest electrode among all the electrodes of the deep trench capacitor is the first electrode. The method of manufacturing a deep trench capacitor according to claim 6, wherein the method of forming the first electrode, the lining layer, the second electrode and the dielectric layer includes: forming on the substrate Lining material layer, wherein the lining material layer is located on the bottom surface of the deep trench, the sidewalls of the deep trench and the top surface of the substrate; forming a first electrode material layer on the lining material layer ; forming a dielectric material layer on the first electrode material layer; forming a second electrode material layer on the dielectric material layer; and respectively forming the second electrode material layer, the dielectric material layer, and the The first electrode material layer and the lining material layer are patterned to form the second electrode, the dielectric layer, the first electrode and the lining layer. The method of manufacturing a deep trench capacitor according to claim 7, wherein the material of the first electrode material layer and the material of the second electrode material layer respectively include doped polycrystalline silicon, metal, conductive metal compound or a combination thereof. The method of manufacturing a deep trench capacitor according to claim 8 further includes: performing a tempering process on the first electrode material layer made of the doped polysilicon. The method of manufacturing a deep trench capacitor according to claim 8 further includes: performing a tempering process on the second electrode material layer made of the doped polysilicon.

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