TWI816541B - Gate driver - Google Patents

Abstract

A gate driving circuit is provided. The gate driver includes a plurality of gate driver circuits. The gate driving circuits are used to provide a plurality of gate signals to a pixel array, and respectively include a main driving block and a secondary driving block. The main driving block is used for setting the corresponding gate signal as a writing voltage level in a corresponding enabling period of an active region period of a frame period. The secondary driving block is used for setting the corresponding gate signal as the writing voltage level during a writing black period of a blanking period of the frame period, and setting the corresponding gate signal as a discharge voltage level during a discharging period of the blanking period, wherein the discharge period is after the write black period.

Description

gate driver

The present invention relates to a driver, and in particular to a gate driver.

With the advancement of semiconductor technology, the size of display panels is getting larger and larger, and the resolution of display panels is getting higher and higher. As the resolution of display panels continues to improve, the application of resolution conversion has been proposed to correspond to display images with different aspect ratios. In some applications, some areas of the display panel are not areas for displaying images, so pure black images (or colors) need to be written to create an overall display environment.

When writing black on some display panels, the corresponding gate signal will be enabled at the same time to turn on the corresponding pixel, and the gate driver will be turned off, causing the gate line to appear in a floating state. However, when the gate line is in a floating state, the charges on the gate line are released through coupling very slowly, so that the voltage on the gate line causes the transistor in the pixel to suffer stress. effect), which reflects the operation of the display panel.

The present invention provides a gate driver that can quickly release the charge of the gate lines in the black area on the display panel to avoid the stress effect on the transistors of the pixels in the black area on the panel.

The gate driver of the present invention includes a plurality of gate driving circuits. These gate driving circuits are used to provide multiple gate signals to the pixel array, and include primary driving blocks and secondary driving blocks respectively. The main driving block is used to set the corresponding gate signal to the write voltage level in the corresponding enable period of the active region period of the frame period. The secondary driving block is used to set the corresponding gate signal to the write voltage level during the write black period of the blank period of the picture period, and to set the corresponding gate signal to the discharge voltage level during the discharge period of the blank period, wherein The discharge period follows the black write period.

Based on the above, in the gate driver of the embodiment of the present invention, the secondary driving block sets the corresponding gate signal to the write voltage level during the write black period of the blank period of the picture period, and sets the corresponding gate signal during the discharge period of the blank period. The gate signal is the discharge voltage level. Thereby, the gate driving circuit can quickly release the charges of the gate lines of the pixels on the display panel that are not displaying images, so as to prevent the transistors of the pixels that are not displaying images on the display panel from suffering stress effects.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings.

100, 200, 300, 400, 500, 600, CTG, CTGa: gate drive circuit

110: Main drive block

120, 220, 320, 420, 520, 620: Secondary drive block

BW: black writing period

C1: Capacitor

Data: display data

DCH: During discharge

DLE: data line

G(n), G(n-4), SG: gate signal

GCG1~GCG6, GCG1a~GCG6a: Gate drive circuit group

GDR, GDRa: gate driver

GLE: gate line

HCn: clock signal

LC1, LC2: low frequency clock signal

P(n), K(n): control signal

P_ACT: active area period

P_BLK: blank period

PD: period of disablement

PE: enabling period

PX: pixel

PXA: pixel array

Q(n): control voltage

ST(n-4), ST(n), ST(n+4): drive signal

T1~T18: transistor

TB1, TB1a: first blank transistor

TB2: The second blank transistor

TB3: The third blank transistor

TB4, TB4a: fourth blank transistor

TB5: The fifth blank transistor

TB6: The sixth blank transistor

Vcom: common voltage

VGH: gate high voltage

VSS: gate low voltage

XOFF: discharge control signal

XON(D), XON(D)-1~XON(D)-6: first write control signal

XON(G): second write control signal

XON, XON1~XON6: write control signal

FIG. 1A is a schematic circuit diagram of a gate driving circuit according to the first embodiment of the present invention.

FIG. 1B is a schematic diagram of the operation waveform of the gate driving circuit according to the first embodiment of the present invention.

FIG. 2 is a circuit schematic diagram of a gate driving circuit according to a second embodiment of the present invention.

FIG. 3A is a circuit schematic diagram of a gate driving circuit according to a third embodiment of the present invention.

FIG. 3B is a schematic diagram of the operation waveform of the gate driving circuit according to the third embodiment of the present invention.

FIG. 4A is a schematic circuit diagram of a gate driving circuit according to a fourth embodiment of the present invention.

FIG. 4B is a schematic diagram of the operation waveform of the gate driving circuit according to the fourth embodiment of the present invention.

FIG. 5 is a circuit schematic diagram of a gate driving circuit according to the fifth embodiment of the present invention.

FIG. 6A is a circuit schematic diagram of a gate driving circuit according to the sixth embodiment of the present invention.

FIG. 6B is a schematic diagram of the operation waveform of the gate driving circuit according to the sixth embodiment of the present invention.

FIG. 7 is a schematic diagram of a system in which a gate driver is coupled to a pixel array according to an embodiment of the present invention.

FIG. 8 is a schematic diagram of a system in which a gate driver is coupled to a pixel array according to another embodiment of the present invention.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be construed to have meanings consistent with their meanings in the context of the relevant technology and the present invention, and are not to be construed as idealistic or excessive Formal meaning, unless expressly defined as such herein.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or sections or parts thereof shall not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element", "component", "region", "layer" or "section" discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms including "at least one" unless the content clearly dictates otherwise. "or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It should also be understood that when in this specification When used, the terms "comprises" and/or "including" designate the presence of stated features, regions, integers, steps, operations, elements and/or components but do not exclude one or more other features, regions integers, steps, operations , elements, parts and/or combinations thereof.

FIG. 1A is a schematic circuit diagram of a gate driving circuit according to the first embodiment of the present invention. Referring to FIG. 1A , in the embodiment of the present invention, multiple gate driving circuits 100 can be connected in series to form a gate driver (gate driver GDR shown in FIG. 7 or gate driver GDRa shown in FIG. 8 ), and These gate driving circuits 100 provide a plurality of gate signals G(n) (or gate signals SG as shown in Figure 7 or Figure 8) to the pixel array (the pixel array PXA as shown in Figure 7 or Figure 8) .

In this embodiment, the gate driving circuit 100 at least includes a primary driving block 110 and a secondary driving block 120 . The main driving block 110 is used to set the corresponding gate signal G(n) to the write voltage level in the corresponding enable period of the active region period of one picture period. The secondary driving block 120 is used to set the corresponding gate signal G(n) to the write voltage level during the write black period of the blank period of the picture period, and to set the corresponding gate signal G(n) during the discharge period of the blank period. n) is the discharge voltage level. Among them, the active area period mainly corresponds to the time for writing to the pixels of the display image, the blank period mainly corresponds to the time for writing to the pixels of the non-display image (that is, displaying black), and the discharge period is located after the black writing period. The above timing sequence can be referred to that shown in FIG. 1B and will be described later. Thereby, the gate driving circuit 100 can quickly release the charges of the gate lines of the pixels on the display panel that are not displaying images, so as to prevent the transistors of the pixels that are not displaying images on the display panel from suffering stress effects.

In the embodiment of the present invention, the blank period is different from the conventional vertical blank period. period, and the blank period may be connected to the vertical blank period or may be separated from the vertical blank period. The embodiment of the present invention is not limited to this.

In this embodiment, the main driving block 110 includes transistors T1 to T18 and a capacitor C1, where the transistors T1 to T18 are N-type transistors as an example. The first end of the transistor T1 receives the gate signal G(n-4) (that is, the gate signal of the previous (or earlier) 4 levels (or 4) horizontal lines (or gate lines)), and the transistor T1 The control end receives the drive signal ST(n-4) (that is, the drive signal of the previous (or earlier) 4 levels (or 4) horizontal lines (or gate lines)), and the second end of the transistor T1 provides control Voltage Q(n). Among them, n is a positive integer.

The first terminal of the transistor T2 receives the clock signal HCn, the control terminal of the transistor T2 receives the control voltage Q(n), and the second terminal of the transistor T2 provides the corresponding driving signal ST(n). The first terminal of the transistor T3 (that is, the driving transistor) receives the clock signal HCn, the control terminal of the transistor T3 receives the control voltage Q(n), and the second terminal of the transistor T3 provides the corresponding gate signal G(n). ).

The first terminal of the transistor T4 receives the low-frequency clock signal LC1, and the control terminal of the transistor T4 receives the low-frequency clock signal LC1. The first terminal of the transistor T5 is coupled to the second terminal of the transistor T4, the control terminal of the transistor T5 receives the control voltage Q(n), and the second terminal of the transistor T5 receives the gate low voltage VSS. The first terminal of the transistor T6 receives the low-frequency clock signal LC1. The control terminal of the transistor T6 is coupled to the second terminal of the transistor T4. The second terminal of the transistor T6 provides the control signal P(n). The first terminal of the transistor T7 is coupled to the second terminal of the transistor T6, the control terminal of the transistor T7 receives the control voltage Q(n), and the second terminal of the transistor T7 receives the gate low voltage VSS.

The capacitor C1 is coupled between the control voltage Q(n) and the corresponding gate signal G(n). The first terminal of the transistor T8 receives the corresponding gate signal G(n), the control terminal of the transistor T8 receives the control signal P(n), and the second terminal of the transistor T8 receives the gate low voltage VSS. The first terminal of the transistor T9 receives the control voltage Q(n), the control terminal of the transistor T9 receives the control signal P(n), and the second terminal of the transistor T9 receives the gate low voltage VSS. The first terminal of the transistor T10 receives the corresponding driving signal ST(n), the control terminal of the transistor T10 receives the control signal P(n), and the second terminal of the transistor T10 receives the gate low voltage VSS.

The first terminal of the transistor T11 receives the low-frequency clock signal LC2, and the control terminal of the transistor T11 receives the low-frequency clock signal LC2, where the low-frequency clock signal LC2 is inverted to the low-frequency clock signal LC1. The first terminal of the transistor T12 is coupled to the second terminal of the transistor T11, the control terminal of the transistor T12 receives the control voltage Q(n), and the second terminal of the transistor T12 receives the gate low voltage VSS. The first terminal of the transistor T13 receives the low-frequency clock signal LC2, the control terminal of the transistor T13 is coupled to the second terminal of the transistor T11, and the second terminal of the transistor T13 provides the control signal K(n). The first terminal of the transistor T14 is coupled to the second terminal of the transistor T13, the control terminal of the transistor T14 receives the control voltage Q(n), and the second terminal of the transistor T14 receives the gate low voltage VSS.

The first terminal of the transistor T15 receives the corresponding gate signal G(n), the control terminal of the transistor T15 receives the control signal K(n), and the second terminal of the transistor T15 receives the gate low voltage VSS. The first terminal of the transistor T16 receives the control voltage Q(n), the control terminal of the transistor T16 receives the control signal K(n), and the second terminal of the transistor T16 receives the gate low voltage VSS. The first terminal of the transistor T17 receives the corresponding driving signal ST(n), and the transistor T17 The control terminal of T17 receives the control signal K(n), and the second terminal of the transistor T17 receives the gate low voltage VSS. The first terminal of the transistor T18 receives the control voltage Q(n), and the control terminal of the transistor T18 receives the driving signal ST(n+4) (that is, 4 levels (or 4) horizontal lines later (or later)). Or the drive signal of the gate line), the second terminal of the transistor T18 receives the gate low voltage VSS.

In this embodiment, the secondary driving block 120 includes a first blank transistor TB1 and a second blank transistor TB2. The first blank transistor TB1 has a first terminal for receiving the write control signal XON, a control terminal for receiving the write control signal XON, and a second terminal coupled to the corresponding gate signal G(n). The second blank transistor TB2 has a first terminal coupled to the corresponding gate signal G(n), a control terminal receiving the discharge control signal XOFF, and receiving the discharge voltage level (here, the gate low voltage VSS is taken as an example). the second end.

FIG. 1B is a schematic diagram of the operation waveform of the gate driving circuit according to the first embodiment of the present invention. Please refer to FIG. 1A and FIG. 1B . In this embodiment, one picture period includes at least an active area period P_ACT and a blank period P_BLK. Among them, the time length of the active area period P_ACT is adjusted in response to the number of horizontal lines in the display image of the pixel array (pixel array PXA as shown in Figure 7 or Figure 8), and the time of the active area period P_ACT and the blank period P_BLK The sum of the lengths reflects the total number of horizontal lines of the pixel array (pixel array PXA shown in FIG. 7 or FIG. 8 ).

The main driving block 110 sets the corresponding gate signal G(n) to the write voltage level (for example, the gate high voltage VGH) in the corresponding enable period of the active region period P_ACT, so as to set the corresponding gate signal G(n) in the display data Data. The pixel voltage is written to the pixel (such as in the pixel PX) shown in Figure 7 or Figure 8. In the active region period P_ACT, the write control signal XON and the discharge control signal XOFF are both the gate low voltage VSS, that is, the secondary driving block 120 is turned off (has no effect).

During the blank period P_BLK, the display data Data is set to the common voltage Vcom (which can be regarded as the lowest brightness gray-scale voltage, or the 0th gray-scale voltage) to convert the corresponding pixel (pixel PX as shown in Figure 7 or Figure 8 ) is set to black. Moreover, the write control signal XON and the discharge control signal XOFF are respectively enabled during the write black period BW and the discharge period DCH, that is, the first blank transistor TB1 is turned on during the write black period BW, and the second blank transistor TB2 is turned on during the discharge period. DCH, where the discharge period DCH is located after the black write period BW, and the time lengths of the black write period BW and the discharge period DCH can be determined according to circuit requirements.

The first terminal of the first blank transistor TB1 receives the write control signal XON which is the write voltage level (ie, the gate high voltage VGH) during the write black period BW. The first terminal of the first blank transistor TB1 During the discharge period, the DCH receives the write control signal XON which is the discharge voltage level (that is, the gate low voltage VSS). In other words, the secondary driving block 120 sets the corresponding gate signal G(n) to the write voltage level (ie, the gate high voltage VGH) during the write black period BW of the blank period P_BLK, and during the discharge of the blank period P_BLK During this period, DCH sets the corresponding gate signal G(n) to the discharge voltage level (that is, the gate low voltage VSS).

FIG. 2 is a circuit schematic diagram of a gate driving circuit according to a second embodiment of the present invention. Referring to FIG. 1A and FIG. 2 , the gate driving circuit 200 is substantially the same as the gate driving circuit 100 , except that the first blank transistor of the secondary driving block 220 TB1a, where the same or similar numbers are used for the same or similar elements. In this embodiment, the first blank transistor TB1a has a first terminal that receives the write voltage level (ie, the gate high voltage VGH), a control terminal that receives the write control signal XON, and is coupled to the corresponding gate. The second terminal of signal G(n).

FIG. 3A is a circuit schematic diagram of a gate driving circuit according to a third embodiment of the present invention. Please refer to FIG. 1A and FIG. 3A. The gate driving circuit 300 is substantially the same as the gate driving circuit 100. The difference is that the secondary driving block 320 only includes the third blank transistor TB3, in which the same or similar components use the same or similar components. Similar labels. In this embodiment, the third blank transistor TB3 has a first terminal that receives the first write control signal XON(D), a control terminal that receives the second write control signal XON(G), and is coupled to the corresponding gate. The second terminal of the pole signal G(n).

FIG. 3B is a schematic diagram of the operation waveform of the gate driving circuit according to the third embodiment of the present invention. Please refer to FIG. 1B, FIG. 3A and FIG. 3B. In this embodiment, the second write control signal XON(G) is enabled during the blank period P_BLK, and the first write control signal XON(D) is enabled during the write black period. BW is the write voltage level (ie, gate high voltage VGH) and DCH is the discharge voltage level (ie, gate low voltage VSS) during the discharge period.

FIG. 4A is a schematic circuit diagram of a gate driving circuit according to a fourth embodiment of the present invention. Referring to FIG. 1A and FIG. 4A , the gate driving circuit 400 is substantially the same as the gate driving circuit 100 , except for the secondary driving block 420 . In this embodiment, the secondary driving block 420 includes a fourth blank transistor TB4 and a fifth blank transistor TB5. The fourth blank transistor TB4 has a fourth blank transistor TB4 that receives the write control signal XON. One end, a control end receiving the write control signal XON, and a second end coupled to the control end of the transistor T3. The fifth blank transistor TB5 has a first terminal coupled to the control terminal of the transistor T3, a control terminal receiving the discharge control signal XOFF, and a second terminal receiving the discharge voltage level (ie, gate low voltage VSS).

In this embodiment, the fourth blank transistor TB4 is only used to control the transistor T3, that is, it does not need a large driving capability, so the circuit area of the transistor can be reduced. However, the circuit area of the first blank transistor TB1 will be approximately equal to the circuit area of the transistor T3 to have sufficient driving capability to drive the corresponding gate signal G(n).

FIG. 4B is a schematic diagram of the operation waveform of the gate driving circuit according to the fourth embodiment of the present invention. Please refer to Figure 1A, Figure 1B, Figure 4A and Figure 4B, in which the write control signal XON and the discharge control signal XOFF are respectively enabled during the write black period BW and the discharge period DCH, and in the blank period P_BLK, the clock signal HCn The enable period PE corresponds to the write black period BW, and the disable period PD of the clock signal HCn corresponds to the discharge period DCH. Among them, the time lengths of the write black period BW, the discharge period DCH, the enable period PE and the disable period PD can be determined according to circuit requirements.

FIG. 5 is a circuit schematic diagram of a gate driving circuit according to the fifth embodiment of the present invention. Please refer to FIG. 4A and FIG. 5 . The gate driving circuit 500 is substantially the same as the gate driving circuit 400 . The difference lies in the fourth blank transistor TB4 a of the secondary driving block 520 , in which the same or similar components are used. Label. In this embodiment, the fourth blank transistor TB4a has a first terminal that receives the write voltage level (ie, the gate high voltage VGH), a control terminal that receives the write control signal XON, and a first terminal that is coupled to the transistor T3. The second end of the control end.

FIG. 6A is a circuit schematic diagram of a gate driving circuit according to the sixth embodiment of the present invention. Please refer to FIG. 1A and FIG. 6A. The gate driving circuit 600 is substantially the same as the gate driving circuit 100. The difference is that the secondary driving block 620 only includes the sixth blank transistor TB6, in which the same or similar components use the same or similar components. Similar labels. In this embodiment, the sixth blank transistor TB6 has a first terminal that receives the first write control signal XON(D), a control terminal that receives the second write control signal XON(G), and a coupling transistor T3 The second end of the control end.

FIG. 6B is a schematic diagram of the operation waveform of the gate driving circuit according to the sixth embodiment of the present invention. Referring to FIG. 3A, FIG. 3B, FIG. 6A and FIG. 6B, the second write control signal XON(G) is enabled in the blank period P_BLK, and the first write control signal XON(D) is enabled in the write black period BW. The writing voltage level (ie, the gate high voltage VGH) is the discharge voltage level (ie, the gate low voltage VSS) during the discharge period DCH. Furthermore, in the blank period P_BLK, the enable period PE of the clock signal HCn corresponds to the write black period BW, and the disable period PD of the clock signal HCn corresponds to the discharge period DCH. Among them, the time lengths of the write black period BW, the discharge period DCH, the enable period PE and the disable period PD can be determined according to circuit requirements.

FIG. 7 is a schematic diagram of a system in which a gate driver is coupled to a pixel array according to an embodiment of the present invention. Please refer to FIGS. 1A, 2, 4A, 5 and 7. In this embodiment, the gate driver GDR includes a plurality of gate drive circuits CTG, and the gate drive circuit CTG may be a gate drive circuit 100, One of the gate driving circuit 200, the gate driving circuit 400, and the gate driving circuit 500. Moreover, the gate drive circuit CTG is divided into multiple gate drive circuit groups GCG1~GCG6, each of which Each gate drive circuit group GCG1 ~ GCG6 receives a corresponding one of the write control signals XON1 ~ XON6, and these gate drive circuit groups GCG1 ~ GCG6 jointly receive the discharge control signal XOFF.

The gate driving circuit CTG provides multiple gate signals SG to the pixel array PXA. The pixels PX in the pixel array PXA are coupled to the corresponding data lines DLE to receive the corresponding display data Data and are coupled to the corresponding gate lines GLE. to receive the corresponding gate signal SG.

FIG. 8 is a schematic diagram of a system in which a gate driver is coupled to a pixel array according to another embodiment of the present invention. Please refer to FIG. 3A, FIG. 6A and FIG. 8. In this embodiment, the gate driver GDRa includes a plurality of gate drive circuits CTGa, and the gate drive circuit CTGa can be one of the gate drive circuits 300 and 600. one of them. Moreover, the gate driving circuit CTGa is divided into a plurality of gate driving circuit groups GCG1a~GCG6a, wherein each gate driving circuit group GCG1a~GCG6a receives the first write control signal XON(D)-1~XON(D) Corresponding to one of -6, these gate drive circuit groups GCG1a~GCG6a jointly receive the second write control signal XON(G).

The gate driving circuit CTG provides multiple gate signals SG to the pixel array PXA. The pixels PX in the pixel array PXA are coupled to the corresponding data lines DLE to receive the corresponding display data Data and are coupled to the corresponding gate lines GLE. to receive the corresponding gate signal SG.

To sum up, in the gate driver according to the embodiment of the present invention, the secondary driving block sets the corresponding gate signal to the writing voltage during the writing black period of the blank period of the picture period. voltage level, and set the corresponding gate signal to the discharge voltage level during the discharge period of the blank period. Thereby, the gate driving circuit can quickly release the charges of the gate lines of the pixels on the display panel that are not displaying images, so as to prevent the transistors of the pixels that are not displaying images on the display panel from suffering stress effects.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.

100: Gate drive circuit

110: Main drive block

120: Secondary drive block

C1: Capacitor

G(n), G(n-4): gate signal

HCn: clock signal

LC1, LC2: low frequency clock signal

P(n), K(n): control signal

Q(n): control voltage

ST(n-4), ST(n), ST(n+4): drive signal

T1~T18: transistor

TB1: The first blank transistor

TB2: The second blank transistor

VSS: gate low voltage

XOFF: discharge control signal

XON: write control signal

Claims (13)

A gate driver includes: a plurality of gate driving circuits for providing a plurality of gate signals to a pixel array, and each includes: a main driving block for driving during an active area during a picture period. The corresponding gate signal is set to a writing voltage level in the corresponding enable period; and the primary driving block is used to set the corresponding gate signal to a writing black period in a blank period of the picture period. A voltage level is written, and the corresponding gate signal is set to a discharge voltage level during a discharge period of the blank period, wherein the discharge period is located after the write black period. The gate driver of claim 1, wherein the secondary driving block includes: a first blank transistor having a first terminal that receives the write voltage level, and a control that receives a write control signal. terminal, and a second terminal coupled to the corresponding gate signal; and a second blank transistor having a first terminal coupled to the corresponding gate signal, a control terminal receiving a discharge control signal, and receiving the second end of the discharge voltage level; wherein the write control signal and the discharge control signal are respectively enabled during the write black period and the discharge period. The gate driver of claim 2, wherein the first terminal of the first blank transistor receives the write control signal to receive the write control signal at the write voltage level. The gate driver of claim 2, wherein the gate drive circuits are divided into a plurality of gate drive circuit groups, wherein each of the gate drive circuit groups receives the corresponding write control signal, and the Some gate driving circuit groups jointly receive the discharge control signal. The gate driver of claim 1, wherein the secondary driving block includes: a third blank transistor having a first terminal for receiving a first write control signal and a second write control signal. A control end, and a second end coupled to the corresponding gate signal; wherein the first write control signal is the write voltage level during the write black period, and is the discharge during the discharge period A voltage level where the second write control signal is enabled during the blank period. The gate driver of claim 5, wherein the gate driving circuits are divided into a plurality of gate driving circuit groups, wherein each of the gate driving circuit groups receives the corresponding first write control signal, And the gate driving circuit groups jointly receive the second write control signal. The gate driver as claimed in claim 1, wherein the main driving block includes: A driving transistor has a first terminal that receives a clock signal, a control terminal that receives a control voltage, and a second terminal that is coupled to a corresponding gate signal. The gate driver of claim 7, wherein the secondary driving block includes: a fourth blank transistor having a first terminal for receiving the write voltage level, and a control for receiving a write control signal. terminal, and a second terminal coupled to the control terminal of the driving transistor; and a fifth blank transistor having a first terminal coupled to the control terminal of the driving transistor, a control receiving a discharge control signal terminal, and the second terminal receiving the discharge voltage level; wherein the write control signal and the discharge control signal are respectively enabled during the write black period and the discharge period. The gate driver of claim 8, wherein the first terminal of the fourth blank transistor receives the write control signal to receive the write control signal at the write voltage level. The gate driver of claim 8, wherein the gate drive circuits are divided into a plurality of gate drive circuit groups, wherein each of the gate drive circuit groups receives the corresponding write control signal, and the Some gate driving circuit groups jointly receive the discharge control signal. The gate driver as claimed in claim 7, wherein the secondary driving block includes: A sixth blank transistor has a first terminal for receiving a first write control signal, a control terminal for receiving a second write control signal, and a second terminal coupled to the control terminal of the driving transistor. ; wherein the first write control signal is at the write voltage level during the write black period, and is at the discharge voltage level during the discharge period, and wherein the second write control signal is at the blank period Enable. The gate driver of claim 11, wherein the gate driving circuits are divided into a plurality of gate driving circuit groups, wherein each of the gate driving circuit groups receives the corresponding first write control signal, And the gate driving circuit groups jointly receive the second write control signal. The gate driver of claim 1, wherein the active area period is adjusted to reflect the number of horizontal lines of a display image of the pixel array, and the sum of the active area period and the blank period reflects the pixel array The total number of multiple horizontal lines.

Images