TWI814511B - Cascading system and method having improved synchronization mechanism of devices - Google Patents

Abstract

A cascading system and method having an improved synchronization mechanism of devices are provided. The devices are connected in series to form the cascading system. Each of the devices determines its position arranged in the devices, according to the number of consecutive same voltage levels that appear later than a head in the received data input signal. Each of the devices calculates a time within which the devices are synchronized with each other according to its position arranged in the devices. Each of the devices obtains its individual device data from the received data input signal. Each of the devices converts all of voltage levels of data of the received data input signal that correspond to the obtained individual device data into same voltage levels so as to generate a data output signal, and then outputs the data output signal to a next one of the devices.

Description

Device serial connection system and method with improved synchronization mechanism

The present invention relates to a data transmission system, and in particular to a device serial connection system and method with an improved synchronization mechanism that can still synchronize multiple devices while saving signal lines.

As shown in Figure 6, in the traditional device serial connection system, multiple devices IC1~ICm are connected in sequence. Each device IC1~ICm uses the clock signal CLK, the synchronization signal Sync, the source data signal DI, and the data output signal. DO1~DOm to transfer data and synchronize. When all devices IC1 ~ ICm have synchronization action requirements, multiple devices IC1 ~ ICm are synchronized by transmitting a synchronization signal Sync to all devices IC1 ~ ICm.

In applications such as driving light emitting diodes (LEDs), the data transmitted between multiple devices IC1 ~ ICm includes command data and individual device data of each device IC1 ~ ICm. When transmitting command data between multiple devices IC1 ~ ICm, each device IC1 ~ ICm needs to transmit individual q bits of command data, so multiple devices IC1 ~ ICm need to transmit a total of m×q bits of command data. . In an application where each device IC1~ICm receives the same command data, (m-1)×q bits of bandwidth will be wasted.

The technical problem to be solved by the present invention is that after reducing the synchronization signal Sync, To solve the problem of synchronization, a device serial connection system with an improved synchronization mechanism is provided, including multiple devices. Each device has a data input terminal for receiving a data input signal, a data output terminal for outputting a data output signal, and a clock signal terminal for receiving a clock signal. Multiple devices are connected in series. The clock signal terminal of each device is coupled to the clock signal. The data input terminal of the first device among the plurality of devices is coupled to the source data signal and serves as the data input signal of the first device. The data input terminals of the other devices are coupled to the data output terminals of the upper-level device to receive the data output signals of the upper-level device. The data output signal of each device is the data input signal of the next-level device. The source data signal includes a header and multiple individual device data for multiple devices. Each device determines its arrangement position among multiple devices based on the number of consecutive identical voltage levels after the header in the data input signal it receives. Each device calculates the synchronization time with other devices based on its sorted position among multiple devices. Each device converts all the data at the individual device data locations of the corresponding device into the same voltage level based on the data input signal it receives, and then outputs the data output signal to the next-level device.

In the embodiment, each device performs synchronization when the number of T clock signals reaches T after the header confirmation of the data input signal it receives, where T is calculated by the equation T=f-p×h, that is, all devices will synchronize at the same time. Synchronization is performed at the Sth clock cycle of the pulse signal, where S is calculated by the following equation: S=d+p×r+(f-p×h), where p represents the time point from which the data output signal of each device is output to the next-level device. The number of clock cycles of the equivalent clock signal that is a delay time between the time points of the data output signal output, r represents the number of delay times of the data output signal of each device compared to the data output signal of the first device, f represents a preset clock cycle number of the clock signal, h represents the order in which each device is sorted in multiple devices, and d represents the clock cycle number of the header. The number of clock cycles of the equivalent clock signal of the delay time can be a multiple of 0.5, for example, the delay time is equal to 0.5 or 1 or 1.5 clock cycles. for For convenience, when the duty cycle of the clock signal is not 50%, 0.5 clock cycles are used to represent 1 high level time or 1 low level time, 1 high level time plus 1 low level time It is 1 clock cycle.

In the embodiment, when each device determines that the number of consecutive first voltage levels or multiple second voltage levels in the received data input signal is equal to or greater than the threshold value, it determines that the number of consecutive occurrences in the received data input signal is header and confirm the header's position in this data input signal.

In the embodiment, the data input signal received by each device uses a combination of a plurality of first voltage levels and a plurality of second voltage levels to represent a header, and each device determines that the data input signal received When combining, it is determined that the header appears in the data input signal, and the position of the header in the data input signal is confirmed.

In an embodiment, the data input signal received by each device further includes common command data of multiple devices.

In the embodiment, the number of bits of individual device data is n bits, and each device determines its arrangement position among multiple devices based on the quotient of the number of consecutive identical voltage levels after the header divided by n.

In an embodiment, each device further has a clock output terminal for outputting the next clock signal to the clock signal terminal of the next-level device.

In addition, the present invention provides a device serial connection method with an improved synchronization mechanism, which includes the following steps: serially connecting multiple devices together; using each device to receive a clock signal; using the first device among the multiple devices to receive A source data signal, as the data input signal of the first device, where the source data signal includes a header and multiple individual device data respectively for multiple devices; each device is used to generate the corresponding data according to the data input signal received by each device. After all the data in the individual device data locations of the device are converted to the same voltage level, the data output signal is output to the next-level device as the data input signal of the next-level device; each device is used to use each device according to the standard in the data input signal it received. The number of consecutive identical voltage levels behind the head to determine its ranking among multiple devices. column position; and use each device to calculate the synchronization time with other devices based on its sorted position among multiple devices.

In this embodiment, the device serial connection method with improved synchronization mechanism further includes the following steps: using each device to perform synchronization when the number of T clock signals is reached after the header confirmation of the data input signal it receives, where T is calculated by the equation T=f-p×h, that is, all devices will perform synchronization at the S-th clock cycle of the clock signal, where S is calculated by the following equation: S=d+p×r+(f-p×h), where p represents the number of clock cycles of the equivalent clock signal of a delay time between the time point when the data output signal of each device is output to the time point when the data output signal of the next-level device is output, and r represents the data output of each device The signal is compared to the number of delay times of the data output signal of the first device, f represents a preset clock cycle number of the clock signal, h represents the order in which each device is sequenced in multiple devices, and d represents the clock cycle of the header Count.

In an embodiment, the device series connection method with improved synchronization mechanism further includes the following steps: using each device to determine whether multiple first voltage levels or multiple second voltages appear continuously in the received data input signal. When the number of levels is equal to or greater than the threshold value, it is determined that a header appears in the received data input signal, and the position of the header in the data input signal is confirmed.

In an embodiment, the device serial connection method with an improved synchronization mechanism further includes the following steps: using a combination of a plurality of first voltage levels and a plurality of second voltage levels to represent a header; and using each device, When it is determined that a combination occurs in the received data input signal, it is determined that a header appears in the data input signal, and the position of the header in the data input signal is confirmed.

In an embodiment, the device serial connection method with improved synchronization mechanism further includes the following steps: using each device to receive a data input signal including a common command data of multiple devices.

In an embodiment, the device serial connection method with improved synchronization mechanism further includes The following steps: set the number of bits of individual device data to n bits; and use each device to determine its arrangement position among multiple devices based on the quotient of the number of consecutive identical voltage levels after the header divided by n.

In an embodiment, the device serial connection method with improved synchronization mechanism further includes the following steps: using each device to output the next clock signal to the next-level device according to the received clock signal.

To sum up, the present invention provides a device serial connection system and method with an improved synchronization mechanism. It does not require multiple devices to be connected to a synchronization control line like a traditional serial connection system. Instead, multiple devices are connected by executing operations. Synchronization is achieved between devices, and a common command data can be transmitted directly to multiple devices through data input signals. This not only simplifies wiring costs, but also reduces bandwidth waste of traditional serial devices transmitting multiple common command data.

In order to further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are only for reference and illustration and are not used to limit the present invention.

IC1~ICm: device

DI: source data signal

DO1~DOm: data output signal

CLK, CLKO1~CLKOm: clock signal

IDLE: idle voltage level

n: Number of bits of individual device data

L: low voltage level

H: high voltage level

q: Number of bits of shared command data

Sync: synchronization signal

S101, S103, S105, S109, S111, S113: steps

FIG. 1 is a block diagram illustrating the sequential transmission of data input signals and simultaneous reception of clock signals among multiple devices in a device serial connection system with an improved synchronization mechanism according to an embodiment of the present invention.

FIG. 2 is a block diagram of sequential transmission of clock signals and sequential transmission of data input signals between multiple devices in a device serial connection system with an improved synchronization mechanism according to an embodiment of the present invention.

FIG. 3 is a waveform diagram when the data input signal of the device serial connection system with improved synchronization mechanism does not contain common command data according to an embodiment of the present invention.

FIG. 4 is a waveform diagram when the data input signal of the device serial connection system with improved synchronization mechanism contains common command data according to an embodiment of the present invention.

FIG. 5 is a step flow chart of a device serial connection method with an improved synchronization mechanism according to an embodiment of the present invention.

Figure 6 is a block diagram of a conventional device cascading system.

The following is a specific example to illustrate the implementation of the present invention. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are only simple schematic illustrations and are not depictions based on actual dimensions, as is stated in advance. The following embodiments will further describe the relevant technical content of the present invention in detail, but the disclosed content is not intended to limit the scope of the present invention. In addition, the term "or" used in this article shall include any one or combination of more of the associated listed items, depending on the actual situation.

Please refer to FIGS. 1 and 5 , wherein FIG. 1 is a block diagram of a device serial connection system with an improved synchronization mechanism according to an embodiment of the present invention, in which data input signals are transmitted sequentially and clock signals are received simultaneously among multiple devices; FIG. 5 is a block diagram. A step flow chart of a device serial connection method with an improved synchronization mechanism according to an embodiment of the present invention.

The device serial connection system with improved synchronization mechanism according to the embodiment of the present invention may include multiple devices IC1 ~ ICm as shown in FIG. 1 , where m is an integer greater than 1. The plurality of devices IC1 to ICm are, for example, but not limited to, display driving devices or driving chips. Multiple devices IC1 to ICm are connected in series in sequence (step S101 shown in Figure 5). That is, the data output terminal of the first-ordered device IC1 is connected to the data input terminal of the next-level device IC2, and the data output terminal of the next-level device IC2 is connected to the data input port of the next-level device IC3, and so on.

The first device IC1 among multiple devices IC1~ICm receives a source data from the outside. The signal DI (step S105 shown in Figure 5), as the data input signal of the first device IC1, may be a source data signal DI provided from the outside. The source data signal DI may include a header and a plurality of individual device data respectively for a plurality of devices IC1~ICm.

The device IC1 can determine the arrangement position of the device IC1 itself among the multiple devices IC1~ICm in the series connection system based on the multiple consecutive numbers of the same voltage level of the received source data signal DI after header confirmation.

The device IC1 can retrieve the corresponding individual device data from the source data signal DI. For example, when the device IC1 in this embodiment is sorted first, the device IC1 retrieves the first individual device data.

The device IC1 converts all the data at the individual device data corresponding to the device IC1 in the received source data signal DI to the same voltage level (step S109 shown in Figure 5), for example, all of them are converted to a high voltage level, or All are converted to low voltage levels to generate data output signal DO1. Finally, the device IC1 outputs the data output signal DO1 to the next-level device IC2 (step S111 shown in Figure 5). The data output signal DO1 of the upper-level device IC1 is used as the data input signal of the lower-level device IC2.

The device IC2 determines the arrangement of the device IC2 itself among the multiple devices IC1~ICm based on the received data output signal DO1 (that is, the data input signal of the device IC2) after the header confirmation of multiple consecutive numbers of the same voltage level. Location.

The device IC2 retrieves the corresponding individual device data from the received data input signal (ie, the data output signal DO1 from the upper-level device IC1). For example, when the device IC2 of this embodiment is sorted in the second place, it retrieves the second individual device data.

The device IC2 converts all the data corresponding to the individual device data of the device IC2 in the data output signal DO1 received from the upper-level device IC1 into the same voltage level to generate the data output signal DO2. Finally, the device IC2 outputs the data output signal DO2 to the next-level device IC3 as the data input signal of the next-level device IC3.

Similarly, other devices IC3~ICm perform operations similar to the above-mentioned device IC2.

Multiple devices IC1 ~ ICm can receive a common clock signal (step S103 shown in Figure 5), and can retrieve data through this clock signal. Multiple devices IC1 ~ ICm can determine the time to acquire required individual device data based on the level change of the received clock signal CLK. For example, multiple devices IC1 ~ ICm can respectively capture data at the rising edge, falling edge, or both of the clock signal CLK.

Multiple devices IC1 ~ ICm can respectively perform corresponding operations based on the captured individual device data, such as but not limited to performing appropriate driving operations on multiple light-emitting elements of the display.

It is worth noting that each device IC1~ICm can calculate which clock cycle the clock signal CLK reaches after header confirmation based on its order/sorting position among the multiple devices IC1~ICm in the serial system. is synchronized with each other device IC1~ICm (step S113 shown in Figure 5).

Each device IC1~ICm can calculate and perform synchronization when the number of T clock signals arrives after individual header confirmation, where T is calculated by the equation T=f-p×h, that is, all devices will perform synchronization on the Sth clock signal CLK. Synchronization is performed during the clock cycle, such as executing the following equation: S=d+p×r+(f-p×h), where p represents the time point when the data output signal of each device is output to the time when the data output signal of the next-level device is output. The number of clock cycles of the equivalent clock signal CLK of a delay time between points, r represents the number of delay times of the data output signals of each device IC1 ~ ICm compared to the data output signal of device IC1, f represents the clock signal A preset number of clock cycles, h represents the order in which each device IC1~ICm is sorted in the serial system, and d represents the number of clock cycles of the header.

Please refer to FIG. 2 , which is a block diagram of sequential transmission of clock signals and sequential transmission of data input signals among multiple devices in a device serial connection system with an improved synchronization mechanism according to an embodiment of the present invention.

As shown in Figure 2, the first device IC1 among multiple devices IC1~ICm receives the clock signal CLK from the outside, and the device IC1 generates the next clock signal CLKO1 based on the clock signal CLK. The output is to the next-level device IC2. The next-level device IC2 generates the next clock signal CLKO2 based on the received clock signal CLKO1 and outputs it to the next-level device IC3, and so on.

Multiple devices IC1~ICm in the serial system can respectively acquire data based on the rising edge, falling edge, or both of the received clock signals CLK, CLKO1~CLKOm-1.

The clock signal CLK, source data signal DI, data output signal DO1~DOm (also the next-level data input signal) and clock output signal CLKO1~CLKm described in this article can be single-ended signals or differential signals, but The present invention is not limited to this. The embodiments described herein take a single-ended signal as an example.

Please refer to FIGS. 1 and 3 , wherein FIG. 3 is a waveform diagram when the data input signal of the device serial connection system with an improved synchronization mechanism does not contain common command data according to an embodiment of the present invention.

The source data signal DI as shown in Figure 1 may include a header as shown in Figure 3 and multiple individual device data of multiple devices IC1 ~ ICm as shown in Figure 1 (i.e., IC1 data ~ ICm in Figure 3 data, where IC1 data ~ ICm data are each n bits). In practice, the source data signal DI may also include common command data based on actual needs.

The voltage levels at the headers of the source data signal DI can all be the first voltage level (for example, the 16 low bits shown in Figure 3 are all low voltage levels) or in practice they can all be the second voltage level ( such as high voltage levels). That is, multiple first voltage levels (such as low voltage levels) may appear continuously in the source data signal DI, or in practice, multiple second voltage levels (such as high voltage levels) may appear continuously in the source data signal DI, representing the source data. Header of signal DI.

Alternatively, the plurality of voltage levels at the header of the source data signal DI may be composed of a first preset number of first voltage levels (for example, high voltage levels) and a second preset number of plurality of second voltage levels. A combination of bits (such as low voltage levels) in a predetermined order. That is, the source data signal DI may be represented by a combination of a plurality of first voltage levels (eg, a high voltage level) and a plurality of second voltage levels (eg, a low voltage level).

The device IC1 can determine based on the multiple voltage levels of the received source data signal DI (that is, the data input signal of the device IC1), for example, it determines that multiple first voltage levels or multiple first voltage levels appear continuously in the received source data signal DI. When the number of second voltage levels is equal to or greater than a threshold, or when a combination of the above occurs, the header position is confirmed. As shown in Figure 3, the number of bits of 16 consecutive low voltage levels represents the header, and the threshold value is represented by k (k=16). This is only an example, and the invention is not limited to this.

After the device IC1 confirms the position of the header, the device IC1 can determine that it is in the series-connected device based on the number of consecutive identical voltage levels after the header (for example, 0 consecutive high voltage (H) levels). The arrangement position among the plurality of devices IC1 to ICm is the first one.

Device IC1 retrieves the first IC1 data among multiple individual device data after header confirmation.

Device IC1 converts the voltage levels of n bits of individual device data corresponding to IC1 data in the source data signal DI into n bits of the same voltage level (for example, high voltage level H) to generate data output signal DO1 and convert the data The output signal DO1 is output to the next-stage device IC2.

Then, the device IC2 can confirm the header position of the data output signal DO1 according to the data output signal DO1 output from the device IC1 (ie, the data input signal of the device IC2). The device IC2 can determine its arrangement position among the multiple devices IC1~ICm based on a plurality of consecutive numbers of the same voltage level (for example, n consecutive numbers of high voltage levels) after the header in the data output signal DO1. For the second person.

Similarly, other devices IC3 ~ ICm respectively confirm the headers in the data output signals DO2 ~ DOm-1 according to the received data output signals DO2 ~ DOm-1 (ie, the data input signals of the devices IC3 ~ ICm). Devices IC3 ~ ICm can determine whether they are in multiple devices IC1 based on multiple consecutive numbers of the same voltage level after the header in the data output signals DO2 ~ DOm-1 (ie, the data input signals of devices IC3 ~ ICm). ~Arrangement position in ICm.

In order to avoid misjudgment of the header position, the voltage levels of multiple individual device data should be avoided as much as possible in order to avoid combinations of voltage levels that represent the same header as the data input signal. Taking Figure 3 as an example, if The 16 low voltage levels represent headers, and when the aforementioned threshold k is 16, the voltage levels of multiple individual device data should avoid 16 consecutive low voltage levels.

The first device IC1 converts multiple voltage levels corresponding to the individual device data (i.e., IC1 data in Figure 3) in the source data signal DI to generate the data output signal DO1, for example, converting all n bits of the corresponding voltage levels bits are converted to high voltage levels, as shown in Figure 3: Data output signal DO1 has a continuous H number = 1n, where n represents the number of bits of data in a particular device. The source data signal DI is converted to form a data output signal DO1 and is output to the next-level device IC2 as a data input signal of the next-level device IC2.

Device IC2 converts the received data output signal DO1 and all n bits signals in the signal band of the corresponding individual device data (i.e., IC2 data in Figure 3) into high voltage levels to form a data output signal DO2 and output it to the next The first-level device IC3 serves as the data input signal of the next-level device IC3. As shown in Figure 3, the data output signal DO2 appears for 2n consecutive high voltage levels at the signal band that originally stores the individual device data of the devices IC1 and IC2 (ie, the IC1 data and IC2 data in the figure).

Other devices are IC3~ICm, and so on.

In practice, each device IC1 ~ ICm can count the number of second voltage (such as high voltage) levels that continuously appear between the header and the corresponding required individual device data to determine its own position in the series system. Under the condition that the data required by each device IC1 ~ ICm is n bits, when the number of consecutive second voltage levels is between 0 ~ (n-1) bits, the device can determine that its arrangement position in the series system is the third First order; when the second voltage level is between n~(2n-1) bits, the device can determine that its arrangement position in the series system is the second order; the second voltage level is between 2n~(3n- 1) bits, the device can determine that its arrangement position in the serial system is the third order, and so on. That is to say, the quotient obtained by dividing the number of consecutive voltage levels by n can be used to determine its position in the series system. For example, if quotient = 0, it is the first order, and if quotient = 1, it is the second order.

The data output signals of multiple devices IC1~ICm will pass through a For example, the data output signal DO2 will be delayed by one delay time than the data output signal DO1, and the data output signal DO3 will be delayed by two delay times than the data output signal DO1. The delay time of each device can be 0.5×g clock cycles (g is greater than or equal to 1). For convenience of explanation, when the duty cycle of the clock signal is not 50%, 0.5 clock cycles are also used to represent one High level time or 1 low level time.

As shown in Figure 3, a design is adopted to capture data on both the rising edge and falling edge of the clock signal. The device IC1 starts to acquire the source data signal DI at the rising edge of the first clock signal, and starts to output the data output signal DO1 after the rising edge of the first clock signal. Device IC2 receives the data output signal DO1 from the upper-level device IC1, starts to acquire the data output signal DO1 at the falling edge of the first clock signal, and starts to transmit the data output signal DO2 after the falling edge of the first clock signal. . Device IC3 receives the data output signal DO2 from the upper-level device IC2, starts to acquire the data output signal DO2 at the rising edge of the second clock signal, and starts to transmit a data output signal after the rising edge of the second clock signal. DO3. The rest of the devices follow this pattern.

Obviously, a clock cycle is divided into high-level time and low-level time. Every time the data output signal passes through a device, it will be delayed by 1 high-level time or 1 low-level time. Every time the data output signal passes through 2 The device will be delayed by 1 clock cycle.

Due to the example in Figure 3, the duty cycle of the clock signal is not 50% (the high level time is smaller than the low level time), but for the sake of convenience, 0.5 clock cycles are used to represent a high level time or a low level time. Time, the sum of the two is 1 clock cycle.

The delay time of the data output signal in this embodiment is 0.5 clock cycles each time it passes through a device. The data output signal DO2 is delayed by a high level time (ie, 1 delay time) compared to the data output signal DO1. The data output signal DO3 Compared with the data output signal DO2, which is delayed by a low level time, the data output signal DO3 is delayed by one clock cycle time (ie, two delay times) compared with the data output signal DO1. When the duty cycle of the clock signal is 50%, the high level time and low level time The time is equal to half the clock cycle time.

That is, in the application of double-edge acquisition, the delay time after each device is equal to the time from the rising edge of a clock pulse of the clock signal CLK to the falling edge of this pulse (high level time) or the falling edge of a clock pulse. The time from the rising edge to the rising edge of the pulse at this time (low level time). Therefore, when the duty cycle of the clock signal CLK is 50% of the clock cycle, the delay time is equal to 0.5 clock cycles. However, the duty cycle of the clock signal CLK may not be 50%, but for convenience of explanation, 0.5 clock cycles are used to represent a high level time or a low level time, and the sum of the two is 1 clock. cycle.

Please refer to FIGS. 1 and 4 , wherein FIG. 4 is a waveform diagram when the data input signal of the device serial connection system with an improved synchronization mechanism contains common command data according to an embodiment of the present invention.

Different from the example in Figure 3, where the header in the source data signal DI is set to 16 low bits/low voltage level, in the example of Figure 4, the header is set to 17 high bits/high voltage level, threshold The value is represented by k (k=16), but the above are examples, and the present invention is not limited thereto. In practice, the voltage level/number of bits representing the header can be adjusted according to actual needs.

In addition, unlike the example in Figure 3, which uses double-edge capture, the example in Figure 4 uses single-edge capture (rising edge), as explained in detail below.

After the device IC1 confirms the position of the header in the source data signal DI, the device IC1 can store the common command data and store other data in the source data signal DI based on the number of consecutive low voltage levels following the header in the source data signal DI. The number of consecutive low-voltage levels between subsequent IC1 data is 0, and it is determined that its arrangement position among the multiple devices IC1 ~ ICm of the series connection device is the first one.

After the device IC2 confirms that the header is at the position of the data output signal DO1, the device IC2 determines that the number of consecutive low voltage levels between the common command data stored after the header of the data output signal DO1 and the IC2 data stored after it is n. , to determine that its arrangement position among the plurality of devices IC1 ~ ICm of the series-connected device is the second one.

As shown in Figure 4, device IC2 receives the data output signal DO1 (that is, the device IC1 The time point when the data input signal of IC2 is set is after the rising edge of the first clock of the clock signal CLK, and the time point when the device IC2 outputs a data output signal DO2 is after the rising edge of the second clock. Obviously, the data output signal DO1 and the data output signal DO2 are separated by 1 clock cycle (ie, delay time).

As shown in Figure 4, the design uses the rising edge of the clock signal to capture data. The device IC1 starts to acquire the source data signal DI at the rising edge of the first clock signal, and starts to output the data output signal DO1 after the rising edge of the first clock signal. Device IC2 receives the data output signal DO1 from the upper-level device IC1, starts to acquire the data output signal DO1 at the rising edge of the second clock signal, and starts to transmit the data output signal DO2 after the rising edge of the second clock signal. . Device IC3 receives the data output signal DO2 from the upper-level device IC2, starts to acquire the data output signal DO2 at the rising edge of the third clock signal, and starts to transmit the data output signal DO3 after the rising edge of the third clock signal. . The rest of the devices follow this pattern. Obviously, the data output signal will be delayed by 1 clock cycle every time it passes through 1 device, and the data output signal will be delayed by 2 clock cycles every time it passes through 2 devices.

From the example of Figure 4, the data output signal DO2 is delayed by one clock cycle (i.e. 1 delay time) compared to the data output signal DO1, and the data output signal DO3 is delayed by one clock cycle compared to the data output signal DO2. The data output Signal DO3 is delayed by a total of 2 clock cycle times (ie, 2 delay times) compared to data output signal DO1.

The first device IC1 converts multiple voltage levels in the source data signal DI where the individual device data is stored (i.e., the IC1 data in Figure 4) to generate the data output signal DO1. For example, all n bits of the corresponding voltage levels are converted. bits all transition to low voltage levels. As shown in Figure 4, the data output signal DO1 has a continuous L number = 1n, where n represents the number of bits of data of an individual device. The source data signal DI is converted to form a data output signal DO1 and is output to the next-level device IC2 as a data input signal of the next-level device IC2.

The next-level device IC2 converts the received data output signal DO1 and all n bits signals in the signal band of the corresponding individual device data (i.e., the IC2 data in Figure 4) into a low voltage level to A data output signal DO2 is formed and output to the next-level device IC3 as a data input signal of the next-level device IC3. As shown in Figure 4, the data output signal DO2 appears for 2n consecutive low voltage levels at the signal band that originally stores the individual device data of the device IC1 and the device IC2 (ie, the IC1 data and IC2 data in the figure). Other devices are IC3~ICm, and so on.

In the example in Figure 4, each device synchronizes in the 100.5th clock cycle (d=17, p=1, f=84.5) after calculating the synchronization time using its own location information. For example: the first device The device position = 1, it confirms its header at the (17+1×0)th clock cycle and performs synchronization at the following (84.5-1×1) clock cycle position, that is, at the (d+p)th clock cycle ×r+(f-p×h)=17+1×0+(84.5-1×1)=100.5) clock cycle to perform synchronization; the device position of the second device=2, which is at the (17+1×1 ) clock cycle to confirm its header and perform synchronization at the following (84.5-1×2) clock cycle position, that is, at the (d+p×r+(f-p×h)=17+1×1+( 84.5-1×2) = 100.5) clock cycles to perform synchronization; and so on, other devices will all perform synchronization in the 100.5th clock cycle.

In the example in Figure 3, after each device uses its own position information to calculate the synchronization time, it synchronizes in the 47th clock cycle (d=8, p=0.5, f=39.5), for example: the first The device's device position = 1, it acknowledges its header at the (8+0.5×0)th clock cycle and performs synchronization at the (39.5-0.5×1)th clock cycle, that is, at the (d+ p×r+(f-p×h)=8+0.5×0+(39.5-0.5×1)=47) clock cycle to perform synchronization; the device position of the second device=2, which is at the (8+0.5× 1) Confirm its header in the first clock cycle and perform synchronization at the following (39.5-0.5×2) clock cycle position, that is, at the (d+p×r+(f-p×h)=8+0.5×1+ (39.5-0.5×2) 47) clock cycles to perform synchronization; and so on, other devices will all perform synchronization in the 47th clock cycle. The above are examples, and the invention is not limited thereto. Different synchronization times of multiple devices IC1~ICm can be set according to actual needs.

To sum up, the present invention provides a device serial connection system and method with an improved synchronization mechanism, which does not require multiple devices to be connected to a synchronization control line like a traditional serial connection system, but transparently By executing operations, multiple devices are synchronized, and a common command data can be directly transmitted to multiple devices through data input signals. This not only simplifies wiring costs, but also reduces the need for traditional serial devices to transmit multiple common commands. Data bandwidth is wasted.

The contents disclosed above are only preferred and feasible embodiments of the present invention, and do not limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made by using the description and drawings of the present invention are included in the application of the present invention. within the scope of the patent.

IC1~ICm: device

DI: source data signal

DO1~DOm: data output signal

CLK: clock signal

Claims (14)

A device serial connection system with an improved synchronization mechanism, including: a plurality of devices, each device having a data input terminal for receiving a data input signal, a data output terminal for outputting a data output signal, and a clock pulse A clock signal terminal of the signal, the plurality of devices are connected together in sequence, the clock signal terminal of each device is coupled to the clock signal, and the data input of the first device among the plurality of devices The terminal is coupled to a source data signal as the data input signal of the first device, and the data input terminals of the other devices are coupled to the data output terminals of the upper-level device to receive the data output signals of the upper-level device. The data output signal of each device is the data input signal of the next-level device. The source data signal includes a header and a plurality of individual device data respectively for the multiple devices; wherein each device receives the data based on the The number of consecutive identical voltage levels after the header in the data input signal is used to determine its arrangement position among the multiple devices; wherein each device calculates the Synchronization time with other devices; wherein each device converts the individual device data of the corresponding device into the same voltage level based on the data input signal it receives and then outputs the data output signal to the next-level device. The device serialization system with an improved synchronization mechanism as described in claim 1, wherein each device performs synchronization when the number of T clock signals reaches T after confirmation of the header of the data input signal it receives, where T is The equation T=f-p×h is calculated, that is, when the S-th clock cycle of the clock signal is reached, it is synchronized with the other multiple devices, where S is calculated according to the following equation: S=d+p×r+(f-p×h ), where p represents the time point at which the data output signal of each device is output to the next level A delay time between the output time points of the device's data output signal is equivalent to the number of clock cycles of the clock signal. r represents the difference between the data output signal of each device and the data output signal of the first device. The number of delay times, f represents a preset clock cycle number of the clock signal, h represents the order in which the devices are sorted in the plurality of devices, and d represents the clock cycle number of the header. The device series connection system with an improved synchronization mechanism as described in claim 1, wherein each device determines that the number of consecutive occurrences of multiple first voltage levels or multiple second voltage levels in the received data input signal is equal to or When it is greater than a threshold, it is determined that the header appears in the received data input signal, and the position of the header in the data input signal is confirmed. The device serial connection system with an improved synchronization mechanism as claimed in claim 1, wherein the data input signal received by each device is represented by a combination of a plurality of first voltage levels and a plurality of second voltage levels. When each device determines that the combination appears in the received data input signal, it determines that the header appears in the data input signal, and confirms the position of the header in the data input signal. The device serial connection system with improved synchronization mechanism as described in claim 1, wherein the data input signal received by each device further includes a common command data of the multiple devices. The device cascading system with improved synchronization mechanism as described in claim 1, wherein the number of bits of the individual device data is n bits, and each device divides the number of consecutive identical voltage levels after the header by n. quotient to determine its position among the multiple devices. The device serial connection system with an improved synchronization mechanism as claimed in claim 1, wherein each device further has a clock output terminal for outputting a next clock signal to the clock signal terminal of the next-level device. A device serial connection method with an improved synchronization mechanism, including the following steps: Connect multiple devices together in sequence; use each device to receive a clock signal; use the first device among the multiple devices to receive a source data signal as the data input signal of the first device, wherein The source data signal includes a header and a plurality of individual device data of the plurality of devices; each device is used to convert the individual device data of the corresponding device to the same voltage level according to the data input signal received by each device. Then, the data output signal is output to the next-level device as the data input signal of the next-level device; each device uses the same number of consecutive voltage levels after the header in the data input signal it receives to Determine its own arrangement position in the multiple devices; and use each device to calculate the synchronization time with each other device according to its own arrangement position in the multiple devices. The device serial connection method with improved synchronization mechanism as described in claim 8 further includes the following steps: using each device, when the number of T clock signals is reached after confirmation of the header of the data input signal received by it Synchronization is performed, where T is calculated by the equation T=f-p×h, that is, when the S-th clock cycle of the clock signal is reached, synchronization is performed with other multiple devices, where S is calculated by the following equation: S=d+p ×r+(f-p×h), where p represents the equivalent of the clock signal of a delay time between the time point when the data output signal of each device is output to the time point when the data output signal of the next stage device is output. The number of clock cycles, r represents the number of delay times between the data output signal of each device and the data output signal of the first device, f represents a preset number of clock cycles of the clock signal, and h represents the number of delay times of each device. The order in which devices are sorted within the multiple devices, d represents the clock cycle of the header Issue number. The device series connection method with an improved synchronization mechanism as described in claim 8 further includes the following steps: using each of the devices to determine whether multiple first voltage levels or multiple second voltage levels appear continuously in the received data input signal. When the number of voltage levels is equal to or greater than a threshold value, it is determined that the header appears in the received data input signal, and the position of the header in the data input signal is confirmed. The device serial connection method with an improved synchronization mechanism as described in claim 8 further includes the following steps: using a combination of a plurality of first voltage levels and a plurality of second voltage levels to represent the header; and using each of the When the device determines that the combination appears in the received data input signal, it determines that the header appears in the data input signal, and confirms the position of the header in the data input signal. The device serial connection method with improved synchronization mechanism as described in claim 8 further includes the following steps: using each of the devices to receive a data input signal including a common command data of the multiple devices. The device serial connection method with improved synchronization mechanism as described in claim 8 further includes the following steps: setting the number of bits of the individual device data to n bits; and using each of the devices, according to the continuous same voltage after the header The quotient of the level number divided by n is used to determine its arrangement position among the multiple devices. The device serial connection method with improved synchronization mechanism as described in claim 8 further includes the following steps: using each device to output the next clock signal to the next-level device according to the received clock signal.

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