TWI812391B - Computing-in-memory circuitry - Google Patents

Abstract

An in-memory computing circuit includes multiple digital-to-analog converters, multiple computing arrays, and multiple charge processing networks. The digital-to-analog converters convert external data into input data and the digital-to-analog converters are connected in series with a corresponding plurality of output capacitor pairs. The computing array receives the input data from both ends and outputs a first computing value. The charge processing network receives and accumulates the first computing values over a predetermined time interval by switching pairs in series with the output capacitor pairs. A plurality of charge processing networks shares the charge of the first computing values equally to selected output capacitor pairs and compare the voltage differences between the two ends of the plurality of output capacitor pairs to output the second computing values.

Description

In-memory computing circuit

The present invention relates to an in-memory computing circuit, and in particular to an in-memory computing circuit using a static random access memory.

With the continuous advancement of artificial intelligence (AI) and machine learning (ML) technologies, machine learning architecture based on neural networks has achieved excellent accuracy in applications such as speech and image recognition. Compared with traditional cloud computing, edge computing can achieve lower computing latency and better performance. At the same time, because there is no need to upload data to the cloud, the risk of data being stolen by third parties is avoided, which can effectively improve data security and reduce the device's dependence on the network.

However, edge computing is limited by the energy and computing resources of terminal devices, making it extremely challenging to implement machine learning architecture on terminal devices. In response to terminal AI applications, the memory circuit architecture of computing-in-memory (CIM) is gradually emerging. By performing operations directly in the memory to avoid large amounts of data transfer, this memory architecture can not only break the memory bottleneck under the traditional Von Neumann architecture, but also achieve parallel operations of multiplication and addition, thereby greatly Significantly improve overall computing performance. However, since in-memory computing requires additional data conversion interfaces, including digital analog and analog-to-digital converters, the performance of these analog components will affect the throughput, energy consumption and area efficiency of the overall circuit. , which limits the performance of the memory for in-memory operations, thereby limiting the application of this memory architecture.

It should be noted that the content of the "Prior Art" paragraph is used to help understand the present invention. Some (or all) of the contents disclosed in the "Prior Art" paragraph may not be conventional techniques known to those with ordinary skill in the relevant technical field. The content disclosed in the "Prior Art" paragraph does not mean that the content has been known to those with ordinary knowledge in the technical field before the application of the present invention.

The invention provides an in-memory computing circuit including a plurality of digital-to-analog converters, a plurality of computing arrays and a plurality of charge processing networks. The digital-to-analog converter converts external data into input data, and the digital-to-analog converter is connected in series with corresponding pairs of output capacitors. The operation array receives the input data from both ends and performs operations to output a first operation value. The charge processing network receives and accumulates the first operation value within a predetermined time interval through a pair of switches connected in series with the pair of output capacitors. The plurality of charge processing networks evenly distribute the charge of the first operation value to the selected output capacitor pair, and compare the voltage differences across the plurality of output capacitor pairs to output the second operation value.

The present invention provides a static random access memory (CIM SRAM) circuit architecture for in-memory computing with high throughput, high energy and area usage efficiency for terminal AI equipment. By improving the data processing and conversion circuits, we can overcome the current limitations of CIM SRAM in circuit performance, and improve the circuit's additional energy consumption and limited computational linearity, thereby increasing the overall memory's computing speed and energy Usage efficiency and linearity. In addition, the present invention also provides a unified charge processing network (UCPN), which simultaneously provides signal processing and data conversion functions to improve energy usage efficiency, and simultaneously improves circuit performance and chip physical design. The usage efficiency of the chip area at that time.

The present invention provides an in-memory computing circuit. In order to make the above features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the attached drawings.

Features of the inventive concept and methods of implementing said features may be more readily understood with reference to the following detailed description of embodiments and the accompanying drawings. Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings, in which like reference numerals refer to like elements throughout. This invention may, however, be embodied in various different forms and should not be construed as limited to the only embodiments set forth herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects and features of the invention to those skilled in the art. Accordingly, processes, elements, and techniques that are not necessary for a person of ordinary skill in the art to fully understand aspects and features of the invention may not be described. Unless otherwise indicated, the same reference numerals refer to the same elements throughout the accompanying drawings and written description, and therefore the description thereof will not be repeated. In the drawings, the relative sizes of components, layers and regions may be exaggerated for clarity.

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various embodiments. It will be apparent, however, that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the various embodiments.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular form "a/an" is intended to include the plural form as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising", "have/having", and "includes/including" when used in this specification mean stated features, integers, steps, operations, The presence of an element and/or element does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, elements and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

As used herein, the terms "substantially," "about," "approximately," and similar terms are used as terms of approximation and not as terms of degree, and are intended to contemplate measurements or calculations that would be recognized by one of ordinary skill in the art inherent bias in. As used herein, "about" or "approximately" encompasses the stated value and is intended to be within a reasonable time limit by one of ordinary skill in the art, taking into account the measurements in question and the errors associated with the measurement of particular quantities (i.e., the limitations of the measurement system). An acceptable range of deviation from a specific value determined by a technician. For example, "about" can mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value. Additionally, when describing embodiments of the invention, the use of "may" means "one or more embodiments of the invention."

While an embodiment may be implemented differently, the specific order of processing may be performed differently than described. For example, two consecutively described circuits or elements may be executed substantially concurrently or in the reverse order than described.

Various embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of embodiments and/or intermediate structures. Thus, differences from the shapes illustrated should be expected, as a result, for example, of manufacturing techniques and/or tolerances. Furthermore, for the purpose of describing embodiments in accordance with the presently disclosed concepts, specific structural or functional descriptions disclosed herein are illustrative only. Therefore, embodiments disclosed herein should not be construed as limited to the particular illustrated shapes of regions but are to include deviations in shapes that result, for example, from manufacturing.

Electronic or electronic devices according to embodiments of the invention described herein and/or any other related devices or components may utilize any suitable hardware, firmware (eg, application specific integrated circuits), software, or software, firmware, and A combination of hardware implementations. For example, the various components of these devices may be formed on an integrated circuit (IC) chip or on separate IC chips. Additionally, various components of these devices may be implemented on flexible printed circuit films, tape carrier packages (TCP), printed circuit boards (PCB), or formed on a substrate. Additionally, the various elements of these devices may be processes running on one or more processors in one or more computing devices, executing computer program instructions, and interacting with other system elements for performing the various functions described herein or thread. Computer program instructions are stored in memory that can be implemented in a computing device using standard memory devices such as random access memory (RAM). Computer program instructions may also be stored on other non-transitory computer-readable media such as CD-ROMs, flash memory drives, or the like. Additionally, those skilled in the art will recognize that the functionality of various computing devices may be combined or integrated into a single computing device, or the functionality of a particular computing device may be distributed across one or more other computing devices without departing from the scope of the present invention. spirit and scope of the exemplary embodiments.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms (such as those defined in commonly used dictionaries) should be interpreted to have a meaning consistent with their meaning in the context of the relevant technology and/or this specification, and should not be interpreted in an idealized or overly formalized sense. unless otherwise explicitly defined herein.

In order to realize emerging artificial intelligence applications, the computing in memory (CIM) architecture is proposed to improve the computing efficiency of machine learning processing tasks. Since the CIM architecture performs calculations directly in memory, it avoids large amounts of data movement. This makes energy usage much more efficient than traditional Von Neumann computing architectures, where energy consumption is mainly caused by data movement. The advantage of CIM static random access memory is that it can directly process information obtained from the bit-line (BL), minimizing the energy required to move data, and can perform parallel processing to perform efficient Multiplication and accumulation (MAC) operations. Although CIM SRAM can achieve higher energy usage efficiency, its operating frequency and throughput are relatively lower than existing ML accelerators. Therefore, the space that CIM SRAM can be applied to will be limited. Therefore, the throughput and execution efficiency of the CIM SRAM circuit architecture must be further improved so that its computing speed and throughput performance can match high-speed computing or high-performance ML accelerators to achieve high-speed computing or high-performance Al applications.

The CIM SRAM of the present invention uses MAC computing processing and data conversion circuits to support ML computing tasks. First, the present invention uses bit line control with a charge redistribution architecture to perform efficient MAC calculations. Through this architecture, the classification performance of CIM SRAM can be effectively improved without being affected by the non-ideal effects caused by the SRAM access transistor, such as transistor mismatch and transistor mismatch. Affected by data-dependent current characteristics.

In addition, the present invention also adopts a dynamic binary-weighted current-steering digital-to-analog converter (DAC) architecture to improve energy under high-speed operation. Efficiency and linearity performance. In addition, an integrated charge processing network (UCPN) is also used to provide efficient signal processing and data conversion functions at the same time, in addition to effectively improving throughput, energy and area efficiency (energy-area-efficiency) , and also respectively overcome the performance bottleneck of CIM SRAM caused by the use of additional data processing and conversion circuits.

On the other hand, the present invention also uses a successive-approximation analog-to-digital converter (SAR ADC) circuit architecture coupled with bottom-plate sampling to improve data conversion performance. In addition to reducing the energy loss in the CIM SRAM circuit architecture, this architecture can also effectively improve the output resolution and conversion time and achieve fast conversion speed to achieve high throughput and high High-performance CIM SRAM with high resolution.

Please refer to FIG. 1 , which is a system block (circuit block) diagram of an in-memory computing circuit according to an embodiment of the present invention.

In this embodiment, the in-memory computing circuit 100 includes: a plurality of charge processing networks 110, a plurality of digital-to-analog converters (DACs) 120, a plurality of computing arrays (101, 1021, 102N), at least one driving circuit (and /or decoding circuit) 130 and an input and output circuit 140 for reading and writing data. Among them, multiple operation arrays include multiple operation libraries (1021, 102N).

In this embodiment, the decoding circuit 130 is used to receive an input enable signal (not shown) to decode the encoded external data to obtain the decoded corresponding address. Among them, each address corresponds to a specific operation (or memory) unit in multiple operation arrays (101, 1021, 102N). The driving circuit 130 drives at least one of the plurality of operation arrays (101, 1021, 102N) corresponding to the corresponding address through the plurality of word lines (WL, WL1, WLN), and through the plurality of word lines (WL , WL1, WLN) and the analog-to-digital converter (analog-to-digital converter; ADC) are electrically connected. In this embodiment, the ADC is a SAR ADC. In an embodiment, the ADC may also be a flash ADC (flash ADC), a pipeline ADC (pipeline ADC), or a pipeline-SAR ADC, which is not limited in this embodiment.

In this embodiment, the plurality of DACs 120 are configured to convert digital external data input from the input-output circuit 140 into analog input data DIN, DIN1, and DINM. In this embodiment, each of the plurality of DACs 120 is connected in series with a corresponding plurality of output capacitor pairs (see below).

In this embodiment, the operation array (101, 1021, 102N) receives the input data (DIN, DIN1, DINM) from the bit lines (BL, BL1, BLM) from the corresponding double terminal (port). The word lines (WL, WL1, WLN) are turned on at specific addresses and output operation enable signals (EN, EN 1, EN N), and the input data on the bit lines (BL, BL1, BLM) ( DIN, DIN1, DINM) and the operation (or memory) unit 101 perform operations. For example, the computing (or memory) unit 101 may be composed of two symmetrical access transistors (2T) (not shown) and four transistors (4T). It is composed of a latch (not shown). For example, one of the transistors on the left is connected to the word line, and the other transistor on the left is connected to the latch. In other words, in this embodiment, the computing unit 101 is composed of a static random access memory (SRAM) composed of 10 transistors, which is not limited by the present invention.

Among them, the latch can store two complementary logic voltage levels as weights at both ends. For example, a latch can store either a logic 1 or a logic 0 on both ends. For example, when the word line WL is turned on, one end of the transmission transistor connected to the latch has a weight of logic 1. In this example, after multiplication with the weight, the value originally located on the bit line BL The input data (DIN, DIN1, DINM) will be released through the transmission transistor, and the output operation value (output voltage or output current) on the bit line BL is logic 0. On the contrary, when the word line WL is turned on, one end of the transmission transistor connected to the latch has a weight of logic 0. In this example, after multiplying with the weight, the value originally located on the bit line BL The input data (DIN, DIN1, DINM) will be released through the transmission transistor, and the output operation value (output voltage or output current) on the bit line BL is logic 1. Therefore, after multiplication with the weight, the endpoints of the bit line BL connected to both ends of the left-right symmetrical SRAM have complementary logic levels. In other words, the two corresponding bit lines BL connected to the arithmetic (or memory) unit 101 have complementary logic levels. In other words, if one of the bit lines connected to the arithmetic (or memory) unit 101 has a voltage level of, for example, logic 1, the other bit line (also called an inverted bit line) has a complementary voltage level, such as logic 0. the reverse voltage level.

In one embodiment, the latch may be a latch composed of an SR flip-flop, which is not limited here. The latch can be used as a clock gating to memorize the comparison status of this time period without having to change the signal status again in the next period. Therefore, the switching of clock signals can be reduced, which can effectively reduce the circuit load. Dynamic power loss, and the clock tree structure can be optimized at the same time to reduce setup timing and increase voltage conversion efficiency.

If the charge processing network 110 receives and accumulates the first operation value (ie, the operation value multiplied by the weight) within a predetermined time interval through a switch pair connected in series with the output capacitor pair (see below). On the one hand, the charge processing network 110 transfers the stored charges from the multiple output capacitors to the global bit lines (see below) for accumulation (or accumulation), and on the other hand, it also transfers the charges of the first operation value through multiple bit lines at the same time. The bit line BL is evenly distributed to the selected (or "valued", "logic level other than 0") output capacitors in the output capacitor pair (i.e., perform a multiplication and then accumulation operation and then take an average value), Finally, the accumulated and averaged voltage difference between the two ends is input into the comparator for comparison, and a second operation value is output based on the comparison result. In other words, the voltage difference of the global bit line (see below) is transmitted to the SAR ADC for calculation, and the output calculation value is exactly the average result of multiplying the input data DIN, DIN1, DINM and the weight.

Please refer to FIG. 2 , which is a partial system block diagram of an in-memory computing circuit according to an embodiment of the present invention.

FIG. 2 shows an exemplary architecture of the CIM SRAM circuit system 200 proposed by the present invention. In this embodiment, the CIM SRAM circuit system 200 consists of 64 7-bit DACs (120, 1201, 120M), 16 operation libraries (102, 1021, 102N'), CIM SRAM macro 150A, 150B and input and output circuit 140. Among them, the set comes from the output (O9, O16) after operation of CIM SRAM macro 150B (for example: with 8 outputs) and the output (O1, O1, O8) (for example: with 8 outputs) is the convolution output (convolution output) 160. In this embodiment, the data conversion capability provided by the CIM SRAM circuit system 200 is equivalent to 16 ADCs with 7-bit resolution. In this embodiment, the maximum filter depth is 64. In this embodiment, each computing bank (102, 1021, 102N') includes a plurality of local computing units (LCU) 103. In one embodiment, the CIM SRAM macro 150 includes 8 operation banks (not shown). In other words, the operation bank (not shown) and the operation bank (102, 1021, 102N′) in the CIM SRAM macro 150 form a CIM SRAM circuit system 200 with 16 operation banks.

In this embodiment, the LCU 103 receives the digital external signal IN from the DAC (120, 1201, 120M) and converts it into a corresponding analog input signal (voltage) in order to precharge the operation library (102, 1021, 102N') (pre-charging). Next, the multiplication (or multiplication) operation is performed in the operation library (102, 1021, 102N’). Finally, UCPN accumulates the results of multiplication (or multiplication) and outputs the corresponding digital signal.

Please refer to FIG. 3. FIG. 3 is a block diagram of an operation library according to an embodiment of FIG. 2 of the present invention.

In this embodiment, the operation library 102 includes a plurality of LCUs 103, a plurality of operation units, and a plurality of signals ( or switches) (EN_RBL0, EN_RBLB0, EN_RBLN, EN_RBLN), the sign bit switch SSW and the charge processing network 170. In this embodiment, after the charge processing network 170 operates, it outputs an operation value ADC_OUT through the ADC. The operation value ADC_OUT output by the ADC is a 7-bits output signal.

In this embodiment, the computing unit includes multiple weight units (W _0,0 ,...,W _15,63 ). In one embodiment, the weight unit of the operation unit is not limited. In this embodiment, multiple weight units (W _0,0 ,...,W _15,0 ), (W _0,63 ,...,W _15,63 ) are connected in parallel to each other. Two ends of each of the multiple weight units (W _0,0 ,...,W _15,0 ) and (W _0,63 ,...,W _15,63 ) are respectively connected to one of the corresponding multiple bit line pairs. At least one is electrically connected. For example, both ends of the weight unit (W _0,0 ,...,W _15,0 ) are electrically connected to the bit line pairs RBL_0 and RBLB_0 respectively. Among them, each weight unit (W _0,0 ,...,W _15,63 ) stores the corresponding weight (logic 0 or logic 1). On the other hand, both ends of the weight unit (W _0,63 ,...,W _15,63 ) are electrically connected to the bit line pairs RBL_N and RBLB_N respectively. Among them, each weight unit (W _0,0 ,...,W _15,63 ) stores the corresponding weight (logic 0 or logic 1). In one embodiment, the weight stored in each weight unit (W _0,0 ,...,W _15,63 ) can be predetermined according to the computing requirements, and is not limited in this embodiment.

In this embodiment, when the operation is performed with the corresponding weights of multiple weight units (W _0,0 ,...,W _15,0 ), (W _0,63 ,...,W _15,63 ) fixed, based on One of the multiple selected weight units (for example, W _15,0 or W _15,63 ) performs the operation, and the remaining unselected weight units (for example, W _0,0 ,…,W _14,0 or W _0,63 ,…,W _14,63 ) remain idle.

In this embodiment, both ends of the sign bit switch SSW are electrically connected to at least one of the corresponding plurality of bit line pairs (RBL_0, RBLB_0), (RBL_N, RBLB_N), where before the precharge period , the corresponding sign bit switch is determined based on the positive and negative values of the input data. In other words, in this embodiment, the sign bit switch SSW is used to control the bit line pairs (RBL_0, RBLB_0), (RBL_N, RBLB_N) so that the input information (input signal) generates positive and negative values (positive and negative voltages).

Please refer to FIG. 4 , which is a schematic circuit diagram of a digital-to-analog converter (DAC) according to an embodiment of the present invention.

Please refer to Figure 3 and Figure 4 at the same time. In this embodiment, the DACs (120, 1201, 120M) are dynamic binary weighted current-oriented DACs. In this embodiment, the DAC (120, 1201, 120M) includes a dynamic binary-weighted current source array CS, and a plurality of bit line pairs with complementary logic voltage levels connected in series with a plurality of output capacitor pairs C1. In other words, the DAC (120, 1201, 120M) includes a dynamic binary-weighted current source array CS composed of a plurality of current source switches SW0, SW1, SWM. Through these current source switches SW0, SW1, and SWM, the required current source array CS can be selected or switched according to the input data to provide the corresponding current. In one embodiment, the input data from the DAC (120, 1201, 120M) is current directed data. In one embodiment, the input data from the DAC (120, 1201, 120M) is voltage directed data.

In one embodiment, the DAC (120, 1201, 120M) has multiple parallel-connected (or parallel) current source groups. For example, the current source group includes at least one current source CS. In an alternative embodiment, the DAC (120, 1201, 120M) has a plurality of parallel-connected (or parallel-connected) current source groups, wherein each current source group includes a plurality of current sources CS connected in parallel with each other. In an alternative embodiment, the number of current sources CS connected in parallel to each other in each current source group presents a power sequence of 2. For example, the first current source group has one current source CS, the second current source group has two current sources CS connected in parallel to each other, ..., and the fifth current source group has thirty-two current sources CS connected in parallel to each other. Current source CS, in other words, the N value of Figure 4 is 32, and so on. In one embodiment, each current source CS includes at least one switch SW0, SW1, and SWM. For example, the first current source group has one current source CS, three gate bias voltages BIAS and one current source switch SW0. For example, the second current source group has two current sources CS, and each current source CS includes three gate bias voltages BIAS and one current source switch SW1. In other words, the second current source group has two current source switches SW1. For example, the fifth current source group has five current sources CS connected in parallel with each other. Each current source CS includes three gate bias voltages BIAS and one current source switch SWM. In other words, the fifth current source group has five current source switches SWM. In one embodiment, the number of current sources connected in parallel in the current source group is not limited and can be designed as required.

In this embodiment, the DAC (120, 1201, 120M) includes an output capacitor C1 composed of a plurality of bit lines RBL, RBLB and capacitors CRBL, CRBLB on the plurality of bit lines (see Figure 5). With this DAC (120, 1201, 120M) architecture design, the energy efficiency of the DAC can be improved by 2.01 times, and its linearity is also effectively improved to 0.65 ENOB (effective number of bits). Among them, ENOB is the number of effective bits, which is a parameter used to measure the conversion quality (in bits) of the data converter relative to the input signal at the Nyquist bandwidth.

Please refer to FIG. 5 , which is a schematic circuit diagram of a local computing unit (local computing unit; LCU) according to an embodiment of the present invention.

In this embodiment, the LCU 103 includes two DAC input switches 410, sixteen memory units 420, four sign bit switches SSW, and a charge processing network 170.

In an exemplary embodiment, there are sixty-four LCUs 103 on the same column of the operation array, and each LCU 103 has sixteen 10T SRAM units as storage locations for filtering operations, of which fifteen groups are idle SRAMs. unit, each operation will only activate one group of SRAM units. During the actual operation process, the required SRAM unit can be switched at any time according to different needs or algorithms.

In this embodiment, the DAC input switch 410 includes bit line enable signals (switches) EN_RBL and EN_RBLB. Among them, the bit line enable signals (switches) EN_RBL and EN_RBLB are used to determine whether to allow receiving input information from the DAC 120. The DAC 120 determines whether to enable the DAC to operate based on the DAC enable signal EN_DAC.

In this embodiment, the memory unit 420 includes complementary bit lines RBL and RBLB, a word line RWL that simultaneously controls whether multiple transfer transistors are turned on during reading, and two symmetrical access control transistors (2T ) and a latch composed of four transistors (4T), where the latch has complementary output terminals Q and QB. In other words, the memory unit 420 is a structure composed of sixteen 10T SRAMs.

In this embodiment, the four symbol bit switches SSW include a DAC input control signal DAC_6 and a control bit that control whether the bit line RBL can transmit input information (signal) to the global bit line GRBL_P in the charge processing network 170 Whether the bit line RBLB can transmit the inverted input information (signal) to the DAC input control signal DAC_6 of the global bit line GRBL_N in the charge processing network 170, and whether the control bit line RBL can transmit the inverted input information (signal) Whether the DAC input control signal DAC_6B of the global bit line GRBL_P in the charge processing network 170 and the control bit line RBLB can transfer the inverted input information (signal) to the global bit line GRBL_N of the charge processing network 170 DAC input control signal DAC_6B.

In this embodiment, the four sign bit switches adopt a cross-coupling configuration, so that the input information (signal) has a positive and negative voltage form.

In this embodiment, the charge processing network 170 has two ADC switch nodes to receive the output information (signal) of the ADC, wherein the output information (signal) passes through an inverter (not shown) with one end receiving an ADC reference voltage. shown) and output the corresponding ADC input control signals ADC_NB, ADCB_NB.

In one embodiment, the inverter can be used to invert the input information (signal) bit by bit (i.e., one's complement), and then add 1 to the result, which is the two's complement of the value. In the two's complement number system, a negative number is represented by its two's complement corresponding positive number. The two's complement number system can be used for addition or subtraction without having to use different calculation methods depending on the sign of the number. Just use an adding circuit to handle the addition of signed numbers. Similarly, subtraction can be expressed by adding one number to the two's complement of another number. Therefore, all kinds of addition and subtraction of signed numbers can be completed by using addition circuits and two's complement circuits.

In this embodiment, the charge processing network 170 also has two switches SEL for making corresponding switches between the bit line RBL and the input control signals ADC_NB and ADCB_NB.

Please refer to FIGS. 6A to 6D . FIGS. 6A to 6D are schematic diagrams of operation steps and timing diagrams of different stages of the LCU according to an embodiment of the present invention.

In this embodiment, the multiplication operation performed by the LCU includes three steps. DAC precharge period T1, multiplication operation period T2 and data transmission period T3.

In this embodiment, before the DAC precharge period T1, the DAC sign bit switch is first set according to the sign bit to be activated, and the bottom-plates of the output capacitors C_RBL and C_RBLB are connected to the bit lines accordingly. RBL, RBLB on. Referring to the operation mode of operation 610, during the DAC precharge period T1, the bit line enable signal (switch) EN_RBL and the DAC enable signal EN_DAC are enabled. The two global read bit lines (global read bit lines) GRBL_P and GRBL_N connected to the output capacitors C_RBL and C_RBLB are initially grounded to release the voltage on the global read bit lines GRBL_P and GRBL_N to the grounded voltage level. (for example, logic 0) to ensure that the voltage difference between the two output capacitors C_RBL and C_RBLB is the voltage at which the DAC is precharged.

In this embodiment, referring to the operation mode of operation 620, during the multiplication operation period T2, the precharge path will be open (that is, the bit line enable signal (switch) EN_RBL is open), and the output capacitors C_RBL and C_RBLB The DAC precharge voltage during precharge period T1 will be maintained. Then, the word line RWL is enabled to perform the multiplication operation. Based on the weight cell data stored in the SRAM, the voltage on the bit line RBL or bit line RBLB will be discharged to zero. After the discharge process is completed, the word line RWL will be disabled to complete the multiplication operation.

In this embodiment, referring to the operation mode of operation 630, during the data transmission period T3, the base plates of the output capacitors C_RBL and C_RBLB are switched to the ADC switch node in the UCPN 170 based on the switch (signal) SEL. The transferred data (charge) is accumulated on the global bit lines GRBL_P and GRBL_N. Correspondingly referring to FIG. 6D , the voltage swings on the global bit lines GRBL_P and GRBL_N gradually decrease as the data transmission period T3 increases. In one embodiment, during the data transmission period T3, the voltage swing on the global bit line GRBL_N is higher than the voltage swing on the global bit line GRBL_P at the beginning. At the end of the data transmission period T3, the voltage swing on the global bit line GRBL_N is higher than the voltage swing on the global bit line GRBL_P. The voltage swing on the bit line GRBL_N will gradually tend to be the same as the voltage swing on the global bit line GRBL_P. The ADC output waveform diagram shows the change of the ADC output signal ADC_OUT. Among them, the output signal ADC_OUT of the ADC is a 7-bit output signal during the data transmission period T3. Finally it is further processed in UCPN170 and converted to digital output. In this embodiment, the plurality of output capacitor pairs C_RBL and C_RBLB have substantially the same capacitance value. In one embodiment, all output capacitors C_RBL and C_RBLB have the same capacitance value to form a unitary capacitor array. During the data transmission period T3, the capacitor array 720 (see FIG. 7) is reusable in the UCPN 170. In one embodiment, in each iterative operation of the SAR ADC, different numbers of output capacitors C_RBL and C_RBLB are gradually switched in a power of 2 to achieve dynamic binary-weighted capacitor switching.

Referring to Figure 6D, the waveform relationship between the DAC precharge period T1, the multiplication operation period T2 and the data transmission period T3 can be referred to Figures 6A to 6C and the above description, and can be clearly interpreted by those skilled in the art, so in This will not be described in detail. In this embodiment, a complete cycle of the clock signal CLK includes a precharge period T1, a multiplication operation period T2 and a data transmission period T3.

Please refer to FIG. 7 , which is a schematic circuit diagram of an integrated charge processing network (unified charge processing network; UCPN) according to an embodiment of the present invention.

In this embodiment, the integrated UCPN 170 is used to not only provide signal processing and data transmission and conversion functions at the same time, but also improve the overall energy usage efficiency and area usage efficiency. Only a single capacitor array 720 is used on multiple complementary bit lines RBL_0, RBLB_0, RBL_63, RBLB_63. The capacitor array 720 includes a plurality of output capacitors C_RBL 0, C_RBL63, C_RBLB, C_RBLB0, and C_RBLB63 to store MAC results during data operations. Under the architecture 720, the capacitor array 720 also serves as a switched capacitor of the ADC, thereby converting the operation results to generate digital information. Accordingly, the present invention improves the area utilization efficiency on the wafer by 1.15 times. In addition, the integrated UCPN 170 also reduces the signal propagation path and effectively reduces the output voltage swing on the global bit lines GRBL_P and GRBL_N caused by the use of multiple output capacitors C_RBL0, C_RBLB0, C_RBL63, and C_RBLB63 for voltage division. It reduces the impact of the data conversion and does not require the use of additional bootstrap circuits to increase the voltage level sent to the comparator for comparison to improve data conversion accuracy and thereby reduce additional area consumption. In other words, under the architecture 710, the integrated UCPN 170 includes a comparator, and its output result OUT is converted into a 7-bits output through the SAR ADC. In particular, the integrated UCPN 170 can effectively avoid the impact of reduced output voltage swing caused by charge redistribution of multiple output capacitors. At the same time, because the capacitor is shared with the SAR ADC, the capacitor overhead on the chip can be saved.

In this embodiment, the integrated UCPN 170 includes a plurality of switch pairs connected in series with a plurality of output capacitor pairs C_RBLO, C_RBLB0, C_RBL63, C_RBLB63, wherein the plurality of switch pairs receive bits through corresponding plurality of inverters. The analog-to-digital conversion control signals (ADC_0, ADCB_0) and (ADC_63, ADCB_63) with complementary logic voltage levels on the element line pairs RBL_0, RBLB_0, RBL_63, and RBLB_63.

In one embodiment, the operation array 420 includes a plurality of bit lines RBL_0, RBLB_0 and a plurality of word lines. The plurality of bit lines RBL_0, RBLB_0, RBL_63, and RBLB_63 include a plurality of bit line pairs with complementary logic voltage levels. The plurality of bit lines RBL_0, RBLB_0, RBL_63, and RBLB_63 are charged to a predetermined voltage by the plurality of DACs during the precharge period to accumulate charges on the plurality of output capacitor pairs C_RBLO, C_RBLB0, C_RBL63, and C_RBLB63, and charge the plurality of output capacitor pairs C_RBLB0, C_RBLB0, C_RBL63, and C_RBLB63. The capacitor bottom plates of the output capacitor pairs C_RBL0, C_RBLB0, C_RBL63, and C_RBLB63 are connected to the corresponding plurality of bit line pairs RBL_0, RBLB_0, RBL_63, and RBLB_63.

In one embodiment, after the precharge period ends, the plurality of word lines determine whether the external data performs corresponding operations with the corresponding plurality of operation arrays based on the word line enable signal. In one embodiment, each of the plurality of DACs determines whether to convert the external data to the external data based on a digital-to-analog conversion enable signal, a bit line enable signal, and an inverted (complementary) bit line enable signal during the precharge period. Input into the corresponding operation array.

In one embodiment, the switch pair includes a first switch and a second switch. The first switch is switched in a predetermined time interval in response to the clock signal to connect the first element line or the first inverter, wherein the first inverter receives the first analog-to-digital conversion control signal. The second switch is switched in a predetermined time interval in response to the clock signal to connect the second bit line or the second inverter, wherein the second inverter receives the second analog-to-digital conversion control signal, wherein the first bit line When the second bit line and the second bit line are executing the operation stage, their corresponding logic voltage levels are complementary to each other.

In one embodiment, the output capacitor pair includes a first output capacitor and a second output capacitor. The first output capacitor electrically connects one end of the first output capacitor to the first element line within a predetermined time interval based on the first switch, wherein the first output capacitor is precharged to a first voltage level.

In one embodiment, the second output capacitor electrically connects one end of the second output capacitor to the second bit line based on the second switch within a predetermined time interval, wherein the first output capacitor is precharged to a second voltage. level, wherein the other end of the first output capacitor and the other end of the second output capacitor are electrically connected to a comparator respectively. The comparator can be used to compare the voltage difference between the first voltage level and the second voltage level.

In one embodiment, the charge processing network includes a first global bit line and a second global bit line. The first global bit line is coupled to the other end of the first output capacitor and the positive end of the comparator. The second global bit line is coupled to the other end of the second output capacitor and the negative terminal of the comparator, wherein before the precharge period, the first global bit line and the second global bit line are grounded, so that the third global bit line The voltage level of a global bit line and the second global bit line is zero.

In one embodiment, during data transmission, the first switch switches one end of the first output capacitor to the first inverter in response to the clock signal during data transmission, and the second switch responds to the clock signal during data transmission. During this period, one end of the second output capacitor is switched to the second inverter. The input data is accumulated on the first global bit line and the second global bit line.

In one embodiment, during the precharging period, the voltage difference between the first output capacitor and the second output capacitor is the voltage at which the DAC is precharged.

In one embodiment, each of the plurality of charge processing networks is electrically connected to a plurality of bit lines, wherein the plurality of bit lines share an output capacitor array composed of a plurality of output capacitor pairs.

In one embodiment, multiple charge processing networks perform backplane sampling on a shared output capacitor capacitance array and perform a charge redistribution process to output corresponding output voltage values on corresponding global bit lines.

In one embodiment, multiple charge processing networks can simultaneously store the results of multiply-and-accumulate operations using a shared output capacitor array during operations using the SAR ADC.

In one embodiment, the output voltage value is based on the average result of the input data after an accumulation operation. Among them, the output voltage value is calculated by the SAR ADC, and the output input data is multiplied by the corresponding weight units in multiple calculation arrays and then averaged.

In summary, the in-memory computing circuit described in the embodiments of the present invention may be an in-memory computing circuit based on using static random access memory. The present invention also provides a static random access memory (CIM SRAM) circuit architecture for in-memory computing with high throughput, high energy and area usage efficiency for terminal AI equipment.

By improving the data processing and conversion circuit, we can overcome the current limitations of CIM SRAM in circuit performance, and improve the circuit's additional energy consumption and limited computational linearity, thereby increasing the overall memory computing speed. Energy efficiency and linearity. In addition, the present invention also provides a UCPN, which simultaneously provides signal processing and data conversion functions to improve energy efficiency, and simultaneously improves circuit performance and chip area utilization efficiency during physical design.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.

100: In-memory arithmetic circuit 101: arithmetic unit 102, 1021, 102N': arithmetic library 103: local arithmetic unit 110, 170: charge processing network 120, 1201, 120M: digital-to-analog converter 130: drive circuit, decoder 140 :Input and output circuit 150A, 150B: CIM SRAM macro 200: CIM SRAM circuit system 410: DAC input switch 420: Memory unit 610, 620, 630: Operation 700, 710, 720: Architecture BIAS: Bias BL, BL1, BLM , RBL_0, RBL_63, RBLB_0, RBLB_63, RBL_N, RBLB_N: bit line C1, C_RBL, C_RBL 0, C_RBL63, C_RBLB, C_RBLB0, C_RBLB63: output capacitor CLK: clock signal CS: current source DIN, DIN1, DINM: input data DAC_6, DAC_6B: DAC input control signals ADC_0, ADC_63, ADC_NB, ADCB_0, ADCB_63, ADCB_NB: ADC input control signals EN, EN1, ENN: word line enable signal EN_DAC: DAC enable signal EN_RBL, EN_RBL0, EN_RBLB, EN_RBLB0, EN_RBLN, EN_RBLBN: bit line enable signal (switch) GRBL_P, GRBL_N: global bit line IN: external data O1, O8, O9, O16, OUT, 160, ADC_OUT: output signal Q, Q_0, Q_63, QB, QB_0 , QB_63: Output terminal SEL, SW0, SW1, SWM: switch SSW: sign bit switch T1: precharge period T2: multiplication operation period T3: data transmission period WL, WL1, WLN, RWL: word line W _{0, 0} , W _1,0 , W _2,0 , W _{13,0, W 14,0 ,} W _15,0 , W _0,63 , W 1,63, W _{2, 63 ,} W _{3, 63} , W _{13, 63} , W _{14, 63} , W _{15, 63} : Weight unit

FIG. 1 is a system block (circuit block) diagram of an in-memory computing circuit according to an embodiment of the present invention. FIG. 2 is a partial system block diagram of an in-memory computing circuit according to an embodiment of the present invention. FIG. 3 is a block diagram of an operation library according to an embodiment of FIG. 2 of the present invention. FIG. 4 is a schematic circuit diagram of a digital-to-analog converter (DAC) according to an embodiment of the present invention. FIG. 5 is a schematic circuit diagram of a local computing unit (LCU) according to an embodiment of the present invention. FIGS. 6A to 6D are schematic diagrams of operation steps and timing diagrams of different stages of the LCU according to an embodiment of the present invention. FIG. 7 is a schematic circuit diagram of an integrated charge processing network (unified charge processing network; UCPN) according to an embodiment of the present invention.

100: In-memory computing circuit

101:Arithmetic unit

102, 1021, 102N’: operation library

110: Charge processing network

120:Digital to analog converter

130: Drive circuit, decoding circuit

140: Input and output circuit

BL, BL1, BLM: bit lines

DIN, DIN1, DINM: input data

EN, EN1, ENN: word line enable signal

WL, WL1, WLN: word lines

Claims (19)

An in-memory computing circuit includes: a plurality of digital-to-analog converters, at least one of the plurality of digital-to-analog converters converts external data into input data, and each of the plurality of digital-to-analog converters A plurality of corresponding output capacitor pairs are connected in series; a plurality of operation arrays, at least one of the plurality of operation arrays receives the input data from both ends and performs an operation to output a first operation value; and a plurality of charge processes network, at least one of the plurality of charge processing networks receives and accumulates the first operation value within a predetermined time interval through a plurality of switch pairs connected in series with the plurality of output capacitor pairs, wherein the The plurality of charge processing networks evenly distribute the charge of the first operation value to at least one of the selected plurality of output capacitor pairs, and divide two of the plurality of at least one of the plurality of output capacitor pairs into The voltage differences at the terminals are compared to output a second operation value, wherein the plurality of operation arrays include: a plurality of bit lines, wherein the plurality of bit lines include a plurality of bit line pairs with complementary logic voltage levels, wherein the plurality of bit lines are charged to a predetermined voltage by the plurality of digital-to-analog converters during a precharge period to accumulate charges on the plurality of output capacitor pairs, and the capacitors of the plurality of output capacitor pairs are The base plate is connected to the corresponding plurality of bit line pairs; and a plurality of word lines. After the precharge period, it is determined based on the word line enable signal whether the external data is consistent with the corresponding plurality of operation arrays. Perform the corresponding operation. The in-memory computing circuit of claim 1, wherein the plurality of digital-to-analog converters include a dynamic binary weighted current source array, and a plurality of logic voltage levels complementary to the plurality of output capacitor pairs in series. Bit line pairs, wherein the input data is current-steering data. The in-memory computing circuit of claim 1, wherein each of the plurality of charge processing networks includes the plurality of switch pairs connected in series with the plurality of output capacitor pairs, wherein the plurality of switch pairs Analog-to-digital conversion control signals with complementary logic voltage levels are received through corresponding plurality of inverters. The in-memory computing circuit of claim 3, wherein the plurality of computing arrays further include: a plurality of computing banks, each of the plurality of computing banks includes a plurality of computing units, the plurality of computing units Each of them includes: a plurality of weight units, wherein the plurality of weight units are connected in parallel to each other, and two ends of each of the plurality of weight units are respectively connected to the corresponding plurality of bit line pairs. At least one of them is electrically connected, and the plurality of weight units store corresponding weights. The in-memory computing circuit as claimed in claim 4, wherein when performing the computation with the corresponding weights of the plurality of weight units being fixed, the computation is performed based on one of the selected weight units, The remaining weight units that are not selected remain idle. The in-memory arithmetic circuit of claim 4, wherein each of the plurality of arithmetic banks further includes: a sign bit switch, the sign bit switch is electrically connected to at least one of the corresponding bit line pairs, wherein the corresponding sign bit switch is determined based on the positive and negative values of the input data before the precharge period The sign bit switches. The in-memory computing circuit of claim 4, wherein each of the computing units is a static random access memory composed of 10 transistors. The in-memory computing circuit of claim 1, wherein the plurality of output capacitor pairs have substantially the same capacitance value. The in-memory computing circuit of claim 1, wherein each of the plurality of digital-to-analog converters is based on a digital-to-analog conversion enable signal, a first element line enable signal, and a second bit during the precharge period. The line enable signal determines whether to input the external data into the corresponding operation array. The in-memory computing circuit of claim 1, wherein the plurality of switch pairs include: a first switch that switches in a predetermined time interval in response to a clock signal to connect the first element line or the first inverter, wherein the first inverter receives a first analog-to-digital conversion control signal; and a second switch switches in response to the clock signal in the predetermined time interval to connect the second bit line or the second inverter , wherein the second inverter receives a second analog-to-digital conversion control signal, wherein the corresponding logic voltage levels of the first bit line and the second bit line are complementary to each other when executing the operation phase. The in-memory computing circuit of claim 10, wherein each of the plurality of output capacitor pairs includes: A first output capacitor, based on the first switch, electrically connects one end of the first output capacitor to the first element line in the predetermined time interval, wherein the first output capacitor is precharged to a a first voltage level; and a second output capacitor, one end of the second output capacitor is electrically connected to the second bit line based on the second switch in the predetermined time interval, wherein the second The output capacitor is precharged to a second voltage level, wherein the other end of the first output capacitor and the other end of the second output capacitor are electrically connected to a comparator respectively to compare the first voltage level. the voltage difference between the voltage level and the second voltage level. The in-memory computing circuit of claim 11, wherein each of the plurality of charge processing networks includes: a first global bit line coupled to the other end of the first output capacitor and the a positive terminal of the comparator; and a second global bit line coupled to the other terminal of the second output capacitor and the negative terminal of the comparator, wherein before the precharge period, the third A global bit line and the second global bit line are grounded, so that the voltage levels on the first global bit line and the second global bit line are zero. The in-memory computing circuit of claim 12, wherein during data transmission, the first switch switches one end of the first output capacitor to the third output capacitor in response to the clock signal during the data transmission. an inverter, and the second switch switches the second input during the data transmission in response to the clock signal. One end of the output capacitor is switched to the second inverter, wherein the input data is accumulated on the first global bit line and the second global bit line. The in-memory computing circuit of claim 11, wherein during the precharge period, the voltage difference between the first output capacitor and the second output capacitor is the voltage at which the digital-to-analog converter is precharged. . The in-memory computing circuit of claim 1, wherein each of the plurality of charge processing networks is electrically connected to the plurality of bit lines, wherein the plurality of bit lines share a common An output capacitor array consists of pairs of output capacitors. The in-memory computing circuit of claim 15, wherein the plurality of charge processing networks perform backplane sampling on the shared output capacitor capacitance array and perform a charge redistribution process to output on the corresponding global bit line corresponding output voltage value. The in-memory computing circuit of claim 16, wherein the plurality of charge processing networks utilize the shared output capacitor capacitor array to simultaneously store the results of the multiplication and addition operations during operations using successive approximation analog-to-digital converters. The in-memory computing circuit as described in claim 16, wherein the output voltage value is based on the average result of the input data after an accumulation operation, wherein the output voltage value is calculated by a successive approximation analog-to-digital converter, The input data is multiplied by the corresponding weight units in the plurality of operation arrays and then averaged. The in-memory computing circuit as described in claim 1 also includes: The decoding circuit receives an input enable signal to decode the encoded external data to obtain the decoded corresponding address; the driving circuit drives the plurality of characters corresponding to the address through a plurality of word lines. At least one of the operation arrays is electrically connected to the digital-to-analog converter through the plurality of word lines; and an input-output circuit, wherein the input-output circuit transmits the external data to the digital-to-analog converter through the plurality of bit lines. At least one of the plurality of digital-to-analog converters.

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