TWI810131B - Method of manufacturing semiconductor structure having contact plug - Google Patents

Abstract

A semiconductor structure and a method of manufacturing a semiconductor structure are provided. The method includes forming an insulation structure over a semiconductor substrate, the insulation structure defining a trench having a trench width. The method also includes forming a first conductive material layer in the trench and over an upper surface of the insulation structure, wherein a portion of the first conductive material layer over the upper surface of the insulation structure has a thickness of greater than half the trench width. The method further includes performing a planarization operation on the first conductive material layer to form a contact plug having a concave upper surface recessed from the upper surface of the insulation structure.

Description

Method for fabricating semiconductor structure with contact plugs

This application claims priority to US Patent Application Nos. 17/687,837 and 17/688,071 (ie, the priority date is "March 7, 2022"), the contents of which are incorporated herein by reference in their entirety.

The disclosure relates to a semiconductor structure and a manufacturing method thereof. In particular, it relates to a semiconductor structure with a contact plug and its preparation method.

Semiconductor components are used in various electronic applications, such as personal computers, mobile phones, digital cameras, or other electronic devices. The size of these semiconductor devices is gradually reduced to meet the increasing demand for computing power. However, during the process of dimension reduction, various problems are added, and such problems continue to increase. Therefore, challenges remain in achieving improved quality, yield, performance and reliability, and reduced complexity.

The above "prior art" description only provides background technology, and does not acknowledge that the above "prior art" description discloses the subject of this disclosure, and does not constitute the prior art of this disclosure, and any description of the above "prior art" is It should not be part of this case.

An embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor base, an isolation structure, a first contact plug and an interconnection layer. The semiconductor base has an upper surface. The isolation structure is disposed on the upper surface of the semiconductor substrate. The first contact plug passes through the isolation structure and has a concave upper surface, and the concave upper surface is recessed from an upper surface of the isolation structure. The interconnection layer directly contacts the concave upper surface of the first contact plug.

Another embodiment of the disclosure provides a method for fabricating a semiconductor structure. The manufacturing method includes forming an isolation structure on a semiconductor substrate, and the isolation structure defines a trench with a trench width. The fabrication method also includes forming a first conductive material layer in the trench and on an upper surface of the isolation structure, wherein a portion of the first conductive material layer on the upper surface of the isolation structure has a thickness greater than that of the trench. A thickness that is half the width of the groove. The manufacturing method further includes performing a planarization process on the first conductive material layer to form a contact plug, the contact plug has a concave upper surface, and the concave upper surface is recessed from the upper surface of the isolation structure.

Another embodiment of the disclosure provides a method for fabricating a semiconductor structure. The preparation method includes forming an isolation structure on a semiconductor substrate, and the isolation structure defines a trench. The manufacturing method also includes forming a titanium nitride layer on an inner wall of the trench and on an upper surface of the isolation structure. The manufacturing method further includes forming a first conductive material layer in the trench and on the titanium nitride layer, wherein a portion of the first conductive material layer on one of the upper surfaces of the isolation structure has a thickness, the thickness more than three times the thickness of one of the titanium nitride layers. The manufacturing method also includes performing a planarization process on the first conductive material layer to form a contact plug, the contact plug has a concave upper surface, and the concave upper surface is recessed from the upper surface of the isolation structure.

In the manufacturing method of the semiconductor structure, with the design of the thickness of a part of the conductive material layer on one of the upper surfaces of an isolation structure, the amount of the conductive material layer can be provided enough to withstand the damage caused by a subsequent planarization process. The resulting dishing effect can therefore minimize the degree of dishing of the concave upper surface of a contact plug formed by the conductive material layer. Therefore, a void or a gap that may have been formed between the contact plug and an interconnect layer due to a deep recess formed on one of the upper surfaces of the contact plug can be avoided, thereby enabling A good electrical connection between the contact plug and the interconnection layer is achieved.

The technical features and advantages of the present disclosure have been broadly summarized above, so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art of the present disclosure should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the disclosure defined by the appended claims.

Embodiments or examples of the present disclosure shown in the drawings will now be described using specific language. It should be understood that the scope of the present disclosure is not intended to be limited thereby. Any modification or improvement of the described embodiments, and any further application of the principles described in this document, would occur as would normally occur to one of ordinary skill in the art. Element numbers may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment apply to another, even if they share the same element number.

It should be understood that although the terms "first", "second", "third" etc. may be used herein to describe various elements, components, regions, layers and/or sections, These elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, a "first element", "component", "region", "layer" or "section" discussed below may be referred to as a second device , component, region, layer or section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that when the terms "comprises" and/or "comprising" are used in this specification, these terms specify the stated features, integers, steps, operations, elements, and/or components. Presence, but not excluding the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups of the above.

FIG. 1 is a schematic cross-sectional view illustrating a semiconductor structure 1 according to some embodiments of the present disclosure. The semiconductor structure 1 includes a semiconductor substrate 10 , an isolation structure 20 , a contact plug 30 and an interconnection structure 40 .

For example, the semiconductor substrate 10 may include silicon, doped silicon, silicon germanium, silicon on insulator, silicon on sapphire, silicon germanium on insulator, silicon carbide, germanium, gallium arsenide, gallium phosphide, arsenic phosphide GaN, InP, InGaP or any other Group IV-IV, III-V or I-VI semiconductor materials.

In some embodiments, the semiconductor substrate 10 includes a peripheral area 10P and an array area (not shown in FIG. 1 ). In some embodiments, the semiconductor substrate 10 may include one or more active regions defined by one or more insulating structures (not shown in FIG. 1 ). In some embodiments, the semiconductor substrate 10 has an upper surface 101 .

The isolation structure 20 may be disposed or formed on the upper surface 101 of the semiconductor substrate 10 . In some embodiments, the isolation structure 20 defines a trench 20T. In some embodiments, the trench 20T extends from an upper surface 201 of the isolation structure 20 to a lower surface 202 of the isolation structure 20 . In some embodiments, the trench 20T extends into a portion of the semiconductor substrate 10 . In some embodiments, trench 20T extends into a portion of the active region of semiconductor substrate 10 . In some embodiments, the trench 20T extends into a portion of the peripheral region 10P of the semiconductor substrate 10 .

In some embodiments, isolation structure 20 includes isolation layers 210 , 220 , 230 . In some embodiments, the trenches 20T pass through the isolation layers 210 , 220 , 230 .

In some embodiments, the isolation layer 210 is disposed or formed on the upper surface 101 of the semiconductor substrate 101 . In some embodiments, the isolation layer 210 can be formed as a stacked layer or a single layer, including silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, fluorine-doped silicate, or the like. In some embodiments, the isolation layer 210 can be or include silicon nitride. In some embodiments, isolation layer 210 has a thickness from about 5 nm to about 10 nm. In some embodiments, isolation layer 210 has a thickness from about 5.5 nm to about 8 nm.

In some embodiments, the isolation layer 220 is disposed or formed on the isolation layer 210 . In some embodiments, the isolation layer 220 can be formed as a stacked layer or as a single layer, including silicon nitride, silicon oxide, silicon oxynitride, flowable oxide, east-fired silazane, doped silicate glass , borosilicate glass, borophosphosilicate glass, plasma enhanced tetra-ethyl orthosilicate (plasma enhanced tetra-ethyl orthosilicate), fluorinated silicate glass, carbon-doped silicon oxide, xerogel ( xerogel), aerogel, amorphous fluorocarbon, organosilicate glass, parylene, bis-benzocyclobutene, polyimide, Porous polymer materials or combinations thereof, but not limited thereto. In some embodiments, the isolation layer 220 can be or include a spin-on dielectric (SOD) layer. In some embodiments, the isolation layer 220 can be or include silicon nitride. In some embodiments, isolation layer 220 has a thickness from about 80 nm to about 120 nm. In some embodiments, isolation layer 220 has a thickness from about 95 nm to about 110 nm.

In some embodiments, the isolation layer 230 is disposed or formed on the isolation layer 220 . In some embodiments, the isolation layer 230 can be formed as a stacked layer or a single layer, including silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, fluorine-doped silicate, or the like. In some embodiments, the isolation layer 230 can be or include silicon nitride. In some embodiments, isolation layer 230 has a thickness from about 10 nm to about 45 nm. In some embodiments, isolation layer 230 has a thickness from about 15 nm to about 35 nm.

The contact plug 30 can pass through the isolation structure 20 . In some embodiments, the contact plug 30 has a concave upper surface 301 recessed from the upper surface 201 of the isolation structure 20 . In some embodiments, the contact plug 30 is formed in the trench 20T of the isolation structure 20 . In some embodiments, the contact plug 30 is disposed on the peripheral region 10P of the semiconductor substrate 10 . In some embodiments, the contact plug 30 may include or include one or more conductive elements. The contact plug 30 may include doped polysilicon, metal or a combination thereof. In some embodiments, the contact plug 30 includes aluminum, tungsten, titanium, titanium nitride, tantalum, tantalum nitride, copper, gold, platinum, cobalt, alloys thereof, silicides thereof, or any combination thereof. In some embodiments, the contact plug 30 includes a conductive layer 310 and a titanium nitride layer 320 .

In some embodiments, the conductive layer 310 fills the trench 20T of the isolation structure 20 . In some embodiments, conductive layer 310 includes tungsten.

In some embodiments, the titanium nitride layer 320 is disposed between the conductive layer 310 and an inner wall 20T1 of the trench 20T of the isolation structure 20 . In some embodiments, conductive layer 310 is conformal on titanium nitride layer 320 . In some embodiments, the titanium nitride layer 320 directly contacts the conductive layer 310 and the inner wall 20T1 of the trench 20T of the isolation structure 20 . In some embodiments, the titanium nitride layer 320 has a thickness T1. In some embodiments, the thickness T1 of the titanium nitride layer 320 is less than about 9 nm. In some embodiments, the thickness T1 of the titanium nitride layer 320 is equal to or less than about 7 nm. In some embodiments, the thickness T1 of the titanium nitride layer 320 is equal to or less than 6 nm. In some embodiments, the thickness T1 of the titanium nitride layer 320 is equal to or less than about 5 nm. In some embodiments, the thickness T1 of the titanium nitride layer 320 is equal to or less than 4 nm. In some embodiments, the thickness T1 of the titanium nitride layer 320 is equal to or less than about 3 nm.

According to some embodiments, the titanium nitride layer 320 physically separates the conductive layer 310 from underlying layers and has a relatively thin thickness. Therefore, the titanium nitride layer 320 not only serves as a carrier, but also provides a relatively low resistance due to its thin thickness, which is beneficial to the conductivity and electrical connection function of the contact plug 30 .

The interconnect layer 40 may directly contact the concave upper surface 301 of the contact plug 30 . In some embodiments, the interconnect layer 40 is disposed or formed on the upper surface 201 of the isolation structure 20 . In some embodiments, interconnect layer 40 includes or includes one or more conductive elements. In some embodiments, interconnect layer 40 includes aluminum, copper, tungsten, cobalt, or alloys thereof. In some embodiments, interconnect layer 40 has a thickness from about 25 nm to about 40 nm. In some embodiments, interconnect layer 40 has a thickness from about 30 nm to about 35 nm.

In some embodiments, the interconnect layer 40 includes a protrusion 410 . The protrusion 410 of the interconnect layer 40 may extend into a portion of the trench 20T of the isolation structure 20 . In some embodiments, the protrusion 410 of the interconnect layer 40 has a convex surface 401 that contacts the concave upper surface 301 of the contact plug 30 . In some embodiments, the convex surface 401 of the protrusion 410 of the interconnect layer 40 conforms to the concave upper surface 301 of the contact plug 30 . In some embodiments, the interface between the convex surface 401 of the protrusion 410 of the interconnect layer 40 and the concave upper surface 301 of the contact plug 30 is disposed within the trench 20T of the isolation structure 20 .

FIG. 2 is a schematic cross-sectional view illustrating a semiconductor structure 2 according to some embodiments of the present disclosure. The semiconductor structure 2 includes a semiconductor substrate 10 , an isolation structure 20 , contact plugs 30 and 50 , an interconnection layer 40 and one or more word line structures 60 .

For example, the semiconductor substrate 10 may include silicon, doped silicon, silicon germanium, silicon on insulator, silicon on sapphire, silicon germanium on insulator, silicon carbide, germanium, gallium arsenide, gallium phosphide, arsenic phosphide GaN, InP, InGaP or any other Group IV-IV, III-V or I-VI semiconductor materials.

In some embodiments, the semiconductor substrate 10 includes a peripheral region 10P and an array region 10A. In some embodiments, the semiconductor substrate 10 may include one or more active regions 110 defined by one or more insulating structures 130 . The insulating structure 130 may include or comprise an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride or a combination thereof. In some embodiments, the semiconductor substrate 10 has an upper surface 101 .

The isolation structure 20 can be disposed or formed on the peripheral region 10P and the array region 10A of the semiconductor substrate 10 . In some embodiments, the isolation structure 20 defines a trench 20T in the peripheral region 10P and a trench 50T in the array region 10A. In some embodiments, the trench 20T and the trench 50T extend from an upper surface 201 of the isolation structure 20 to a lower surface 202 of the isolation structure 20 . In some embodiments, trenches 20T and 50T extend into portions of semiconductor substrate 10 . In some embodiments, the trench 20T extends into a portion of the peripheral region 10P of the semiconductor substrate 10 . In some embodiments, the trench 50T extends into a portion of the array region 10A of the semiconductor substrate 10 . In some embodiments, the trench 50T extends into a portion of the active region 110 of the semiconductor substrate 10 .

In some embodiments, isolation structure 20 includes isolation layers 210 , 220 , 230 . In some embodiments, the trench 20T and the trench 50T pass through the isolation layers 210 , 220 , 230 .

In some embodiments, the isolation layer 210 is disposed or formed on the upper surface 101 of the semiconductor substrate 101 . In some embodiments, the isolation layer 210 can be formed as a stacked layer or a single layer, including silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, fluorine-doped silicate, or the like. In some embodiments, the isolation layer 210 can be or include silicon nitride. In some embodiments, isolation layer 210 has a thickness from about 5 nm to about 10 nm. In some embodiments, isolation layer 210 has a thickness from about 5.5 nm to about 8 nm.

In some embodiments, the isolation layer 220 is disposed or formed on the isolation layer 210 . In some embodiments, the isolation layer 220 can be formed as a stacked layer or as a single layer, including silicon nitride, silicon oxide, silicon oxynitride, flowable oxide, east-fired silazane, doped silicate glass , borosilicate glass, borophosphosilicate glass, plasma enhanced tetra-ethyl orthosilicate (plasma enhanced tetra-ethyl orthosilicate), fluorinated silicate glass, carbon-doped silicon oxide, xerogel ( xerogel), aerogel, amorphous fluorocarbon, organosilicate glass, parylene, bis-benzocyclobutene, polyimide, Porous polymer materials or combinations thereof, but not limited thereto. In some embodiments, the isolation layer 220 can be or include a spin-on dielectric (SOD) layer. In some embodiments, the isolation layer 220 can be or include silicon nitride. In some embodiments, isolation layer 220 has a thickness from about 80 nm to about 120 nm. In some embodiments, isolation layer 220 has a thickness from about 95 nm to about 110 nm.

In some embodiments, the isolation layer 230 is disposed or formed on the isolation layer 220 . In some embodiments, the isolation layer 230 can be formed as a stacked layer or a single layer, including silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, fluorine-doped silicate, or the like. In some embodiments, the isolation layer 230 can be or include silicon nitride. In some embodiments, isolation layer 230 has a thickness from about 10 nm to about 45 nm. In some embodiments, isolation layer 230 has a thickness from about 15 nm to about 35 nm.

The contact plug 30 can pass through the isolation structure 20 . In some embodiments, the contact plug 30 has a concave upper surface 301 recessed from the upper surface 201 of the isolation structure 20 . In some embodiments, the contact plug 30 is formed in the trench 20T of the isolation structure 20 . In some embodiments, the contact plug 30 is disposed on the peripheral region 10P of the semiconductor substrate 10 . In some embodiments, the contact plug 30 may include or include one or more conductive elements. The contact plug 30 may include doped polysilicon, metal or a combination thereof. In some embodiments, the contact plug 30 includes aluminum, tungsten, titanium, titanium nitride, tantalum, tantalum nitride, copper, gold, platinum, cobalt, alloys thereof, silicides thereof, or any combination thereof. In some embodiments, the contact plug 30 includes a conductive layer 310 and a titanium nitride layer 320 .

In some embodiments, the conductive layer 310 fills the trench 20T of the isolation structure 20 . In some embodiments, conductive layer 310 includes tungsten.

In some embodiments, the titanium nitride layer 320 is disposed between the conductive layer 310 and an inner wall 20T1 of the trench 20T of the isolation structure 20 . In some embodiments, conductive layer 310 is conformal on titanium nitride layer 320 . In some embodiments, the titanium nitride layer 320 directly contacts the conductive layer 310 and the inner wall 20T1 of the trench 20T of the isolation structure 20 . In some embodiments, the titanium nitride layer 320 has a thickness T1. In some embodiments, the thickness T1 of the titanium nitride layer 320 is less than about 9 nm. In some embodiments, the thickness T1 of the titanium nitride layer 320 is equal to or less than about 7 nm. In some embodiments, the thickness T1 of the titanium nitride layer 320 is equal to or less than 6 nm. In some embodiments, the thickness T1 of the titanium nitride layer 320 is equal to or less than about 5 nm. In some embodiments, the thickness T1 of the titanium nitride layer 320 is equal to or less than 4 nm. In some embodiments, the thickness T1 of the titanium nitride layer 320 is equal to or less than about 3 nm.

The interconnect layer 40 may directly contact the concave upper surface 301 of the contact plug 30 . In some embodiments, the interconnect layer 40 is disposed or formed on the upper surface 201 of the isolation structure 20 . In some embodiments, interconnect layer 40 includes or includes one or more conductive elements. In some embodiments, interconnect layer 40 includes aluminum, copper, tungsten, cobalt, or alloys thereof. In some embodiments, interconnect layer 40 has a thickness from about 25 nm to about 40 nm. In some embodiments, interconnect layer 40 has a thickness from about 30 nm to about 35 nm.

In some embodiments, the interconnect layer 40 includes a protrusion 410 . The protrusion 410 of the interconnect layer 40 may extend into a portion of the trench 20T of the isolation structure 20 . In some embodiments, the protrusion 410 of the interconnect layer 40 has a convex surface 401 that contacts the concave upper surface 301 of the contact plug 30 . In some embodiments, the convex surface 401 of the protrusion 410 of the interconnect layer 40 conforms to the concave upper surface 301 of the contact plug 30 . In some embodiments, the interface between the convex surface 401 of the protrusion 410 of the interconnect layer 40 and the concave upper surface 301 of the contact plug 30 is disposed within the trench 20T of the isolation structure 20 .

The contact plug 50 can pass through the isolation structure 20 . In some embodiments, the contact plug 50 has a concave upper surface 501 recessed from the upper surface 201 of the isolation structure 20 . In some embodiments, the contact plug 50 is formed in the trench 50T of the isolation structure 20 . In some embodiments, the contact plug 30 is disposed on the array region 10A of the semiconductor substrate 10 . In some embodiments, the contact plug 50 may include or include one or more conductive elements. The contact plug 50 may comprise doped polysilicon, metal or a combination thereof. In some embodiments, the contact plug 50 includes aluminum, tungsten, titanium, titanium nitride, tantalum, tantalum nitride, copper, gold, platinum, cobalt, alloys thereof, silicides thereof, or any combination thereof. In some embodiments, the contact plug 50 includes a conductive layer 510 and a titanium nitride layer 520 .

In some embodiments, the conductive layer 510 fills the trench 50T of the isolation structure 20 . In some embodiments, conductive layer 510 includes tungsten.

In some embodiments, the titanium nitride layer 520 is disposed between the conductive layer 510 and an inner wall 50T1 of the trench 50T of the isolation structure 20 . In some embodiments, conductive layer 510 is conformal on titanium nitride layer 320 . In some embodiments, the titanium nitride layer 520 directly contacts the conductive layer 510 and the inner wall 50T1 of the trench 50T of the isolation structure 20 . In some embodiments, the titanium nitride layer 520 has a thickness T2. In some embodiments, the thickness T2 of the titanium nitride layer 520 is less than about 9 nm. In some embodiments, the thickness T2 of the titanium nitride layer 520 is equal to or less than about 7 nm. In some embodiments, the thickness T2 of the titanium nitride layer 520 is equal to or less than 6 nm. In some embodiments, the thickness T2 of the titanium nitride layer 520 is equal to or less than about 5 nm. In some embodiments, the thickness T2 of the titanium nitride layer 520 is equal to or less than 4 nm. In some embodiments, the thickness T1 of the titanium nitride layer 320 is equal to or less than about 3 nm. In some embodiments, the thickness T1 of the titanium nitride layer 320 and the thickness T2 of the titanium nitride layer 520 may be the same or different.

According to some embodiments, the titanium nitride layer 520 physically separates the conductive layer 510 from underlying layers and has a relatively thin thickness. Therefore, the titanium nitride layer 520 not only serves as a carrier, but also provides a relatively low resistance due to its thin thickness, which is beneficial to the conductivity and electrical connection function of the contact plug 50 .

In some embodiments, the interconnect layer 40 directly contacts the concave upper surface 501 of the contact plug 50 . In some embodiments, the interconnect layer 40 further includes a protrusion 420 . The protrusion 420 of the interconnect layer 40 may extend into a portion of the trench 50T of the isolation structure 20 . In some embodiments, the protrusion 420 of the interconnect layer 40 has a convex surface 402 that contacts the concave upper surface 501 of the contact plug 50 . In some embodiments, the convex surface 402 of the protrusion 420 of the interconnect layer 40 conforms to the concave upper surface 501 of the contact plug 50 . In some embodiments, the interface between the convex surface 402 of the protrusion 420 of the interconnect layer 40 and the concave upper surface 501 of the contact plug 50 is disposed within the trench 50T of the isolation structure 20 .

In some embodiments, the contact plug 50 is electrically connected to the interconnection layer 40 . In some embodiments, the contact plug 50 is electrically connected to the active region 110 of the semiconductor substrate 10 . In some embodiments, the contact plug 50 can be electrically connected to the word line structure 60 . In some embodiments, the interconnection layer 40 electrically connecting the contact plug 30 and the contact plug 50 can provide an electrical connection between a plurality of elements or components on the peripheral region 10P and a plurality of elements or components on the array region 10A. sexual connection.

In some embodiments, the word line structure 60 includes a word line isolation layer 610 , a conductive layer 630 and a capping layer 650 .

In some embodiments, the word line isolation layer 610 may be formed to conformally cover an inner surface of a word line trench in the semiconductor substrate 10 . In some embodiments, for example, the word line isolation layer 610 may comprise or include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide oxide, fluorine-doped silicate, or the like.

In some embodiments, a conductive layer 630 may be formed on the word line isolation layer 610 in the word line trench. In some embodiments, the conductive layer 630 can be or include a conductive material, such as doped polysilicon, metal or metal silicide. For example, the metal can be aluminum, copper, tungsten, cobalt, or alloys thereof. For example, the metal silicide may be nickel silicide, platinum silicide, titanium silicide, molybdenum silicide, cobalt silicide, tantalum silicide, tungsten silicide, or the like.

In some embodiments, a cap layer 650 may be formed on the conductive layer 630 in the word line trench. An upper surface of the capping layer 650 may be at the same height as the upper surface 101 of the semiconductor substrate 10 . The capping layer 650 can form a stacked layer or a single layer. In some embodiments, capping layer 650 may comprise or include barium strontium titanate, lead zirconium titanate, titanium oxide, aluminum oxide, hafnium oxide, for example. , yttrium oxide, zirconium oxide, silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, fluorine-doped silicate or the like.

FIG. 3 is a schematic cross-sectional view illustrating a semiconductor structure 3 according to some embodiments of the present disclosure. The semiconductor structure 3 includes a semiconductor substrate 10 , an isolation structure 20 , contact plugs 30 and 50 , an interconnection layer 40 and one or more bit line structures 70 .

For example, the semiconductor substrate 10 may include silicon, doped silicon, silicon germanium, silicon on insulator, silicon on sapphire, silicon germanium on insulator, silicon carbide, germanium, gallium arsenide, gallium phosphide, arsenic phosphide GaN, InP, InGaP or any other Group IV-IV, III-V or I-VI semiconductor materials.

In some embodiments, the semiconductor substrate 10 includes a peripheral region 10P and an array region 10A. In some embodiments, the semiconductor substrate 10 may include one or more active regions 110 defined by one or more insulating structures 130 . The insulating structure 130 may include or comprise an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride or a combination thereof. In some embodiments, the semiconductor substrate 10 has an upper surface 101 .

The isolation structure 20 can be disposed or formed on the peripheral region 10P and the array region 10A of the semiconductor substrate 10 . In some embodiments, the isolation structure 20 defines a trench 20T in the peripheral region 10P and a trench 50T in the array region 10A. In some embodiments, the trench 20T and the trench 50T extend from an upper surface 201 of the isolation structure 20 to a lower surface 202 of the isolation structure 20 . In some embodiments, trenches 20T and 50T extend into portions of semiconductor substrate 10 . In some embodiments, the trench 20T extends into a portion of the peripheral region 10P of the semiconductor substrate 10 . In some embodiments, the trench 50T extends into a portion of the array region 10A of the semiconductor substrate 10 . In some embodiments, the trench 50T extends into a portion of the active region 110 of the semiconductor substrate 10 .

In some embodiments, isolation structure 20 includes isolation layers 210 , 220 , 230 . In some embodiments, the trench 20T and the trench 50T pass through the isolation layers 210 , 220 , 230 .

In some embodiments, the isolation layer 210 is disposed or formed on the upper surface 101 of the semiconductor substrate 101 . In some embodiments, the isolation layer 210 can be formed as a stacked layer or a single layer, including silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, fluorine-doped silicate, or the like. In some embodiments, the isolation layer 210 can be or include silicon nitride. In some embodiments, isolation layer 210 has a thickness from about 5 nm to about 10 nm. In some embodiments, isolation layer 210 has a thickness from about 5.5 nm to about 8 nm.

In some embodiments, the isolation layer 220 is disposed or formed on the isolation layer 210 . In some embodiments, the isolation layer 220 can be formed as a stacked layer or as a single layer, including silicon nitride, silicon oxide, silicon oxynitride, flowable oxide, east-fired silazane, doped silicate glass , borosilicate glass, borophosphosilicate glass, plasma enhanced tetra-ethyl orthosilicate (plasma enhanced tetra-ethyl orthosilicate), fluorinated silicate glass, carbon-doped silicon oxide, xerogel ( xerogel), aerogel, amorphous fluorocarbon, organosilicate glass, parylene, bis-benzocyclobutene, polyimide, Porous polymer materials or combinations thereof, but not limited thereto. In some embodiments, the isolation layer 220 can be or include a spin-on dielectric (SOD) layer. In some embodiments, the isolation layer 220 can be or include silicon nitride. In some embodiments, isolation layer 220 has a thickness from about 80 nm to about 120 nm. In some embodiments, isolation layer 220 has a thickness from about 95 nm to about 110 nm.

In some embodiments, the isolation layer 230 is disposed or formed on the isolation layer 220 . In some embodiments, the isolation layer 230 can be formed as a stacked layer or a single layer, including silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, fluorine-doped silicate, or the like. In some embodiments, the isolation layer 230 can be or include silicon nitride. In some embodiments, isolation layer 230 has a thickness from about 10 nm to about 45 nm. In some embodiments, isolation layer 230 has a thickness from about 15 nm to about 35 nm.

The contact plug 30 can pass through the isolation structure 20 . In some embodiments, the contact plug 30 has a concave upper surface 301 recessed from the upper surface 201 of the isolation structure 20 . In some embodiments, the contact plug 30 is formed in the trench 20T of the isolation structure 20 . In some embodiments, the contact plug 30 is disposed on the peripheral region 10P of the semiconductor substrate 10 . In some embodiments, the contact plug 30 may include or include one or more conductive elements. The contact plug 30 may include doped polysilicon, metal or a combination thereof. In some embodiments, the contact plug 30 includes aluminum, tungsten, titanium, titanium nitride, tantalum, tantalum nitride, copper, gold, platinum, cobalt, alloys thereof, silicides thereof, or any combination thereof. In some embodiments, the contact plug 30 includes a conductive layer 310 and a titanium nitride layer 320 .

In some embodiments, the conductive layer 310 fills the trench 20T of the isolation structure 20 . In some embodiments, conductive layer 310 includes tungsten.

In some embodiments, the titanium nitride layer 320 is disposed between the conductive layer 310 and an inner wall 20T1 of the trench 20T of the isolation structure 20 . In some embodiments, conductive layer 310 is conformal on titanium nitride layer 320 . In some embodiments, the titanium nitride layer 320 directly contacts the conductive layer 310 and the inner wall 20T1 of the trench 20T of the isolation structure 20 . In some embodiments, the titanium nitride layer 320 has a thickness T1. In some embodiments, the thickness T1 of the titanium nitride layer 320 is less than about 9 nm. In some embodiments, the thickness T1 of the titanium nitride layer 320 is equal to or less than about 7 nm. In some embodiments, the thickness T1 of the titanium nitride layer 320 is equal to or less than 6 nm. In some embodiments, the thickness T1 of the titanium nitride layer 320 is equal to or less than about 5 nm. In some embodiments, the thickness T1 of the titanium nitride layer 320 is equal to or less than 4 nm. In some embodiments, the thickness T1 of the titanium nitride layer 320 is equal to or less than about 3 nm.

The interconnect layer 40 may directly contact the concave upper surface 301 of the contact plug 30 . In some embodiments, the interconnect layer 40 is disposed or formed on the upper surface 201 of the isolation structure 20 . In some embodiments, interconnect layer 40 includes or includes one or more conductive elements. In some embodiments, interconnect layer 40 includes aluminum, copper, tungsten, cobalt, or alloys thereof. In some embodiments, interconnect layer 40 has a thickness from about 25 nm to about 40 nm. In some embodiments, interconnect layer 40 has a thickness from about 30 nm to about 35 nm.

In some embodiments, the interconnect layer 40 includes a protrusion 410 . The protrusion 410 of the interconnect layer 40 may extend into a portion of the trench 20T of the isolation structure 20 . In some embodiments, the protrusion 410 of the interconnect layer 40 has a convex surface 401 that contacts the concave upper surface 301 of the contact plug 30 . In some embodiments, the convex surface 401 of the protrusion 410 of the interconnect layer 40 conforms to the concave upper surface 301 of the contact plug 30 . In some embodiments, the interface between the convex surface 401 of the protrusion 410 of the interconnect layer 40 and the concave upper surface 301 of the contact plug 30 is disposed within the trench 20T of the isolation structure 20 .

The contact plug 50 can pass through the isolation structure 20 . In some embodiments, the contact plug 50 has a concave upper surface 501 recessed from the upper surface 201 of the isolation structure 20 . In some embodiments, the contact plug 50 is formed in the trench 50T of the isolation structure 20 . In some embodiments, the contact plug 30 is disposed on the array region 10A of the semiconductor substrate 10 . In some embodiments, the contact plug 50 may include or include one or more conductive elements. The contact plug 50 may comprise doped polysilicon, metal or a combination thereof. In some embodiments, the contact plug 50 includes aluminum, tungsten, titanium, titanium nitride, tantalum, tantalum nitride, copper, gold, platinum, cobalt, alloys thereof, silicides thereof, or any combination thereof.

In some embodiments, the contact plug 50 includes a conductive layer filled in the trench 50T of the isolation structure 20 . In some embodiments, the contact plug 50 may include tungsten. In some embodiments, the contact plug 50 may include a conductive layer and a titanium nitride layer (not shown in FIG. 3 ), and the titanium nitride layer is disposed between the conductive layer and an inner wall 50T1 of the trench 50T. .

In some embodiments, the interconnect layer 40 directly contacts the concave upper surface 501 of the contact plug 50 . In some embodiments, the interconnect layer 40 further includes a protrusion 420 . The protrusion 420 of the interconnect layer 40 may extend into a portion of the trench 50T of the isolation structure 20 . In some embodiments, the protrusion 420 of the interconnect layer 40 has a convex surface 402 that contacts the concave upper surface 501 of the contact plug 50 . In some embodiments, the convex surface 402 of the protrusion 420 of the interconnect layer 40 conforms to the concave upper surface 501 of the contact plug 50 . In some embodiments, the interface between the convex surface 402 of the protrusion 420 of the interconnect layer 40 and the concave upper surface 501 of the contact plug 50 is disposed within the trench 50T of the isolation structure 20 .

In some embodiments, the contact plug 50 is electrically connected to the interconnection layer 40 . In some embodiments, the contact plug 50 is electrically connected to the active region 110 of the semiconductor substrate 10 . In some embodiments, the contact plug 50 can be electrically connected to the bit line structure 70 . In some embodiments, the interconnection layer 40 electrically connecting the contact plug 30 and the contact plug 50 can provide an electrical connection between a plurality of elements or components on the peripheral region 10P and a plurality of elements or components on the array region 10A. sexual connection.

In some embodiments, the bitline structure 70 includes a bitline contact 710 and conductive layers 720 , 730 . In some embodiments, the combination of conductive layers 720, 730 is considered a bit line.

In some embodiments, the bit line contact 710 is formed in an opening defined by the active region 110 of the semiconductor substrate 10 and the insulating structures 130 . The bit line contact 710 may comprise a conductive material such as doped polysilicon, a metal, or a metal silicide. For example, the metal can be aluminum, copper, tungsten, cobalt, or alloys thereof. For example, the metal silicide may be nickel silicide, platinum silicide, titanium silicide, molybdenum silicide, cobalt silicide, tantalum silicide, tungsten silicide, or the like. The bit line contact 710 can be electrically connected to the conductive plug 50 .

In some embodiments, a conductive layer 720 is disposed or formed on the bit line contact 710 . For example, the conductive layer 720 may include polysilicon or titanium nitride.

In some embodiments, conductive layer 730 is disposed or formed on conductive layer 720 . For example, the conductive layer 730 may include copper, nickel, cobalt, aluminum or tungsten.

4A, 4B, 4C, 4D, 4E, 4F, and 4G are schematic cross-sectional views illustrating different stages of the method for preparing the semiconductor structure 1 according to some embodiments of the present disclosure.

Please refer to FIG. 4A , an isolation structure 20 may be formed on a semiconductor substrate 10 . In some embodiments, the isolation structure 20 defines a trench 20T having a trench width W1. In some embodiments, the formation technique of trench 20T includes performing one or more etching processes.

In some embodiments, the trench width W1 can be regarded as an average trench width. In some embodiments, the trench width W1 can be regarded as a minimum trench width. In some embodiments, the trench width W1 can be regarded as a maximum trench width. In some embodiments, the trench width W1 may be regarded as a width of the opening of the trench 20T. In some embodiments, the trench width W1 of the trench 20T of the isolation structure 20 is greater than 32 nm. In some embodiments, the trench width W1 of the trench 20T of the isolation structure 20 is from about 35 nm to about 50 nm. In some embodiments, the trench width W1 of the trench 20T of the isolation structure 20 is from about 40 nm to about 46 nm.

Referring to FIG. 4B , a titanium nitride layer 320A may be formed on an inner wall 20T1 of the trench 20T. In some embodiments, the titanium nitride layer 320A is formed on the inner wall 20T1 of the trench 20T and above an upper surface 201 of the isolation structure 20 . In some embodiments, the titanium nitride layer 320A has a thickness T1 less than about 9 nm. In some embodiments, the thickness T1 of the titanium nitride layer 320A is equal to or less than 7 nm. In some embodiments, the thickness T1 of the titanium nitride layer 320A is equal to or less than 6 nm. In some embodiments, the thickness T1 of the titanium nitride layer 320A is equal to or less than 5 nm. In some embodiments, the thickness T1 of the titanium nitride layer 320A is equal to or less than 4 nm. In some embodiments, the thickness T1 of the titanium nitride layer 320A is equal to or less than 3 nm. In some embodiments, the fabrication technique of the titanium nitride layer 320A includes a chemical vapor deposition (CVD) process.

According to some embodiments of the present disclosure, the thickness T1 of the titanium nitride layer 320A is relatively thin, so that the resistance of the subsequently formed contact plug 30 can provide a minimum satisfactory value. The thickness T1 of the titanium nitride layer 320A can be as thin as possible, as long as it can still provide sufficient barrier function.

Referring to FIG. 4C , a conductive material layer 310A may be formed on the titanium nitride layer 320A. In some embodiments, the layer of conductive material 310A is conformally formed on the titanium nitride layer 320A. In some embodiments, the conductive material layer 310A is also formed on the upper surface 201 of the isolation structure 20 . In some embodiments, the conductive material layer 310A can be or include doped polysilicon, aluminum, tungsten, copper, gold, platinum, cobalt, alloys thereof, or any combination thereof. In some embodiments, the layer of conductive material 310A includes tungsten. In some embodiments, the fabrication technique of the conductive material layer 310A includes a chemical vapor deposition (CVD) process.

Referring to FIG. 4D , an etching process P1 may be performed on the conductive material layer 310A to form a thinned conductive material layer 310A′. In some embodiments, after the conductive material layer 310A is deposited in the trench 20T and over the upper surface 201 of the isolation structure 20, some portion of the conductive material layer 310A may be formed directly over the trench 20T, thereby plugging the trench. This opening of the slot 20T. Etching process P1 may etch away portions of conductive material layer 310A directly above trench 20T to "open up" trench 20T so that formation of the next plurality of materials inside trench 20T may be successfully performed. layer (eg conductive material layer 310B).

Referring to FIG. 4E , a conductive material layer 310B may be formed in the trench 20T and on the upper surface 201 of the isolation structure 20 . In some embodiments, conductive material layer 310B is formed in trench 20T and on titanium nitride layer 320 . In some embodiments, conductive material layer 310B is formed directly on conductive material layer 310A′ in trench 20T. In some embodiments, after the etching process P1 is performed, the conductive material layer 310B is directly formed on the conductive material layer 310A′. In some embodiments, the fabrication technique of the conductive material layer 310B includes a chemical vapor deposition (CVD) process. In some embodiments, the conductive material layer 310B includes a portion 310B1 disposed within the trench 20T and a portion 310B2 disposed on the upper surface 201 of the isolation structure 20 .

In some embodiments, the portion 301B2 of the conductive material layer 310B on the upper surface 201 of the isolation structure 20 has a thickness T3. In some embodiments, the thickness T3 of the portion 310B2 of the conductive material layer 310B is greater than about half of the trench width W1 . In some embodiments, the thickness T3 of the portion 310B2 of the conductive material layer 310B is greater than about 0.6 times the trench width W1 . In some embodiments, the thickness T3 of the portion 310B2 of the conductive material layer 310B is greater than about 0.7 times the trench width W1 . In some embodiments, the thickness T3 of the portion 301B2 of the conductive material layer 310B on the upper surface 201 of the isolation structure 20 is greater than about 23 nm. In some embodiments, the thickness T3 of the portion 310B2 of the layer of conductive material 310B is greater than about 31 nm. In some embodiments, the thickness T3 of the portion 310B2 of the conductive material layer 310B is greater than about 33 nm. In some embodiments, the thickness T3 of the portion 310B2 of the layer of conductive material 310B is greater than about 36 nm.

In some embodiments, the thickness T3 of the portion 310B2 of the conductive material layer 310B is greater than about three times the thickness T1 of the titanium nitride layer 320A. In some embodiments, the thickness T3 of the portion 310B2 of the conductive material layer 310B is greater than about four times the thickness T1 of the titanium nitride layer 320A. In some embodiments, the thickness T3 of the portion 310B2 of the conductive material layer 310B is greater than about five times the thickness T1 of the titanium nitride layer 320A. In some embodiments, the thickness T3 of the portion 310B2 of the conductive material layer 310B is greater than about eight times the thickness T1 of the titanium nitride layer 320A.

4F, a planarization process P2 can be performed on the conductive material layer 310B to form a contact plug 30, the contact plug 30 has a concave upper surface 301, and the concave upper surface 301 is formed from the upper surface of the isolation structure 20 201 sunken. In some embodiments, the planarization process P2 may be or include a chemical mechanical polishing (CMP) process. In some embodiments, a portion of the titanium nitride layer 320A on the upper surface 201 of the isolation structure 20 is completely removed by a CMP process to form a titanium nitride layer 320 in the trench 20T. In some embodiments, the portion 310B2 of the conductive material layer 310B on the upper surface 201 of the isolation structure 20 is completely removed by the CMP process P2. In some embodiments, a portion of the conductive material layer 310A′ on the upper surface 201 of the isolation structure 20 is completely removed by a CMP process. Therefore, a contact plug 30 including the conductive layer 310 and the TiN layer 320 is formed in the trench 20T of the isolation structure 20 .

Referring to FIG. 4G , an interconnection layer 40 may be directly formed on the concave upper surface 301 of the contact plug 30 . In some embodiments, the fabrication technique of the interconnection layer 40 includes a physical vapor deposition (PVD) process. In some embodiments, interconnect layer 40 includes aluminum, copper, tungsten, cobalt, or alloys thereof.

According to some aspects of the present disclosure, with the design of the thickness T3 of the portion 310B2 of the conductive material layer 310B on the upper surface 201 of the isolation structure 20, the amount of the conductive material layer 310B can be sufficient to withstand the disc caused by the planarization process P2. Shaped dishing effect (dishing effect), so the degree of dishing by the concave upper surface 301 can be minimized. Therefore, a hole (void) or a gap (gap) that may have been formed between the contact plug 30 and the interconnection layer 40 due to a deep recess formed on one of the upper surfaces of the contact plug 30 can be avoided, thereby enabling A good electrical connection between the contact plug 30 and the interconnection layer 40 is achieved.

In addition, in order to enhance the ability to withstand the dishing effect caused by the planarization process P2 and thereby reduce the degree of depression on the concave upper surface 301 of the contact plug 30, the titanium nitride layer 320A is formed on the upper surface 201 of the isolation structure 20 The thickness T1 is relatively thick. However, the relative thickness of the titanium nitride layer 320 remaining in the contact plug 30 undesirably increases the resistance of the contact plug 30 . In other words, in order to increase the conductivity of the contact plug 30 or reduce the resistance, the thickness T1 of the titanium nitride layer 320 should be as small as possible. According to some embodiments of the present disclosure, with the design of the thickness T3 of the portion 310B2 of the conductive material layer 310B on the upper surface 201 of the isolation structure 20, the amount of the conductive material layer 310B may be sufficient to increase the thickness of the relatively thin titanium nitride The support of the layer 320A can better withstand the dishing effect caused by the planarization process P2, thereby minimizing the degree of dishing caused by the concave upper surface 301 . Therefore, by providing the contact plug 30 with an increased conductivity or a reduced resistance, a satisfactory electrical connection between the contact plug 30 and the interconnection layer 40 can be further achieved.

FIG. 5 is a schematic flow diagram illustrating a method 500 for fabricating a semiconductor structure according to some embodiments of the present disclosure.

The manufacturing method 500 starts with step S51, which is to form an isolation structure on a semiconductor substrate. In some embodiments, the isolation structure defines a trench having a trench width.

Fabrication method 500 continues with step S52, which is a first conductive material layer is formed in the trench and on an upper surface of the isolation structure. In some embodiments, a portion of the first conductive material layer on the upper surface of the isolation structure has a thickness greater than half the width of the trench.

The manufacturing method 500 continues with step S53, which is to perform a planarization process on the first conductive material layer to form a contact plug, the contact plug has a concave upper surface from the isolation structure. The upper surface is sunken.

The preparation method 500 is just an example, and is not intended to limit the present disclosure beyond the scope clearly stated in the patent claims. Additional operations may be provided before, during, or after each step of manufacturing method 500, and some of the steps described may be replaced, eliminated, or moved for such additional embodiments of the manufacturing method. In some embodiments, the preparation method 500 may further include some steps not shown in FIG. 5 . In some embodiments, preparation method 500 may include one or more steps described in FIG. 5 .

FIG. 6 is a schematic flow diagram illustrating a method 600 for fabricating a semiconductor structure according to some embodiments of the present disclosure.

The fabrication method 600 starts with step S61, which is to form an isolation structure on a semiconductor substrate. In some embodiments, the isolation structure defines a trench.

Fabrication method 600 continues with step S62, in which a TiN layer is formed on an inner wall of the trench and on an upper surface of the isolation structure.

Fabrication method 600 continues with step S63, which is a first conductive material layer is formed in the trench and on the titanium nitride layer. In some embodiments, a portion of the first layer of conductive material on an upper surface of one of the isolation structures has greater than about three times the thickness of one of the titanium nitride layers.

The fabrication method 600 continues with step S64, which is to perform a planarization process on the first conductive material layer to form a contact plug having a concave upper surface from the isolation structure. The upper surface is sunken.

The preparation method 600 is just an example, and is not intended to limit the present disclosure beyond the scope clearly stated in the patent claims. Additional operations may be provided before, during, or after each step of manufacturing method 600, and some of the steps described may be replaced, eliminated, or moved for such additional embodiments of the manufacturing method. In some embodiments, the preparation method 600 may further include some steps not shown in FIG. 6 . In some embodiments, preparation method 600 may include one or more steps described in FIG. 6 .

An embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor base, an isolation structure, a first contact plug and an interconnection layer. The semiconductor base has an upper surface. The isolation structure is disposed on the upper surface of the semiconductor substrate. The first contact plug passes through the isolation structure and has a concave upper surface, and the concave upper surface is recessed from an upper surface of the isolation structure. The interconnection layer directly contacts the concave upper surface of the first contact plug.

Another embodiment of the disclosure provides a method for fabricating a semiconductor structure. The manufacturing method includes forming an isolation structure on a semiconductor substrate, and the isolation structure defines a trench with a trench width. The fabrication method also includes forming a first conductive material layer in the trench and on an upper surface of the isolation structure, wherein a portion of the first conductive material layer on the upper surface of the isolation structure has a thickness greater than that of the trench. A thickness that is half the width of the groove. The manufacturing method further includes performing a planarization process on the first conductive material layer to form a contact plug, the contact plug has a concave upper surface, and the concave upper surface is recessed from the upper surface of the isolation structure.

Another embodiment of the disclosure provides a method for fabricating a semiconductor structure. The preparation method includes forming an isolation structure on a semiconductor substrate, and the isolation structure defines a trench. The manufacturing method also includes forming a titanium nitride layer on an inner wall of the trench and on an upper surface of the isolation structure. The manufacturing method further includes forming a first conductive material layer in the trench and on the titanium nitride layer, wherein a portion of the first conductive material layer on one of the upper surfaces of the isolation structure has a thickness, the thickness more than three times the thickness of one of the titanium nitride layers. The manufacturing method also includes performing a planarization process on the first conductive material layer to form a contact plug, the contact plug has a concave upper surface, and the concave upper surface is recessed from the upper surface of the isolation structure.

In the manufacturing method of the semiconductor structure, with the design of the thickness of a part of the conductive material layer on one of the upper surfaces of an isolation structure, the amount of the conductive material layer can be provided enough to withstand the damage caused by a subsequent planarization process. The resulting dishing effect can therefore minimize the degree of dishing of the concave upper surface of a contact plug formed by the conductive material layer. Therefore, a void or a gap that may have been formed between the contact plug and an interconnect layer due to a deep recess formed on one of the upper surfaces of the contact plug can be avoided, thereby enabling A good electrical connection between the contact plug and the interconnection layer is achieved.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above can be performed in different ways and replaced by other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, A composition of matter, means, method, or step. Accordingly, such process, machinery, manufacture, material composition, means, method, or steps are included in the patent scope of this application.

1: Semiconductor structure

10: Semiconductor substrate

10A: Array area

10P: surrounding area

2: Semiconductor structure

20: Isolation structure

20T: Groove

20T1: inner wall

3: Semiconductor structure

30: Contact plug

40:Interconnect layer

401: Convex surface

402: Convex surface

50: contact embolism

501: upper surface

50T: Groove

50T1: inner wall

60: Character line structure

70: Bit line structure

101: upper surface

110: active area

130: Insulation structure

201: upper surface

202: lower surface

210: isolation layer

220: isolation layer

230: isolation layer

301: upper surface

310: conductive layer

310A: layer of conductive material

310A': conductive material layer

310B: layer of conductive material

310B1: part

310B2: part

320: titanium nitride layer

320A: titanium nitride layer

410: protrusion

420:Protrusion

500: Preparation method

510: conductive layer

520: titanium nitride layer

600: Preparation method

610: word line isolation layer

630: conductive layer

650: cover layer

710: bit line contact point

720: conductive layer

730: conductive layer

P1: Etching process

P2: Planarization process

S51: step

S52: step

S53: step

S61: step

S62: step

S63: step

S64: step

T1: Thickness

T2: Thickness

T3: Thickness

W1: groove width

A more complete understanding of the present disclosure can be obtained by reference to the detailed description and claims. The disclosure should also be understood in association with drawing element numbers that represent like elements throughout the description. FIG. 1 is a schematic cross-sectional view illustrating a semiconductor structure of some embodiments of the present disclosure. FIG. 2 is a schematic cross-sectional view illustrating semiconductor structures of some embodiments of the present disclosure. FIG. 3 is a schematic cross-sectional view illustrating semiconductor structures of some embodiments of the present disclosure. 4A is a schematic cross-sectional view illustrating a stage of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. 4B is a schematic cross-sectional view illustrating a stage of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. 4C is a schematic cross-sectional view illustrating a stage of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. 4D is a schematic cross-sectional view illustrating a stage of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. 4E is a schematic cross-sectional view illustrating a stage of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. 4F is a schematic cross-sectional view illustrating a stage of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. 4G is a schematic cross-sectional view illustrating a stage of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. FIG. 5 is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to some embodiments of the present disclosure. FIG. 6 is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

1: Semiconductor structure

10: Semiconductor substrate

10P: surrounding area

20: Isolation structure

20T: Groove

20T1: inner wall

30: Contact plug

40:Interconnect layer

101: upper surface

201: upper surface

202: lower surface

210: isolation layer

220: isolation layer

230: isolation layer

301: upper surface

310: conductive layer

320: titanium nitride layer

401: Convex surface

410: protrusion

T1: Thickness

Claims (8)

A method for preparing a semiconductor structure, comprising: forming an isolation structure on a semiconductor substrate, the isolation structure defining a trench; forming a titanium nitride layer on an inner wall of the trench and on one of the isolation structures on the surface; forming a first conductive material layer in the trench and on the titanium nitride layer, wherein a portion of the first conductive material layer on one of the upper surfaces of the isolation structure has a thickness greater than the Three times the thickness of a titanium nitride layer; performing a planarization process on the first conductive material layer to form a contact plug, the contact plug has a concave upper surface, the concave upper surface from the isolation structure the upper surface is recessed, wherein the planarization process includes a chemical mechanical polishing process, and a portion of the titanium nitride layer on the upper surface of the isolation structure is completely removed by the chemical mechanical polishing process; and after forming the Before the first conductive material layer, a second conductive material layer is formed on the titanium nitride layer, wherein the chemical mechanical polishing process completely removes the second conductive material layer on the upper surface of the isolation structure part. The preparation method as claimed in claim 1, wherein the thickness of the titanium nitride layer is less than about 9 nm. The manufacturing method as claimed in claim 1, wherein the thickness of the portion of the first conductive material layer on the upper surface of the isolation structure is greater than about 23 nm. The manufacturing method according to claim 1, wherein the trench has a trench width, and the thickness of the portion of the first conductive material layer on the upper surface of the isolation structure is greater than half of the trench width. The manufacturing method as claimed in claim 1, wherein the trench width of the trench of the isolation structure is greater than about 32 nm. The manufacturing method as claimed in claim 1, wherein the part of the first conductive material layer on the upper surface of the isolation structure is completely removed by the chemical mechanical polishing process. The manufacturing method according to claim 1, further comprising performing an etching process on the second conductive material layer before forming the first conductive material layer. The manufacturing method according to claim 1, further comprising directly forming an interconnection layer on the concave upper surface of the contact plug, wherein the fabrication technique of the interconnection layer includes a physical vapor deposition process.