TWI809311B - Light-emitting device - Google Patents

Abstract

A light-emitting device comprises a semiconductor stack comprising a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer; a first bonding pad formed on the semiconductor stack; a second bonding pad formed on the semiconductor stack and separated from the first bonding pad by a distance to define a region therebetween on the semiconductor stack; and multiple vias penetrating through the active layer to expose the first semiconductor layer, wherein the first bonding pad and the second bonding pad are formed on regions outside of the multiple vias in top view.

Description

Light emitting element

The present invention relates to a light-emitting element, and in particular to a light-emitting element, which includes a semiconductor stack and a welding pad located on the semiconductor stack.

Light-Emitting Diode (Light-Emitting Diode, LED) is a solid-state semiconductor light-emitting element, which has the advantages of low power consumption, low heat generation, long working life, shockproof, small size, fast response and good photoelectric properties, such as Stable emission wavelength. Therefore, light-emitting diodes are widely used in household appliances, equipment indicator lights, and optoelectronic products.

A light-emitting element includes a semiconductor stack with a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer; a first welding pad is located on the semiconductor stack; a The second pad is located on the semiconductor stack, wherein the first pad and the second pad are separated by a distance, and a region is defined on the semiconductor stack between the first pad and the second pad; and a plurality of The holes pass through the active layer to expose the first semiconductor layer, wherein in the top view of the light-emitting element, the first welding pad and the second welding pad are formed in areas other than the positions of the plurality of holes.

A light-emitting element includes a semiconductor stack with a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer; a first contact layer located on the second semiconductor layer , surrounding one side wall of the second semiconductor layer, and connected to the first semiconductor layer; a second contact layer located on the second semiconductor layer, and connected to the second semiconductor layer; a first pad located on the semiconductor stack and connected to the first contact layer; a second pad is located on the semiconductor stack and connected to the second contact layer, wherein the first pad and the second pad are separated by a distance and defined on the semiconductor stack A region is located between the first welding pad and the second welding pad, wherein the first contact layer located on the second semiconductor layer surrounds the second contact layer in the top view of the light-emitting element.

In order to make the description of the present invention more detailed and complete, please refer to the description of the following embodiments together with the relevant figures. However, the examples shown below are for illustrating the light-emitting device of the present invention, and the present invention is not limited to the following examples. In addition, the dimensions, materials, shapes, relative arrangements, etc. of the constituent parts described in the embodiments in this specification are not limited, and the scope of the present invention is not limited thereto, but is merely illustrative. In addition, the size and positional relationship of components shown in the drawings may be exaggerated for clarity. In addition, in the following description, in order to omit detailed description appropriately, the same name and symbol are used for the same or similar member.

FIGS. 1A-11B are a manufacturing method of a light-emitting element 1 or a light-emitting element 2 disclosed in an embodiment of the present invention.

As shown in the top view of FIG. 1A and the cross-sectional view of FIG. 1B along the line AA' of FIG. 1A, the manufacturing method of the light-emitting element 1 or the light-emitting element 2 includes a step of forming a platform, which includes providing a substrate 11a; and Forming a semiconductor stack 10a on the substrate 11a, wherein the semiconductor stack 10a includes a first semiconductor layer 101a, a second semiconductor layer 102a, and an active layer 103a between the first semiconductor layer 101a and the second semiconductor layer 102a . The semiconductor stack 10a can be patterned by lithography and etching to remove part of the second semiconductor layer 102a and the active layer 103a to form one or more semiconductor structures 1000a; and a surrounding portion 111a surrounds one or more Semiconductor structure 1000a. The surrounding portion 111a exposes a first surface 1011a of the first semiconductor layer 101a. One or more semiconductor structures 1000a each include a plurality of first outer sidewalls 1003a, a second outer sidewall 1001a, and a plurality of inner sidewalls 1002a, wherein the first outer sidewall 1003a is the sidewall of the first semiconductor layer 101a, and the second outer sidewall 1001a It is the sidewall of the active layer 103a and/or the second semiconductor layer 102a. One end of the second outer sidewall 1001a is connected to the first surface 102s of the second semiconductor layer 102a, and the other end of the second outer sidewall 1001a is connected to the second sidewall of the first semiconductor layer 101a. One surface 1011a is connected; one end of the inner sidewall 1002a is connected with the surface 102s of the second semiconductor layer 102a, and the other end of the inner sidewall 1002a is connected with the second surface 1012a of the first semiconductor layer 101a; a plurality of semiconductor structures 1000a are connected by the first semiconductor layer Layers 101a are connected to each other. From FIG. 1B, there is an obtuse angle between the inner sidewall 1002a of the semiconductor structure 1000a and the second surface 1012a of the first semiconductor layer 101a, and there is an obtuse angle between the first outer sidewall 1003a of the semiconductor structure 1000a and the surface 11s of the substrate 11a. An obtuse angle or a right angle, there is an obtuse angle between the second outer wall 1001a of the semiconductor structure 1000a and the first surface 1011a of the first semiconductor layer 101a. The surrounding portion 111 a surrounds the periphery of the semiconductor structure 1000 a, and the surrounding portion 111 a is a rectangle or a polygon in a top view of the light emitting element 1 or the light emitting element 2 .

In one embodiment of the present invention, the light-emitting element 1 or the light-emitting element 2 includes a side length of less than 30 mils. When an external current is injected into the light-emitting element 1 or the light-emitting element 2, the light field distribution of the light-emitting element 1 or the light-emitting element 2 can be made uniform by surrounding the surrounding portion 111a around the semiconductor structure 1000a, and the forward direction of the light-emitting element can be reduced. Voltage.

In one embodiment of the present invention, the light-emitting element 1 or the light-emitting element 2 includes a side length greater than 30 mils. The semiconductor stack 10a can be patterned by lithography and etching to remove part of the second semiconductor layer 102a and the active layer 103a, forming one or more holes 100a through the second semiconductor layer 102a and the active layer 103a , wherein one or more holes 100a expose one or more second surfaces 1012a of the first semiconductor layer 101a. When an external current is injected into the light-emitting element 1 or the light-emitting element 2, the light field distribution of the light-emitting element 1 or the light-emitting element 2 can be made uniform by the scattered arrangement of the surrounding portion 111a and the plurality of hole portions 100a, and the light-emitting element can be reduced. the forward voltage.

In one embodiment of the present invention, the light emitting device 1 or the light emitting device 2 includes a side length less than 30 mils, and the light emitting device 1 or the light emitting device 2 may not include one or more holes 100a.

In an embodiment of the present invention, the opening shape of one or more hole portions 100 a includes circular, elliptical, rectangular, polygonal, or arbitrary shapes. The plurality of hole portions 100a can be arranged in multiple rows, and the hole portions 100a in two adjacent rows can be aligned with each other or staggered.

In one embodiment of the present invention, the substrate 11a may be a growth substrate, including a gallium arsenide (GaAs) wafer for growing aluminum gallium indium phosphide (AlGaInP), or a gallium arsenide (GaAs) wafer for growing indium gallium nitride (InGaN) Sapphire (Al ₂ O ₃ ) wafers, gallium nitride (GaN) wafers or silicon carbide (SiC) wafers. On this substrate 11a, a semiconductor stack with photoelectric characteristics can be formed by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor deposition (HVPE), evaporation or ion plating. Layer 10a, for example a light-emitting (light-emitting) stack.

In one embodiment of the present invention, the first semiconductor layer 101a and the second semiconductor layer 102a are, for example, a cladding layer or a confinement layer, which have different conductivity types, electrical properties, Polarity, or can provide electrons or holes according to doped elements, for example, the first semiconductor layer 101a is an n-type semiconductor, and the second semiconductor layer 102a is a p-type semiconductor. The active layer 103a is formed between the first semiconductor layer 101a and the second semiconductor layer 102a. Electrons and holes recombine in the active layer 103a driven by a current to convert electrical energy into light energy to emit a light. The wavelength of the light emitted by the light emitting element 1 or the light emitting element 2 is adjusted by changing the physical and chemical composition of one or more layers in the semiconductor stack 10a. The material of the semiconductor stack 10a includes III-V group semiconductor materials, such as Al _x In _y Ga _(1-xy) N or Al _x In _y Ga _(1-xy) P, wherein 0≦x, y≦1; (x +y)≦1. According to the material of the active layer 103a, when the material of the semiconductor stack 10a is an AlInGaP series material, it can emit red light with a wavelength between 610 nm and 650 nm, and green light with a wavelength between 530 nm and 570 nm. When the semiconductor stack 10a material is an InGaN series material, it can emit blue light with a wavelength between 450 nm and 490 nm, or when the semiconductor stack 10a material is an AlGaN series material, it can emit blue light with a wavelength between 400 nm and 250 nm. UV light between. The active layer 103a can be single heterostructure (single heterostructure, SH ), double heterostructure (double heterostructure, DH ), double-side double heterostructure (double-side double heterostructure, DDH ), multi-layer quantum well structure (multi-quantum well, MQW ). The material of the active layer 103a can be neutral, p-type or n-type semiconductor.

Following the step of forming the platform, as shown in the top view of FIG. 2A and the cross-sectional view along the line AA' of FIG. 2A in FIG. 2B , the manufacturing method of the light-emitting element 1 or the light-emitting element 2 includes a first insulating layer forming steps. A first insulating layer 20a can be formed on the semiconductor structure 1000a by evaporation or deposition, and then patterned by lithography and etching to cover the first surface 1011a and the hole 100a of the surrounding portion 111a The second surface 1012a of the semiconductor structure 1000a covers the second semiconductor layer 102a, the second outer sidewall 1001a and the inner sidewall 1002a of the active layer 103a, wherein the first insulating layer 20a includes a first insulating layer surrounding region 200a to cover The surrounding portion 111a makes the first surface 1011a of the first semiconductor layer 101a located in the surrounding portion 111a covered by the first insulating layer surrounding region 200a; a first group of first insulating layer covering regions 201a to cover the hole portion 100a , so that the second surface 1012a of the first semiconductor layer 101a located in the hole portion 100a is covered by the first group of first insulating layer covering regions 201a; and a second group of first insulating layer openings 202a to expose the first insulating layer The surface 102s of the second semiconductor layer 102a. The first insulating layer covering regions 201a of the first group are separated from each other and respectively correspond to the plurality of hole portions 100a. The first insulating layer 20a can be a single-layer or multi-layer structure. When the first insulating layer 20a is a single-layer film, the first insulating layer 20a can protect the sidewall of the semiconductor structure 1000a to prevent the active layer 103a from being damaged by subsequent processes. When the first insulating layer 20a is a multi-layer film, the first insulating layer 20a may include two or more materials with different refractive indices stacked alternately to form a Bragg reflector (DBR) structure, which selectively reflects light of a specific wavelength. The first insulating layer 20a is formed of non-conductive materials, including organic materials, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin) ), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide), fluorocarbon Polymer (Fluorocarbon Polymer), or inorganic materials, such as silicone (Silicone), glass (Glass), or dielectric materials, such as aluminum oxide (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide ( SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ).

In one embodiment of the present invention, following the step of forming the first insulating layer, as shown in the top view of FIG. 3A and the cross-sectional view along the line AA' of FIG. 3A in FIG. 3B , the light-emitting element 1 or The manufacturing method of the light-emitting element 2 includes a step of forming a transparent conductive layer. A transparent conductive layer 30a can be formed in the second group of openings 202a of the first insulating layer by evaporation or deposition, wherein the outer edge 301a of the transparent conductive layer 30a is separated from the first insulating layer 20a by a distance to expose the first insulating layer. The surface 102s of the second semiconductor layer 102a. Since the transparent conductive layer 30a is formed on substantially the entire surface of the second semiconductor layer 102a and is in contact with the second semiconductor layer 102a, the transparent conductive layer 30a can uniformly diffuse current throughout the second semiconductor layer 102a. The material of the transparent conductive layer 30a includes a material transparent to the light emitted by the active layer 103a, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

In another embodiment of the present invention, after the step of forming the platform, the step of forming the transparent conductive layer can be performed first, and then the step of forming the first insulating layer can be performed.

In another embodiment of the present invention, after the step of forming the platform, the step of forming the first insulating layer can be omitted, and the step of forming the transparent conductive layer can be performed directly.

In one embodiment of the present invention, following the step of forming the transparent conductive layer, as shown in the top view of Figure 4A and the cross-sectional view of Figure 4B along line AA' of Figure 4A, the light-emitting element 1 or the light-emitting element The manufacturing method of 2 includes a reflective structure forming step. The reflective structure includes a reflective layer 40a and/or a barrier layer 41a, which can be directly formed on the transparent conductive layer 30a by evaporation or deposition, wherein the reflective layer 40a is located between the transparent conductive layer 30a and the barrier layer 41a . In the top view of the light-emitting element 1 or light-emitting element 2, the outer edge 401a of the reflective layer 40a can be disposed inside, outside, or aligned with the outer edge 301a of the transparent conductive layer 30a The outer edge 411a of the barrier layer 41a can be disposed inside, outside, or aligned with the outer edge 401a of the reflective layer 40a.

In another embodiment of the present invention, the step of forming the transparent conductive layer can be omitted, and the step of forming the reflective structure, such as the reflective layer 40a and/or the barrier layer, can be directly performed after the step of forming the platform or the step of forming the first insulating layer 41a is directly formed on the second semiconductor layer 102a, and the reflective layer 40a is located between the second semiconductor layer 102a and the barrier layer 41a.

The reflective layer 40a can be one or multi-layer structure, such as a Bragg reflective structure. The material of the reflective layer 40 a includes metal materials with high reflectivity, such as silver (Ag), aluminum (Al), or rhodium (Rh), or alloys of the above materials. Here, having a high reflectivity refers to having a reflectivity of more than 80% for the wavelength of light emitted by the light emitting element 1 or the light emitting element 2 . In one embodiment of the present invention, the barrier layer 41a covers the reflective layer 40a to prevent the surface oxidation of the reflective layer 40a from deteriorating the reflectivity of the reflective layer 40a. The material of the barrier layer 41a includes metal materials, such as titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt) and other metals or the above materials alloy. The barrier layer 41a can be one or multi-layer structure, such as titanium (Ti)/aluminum (Al), and/or titanium (Ti)/tungsten (W). In one embodiment of the present invention, the barrier layer 41a includes a stacked structure of titanium (Ti)/aluminum (Al) on the side away from the reflective layer 40a, and a stacked structure of titanium (Ti)/tungsten (W) on the side close to the reflective layer 40a. In an embodiment of the present invention, the materials of the reflective layer 40 a and the barrier layer 41 a preferably include gold (Au) or metal materials other than copper (Cu).

In one embodiment of the present invention, following the step of forming the reflective structure, such as the top view of Figure 5A, Figure 5B is the cross-sectional view of Figure 5A along AA', and Figure 5C is the line segment along Figure 5A As shown in the sectional view of BB', the manufacturing method of the light emitting element 1 or the light emitting element 2 includes a second insulating layer forming step. A second insulating layer 50a can be formed on the semiconductor structure 1000a by evaporation or deposition, and then patterned by means of lithography and etching to form a first group of second insulating layer openings 501a. The first semiconductor layer 101a is exposed, and a second group of second insulating layer openings 502a are exposed to expose the reflective layer 40a or the barrier layer 41a, wherein in the process of patterning the second insulating layer 50a, in the aforementioned first In the insulating layer forming step, the first insulating layer covering region 200a covering the surrounding portion 111a and the first group of first insulating layer covering regions 201a in the hole portion 100a are partially etched away to expose the first semiconductor layer 101a; A first group of first insulating layer openings 203a are formed in the hole portion 100a to expose the first semiconductor layer 101a. In this embodiment, on the cross-sectional view of the light-emitting element 1 or the light-emitting element 2, as shown in FIG. 5B, the first group of second insulating layer openings 501a and the second group of second insulating layer openings 502a have Different width, number. The opening shapes of the first group of second insulating layer openings 501 a and the second group of second insulating layer openings 502 a include circular, elliptical, rectangular, polygonal, or arbitrary shapes. In this embodiment, as shown in FIG. 5A, the openings 501a of the second insulating layer of the first group are separated from each other and arranged in plural rows, corresponding to the plurality of holes 100a and the first insulating layer of the first group respectively. Opening 203a, the second insulating layer openings 502a of the second group are all close to one side of the substrate 11a, such as the left or right side of the centerline of the substrate 11a, the second insulating layer openings 502a of the second group are separated from each other and located on the same side. Between the second insulating layer openings 501a of the first group of two adjacent columns. The second insulating layer 50a can be a single-layer or multi-layer structure. When the second insulating layer 50a is a single-layer film, the second insulating layer 50a can protect the sidewall of the semiconductor structure 1000a to prevent the active layer 103a from being damaged by subsequent processes. When the second insulating layer 50a is a multi-layer film, the second insulating layer 50a may include two or more materials with different refractive indices stacked alternately to form a Bragg reflector (DBR) structure, which selectively reflects light of a specific wavelength. The second insulating layer 50a is formed of non-conductive materials, including organic materials, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin ), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide), fluorocarbon Polymer (Fluorocarbon Polymer), or inorganic materials, such as silicone (Silicone), glass (Glass), or dielectric materials, such as aluminum oxide (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide ( SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ).

Following the step of forming the second insulating layer, in one embodiment of the present invention, as shown in Figure 6A, the top view, Figure 6B is a cross-sectional view along line AA' of Figure 6A, and Figure 6C is a cross-sectional view along line AA' of Figure 6A. As shown in the cross-sectional view of the line BB' in FIG. 6A, the method for manufacturing the light-emitting element 1 or the light-emitting element 2 includes a step of forming a contact layer. A contact layer 60a can be deposited on the first semiconductor layer 101a and the second semiconductor layer 102a by evaporation or deposition, and then patterned by lithography and etching. On the second insulating layer of the second group One or more contact layer openings 602a are formed on the opening 502a to expose the reflective layer 40a or the barrier layer 41a, and define a pin region 600a at the geometric center of the light emitting device 1 or the light emitting device 2 . In the cross-sectional view of the light-emitting element 1 or the light-emitting element 2, the contact layer opening 602a includes a width greater than that of any one of the second insulating layer openings 502a of the second group. In the top view of the light-emitting device 1 or the light-emitting device 2, the plurality of contact layer openings 602a are all close to one side of the substrate 11a, such as the left or right side of the centerline of the substrate 11a. The contact layer 60a can be one or multi-layer structure. In order to reduce the resistance in contact with the first semiconductor layer 101a, the material of the contact layer 60a includes metal materials, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium ( In), tin (Sn), nickel (Ni), platinum (Pt) and other metals or alloys of the above materials. In an embodiment of the present invention, the material of the contact layer 60 a preferably includes metal materials other than gold (Au) and copper (Cu). In an embodiment of the present invention, the material of the contact layer 60 a preferably includes metals with high reflectivity, such as aluminum (Al) and platinum (Pt). In an embodiment of the present invention, the side of the contact layer 60a in contact with the first semiconductor layer 101a preferably contains chromium (Cr) or titanium (Ti) to increase the bonding strength with the first semiconductor layer 101a.

In one embodiment of the present invention, the contact layer 60a covers all the holes 100a and extends to cover the second semiconductor layer 102a, wherein the contact layer 60a is insulated from the second semiconductor layer 102a through the second insulating layer 50a, and the contact layer 60a is in contact with the first semiconductor layer 101a through the hole portion 100a. When an external current is injected into the light emitting element 1 or the light emitting element 2, the current is conducted to the first semiconductor layer 101a through the plurality of holes 100a. In this embodiment, a first shortest distance is included between two adjacent hole portions 100a located on the same column, between any hole portion 100a adjacent to the edge of the light-emitting element and the first outer wall 1003a of the first semiconductor layer 101a A second shortest distance is included, wherein the first shortest distance is greater than the second shortest distance.

In another embodiment of the present invention, the contact layer 60a covers the surrounding portion 111a and the hole portion 100a, and extends to cover the second semiconductor layer 102a, wherein the contact layer 60a is in contact with the second semiconductor layer 102a through the second insulating layer 50a. Insulation, the contact layer 60a is in contact with the first semiconductor layer 101a through the surrounding portion 111a and the hole portion 100a. When an external current is injected into the light emitting element 1 or the light emitting element 2, part of the current is conducted to the first semiconductor layer 101a through the surrounding portion 111a, and another part of the current is conducted to the first semiconductor layer 101a through the plurality of holes 100a. In this embodiment, a first shortest distance is included between two adjacent hole portions 100a located on the same column, between any hole portion 100a adjacent to the edge of the light-emitting element and the first outer wall 1003a of the first semiconductor layer 101a A second shortest distance is included, wherein the first shortest distance is less than or equal to the second shortest distance.

In another embodiment of the present invention, a plurality of hole portions 100a can be arranged in a first row and a second row, and there is a first shortest distance between two adjacent hole portions 100a in the same row, which is located in the first row. A second shortest distance is included between the hole portion 100a on the row and the hole portion 100a on the second row, wherein the first shortest distance is greater than or smaller than the second shortest distance.

In one embodiment of the present invention, a plurality of hole portions 100a may be arranged in a first row, a second row and a third row, the hole portions 100a on the first row and the hole portions 100a on the second row A first shortest distance is included between them, and a second shortest distance is included between the holes 100a on the second row and the holes 100a on the third row, wherein the first shortest distance is smaller than the second shortest distance.

In one embodiment of the present invention, following the step of forming the contact layer shown in FIG. 6A, FIG. 6B and FIG. 6C, the manufacturing method of the light-emitting element 1 or the light-emitting element 2 includes a third insulating layer forming step, such as Figure 7A is a top view, Figure 7B is a sectional view along line segment A-A' of Figure 7A, and Figure 7C is a sectional view along line segment BB' of Figure 7A, a third The insulating layer 70a can be formed on the semiconductor structure 1000a by evaporation or deposition, and then patterned by lithography and etching to form a first group of third insulating layer openings 701a on the contact layer 60a To expose the contact layer 60a shown in Figure 6A, and form a second group of third insulating layer openings 702a on one or more contact layer openings 602a to expose the reflective layer 40a or barrier shown in Figure 6A Layer 41a, wherein the contact layer 60a located on the second semiconductor layer 102a is sandwiched between the second insulating layer 50a and the third insulating layer 70a, the openings 701a of the third insulating layer of the first group are connected with the openings 701a of the first group The openings 501a of the two insulating layers are staggered and do not overlap each other. The ejector pin region 600a is surrounded and covered by the third insulating layer. In this embodiment, as shown in FIG. 7A , the openings 701a of the third insulating layer of the first group are separated from each other and staggered from the plurality of hole portions 100a. The third insulating layer openings 702a of the second group are separated from each other and respectively correspond to the plurality of contact layer openings 602a. In the top view of FIG. 7A, the third insulating layer openings 701a of the first group are close to one side of the substrate 11a, for example, the right side, and the third insulating layer openings 702a of the second group are close to the other side of the substrate 11a, for example The left side of the center line of the substrate 11a. In the cross-sectional view of the light-emitting element 1 or the light-emitting element 2, any third insulating layer opening 702a of the second group has a width smaller than that of any contact layer opening 602a, and the third insulating layer 70a is filled in accordance with the contact layer opening 602a. The side walls of the openings 602a in the cladding contact layer expose the reflective layer 40a or the barrier layer 41a, forming the second group of openings 702a in the third insulating layer. The third insulating layer 70a can be a single-layer or multi-layer structure. When the third insulating layer 70a is a multi-layer film, the third insulating layer 70a may include two or more materials with different refractive indices stacked alternately to form a Bragg reflector (DBR) structure, which selectively reflects light of a specific wavelength. The third insulating layer 70a is formed of non-conductive materials, including organic materials, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin ), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide), fluorocarbon Polymer (Fluorocarbon Polymer), or inorganic materials, such as silicone (Silicone), glass (Glass), or dielectric materials, such as aluminum oxide (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide ( SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ).

Following the step of forming the third insulating layer, the manufacturing method of the light emitting element 1 or the light emitting element 2 includes a pad forming step. As shown in the top view of FIG. 8, a first pad 80a and a second pad 90a can be formed on one or more semiconductor structures 1000a by means of electroplating, evaporation or deposition, and then by lithography , Patterning by etching. In the top view of FIG. 8, the first pad 80a is close to one side of the centerline of the substrate 11a, such as the right side, and the second pad 90a is close to the other side of the centerline of the substrate 11a, such as the left side. The first pad 80a covers all the openings 701a of the first group of the third insulating layer to be in contact with the contact layer 60a, and to form an electrical connection with the first semiconductor layer 101a through the contact layer 60a and the hole portion 100a. The second pad 90a covers all the third insulating layer openings 702a of the second group, is in contact with the reflective layer 40a or the barrier layer 41a, and passes through the reflective layer 40a or the barrier layer 41a to form an electrical connection with the second semiconductor layer 102a. connect. The first pad 80a has one or more first pad openings 800a; and a first side 802a and a plurality of first recesses 804a extending from the first side 802a toward a direction away from the second pad 90a. The second pad 90a has one or more second pad openings 900a; and a second side 902a and a plurality of second recesses 904a extending from the second side 902a toward a direction away from the first pad 80a. The positions of the first pad opening 800a and the second pad opening 900a approximately correspond to the position of the hole portion 100a, and the positions of the first recess 804a and the second recess 904a approximately correspond to the position of the hole portion 100a. In other words, the first pad 80a and the second pad 90a do not cover any hole 100a, the first pad 80a and the second pad 90a bypass the hole 100a, and are formed around the hole 100a, so as to The first pad opening 800a or the second pad opening 900a includes a diameter larger than any hole portion 100a, and the first concave portion 804a or the second concave portion 904a includes a diameter larger than any hole portion 100a. In an embodiment of the present invention, the plurality of first recesses 804a are substantially aligned with the plurality of second recesses 904a in a top view. In another embodiment of the present invention, the plurality of first recesses 804a and the plurality of second recesses 904a are staggered in the top view. In one embodiment of the present invention, in the top view of the light-emitting element 1 or the light-emitting element 2 , the shape of the first pad 80 a is the same as or different from that of the second pad 90 a.

Figure 9A is a cross-sectional view along line AA' in Figure 8, and Figure 9B is a cross-sectional view along line BB' in Figure 8. The light emitting device 1 disclosed according to this embodiment is a flip chip light emitting diode device. The light emitting device 1 includes a substrate 11a; one or more semiconductor structures 1000a are located on the substrate 11a; the surrounding portion 111a surrounds the one or more semiconductor structures 1000a; and the first pad 80a and the second pad 90a are located on the semiconductor stack 10a. Each of the one or more semiconductor structures 1000a includes a semiconductor stack 10a, the semiconductor stack 10a includes a first semiconductor layer 101a, a second semiconductor layer 102a, and an active layer 103a between the first semiconductor layer 101a and the second semiconductor layer 102a. The plurality of semiconductor structures 1000a are connected to each other through the first semiconductor layer 101a. As shown in FIG. 8, FIG. 9A and FIG. 9B, the second semiconductor layer 102a and the active layer 103a around one or more semiconductor structures 1000a are removed to expose the first surface 1011a of the first semiconductor layer 101a. In other words, the surrounding portion 111a includes the first surface 1011a of the first semiconductor layer 101a to surround the periphery of the semiconductor structure 1000a.

The light-emitting element 1 further includes one or more holes 100a passing through the second semiconductor layer 102a and the active layer 103a to expose one or more second surfaces 1012a of the first semiconductor layer 101a; and the contact layer 60a is formed on the first semiconductor layer The first surface 1011a of the first semiconductor layer 101a is formed on one or more second surfaces 1012a of the first semiconductor layer 101a to cover one or more Each hole portion 100a is in contact with the first semiconductor layer 101a to form an electrical connection. In this embodiment, in the top view of the light-emitting element 1, the contact layer 60a has a total surface area larger than the total surface area of the active layer 103a, or the contact layer 60a has a peripheral edge length larger than the peripheral edge length of the active layer 103a.

In one embodiment of the present invention, the first bonding pad 80a and/or the second bonding pad 90a cover the plurality of semiconductor structures 1000a.

In one embodiment of the present invention, the first pad 80a has one or more first pad openings 800a, and the second pad 90a has one or more second pad openings 900a. The formation position of the first welding pad 80a and the second welding pad 90a is to bypass the formation position of the hole portion 100a, so that the formation position of the first welding pad opening 800a and the second welding pad opening 900a is the same as the formation position of the hole portion 100a. overlapping.

In one embodiment of the present invention, on the top view of the light-emitting element 1, the shape of the first welding pad 80a is the same as that of the second welding pad 90a, for example, the shapes of the first welding pad 80a and the second welding pad 90a are Comb shape, as shown in Figure 8, the radius of curvature of the first pad opening 800a of the first pad 80a and the radius of curvature of the first recess 804a are respectively greater than the radius of curvature of the hole 100a, so that the first pad The pads 80a are formed in regions other than the positions of the plurality of hole portions 100a. The radius of curvature of the second pad opening 900a of the second pad 90a and the radius of curvature of the second concave portion 904a are respectively greater than the radius of curvature of the hole portion 100a, so that the second pad 90a is formed in a plurality of hole portions 100a. outside the area.

In one embodiment of the present invention, on the top view of the light-emitting element 1, the shape of the first welding pad 80a is different from that of the second welding pad 90a, for example, the shape of the first welding pad 80a is a rectangle, and the shape of the second welding pad When the shape of 90a is a comb shape, the first pad 80a includes a first pad opening 800a, so that the first pad 80a is formed in an area other than the plurality of holes 100a, and the second pad 90a includes a second concave portion 904a or At the same time, the second concave portion 904a and the second pad opening 900a are included, so that the second pad 90a is formed in a region other than the plurality of hole portions 100a.

In an embodiment of the present invention, the size of the first bonding pad 80a is different from that of the second bonding pad 90a, for example, the area of the first bonding pad 80a is greater than that of the second bonding pad 90a. The first pad 80a and the second pad 90a can be one or more layers of structures including metal materials. The material of the first welding pad 80a and the second welding pad 90a includes metal materials, such as chromium (Cr), titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel ( Ni), platinum (Pt) and other metals or alloys of the above materials. When the first welding pad 80a and the second welding pad 90a are multilayer structures, the first welding pad 80a includes a first upper layer welding pad 805a and a first lower layer welding pad 807a, and the second welding pad 90a includes a second upper layer Welding pad 905a and a second lower layer welding pad 907a. The upper layer pads and the lower layer pads have different functions respectively. The function of the upper pad is mainly used for welding and forming leads. With the upper pads, the light-emitting element 1 can be mounted on the packaging substrate in the form of flip-chip, using solder or AuSn eutectic bonding. The specific metal material of the upper pad includes highly ductile materials such as nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), copper (Cu), gold (Au), tungsten (W), Zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), Osmium (Os). The upper pad can be a single layer, alloy or multilayer film of the above materials. In an embodiment of the present invention, the material of the upper pad preferably includes nickel (Ni) and/or gold (Au), and the upper pad is a single layer or multiple layers. The function of the lower layer pad is to form a stable interface with the contact layer 60a, the reflective layer 40a, or the barrier layer 41a, such as improving the interface bonding strength between the first lower layer pad 807a and the contact layer 60a, or improving the second lower layer solder pad 807a. The bonding strength of the interface between the pad 907a and the reflective layer 40a or the barrier layer 41a. Another function of the lower pad is to prevent tin (Sn) in the solder or the AuSn eutectic from diffusing into the reflective structure and destroying the reflectivity of the reflective structure. Therefore, the underlying pad preferably contains metal materials other than gold (Au), copper (Cu), such as nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), tungsten (W), zirconium ( Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), osmium ( Os), the lower pad can be a single layer, alloy or multilayer film of the above materials. In an embodiment of the present invention, the lower pad preferably includes a multilayer film of titanium (Ti) and aluminum (Al), or a multilayer film of chromium (Cr) and aluminum (Al).

In one embodiment of the present invention, under the cross-sectional view of the light emitting element 1 , the part of the contact layer 60a connected to the first semiconductor layer 101a is located under the second pad 90a.

In one embodiment of the present invention, under the cross-sectional view of the light-emitting element 1 , the part of the contact layer 60a connected to the first semiconductor layer 101a is located above the reflective layer 40a and/or the barrier layer 41a.

In one embodiment of the present invention, on the top view of the light-emitting element 1, the hole portion 100a includes a maximum width smaller than the maximum width of the first pad opening 800a; and/or the hole portion 100a includes a maximum width smaller than the second pad opening 800a; One of the pad openings 900a has a maximum width.

In one embodiment of the present invention, in the top view of the light-emitting element 1, the plurality of holes 100a are respectively located in the plurality of first recesses 804a of the first welding pad 80a and the plurality of second recesses 904a of the second welding pad 90a middle.

Fig. 10 is a cross-sectional view of a light emitting element 2 disclosed in an embodiment of the present invention. Compared with the light-emitting element 1 in the above-mentioned embodiment, the light-emitting element 2 further includes a first buffer pad 810a and a second buffer pad 910a respectively located under the first welding pad 80a and the second welding pad 90a. In addition, the light-emitting element 2 has substantially the same structure as the light-emitting element 1. Therefore, the light-emitting element 2 in FIG. 10 and the structure of the light-emitting element 1 in FIG. materials, or have the same function, the description will be omitted here or will not be repeated here. In this embodiment, the light-emitting element 2 includes a first buffer pad 810a located between the first pad 80a and the semiconductor stack 10a, and a second buffer pad 910a located between the second pad 90a and the semiconductor stack 10a, wherein The first buffer pad 810a and the second buffer pad 910a cover part or all of the hole portion 100a; The stress generated when 80a, 90a is bonded with solder or AuSn eutectic will cause cracks between the pads 80a, 90a and the insulating layer, so the buffer pads 810a, 910a are respectively located between the pads 80a, 90a and the third insulating layer 70a , the first buffer pad 810a and the second buffer pad 910a cover the entire hole portion 100a, the formation position of the first solder pad 80a and the second solder pad 90a is to bypass the formation position of the hole portion 100a, by selecting the material of the buffer pad , and reduce the thickness to reduce the stress between the pad and the insulating layer. In other words, the first pad 80a and the second pad 90a do not cover the hole 100a.

In one embodiment of the present invention, as shown in FIG. 10, on the top view of the light-emitting element 2, the shapes of the buffer pads 810a, 910a are the same as the shapes of the solder pads 80a, 90a, for example, the first buffer pad 810a and the first buffer pad 810a. The shape of the first pad 80a is a comb shape.

In one embodiment of the present invention, on the top view of the light-emitting element 2 (not shown), the shapes of the buffer pads 810a, 910a are different from the shapes of the welding pads 80a, 90a, for example, the shape of the first buffer pad 810a is Rectangular, the shape of the first welding pad 80a is a comb shape.

In another embodiment of the present invention, the sizes of the buffer pads 810a, 910a are different from those of the solder pads 80a, 90a, for example, the area of the first buffer pad 810a is larger than the area of the first solder pad 80a, and the second buffer pad 910a The area is larger than the area of the second pad 90a.

In another embodiment of the present invention, a distance between the first pad 80a and the second pad 90a is greater than a distance between the first buffer pad 810a and the second buffer pad 910a.

In another embodiment of the present invention, compared with the bonding pads 80a, 90a, the buffer pads 810a, 910a have a larger area to release the pressure of the bonding pads 80a, 90a during die bonding. In the cross-sectional view of the light-emitting element 2 , the first buffer pad 810 a includes a width that is 1.5 to 2.5 times, preferably twice, the width of the first welding pad 80 a.

In another embodiment of the present invention, compared with the bonding pads 80a, 90a, the buffer pads 810a, 910a have a larger area to release the pressure of the bonding pads 80a, 90a during die bonding. In the cross-sectional view of the light-emitting element 2, the expansion distance of the first buffer pad 810a is more than 1 times its own thickness, preferably more than 2 times its own thickness.

In another embodiment of the present invention, the pads 80a, 90a include a thickness between 1-100 μm, preferably between 2-6 μm, and the buffer pads 810a, 910a include a thickness greater than 0.5 μm to release the pads 80a, 90a are the pressure during crystal bonding.

In another embodiment of the present invention, the first buffer pad 810a and the second buffer pad 910a can be one or more layers of structures including metal materials. The function of the first buffer pad 810a and the second buffer pad 910a is to form a stable interface with the contact layer 60a, the reflective layer 40a, or the barrier layer 41a, for example, the first buffer pad 810a is in contact with the contact layer 60a, and the second buffer pad 910a is in contact with the reflective layer 40a or the barrier layer 41a. The buffer pads 810a, 910a preferably include metal materials other than gold (Au) and copper (Cu), such as chromium (Cr), nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), tungsten ( W), zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium ( Ru), osmium (Os), to prevent tin (Sn) in solder or AuSn eutectic from diffusing into the light-emitting element.

In another embodiment of the present invention, the first buffer pad 810a and/or the second buffer pad 910a is a multi-layer structure including a metal material, wherein the multi-layer structure includes a high ductility layer and a low ductility layer to prevent soldering. Stress generated when the pads 80a, 90a are bonded to solder or AuSn eutectically cracks the insulating layer between the pads 80a, 90a and the semiconductor stack 10a. The high ductility layer and the low ductility layer contain metals with different Young's modulus.

In another embodiment of the present invention, the high ductility layer of the first buffer pad 810a and the second buffer pad 910a includes a thickness greater than or equal to that of the low ductility layer.

In another embodiment of the present invention, the first buffer pad 810a and the second buffer pad 910a are a multi-layer structure containing metal materials, and when the first welding pad 80a and the second welding pad 90a are a multi-layer structure containing metal materials, the second A buffer pad 810a includes the same metal material on the side that is connected to the first solder pad 80a, and a side that connects the second buffer pad 910a to the second solder pad 90a includes the same metal material, such as chromium (Cr), nickel (Ni ), titanium (Ti), platinum (Pt), to improve the bonding strength of the interface between the pad and the buffer pad.

As shown in FIG. 11A and FIG. 11B, a fourth insulating layer 110a can be formed on the first buffer pad 810a and the second buffer pad 910a by evaporation or deposition, and then by lithography and etching. For patterning, the first pad 80a and the second pad 90a are respectively formed on the first buffer pad 810a and the second buffer pad 910a by the above-mentioned method, wherein the fourth insulating layer 110a surrounds the first buffer pad 810a and the first buffer pad 810a. The side wall of the second buffer pad 910a. The fourth insulating layer 110a can be a single-layer or multi-layer structure. When the fourth insulating layer 110a is a multilayer film, the fourth insulating layer 110a may include two or more materials with different refractive indices stacked alternately to form a Bragg reflector (DBR) structure, which selectively reflects light of a specific wavelength. The material of the fourth insulating layer 110a is formed of non-conductive materials, including organic materials, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide), fluorine Carbon polymer (Fluorocarbon Polymer), or inorganic materials, such as silicone (Silicone), glass (Glass), or dielectric materials, such as aluminum oxide (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide (SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ).

In one embodiment of the present invention, the manufacturing process of the first pad 80a and the second pad 90a may be directly followed by the manufacturing process of the first buffer pad 810a and the second buffer pad 910a. In another embodiment of the present invention, after the manufacturing process of the first buffer pad 810a and the second buffer pad 910a, the step of forming the fourth insulating layer 110a is performed first, and then the first solder pad 80a and the second solder pad are connected 90a Manufacturing process.

12A-22 are the manufacturing method of a light emitting element 3 or a light emitting element 4 disclosed in an embodiment of the present invention.

As shown in the top view of FIG. 12A and the cross-sectional view of FIG. 12B along the line AA' of FIG. 12A, the manufacturing method of the light-emitting element 3 or the light-emitting element 4 includes a step of forming a platform, which includes providing a substrate 11b; and Forming a semiconductor stack 10b on the substrate 11b, wherein the semiconductor stack 10b includes a first semiconductor layer 101b, a second semiconductor layer 102b, and an active layer 103b between the first semiconductor layer 101b and the second semiconductor layer 102b . The semiconductor stack 10b can be patterned by lithography and etching to remove part of the second semiconductor layer 102b and the active layer 103b to form one or more semiconductor structures 1000b; and a surrounding portion 111b surrounds one or more Semiconductor structure 1000b. The surrounding portion 111b exposes a first surface 1011b of the first semiconductor layer 101b. One or more semiconductor structures 1000b each include a plurality of first outer sidewalls 1003b, a second outer sidewall 1001b, and a plurality of inner sidewalls 1002b, wherein the first outer sidewalls 1003b are sidewalls of the first semiconductor layer 101b, and the second outer sidewalls 1001b It is the sidewall of the active layer 103b and/or the second semiconductor layer 102b, one end of the second outer sidewall 1001b is connected with the first surface 102s of the second semiconductor layer 102b, and the other end of the second outer sidewall 1001b is connected with the second sidewall of the first semiconductor layer 101b. One surface 1011b is connected; one end of the inner sidewall 1002b is connected with the surface 102s of the second semiconductor layer 102b, and the other end of the inner sidewall 1002b is connected with the second surface 1012b of the first semiconductor layer 101b; a plurality of semiconductor structures 1000b are connected by the first semiconductor layer Layers 101b are connected to each other. From FIG. 12B, there is an obtuse angle between the inner sidewall 1002b of the semiconductor structure 1000b and the second surface 1012b of the first semiconductor layer 101b, and there is an obtuse angle between the first outer sidewall 1003b of the semiconductor structure 1000b and the surface 11s of the substrate 11b. An obtuse angle or a right angle, there is an obtuse angle between the second outer wall 1001b of the semiconductor structure 1000b and the first surface 1011b of the first semiconductor layer 101b. The surrounding portion 111b surrounds the periphery of the semiconductor structure 1000b, and the surrounding portion 111b is a rectangle or a polygon in a top view of the light emitting element 3 or the light emitting element 4 .

In one embodiment of the present invention, the light-emitting element 3 or the light-emitting element 4 includes a side length of less than 30 mils. When an external current is injected into the light-emitting element 3 or the light-emitting element 4, the surrounding portion 111b surrounds the semiconductor structure 1000b, so that the light field distribution of the light-emitting element 3 or the light-emitting element 4 can be made uniform, and the forward direction of the light-emitting element can be reduced. Voltage.

In one embodiment of the present invention, the light-emitting element 3 or the light-emitting element 4 includes a side length greater than 30 mils. The semiconductor stack 10b can be patterned by lithography and etching to remove part of the second semiconductor layer 102b and the active layer 103b, forming one or more holes 100b through the second semiconductor layer 102b and the active layer 103b , wherein one or more holes 100b expose one or more second surfaces 1012b of the first semiconductor layer 101b. When an external current is injected into the light-emitting element 3 or the light-emitting element 4, the light field distribution of the light-emitting element 3 or the light-emitting element 4 can be made uniform by the scattered arrangement of the surrounding portion 111b and the plurality of hole portions 100b, and the light-emitting element can be reduced. the forward voltage.

In an embodiment of the present invention, the shape of the opening of the one or more hole portions 100b includes a circle, an ellipse, a rectangle, a polygon, or any shape. The plurality of hole portions 100b can be arranged in multiple rows, and the hole portions 100b in two adjacent rows can be aligned with each other or staggered.

In one embodiment of the present invention, the substrate 11b may be a growth substrate, including a gallium arsenide (GaAs) wafer for growing aluminum gallium indium phosphide (AlGaInP), or a gallium arsenide (GaAs) wafer for growing indium gallium nitride (InGaN) Sapphire (Al ₂ O ₃ ) wafers, gallium nitride (GaN) wafers or silicon carbide (SiC) wafers. On this substrate 11b, a semiconductor stack with photoelectric characteristics can be formed by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor deposition (HVPE), evaporation or ion plating. Layer 10b, for example a light-emitting stack.

In one embodiment of the present invention, the first semiconductor layer 101b and the second semiconductor layer 102b are, for example, a cladding layer or a confinement layer, which have different conductivity types, electrical properties, Polarity, or can provide electrons or holes according to doped elements, for example, the first semiconductor layer 101b is an n-type semiconductor, and the second semiconductor layer 102b is a p-type semiconductor. The active layer 103b is formed between the first semiconductor layer 101b and the second semiconductor layer 102b. Electrons and holes recombine in the active layer 103b driven by a current to convert electrical energy into light energy to emit a light. The wavelength of the light emitted by the light emitting element 3 or the light emitting element 4 is adjusted by changing the physical and chemical composition of one or more layers in the semiconductor stack 10b. The material of the semiconductor stack 10b includes III-V group semiconductor materials, such as Al _x In _y Ga _(1-xy) N or Al _x In _y Ga _(1-xy) P, wherein 0≦x, y≦1; (x +y)≦1. According to the material of the active layer 103b, when the material of the semiconductor stack 10b is an AlInGaP series material, it can emit red light with a wavelength between 610 nm and 650 nm, and green light with a wavelength between 530 nm and 570 nm. When the semiconductor stack 10b material is an InGaN series material, it can emit blue light with a wavelength between 450 nm and 490 nm, or when the semiconductor stack 10b material is an AlGaN series material, it can emit blue light with a wavelength between 400 nm and 250 nm. UV light between. The active layer 103b can be single heterostructure (single heterostructure, SH ), double heterostructure (double heterostructure, DH ), double-side double heterostructure (double-side double heterostructure, DDH ), multi-layer quantum well structure (multi-quantum well, MQW ). The material of the active layer 103b can be neutral, p-type or n-type semiconductor.

Following the step of forming the platform, as shown in the top view of FIG. 13A and the cross-sectional view along the line AA' of FIG. 13A in FIG. 13B , the manufacturing method of the light-emitting element 3 or the light-emitting element 4 includes a first insulating layer forming steps. A first insulating layer 20b can be formed on the semiconductor structure 1000b by evaporation or deposition, and then patterned by lithography and etching to cover the first surface 1011b and the hole 100b of the surrounding portion 111b and cover the second semiconductor layer 102b of the semiconductor structure 1000b, the second outer sidewall 1001b and the inner sidewall 1002b of the active layer 103b, wherein the first insulating layer 20b includes a first insulating layer surrounding region 200b to cover The surrounding portion 111b makes the first surface 1011b of the first semiconductor layer 101b located in the surrounding portion 111b covered by the first insulating layer surrounding region 200b; a first group of first insulating layer covering regions 201b to cover the hole portion 100b , so that the second surface 1012b of the first semiconductor layer 101b located in the hole portion 100b is covered by the first group of first insulating layer covering regions 201b; and a second group of first insulating layer openings 202b to expose the first insulating layer The surface 102s of the second semiconductor layer 102b. The first insulating layer covering regions 201b of the first group are separated from each other and respectively correspond to the plurality of hole portions 100b. The first insulating layer 20b can be a single-layer or multi-layer structure. When the first insulating layer 20b is a single-layer film, the first insulating layer 20b can protect the sidewall of the semiconductor structure 1000b to prevent the active layer 103b from being damaged by subsequent processes. When the first insulating layer 20b is a multi-layer film, the first insulating layer 20b may include two or more materials with different refractive indices stacked alternately to form a Bragg reflector (DBR) structure, which selectively reflects light of a specific wavelength. The first insulating layer 20b is formed of non-conductive materials, including organic materials, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin ), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide), fluorocarbon Polymer (Fluorocarbon Polymer), or inorganic materials, such as silicone (Silicone), glass (Glass), or dielectric materials, such as aluminum oxide (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide ( SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ).

In one embodiment of the present invention, following the step of forming the first insulating layer, as shown in the top view of FIG. 14A and the cross-sectional view along the line AA' of FIG. 14A in FIG. 14B , the light-emitting element 3 or The manufacturing method of the light-emitting element 4 includes a step of forming a transparent conductive layer. A transparent conductive layer 30b can be formed on the semiconductor structure 1000b by evaporation or deposition, and is in contact with the second semiconductor layer 102, wherein the transparent conductive layer 30b does not cover the hole portion 100b. In a top view of the light emitting element 3 or the light emitting element 4, the transparent conductive layer 30b is formed on substantially the entire surface of the second semiconductor layer 102b. Specifically, the transparent conductive layer 30b can be formed in the second group of openings 202b of the first insulating layer by evaporation or deposition, wherein the outer edge 301b of the transparent conductive layer 30b is separated from the first insulating layer 20b by a certain distance. to expose the surface 102s of the second semiconductor layer 102b. The transparent conductive layer 30b includes one or more transparent conductive layer openings 300b respectively corresponding to one or more hole portions 100b and/or respectively corresponding to the first group of first insulating layer covering regions 201b, wherein the outer edges 301b of the transparent conductive layer openings 300b There is a distance from the inner sidewall 1002b of the semiconductor structure 1000b and/or the outer edge of the hole portion 100b, and the outer edge of the transparent conductive layer opening 300b surrounds the outer edge of the hole portion 100b or surrounds the first group of first insulating layer covering regions 201b. The material of the transparent conductive layer 30b includes a material transparent to the light emitted by the active layer 103b, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

In another embodiment of the present invention, after the step of forming the platform, the step of forming the transparent conductive layer can be performed first, and then the step of forming the first insulating layer can be performed.

In another embodiment of the present invention, after the step of forming the platform, the step of forming the first insulating layer can be omitted, and the step of forming the transparent conductive layer can be performed directly.

In one embodiment of the present invention, following the step of forming the transparent conductive layer, as shown in the top view of Figure 15A and the cross-sectional view along the line AA' of Figure 15A in Figure 15B, the light-emitting element 3 or the light-emitting element The manufacturing method of 4 includes a reflective structure forming step. The reflective structure includes a reflective layer 40b and/or a barrier layer 41b, which can be directly formed on the transparent conductive layer 30b by evaporation or deposition, wherein the reflective layer 40b is located between the transparent conductive layer 30b and the barrier layer 41b . In the top view of the light-emitting element 3 or the light-emitting element 4, the reflective layer 40b and/or the barrier layer 41b are formed on substantially the entire surface of the second semiconductor layer 102b. The outer edge 401b of the reflective layer 40b can be arranged on the inside or outside of the outer edge 301b of the transparent conductive layer 30b, or arranged to coincide with the outer edge 301b of the transparent conductive layer 30b, and the outer edge 411b of the barrier layer 41b can be arranged on the reflective The inner side, the outer side, or the outer edge 401b of the layer 40b is arranged to coincide with the outer edge 401b of the reflective layer 40b. The reflective layer 40b includes one or more reflective layer openings 400b respectively corresponding to one or more hole portions 100b, and the barrier layer 41b includes one or more barrier layer openings 410b respectively corresponding to one or more hole portions 100b. The opening 300b of the transparent conductive layer, the opening 400b of the reflective layer, and the opening 410b of the barrier layer overlap each other. The outer edge of the reflective layer opening 400b and/or the outer edge of the barrier layer opening 410b is at a distance from the outer edge of the hole portion 100b, and the outer edge of the reflective layer opening 400b and/or the outer edge of the barrier layer opening 410b surrounds the outer edge of the hole portion 100b .

In another embodiment of the present invention, the step of forming the transparent conductive layer can be omitted, and the step of forming the reflective structure, such as the reflective layer 40b and/or the barrier layer, can be directly performed after the step of forming the platform or the step of forming the first insulating layer 41b is directly formed on the second semiconductor layer 102b, and the reflective layer 40b is located between the second semiconductor layer 102b and the barrier layer 41b. The reflective layer 40b can be one or multi-layer structure, such as a Bragg reflective structure. The material of the reflective layer 40b includes metal materials with high reflectivity, such as silver (Ag), aluminum (Al), or rhodium (Rh), or alloys of the above materials. Here, having a high reflectivity refers to having a reflectivity of more than 80% for the wavelength of the light emitted by the light emitting element 3 . In one embodiment of the present invention, the barrier layer 41b covers the reflective layer 40b to prevent the surface oxidation of the reflective layer 40b from deteriorating the reflectivity of the reflective layer 40b. The material of the barrier layer 41b includes metal materials, such as titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt) and other metals or the above materials alloy. The barrier layer 41b can be one or multi-layer structure, such as titanium (Ti)/aluminum (Al), and/or titanium (Ti)/tungsten (W). In one embodiment of the present invention, the barrier layer 41b includes a stacked structure of titanium (Ti)/aluminum (Al) on the side close to the reflective layer 40b, and a stacked structure of titanium (Ti)/tungsten (W) on the side away from the reflective layer 40b. In an embodiment of the present invention, the materials of the reflective layer 40b and the barrier layer 41b preferably include gold (Au) or metal materials other than copper (Cu).

In one embodiment of the present invention, following the step of forming the reflective structure, as shown in the top view of Figure 16A and the cross-sectional view along the line AA' of Figure 16A in Figure 16B, the light emitting element 3 or the light emitting element 4 The manufacturing method includes a second insulating layer forming step. A second insulating layer 50b can be formed on the semiconductor stack 10b by evaporation or deposition, and then patterned by lithography and etching to form a first group of second insulating layer openings 501b To expose the first semiconductor layer 101b and a second group of second insulating layer openings 502b to expose the reflective layer 40b or the barrier layer 41b, wherein in the process of patterning the second insulating layer 50b, in the aforementioned first In the insulating layer forming step, the first insulating layer covering region 201b of the first group covering the first insulating layer surrounding region 200b of the surrounding portion 111b and the hole portion 100b is removed by etching to expose the first semiconductor layer 101b, and A first group of first insulating layer openings 203b are formed on the hole portion 100b to expose the first semiconductor layer 101b. In one embodiment of the present invention, as shown in FIG. 16A, the first group of second insulating layer openings 501b are separated from each other and respectively correspond to a plurality of holes 100b, and the second group of second insulating layer openings 502b They are all close to one side of the substrate 11b, such as the left side or the right side of the center line of the substrate 11b. In one embodiment, the number of the second insulating layer openings 502b in the second group includes one or more. In this embodiment, the first The two groups of second insulating layer openings 502b are connected to each other to jointly form an annular opening 5020b. The annular opening 5020b can be comb-shaped, rectangular, elliptical, circular, or polygonal in the top view of the light-emitting element 3 . In an embodiment of the present invention, the second insulating layer 50b can be a single-layer or multi-layer structure. When the second insulating layer 50b is a multi-layer film, the second insulating layer 50b may include two or more materials with different refractive indices stacked alternately to form a Bragg reflector (DBR) structure, which selectively reflects light of a specific wavelength. The second insulating layer 50b is formed of non-conductive materials, including organic materials, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin ), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide), fluorocarbon Polymer (Fluorocarbon Polymer), or inorganic materials, such as silicone (Silicone), glass (Glass), or dielectric materials, such as aluminum oxide (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide ( SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ).

Following the step of forming the second insulating layer, in one embodiment of the present invention, as shown in the cross-sectional view of the top view of FIG. 17A and the cross-sectional view of FIG. 17B, the manufacturing method of the light-emitting element 3 or the light-emitting element 4 includes a contact layer formation step. A contact layer 60b can be deposited on the semiconductor stack 10b by evaporation or deposition, and then patterned by lithography and etching to form a first contact layer 601b and a second contact layer 602b. The first contact layer 601b covers all the second insulating layer openings 501b of the first group, fills in one or more holes 100b to be in contact with the first semiconductor layer 101b, and extends to cover the second insulating layer 50b and On the second semiconductor layer 102b, the first contact layer 601b is insulated from the second semiconductor layer 102b through the second insulating layer 50b. The second contact layer 602b is formed in the annular opening 5020b of the second insulating layer 50b to be in contact with the reflective layer 40b and/or the barrier layer 41b, wherein the sidewall 6021b of the second contact layer 602b is in contact with the sidewall 5021b of the annular opening 5020b separated by a distance. The sidewall 6011b of the first contact layer 601b is separated from the sidewall 6021b of the second contact layer 602b by a distance, so that the first contact layer 601b does not touch the second contact layer 602b, and the first contact layer 601b and the second contact layer 602b It is electrically isolated by a part of the second insulating layer 50b. In the top view, the first contact layer 601b covers the surrounding portion 111b of the semiconductor stack 10b, so that the first contact layer 601b surrounds the second contact layer 602b. In the top view of FIG. 17A, the second contact layer 602b is close to one side of the substrate 11b, for example, the left or right side of the centerline of the substrate 11b. The contact layer 60b defines a pin region 600b at the geometric center on the semiconductor stack 10b. The pin area 600b is not in contact with the first contact layer 601b and the second contact layer 602b, and is electrically isolated from each other. The pin area 600b includes the same material as the first contact layer 601b and/or the second contact layer 602b. The thimble area 600b is used as a structure to protect the epitaxial layer to prevent the epitaxial layer from being damaged by probes in the back-end process, such as die separation, test die, and packaging. The contact layer 60b can be one or multi-layer structure. In order to reduce the resistance in contact with the first semiconductor layer 101b, the material of the contact layer 60b includes metal materials, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium ( In), tin (Sn), nickel (Ni), platinum (Pt) and other metals or alloys of the above materials. In an embodiment of the present invention, the material of the contact layer 60b preferably includes metal materials other than gold (Au) and copper (Cu). In an embodiment of the present invention, the material of the contact layer 60b preferably includes metals with high reflectivity, such as aluminum (Al) and platinum (Pt). In an embodiment of the present invention, the side of the contact layer 60b in contact with the first semiconductor layer 101b preferably contains chromium (Cr) or titanium (Ti) to increase the bonding strength with the first semiconductor layer 101b.

In one embodiment of the present invention, following the step of forming the contact layer shown in FIG. 17A and FIG. 17B, the manufacturing method of the light-emitting element 3 or the light-emitting element 4 includes a step of forming a third insulating layer, as shown in FIG. 18A Figure 18B is a cross-sectional view along the line AA' of Figure 18A, a third insulating layer 70b can be formed on the semiconductor stack 10b by evaporation or deposition, and then by lithography , patterning by etching, forming a third insulating layer opening 701b on the first contact layer 601b to expose the first contact layer 601b shown in Figure 17A, and forming another third insulating layer opening 701b on the second contact layer 602b. The insulating layer opening 702b is used to expose the second contact layer 602b shown in FIG. 17A, wherein the first contact layer 601b partially located on the second semiconductor layer 102b is sandwiched between the second insulating layer 50b and the third insulating layer 70b. In this embodiment, as shown in FIG. 18A , the third insulating layer opening 701 b and another third insulating layer opening 702 b bypass one or more hole portions 100 b. In this embodiment, the opening 701b of the third insulating layer and/or another opening 702b of the third insulating layer is an annular opening, and the annular opening can be comb-shaped, rectangular, oval, circular, or circular in a top view. or polygons. In the top view of FIG. 18A, the third insulating layer opening 701b is close to one side of the centerline of the substrate 11b, for example, the right side, and the other third insulating layer opening 702b is close to the other side of the centerline of the substrate 11b, such as the left side. In the cross-sectional view, the third insulating layer opening 701b has a width greater than that of another third insulating layer opening 702b. The third insulating layer 70b can be a single-layer or multi-layer structure. When the third insulating layer 70b is a multi-layer film, the third insulating layer 70b may include two or more materials with different refractive indices stacked alternately to form a Bragg reflector (DBR) structure, which selectively reflects light of a specific wavelength. The third insulating layer 70b is formed of non-conductive materials, including organic materials, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin ), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide), fluorocarbon Polymer (Fluorocarbon Polymer), or inorganic materials, such as silicone (Silicone), glass (Glass), or dielectric materials, such as aluminum oxide (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide ( SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ).

Following the step of forming the third insulating layer, the manufacturing method of the light emitting element 3 or the light emitting element 4 includes a pad forming step. As shown in the top view of FIG. 19, a first pad 80b and a second pad 90b can be formed on the semiconductor stack 10b by electroplating, evaporation or deposition, and then by lithography and etching. way of patterning. In the top view of FIG. 19, the first pad 80b is close to one side of the centerline of the substrate 11b, for example, the right side, and the second pad 90b is close to the other side of the centerline of the substrate 11b, for example, the left side. The first pad 80b is in contact with the first contact layer 601b through the third insulating layer opening 701b, and is electrically connected to the first semiconductor layer 101b through the first contact layer 601b. The second pad 90b is in contact with the reflective layer 40b and/or the barrier layer 41b through another opening 702b of the third insulating layer, and forms an electrical connection with the second semiconductor layer 102b through the reflective layer 40b and/or the barrier layer 41b . The first pad 80b has a plurality of first protrusions 801b and a plurality of first recesses 802b alternately connected to each other. The second pad 90b has a plurality of second protrusions 901b and a plurality of second recesses 902b alternately connected to each other. The position of the first concave portion 802b of the first pad 80b and the position of the second concave portion 902b of the second pad 90b roughly correspond to the position of the hole portion 100b. In other words, the first pad 801b and the second pad 802b do not cover any hole 100b, and the first concave portion 802b of the first pad 80b and the second concave portion 902b of the second pad 90b bypass the hole 100b. , and formed around the hole portion 100b, so that the width of the first concave portion 802b of the first pad 80b or the width of the second concave portion 902b of the second pad 90b is larger than the diameter of any hole portion 100b. In one embodiment of the present invention, the plurality of first recesses 802b are roughly aligned with the plurality of second recesses 902b in a top view. In another embodiment of the present invention, the plurality of first recesses 802b and the plurality of second recesses 902b are staggered in the top view.

In one embodiment of the present invention, as shown in FIG. 19, the first welding pad 80b covers the opening 701b of the third insulating layer, and the second welding pad 90b covers another opening 702b of the third insulating layer. The third insulating layer opening 701b has a maximum width greater than that of the other third insulating layer opening 702b, so that the first pad 80b has a maximum width greater than that of the second pad 90b. The different sizes of the first pad 80b and the second pad 90b can facilitate identification of the electrical properties of the corresponding connection of the pads during package soldering, and avoid soldering to wrong electrical pads.

In an embodiment of the present invention, in the top view of the light-emitting device, the opening 701b of the third insulating layer includes an area larger or smaller than that of the first pad 80b.

In another embodiment of the present invention, the shortest distance between the first convex portion 801b and the second convex portion 901b is smaller than the maximum distance between the first concave portion 802b and the second concave portion 902b.

In another embodiment of the present invention, the first pad 80b includes a first flat side 803b opposite to the first convex portion 801b and the first concave portion 802b, and the second pad 90b includes a second flat side 903b opposite to the second The convex portion 901b is opposite to the second concave portion 902b. A maximum distance between the first flat side 803b of the first pad 80b and the first protrusion 801b is greater than the shortest distance between the first protrusion 801b and the second protrusion 901b. A maximum distance between the second flat side 903b of the second pad 90b and the second protrusion 901b is greater than the shortest distance between the first protrusion 801b and the second protrusion 901b.

In another embodiment of the present invention, the radius of curvature of the plurality of first recesses 802b of the first welding pad 80b is different from the radius of curvature of the plurality of first protrusions 801b of the first welding pad 80b, for example, the first welding pad The radius of curvature of the plurality of first concave portions 802b of the first welding pad 80b is greater than or smaller than the radius of curvature of the plurality of first convex portions 801b of the first welding pad 80b. In another embodiment of the present invention, the curvature radii of the plurality of second recesses 902b of the second welding pad 90b are larger or smaller than the curvature radii of the plurality of second protrusions 901b of the second welding pad 90b.

In another embodiment of the present invention, the radius of curvature of the first protrusion 801b of the first pad 80b is larger or smaller than the radius of curvature of the second protrusion 901b of the second pad 90b of the second pad 90b.

In another embodiment of the present invention, the plurality of first recesses 802b of the first welding pad 80b are opposite to the plurality of second recesses 902b of the second welding pad 90b, and the radius of curvature of the plurality of first recesses 802b is larger or smaller than One of the curvature radii of the plurality of second recesses 902b.

In another embodiment of the present invention, the shape of the first bonding pad 80b is different from that of the second bonding pad 90b, for example, the shape of the first bonding pad 80b is rectangular, and the shape of the second bonding pad 90b is comb-shaped.

In another embodiment of the present invention, the size of the first bonding pad 80b is different from that of the second bonding pad 90b, for example, the area of the first bonding pad 80b is larger than that of the second bonding pad 90b.

Fig. 20 is a sectional view along AA' of Fig. 19. The light emitting device 3 disclosed according to this embodiment is a flip-chip light emitting diode device. The light emitting element 3 includes a substrate 11b; one or more semiconductor structures 1000b are located on the substrate 11b, wherein the semiconductor structure 1000b includes a semiconductor stack 10, and the semiconductor stack 101l includes a first semiconductor layer 101b, a second semiconductor layer 102b, And an active layer 103b is located between the first semiconductor layer 101b and the second semiconductor layer 102b, a plurality of semiconductor structures 1000b are connected to each other through the first semiconductor layer 101b; a surrounding portion 111b surrounds one or more semiconductor structures 1000b, wherein The portion 111b exposes a first surface 1011b of the first semiconductor layer 101b; and a first bonding pad 80b and a second bonding pad 90b are located on one or more semiconductor structures 1000b. As shown in FIG. 19 and FIG. 20, one or more semiconductor structures 1000b each include a plurality of outer sidewalls 1001b and a plurality of inner sidewalls 1002b, wherein one end of the outer sidewall 1001b is connected to a surface 102s of the second semiconductor layer 102b, The other end of the outer sidewall 1001b is connected to the first surface 1011b of the first semiconductor layer 101b; one end of the inner sidewall 1002b is connected to the surface 102s of the second semiconductor layer 102b, and the other end of the inner sidewall 1002b is connected to the second surface of the first semiconductor layer 101b. Surfaces 1012b are connected.

In one embodiment of the present invention, when the length of one side of the light-emitting element 3 is greater than 30 mil, the light-emitting element 3 further includes one or more holes 100b passing through the second semiconductor layer 102b and the active layer 103b to expose the first semiconductor layer 101b one or more second surfaces 1012b; and a contact layer 60b located on one first surface 1011b of the first semiconductor layer 101b to surround one or more semiconductor structures 1000b and contact the first semiconductor layer 101b to form an electrical connection , and formed on one or more second surfaces 1012b of the first semiconductor layer 101b to cover one or more holes 100b and contact the first semiconductor layer 101b to form an electrical connection, wherein the contact layer 60b includes a first contact layer 601b and a second contact layer 602b, the first contact layer 601b is located on the second semiconductor layer, surrounds one side wall of the second semiconductor layer, and is connected to the first semiconductor layer, and the second contact layer is located on the second semiconductor layer , and connected to the second semiconductor layer, the second contact layer 602b is surrounded by the first contact layer 601b, and the first contact layer 601b and the second contact layer 602b do not overlap each other.

In an embodiment of the present invention, when the length of one side of the light emitting element 3 is less than 30 mils, in order to obtain a larger light emitting area, the light emitting element 3 may not include any hole 100b.

In one embodiment of the present invention, the total surface area of the contact layer 60b is larger than the total surface area of the active layer 103b in the top view of the light emitting element 3 .

In one embodiment of the present invention, in the top view of the light-emitting element 3 , the total side length of the periphery of the contact layer 60 b is greater than the total side length of the periphery of the active layer 103 b.

In an embodiment of the present invention, in the top view of the light emitting element 3 , the first contact layer 601b includes an area larger than that of the second contact layer 602b.

In one embodiment of the present invention, the first welding pad 80b and the second welding pad 90b are formed around the hole 100b, so that any hole 100b is not covered by the first welding pad 80b or the second welding pad 90b. covered by.

In one embodiment of the present invention, under the cross-sectional view of the light emitting element 3 , the first contact layer 601b connected to the first semiconductor layer 101b is not located under the second pad 90b.

In one embodiment of the present invention, the minimum distance between the first pad 80b and the second pad 90b is greater than 50 μm.

In one embodiment of the present invention, the distance between the first pad 80b and the second pad 90b is less than 300 μm.

In an embodiment of the present invention, the first pad 80b and the second pad 90b can be one or more layers of structures including metal materials. The materials of the first welding pad 80b and the second welding pad 90b include metal materials, such as chromium (Cr), titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel ( Ni), platinum (Pt) and other metals or alloys of the above materials. When the first welding pad 80b and the second welding pad 90b are multilayer structures, the first welding pad 80b includes a first lower layer welding pad (not shown) and a first upper layer welding pad (not shown), and the second welding pad 90b includes a second lower pad (not shown) and a second upper pad (not shown). The upper layer pads and the lower layer pads have different functions respectively. The function of the upper pad is mainly used for soldering and forming leads. Through the upper pad, the light-emitting element 3 can be mounted on the mounting substrate in the form of flip-chip using solder or AuSn eutectic bonding. The specific metal material of the upper pad includes highly ductile materials such as nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), copper (Cu), gold (Au), tungsten (W), Zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), Osmium (Os). The upper pad can be a single layer, alloy or multilayer film of the above materials. In an embodiment of the present invention, the material of the upper pad preferably includes nickel (Ni) and/or gold (Au), and the upper pad is a single layer or multiple layers. The function of the lower layer pad is to form a stable interface with the contact layer 60b, the reflective layer 40b, or the barrier layer 41b, such as improving the bonding strength of the interface between the first lower layer pad and the contact layer 60b, or improving the bonding strength of the second lower layer solder pad. The bonding strength of the interface between the pad and the reflective layer 40b and/or the barrier layer 41b. Another function of the lower pad is to prevent tin (Sn) in the solder or the AuSn eutectic from diffusing into the reflective structure and destroying the reflectivity of the reflective structure. Therefore, the underlying pad preferably contains metal materials other than gold (Au), copper (Cu), such as nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), tungsten (W), zirconium ( Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), osmium ( Os), the lower pad can be a single layer, alloy or multilayer film of the above materials. In an embodiment of the present invention, the lower pad preferably includes a multilayer film of titanium (Ti) and aluminum (Al), or a multilayer film of chromium (Cr) and aluminum (Al).

In one embodiment of the present invention, when the light-emitting element 3 is flip-chip mounted on the packaging substrate by solder, there may be a height difference H between the first pad 80b and the second pad 90b. As shown in FIG. 20, since the second insulating layer 50b below the first pad 80b covers the reflective layer 40b, the second insulating layer 50b below the second pad 90b includes a second insulating layer opening 502b to expose the reflective layer. layer 40b or barrier layer 41b, so when the first pad 80b and the second pad 90b are respectively formed in the third insulating layer opening 701b and another third insulating layer opening 702b, the topmost portion of the first pad 80b Compared with the topmost surface 90s of the second welding pad 90b, the topmost surface 80s of the first welding pad 80b is higher than the topmost surface 90s of the second welding pad 90b. In other words, there is a height difference H between the topmost surface 80s of the first welding pad 80b and the topmost surface 90s of the second welding pad 90b, and the height difference H between the first welding pad 80b and the second welding pad 90b It is roughly the same as the thickness of the second insulating layer 50b. In one embodiment, the height difference between the first pad 80 b and the second pad 90 b may be between 0.5 μm˜2.5 μm, for example, 1.5 μm. When the first welding pad 80b and the second welding pad 90b are respectively formed in the third insulating layer opening 701b and another third insulating layer opening 702b, the first welding pad 80b communicates with the first insulating layer opening 701b through the third insulating layer opening 701b. When the contact layer 601b is in contact, it extends from the third insulating layer opening 701b to cover part of the surface of the third insulating layer 70b, and the second pad 90b is connected to the second contact layer through another third insulating layer opening 702b. 602b are in contact with each other and extend from another opening 702b of the third insulating layer to cover part of the surface of the third insulating layer 70b.

Fig. 21 is a top view of a light emitting element 4 disclosed in an embodiment of the present invention. FIG. 22 is a cross-sectional view of a light emitting element 4 disclosed in an embodiment of the present invention. Compared with the light-emitting element 3 in the above-mentioned embodiment, the light-emitting element 4 has substantially the same structure as the light-emitting element 3 except for the structure of the first pad and the second pad. The light-emitting element 4 and the light-emitting element 3 Components with the same reference numbers will not be repeated here. When the light-emitting element 4 is mounted on the package substrate in the form of flip-chip by AuSn eutectic bonding, the height difference between the first pad 80b and the second pad 90b should be as small as possible, so as to increase the bonding between the pad and the package. Stability between substrates. As shown in FIG. 22, the second insulating layer 50b below the first pad 80b covers the reflective layer 40b, and the second insulating layer 50b below the second pad 90b includes a second insulating layer opening 502b to expose the reflective layer. 40b or barrier layer 41b. In this embodiment, in order to reduce the height difference between the topmost surface 80s of the first pad 80b and the topmost surface 90s of the second pad 90b, the opening 701b of the third insulating layer includes a width greater than that of the other third insulating layer. One width of layer opening 702b. When the first welding pad 80b and the second welding pad 90b are respectively formed in the third insulating layer opening 701b and another third insulating layer opening 702b, the whole of the first welding pad 80b is formed in the third insulating layer opening 701b to In contact with the first contact layer 601b, the second pad 90b is formed in another opening 702b of the third insulating layer and is in contact with the reflective layer 40b and/or the barrier layer 41b, and the second pad 90b is formed from the third insulating layer The opening 702b extends to cover part of the surface of the third insulating layer 70b. In other words, the third insulating layer is not formed under the first pad 80b, but a part of the third insulating layer is formed under the second pad 90b. In this embodiment, the height difference between the first pad 80b and the second pad 90b is less than 0.5 μm, preferably less than 0.1 μm, more preferably less than 0.05 μm.

Fig. 23 is a cross-sectional view of a light emitting element 5 disclosed in an embodiment of the present invention. Compared with the light-emitting element 3 and the light-emitting element 4 in the above-mentioned embodiments, the light-emitting element 5 has substantially the same structure as the light-emitting element 3 and the light-emitting element 4 except for the structure of the second welding pad. Elements with the same reference numerals as the light emitting element 3 and the light emitting element 4 will not be repeated here. When the light-emitting element 5 is mounted on the packaging substrate in the form of flip-chip by AuSn eutectic bonding, the height difference between the first pad 80b and the second pad 90b should be as small as possible, so as to increase the connection between the pad and the package. Stability between substrates. As mentioned above, in addition to forming part of the third insulating layer under the second pad 90b, it is also possible to reduce the top surface of the first pad 80b by forming a second buffer pad 910b under the second pad 90b. and the height difference between the top surface of the second pad 90b. As shown in FIG. 23, the second insulating layer 50b below the first pad 80b covers the reflective layer 40b, and the second insulating layer 50b below the second pad 90b includes a second insulating layer opening 502b to expose the reflective layer. 40b or barrier layer 41b. In this embodiment, the entirety of the first pad 80b is formed in the opening 701b of the third insulating layer to be in contact with the first contact layer 601b, and the entirety of the second pad 90b is formed in another opening 702b of the third insulating layer. To be in contact with the second contact layer 602b, in other words, the third insulating layer is not formed under the first pad 80b and under the second pad 90b. In this embodiment, by using the second buffer pad 910b between the second pad 90b and the second contact layer 602b, the distance between the top surface of the first pad 80b and the top surface of the second pad 90b is reduced. height difference, wherein the second buffer pad 910b preferably contains metal materials other than gold (Au) and copper (Cu), such as chromium (Cr), nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti ), tungsten (W), zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir ), ruthenium (Ru), osmium (Os), to prevent tin (Sn) in the AuSn eutectic from diffusing into the light-emitting element 5 . In this embodiment, the height difference between the top surface of the first pad 80b and the top surface of the second pad 90b is less than 0.5 μm, preferably less than 0.1 μm, more preferably less than 0.05 μm. In this embodiment, the second buffer pad 910b has a thickness substantially the same as that of the second insulating layer 50b.

FIG. 24 is a cross-sectional view of a light emitting element 6 disclosed in an embodiment of the present invention. Compared with the light-emitting element 3 and the light-emitting element 4 in the above-mentioned embodiments, the light-emitting element 6 has substantially the same features as the light-emitting element 3 and the light-emitting element 4 except that the structure of the third insulating layer 70b under the first pad 80b is different. The structure of the light-emitting element 6 and the light-emitting element 3 and the light-emitting element 4 have the same reference numerals and will not be repeated here. As shown in FIG. 24, the third insulating layer 70b can be formed on the semiconductor stack 10b by evaporation or deposition, and then patterned by lithography and etching to form on the first contact layer 601b. A third insulating layer opening 701b is formed to expose the first contact layer 601b, and another third insulating layer opening 702b is formed on the second contact layer 602b to expose the second contact layer 602b. The first pad 80b and the second pad 90b can be formed on the semiconductor stack 10b by electroplating, evaporation or deposition, and then patterned by lithography and etching. The first pad 80b is in contact with the first contact layer 601b through the third insulating layer opening 701b, and is electrically connected to the first semiconductor layer 101b through the first contact layer 601b. In order to avoid the etching process of forming the third insulating layer opening 701b, the first contact layer 601b and the second insulating layer 50b under the first pad 80b are removed by over-etching when etching the third insulating layer 70b to expose the reflective layer 40b and/or the barrier layer 41b, thus reducing the area where the third insulating layer 70b under the first pad 80b is etched to form the third insulating layer opening 701b, and the first part of the third insulating layer 70b is located between the first pad 80b and the second insulating layer. Between the first contact layer 601b and completely covered by the first welding pad 80b, another second part of the third insulating layer 70b is located around the first welding pad 80b, and between the first part and the second part of the third insulating layer 70b The gap between them constitutes the opening 701b of the third insulating layer. Specifically, the first portion of the third insulating layer 70b completely covered by the first pad 80b includes a width greater than that of the third insulating layer opening 701b below the pad 80b. In this embodiment, the opening 701b of the third insulating layer is a ring-shaped opening in the top view of the light-emitting element.

Fig. 25 is a schematic diagram of a light emitting device according to an embodiment of the present invention. The semiconductor light-emitting element 1, light-emitting element 2, light-emitting element 3, light-emitting element 4, light-emitting element 5, or light-emitting element 6 in the foregoing embodiments are mounted on the first pad 511 and the second pad 511 of the packaging substrate 51 in the form of a flip chip. Spacer 512 on. The first spacer 511 and the second spacer 512 are electrically insulated by an insulating portion 53 including insulating material. In flip-chip mounting, one side of the growth substrates 11a, 11b opposite to the electrode formation surface is used as the main light extraction surface. In order to increase the light extraction efficiency of the light emitting device, a reflective structure 54 can be provided around the semiconductor light emitting element 1 , light emitting element 2 , light emitting element 3 , light emitting element 4 , light emitting element 5 or light emitting element 6 .

Fig. 26 is a schematic diagram of a light emitting device according to an embodiment of the present invention. A bulb lamp 600 includes a lampshade 602 , a reflector 604 , a light emitting module 610 , a lamp holder 612 , a heat sink 614 , a connection portion 616 and an electrical connection element 618 . The light-emitting module 610 includes a carrying portion 606, and a plurality of light-emitting elements 608 are located on the carrying portion 606, wherein the plurality of light-emitting elements 608 can be the semiconductor light-emitting element 1, light-emitting element 2, light-emitting element 3, light-emitting element 4. The light emitting element 5 or the light emitting element 6 .

The various embodiments listed in the present invention are only used to illustrate the present invention, and are not intended to limit the scope of the present invention. Any obvious modifications or changes made by anyone to the present invention will not depart from the spirit and scope of the present invention.

1, 2, 3, 4, 5, 6: light emitting elements 11a, 11b: substrate 10a, 10b: semiconductor stack 101a, 101b: first semiconductor layer 102a, 102b: second semiconductor layer 103a, 103b: active layer 100a, 100b: Hole 102s: surface 1011a, 1011b: first surface 1012a, 1012b: second surface 110a: the fourth insulating layer 111a, 111b: surrounding part 20a, 20b: first insulating layer 200a, 200b: the surrounding area of the first insulating layer 201a, 201b: first insulating layer coverage area 202a, 202b: openings in the first insulating layer 203a, 203b: openings in the first insulating layer 30a, 30b: transparent conductive layer 300b: Opening of the transparent conductive layer 301a, 301b: the outer edge of the transparent conductive layer 40a, 40b: reflective layer 400b: Reflective layer opening 401a, 401b: the outer edge of the reflective layer 41a, 41b: barrier layer 410b: barrier opening 411a, 411b: the outer edge of the barrier layer 50a, 50b: second insulating layer 501a, 501b: openings in the second insulating layer 502a, 502b: openings in the second insulating layer 5020b: ring opening 5021b: side wall 60a, 60b: contact layer 600a, 600b: thimble area 602a: contact layer opening 601b: first contact layer 6011b: First contact layer sidewall 602b: second contact layer 6021b: Second contact layer sidewall 70a, 70b: third insulating layer 701a, 702a: openings in the third insulating layer 701b, 702b: openings in the third insulating layer 80a, 80b: the first welding pad 90a, 90b: the second welding pad 800a: first pad opening 801b: first convex part 802a: first side 802b: first recess 803b: The first flat edge 804a: first recess 805a: The first upper pad 807a: The first lower pad 810a: first cushioning pad 900a: second pad opening 901b: second convex part 902a: second side 902b: second recess 903b: second flat edge 904a: second recess 905a: Second upper pad 907a: Second lower pad 910a, 910b: Second cushioning pad 1000a, 1000b: semiconductor structure 1001a, 1001b: second outer side wall 1002a, 1002b: inner side wall 1003a, 1003b: first outer side wall 51: Package substrate 511: The first gasket 512: second gasket 53: Insulation part 54: Reflection structure 600: bulb lamp 602: lampshade 604: Mirror 606: bearing part 608: Light emitting element 610: Lighting module 612: lamp holder 614: heat sink 616: connection part 618: Electrical connection components

1A-7C are the manufacturing method of the light-emitting element 1 or the light-emitting element 2 disclosed in an embodiment of the present invention.

Fig. 8 is a top view of the light emitting element 1 disclosed in an embodiment of the present invention.

FIG. 9A is a cross-sectional view of a light-emitting element 1 disclosed in an embodiment of the present invention.

FIG. 9B is a cross-sectional view of the light-emitting element 1 disclosed in an embodiment of the present invention.

Fig. 10 is a top view of the light-emitting element 2 disclosed in an embodiment of the present invention.

FIG. 11A is a cross-sectional view of a light-emitting element 2 disclosed in an embodiment of the present invention.

FIG. 11B is a cross-sectional view of a light-emitting element 2 disclosed in an embodiment of the present invention.

12A-18B are the manufacturing method of the light-emitting element 3 or the light-emitting element 4 disclosed in an embodiment of the present invention.

Fig. 19 is a top view of the light-emitting element 3 disclosed in an embodiment of the present invention.

Fig. 20 is a cross-sectional view of a light emitting element 3 disclosed in an embodiment of the present invention.

Fig. 21 is a top view of a light emitting element 4 disclosed in an embodiment of the present invention.

FIG. 22 is a cross-sectional view of a light emitting element 4 disclosed in an embodiment of the present invention.

Fig. 23 is a cross-sectional view of a light emitting element 5 disclosed in an embodiment of the present invention.

FIG. 24 is a cross-sectional view of a light emitting element 6 disclosed in an embodiment of the present invention.

Fig. 25 is a schematic structural view of a light emitting device according to an embodiment of the present invention.

Fig. 26 is a schematic structural view of a light emitting device according to an embodiment of the present invention.

1: Light emitting element

11a: Substrate

10a: Semiconductor stack

101a: first semiconductor layer

102a: second semiconductor layer

103a: active layer

100a: Hole

1011a: first surface

1012a: second surface

111a: Surrounding part

20a: first insulating layer

30a: transparent conductive layer

40a: reflective layer

41a: barrier layer

50a: second insulating layer

60a: contact layer

70a: the third insulating layer

80a: The first welding pad

90a: the second welding pad

600a:Thimble area

800a: first pad opening

900a: second pad opening

805a: The first upper pad

807a: The first lower pad

905a: Second upper pad

907a: Second lower pad

1000a: Semiconductor structure

1003a: first outer side wall

1001a: second outer side wall

1002a: inner side wall

Claims (10)

A light-emitting element, comprising: a substrate with a central line; a semiconductor stack with a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer a plurality of holes, passing through the second semiconductor layer and the active layer to expose the first semiconductor layer; a first contact layer covering the plurality of holes; a second contact layer located in the second semiconductor layer a first pad is located on the semiconductor stack to contact the first contact layer, to form an electrical connection with the first semiconductor layer, and is located on one side of the center line of the substrate; and a second pad, Located on the semiconductor stack to contact the second contact layer, to form electrical connection with the second semiconductor layer, and located on the other side of the centerline of the substrate, the first pad is separated from the second pad distance, and define a region between the first pad and the second pad on the semiconductor stack, wherein in a top view of the light-emitting element, the plurality of holes include the same row Two adjacent holes, including a first shortest distance between the two adjacent holes, the plurality of holes further include a hole adjacent to the edge of the light-emitting element, the hole and the first outer side of the first semiconductor layer A second shortest distance is included between the walls, wherein the first shortest distance is greater than the second shortest distance. A light-emitting element, comprising: a substrate with a central line; a semiconductor stack with a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer a plurality of holes, passing through the second semiconductor layer and the active layer to expose the first semiconductor layer; a first contact layer covering the plurality of holes; a second contact layer located in the second semiconductor layer superior; A first pad is located on the semiconductor stack to contact the first contact layer, to form electrical connection with the first semiconductor layer, and is located on one side of the center line of the substrate; and a second pad is located on the On the semiconductor stack to contact the second contact layer, form an electrical connection with the second semiconductor layer, and be located on the other side of the center line of the substrate, the first pad is separated from the second pad by a distance, And a region is defined on the semiconductor stack between the first pad and the second pad, wherein in a top view of the light-emitting element, the plurality of holes include two phases in the same row Adjacent holes, the two adjacent holes include a first shortest distance, the plurality of holes further include a hole adjacent to the edge of the light-emitting element, the hole and the first outer wall of the first semiconductor layer includes a second shortest distance, wherein the first shortest distance is less than or equal to the second shortest distance. A light-emitting element, comprising: a substrate with a central line; a semiconductor stack with a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer a plurality of holes, passing through the second semiconductor layer and the active layer to expose the first semiconductor layer; a first contact layer covering the plurality of holes; a second contact layer located in the second semiconductor layer a first pad is located on the semiconductor stack to contact the first contact layer, to form an electrical connection with the first semiconductor layer, and is located on one side of the center line of the substrate; and a second pad, Located on the semiconductor stack to contact the second contact layer, to form electrical connection with the second semiconductor layer, and located on the other side of the centerline of the substrate, the first pad is separated from the second pad distance, and define a region between the first pad and the second pad on the semiconductor stack, wherein on a top view of the light-emitting element, the plurality of holes are arranged in plural rows, the The plurality of rows includes a first row and a second row, and a first row is included between two adjacent holes on the same row. The shortest distance includes a second shortest distance between the holes on the first row and the holes on the second row, wherein the first shortest distance is greater than or smaller than the second shortest distance. A light-emitting element, comprising: a substrate with a central line; a semiconductor stack with a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer a plurality of holes, passing through the second semiconductor layer and the active layer to expose the first semiconductor layer; a first contact layer covering the plurality of holes; a second contact layer located in the second semiconductor layer a first pad is located on the semiconductor stack to contact the first contact layer, to form an electrical connection with the first semiconductor layer, and is located on one side of the center line of the substrate; and a second pad, Located on the semiconductor stack to contact the second contact layer, to form electrical connection with the second semiconductor layer, and located on the other side of the centerline of the substrate, the first pad is separated from the second pad distance, and define a region between the first pad and the second pad on the semiconductor stack, wherein on a top view of the light-emitting element, the plurality of holes are arranged in plural rows, the The plural rows include a first row, a second row and a third row, and a first shortest distance is included between the holes on the first row and the holes on the second row. A second shortest distance is included between the holes on the row and the holes on the third row, and the first shortest distance is smaller than the second shortest distance. The light-emitting element as described in claim 1, 2, 3 or 4 of the patent scope further comprises a surrounding portion surrounding the semiconductor stack, wherein the surrounding portion exposes the first semiconductor stack, and the first contact layer covers The surround. The light-emitting device as described in claim 1, 2, 3 or 4 of the patent claims, wherein in a cross-sectional view of the light-emitting device, the first contact layer is not located under the second pad. The light-emitting device as described in claim 1, 2, 3 or 4, wherein in the top view of the light-emitting device, the area of the first contact layer is larger than the area of the second contact layer. The light-emitting device as described in claim 1, 2, 3 or 4, wherein the first contact layer and the second contact layer do not overlap with each other. The light-emitting element as described in claim 1, 2, 3 or 4 of the patent claims, wherein in the top view of the light-emitting element, the first contact layer surrounds the second contact layer. A light-emitting device, including the light-emitting element described in any one of items 1 to 9 of the scope of the patent application, and further including a packaging substrate, a first pad and a second pad, wherein the light-emitting element is flip-chip mounted on the first pad and the second pad of the packaging substrate in a form.

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