TWI807456B - Input and output circuit for wafer on wafer technology, and chip device using thereof - Google Patents

Abstract

An input and output circuit for wafer on wafer technology and a chip device are provided in the present disclosure. The input and output circuit includes a plurality of first connection node groups, a plurality of second connection node groups, and a plurality of connection structure groups. A connection structure group is arranged between each of the first connection node group and the corresponding second connection node group. Each of the first connection node group includes a plurality of first connection nodes. Each of the second connection node group includes a plurality of second connection nodes. The first connection nodes of each of the first connection node group are connected. The second connection nodes of each of the second connection node group are connected.

Description

Input and output circuits of wafer-to-wafer technology and chip devices using the same

The invention relates to an input and output circuit and a chip device, in particular to a high-yield wafer-to-wafer technology input and output circuit and a chip device using the same.

The demand for wafer on wafer and chip level circuits is gradually increasing in today's semiconductor manufacturing process. However, the wafer stacking process or the input and output circuit design of the chip-level circuit will affect the yield of the final product.

Therefore, how to provide a high-yield input and output circuit and chip device to overcome the above-mentioned defects has become one of the important issues to be solved by this business.

The technical problem to be solved by the present invention is to provide an input and output circuit, which is suitable for connecting a first circuit and a second circuit. The input and output circuit is arranged between the first circuit and the second circuit. The input and output circuit includes: multiple sets of first connection node groups, the multiple sets of first connection node groups are arranged on one side of the first circuit; The first connection node group corresponds to a set of the second connection node group; and multiple sets of connection structure groups are arranged between the multiple first connection node groups and the multiple second connection node groups; wherein, a set of connection structure groups is set between each group of the first connection node group and a corresponding group of the second connection nodes, the first connection node group includes a plurality of first connection nodes, the first connection nodes of the first connection node group are connected to each other, the second connection node group includes a plurality of second connection nodes, the second connection node group The plurality of second connection nodes are connected to each other, and the connection structure group includes a plurality of connection structures .

The present invention also discloses an input and output circuit, which is suitable for connecting a first circuit and a second circuit. The input and output circuit is arranged between the first circuit and the second circuit. The input and output circuit includes: a plurality of first connection node groups, the plurality of first connection node groups are arranged on one side of the first circuit; A plurality of connection structure groups are arranged between the plurality of first connection node groups and the plurality of second connection node groups, one connection structure group is arranged between each first connection node group and the corresponding second connection node group; a first auxiliary connection node is arranged on one side of the first circuit; a second auxiliary connection node is arranged on one side of the second circuit, and the first auxiliary connection node and the second auxiliary connection node are set correspondingly; Auxiliary connection nodes; wherein, when one of the first connection node groups of the plurality of first connection node groups, one of the corresponding second connection nodes of the plurality of second connection nodes, and the corresponding connection structure group are in an abnormal transmission state, the first auxiliary connection node and the second auxiliary connection node are connected to the first connection node group in the abnormal transmission state and the corresponding second connection node group to transmit a control signal of the first connection node group in the abnormal transmission state and the corresponding second connection node group.

The present invention also discloses a chip device, comprising: a first circuit; a second circuit; and an input and output circuit, including a plurality of first connection node groups, a plurality of second connection node groups, and a plurality of connection structure groups. A set of first connection node groups is set corresponding to the plurality of second connection node groups; wherein, each of the first connection node groups includes a plurality of first connection nodes, and the plurality of first connection nodes of the first connection node group are connected to each other, and each of the second connection node groups includes a plurality of second connection nodes, and the plurality of second connection nodes of the second connection node group are connected to each other.

The present invention also discloses a chip device, comprising: a first circuit; a second circuit; and an input and output circuit connected to the first circuit and the second circuit, the input and output circuit being arranged between the first circuit and the second circuit, the input and output circuit comprising: multiple first connection node groups, the multiple first connection node groups being arranged on one side of the first circuit; multiple second connection node groups, the multiple second connection node groups being arranged on one side of the second circuit, the multiple first connection node groups and the multiple second connection node groups being set correspondingly, each The first connection node group corresponds to one second connection node group; multiple connection structure groups are set between the multiple first connection node groups and the multiple second connection node groups, and one connection structure group is set between each first connection node group and the corresponding second connection node group; a first auxiliary connection node is set on one side of the first circuit; a second auxiliary connection node is set on the second circuit side, and the first auxiliary connection node and the second auxiliary connection node are set correspondingly; and an auxiliary connection structure is set on the first auxiliary connection node and the second auxiliary connection node between, and connect the first auxiliary connection node and the second auxiliary connection node; wherein, when one of the first connection node groups of the plurality of first connection node groups, one of the corresponding second connection node groups of the plurality of second connection node groups, and the correspondingly set connection structure group are in an abnormal transmission state, the first auxiliary connection node and the second auxiliary connection node are connected to the first connection node group in the abnormal transmission state and the corresponding second connection node group, so that transmission must pass through the first connection node group in the abnormal transmission state and the corresponding A control signal transmitted by the second connected node group.

In order to solve the above technical problems, one of the technical solutions adopted by the present invention is to provide an input and output circuit, which is suitable for connecting a first circuit and a second circuit. The input and output circuit is arranged between the first circuit and the second circuit. The input and output circuit includes: a plurality of first connection nodes, the plurality of first connection nodes are arranged on one side of the first circuit; A connection node; a plurality of connection structures arranged between the plurality of first connection nodes and the second connection node, one connection structure is arranged between each first connection node and the corresponding second connection node; a first auxiliary connection node is arranged on one side of the first circuit; a second auxiliary connection node is arranged on one side of the second circuit, the first auxiliary connection node and the second auxiliary connection node are correspondingly arranged; When one of the first connection nodes of the plurality of first connection nodes, one of the corresponding second connection node groups of the plurality of second connection node groups, and the corresponding connection structure group are in an abnormal transmission state, the first auxiliary connection node and the second auxiliary connection node are connected to the first connection node in the abnormal transmission state and the corresponding second connection node to transmit a control signal of the first connection node in the abnormal transmission state and the corresponding second connection node.

In order to solve the above-mentioned technical problem, another technical solution adopted by the present invention is to provide a chip device, comprising: a first circuit; a second circuit; and an input and output circuit connected to the first circuit and the second circuit, the input and output circuit is arranged between the first circuit and the second circuit, the input and output circuit includes: multiple first connection node groups, the multiple first connection node groups are arranged on one side of the first circuit; Corresponding to the multiple sets of second connection node groups, one second connection node group is set corresponding to each of the first connection node groups; multiple connection structure groups are set between the multiple first connection node groups and the multiple second connection node groups, and one connection structure group is set between each first connection node group and the corresponding second connection node group; a first auxiliary connection node is set on one side of the first circuit; a second auxiliary connection node is set on one side of the second circuit, the first auxiliary connection node and the second auxiliary connection node are correspondingly set; , arranged between the first auxiliary connection node and the second auxiliary connection node, and connected to the first auxiliary connection node and the second auxiliary connection node; wherein, when one of the first connection node groups of the plurality of first connection node groups, one of the corresponding second connection node groups of the plurality of second connection node groups, and the correspondingly set connection structure group are in an abnormal transmission state, the first auxiliary connection node and the second auxiliary connection node are connected to the first connection node group and the corresponding second connection node group in the abnormal transmission state, so that the transmission must pass through the A control signal transmitted by the first connection node group and the corresponding second connection node group in the abnormal transmission state.

One of the beneficial effects of the present invention is that the input and output circuits and the chip device provided by the present invention can effectively improve the yield rate of the connection circuit between the wafer circuits by adding a plurality of connection nodes and auxiliary connection nodes, and thus improve the yield rate of the chip device.

In order to further understand the features and technical content of the present invention, please refer to the following detailed description and drawings related to the present invention. However, the provided drawings are only for reference and description, and are not intended to limit the present invention.

The following is an illustration of the implementation of the "input and output circuits and chip device" disclosed by the present invention through specific specific embodiments. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various modifications and changes can be made to the details in this specification based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are only for simple illustration, and are not drawn according to the actual size, which is stated in advance. The following embodiments will further describe the relevant technical content of the present invention in detail, but the disclosed content is not intended to limit the protection scope of the present invention. In addition, the term "or" used herein may include any one or a combination of more of the associated listed items depending on the actual situation.

[first embodiment]

Please refer to FIG. 1 and FIG. 2 . FIG. 1 is a schematic diagram of the input and output circuits of the first embodiment of the present invention. FIG. 2 is another schematic diagram of the input and output circuits of the first embodiment of the present invention.

The input and output circuit 1 is suitable for connecting a first circuit 2 and a second circuit 3 . The input and output circuit 1 is arranged between the first circuit 2 and the second circuit 3 . The input and output circuit 1 includes a plurality of first connection node groups 11 , a plurality of second connection node groups 12 and a plurality of connection structure groups 13 .

A plurality of first connection nodes 11 are provided on one side of the first circuit 2 . A plurality of second connection nodes 12 are provided on one side of the second circuit 3 .

A plurality of first connection node groups 11 and a plurality of second connection node groups 12 are set correspondingly, and each first connection node group corresponds to a second connection node group.

The plurality of connection structure groups 13 are arranged between the plurality of first connection node groups 11 and the second connection node groups 12 .

In this embodiment, a connection structure group 13 is provided between each first connection node group 11 and the corresponding second connection node group 12 . The first connection node group 11 includes one or more first connection nodes 11A. The second connection node group 12 includes one or more second connection nodes 12A. One or more first connection nodes 11A of each first connection node group 11 and one or more second connection nodes 12A of the corresponding second connection node group 12 are respectively arranged correspondingly. A connection structure 13A is provided between each first connection node 11A and the corresponding second connection node 12A.

Each first connection node group 11 includes one or more first connection nodes 11A. When the first connection node group 11 includes a plurality of first connection nodes 11A, the plurality of first connection nodes 11A of the first connection node group 11 are connected to each other. Each second connection node group 12 includes one or more second connection nodes 12A. When the second connection node group 12 includes a plurality of second connection nodes 12A, the plurality of second connection nodes 12A of the second connection node group 12 are connected to each other. The connection structure group 13 also includes one or more connection structures 13A. The number of first connection nodes 11A in the first connection node group 11 is equal to the number of second connection nodes 12A in the second connection node group 12 . Similarly, the number of first connection nodes 11A in the first connection node group 11 and the number of second connection nodes 12A in the second connection node group 12 are equal to the number of connection structures 13A in the connection structure group 13 .

In this embodiment, the first connection node group 11 includes a plurality of first connection nodes 11A. The second connection node group 12 includes a plurality of second connection nodes 12A. The connection structure group 13 includes a plurality of connection structures 13A. That is, the number of the first connection nodes 11A of the first connection node group 11 may be two, three or more than three. The number of the second connection nodes 12A of the second connection node group 12 may be two, three or more than three. Similarly, the number of connection structures 13A in the connection structure group 13 can be two, three or more than three.

That is, when the first circuit 2 and the second circuit 3 are stacked, they will be aligned and then connected: for example, wafer bonding (wafer bonding), wire bonding (wire bonding), so as to perform the stacking arrangement of the first circuit 2 and the second circuit 3 . When the circuit is aligned, the accuracy is very important. The distance between the first circuit 2 and the second circuit 3 will affect the yield rate of the input and output circuit 1 connecting the first circuit 2 and the second circuit 3 . In this embodiment, the connection structure 13A can be, for example, a pin header structure, a wafer bonding structure (wafer bonding) or a wire bonding structure (wire bonding).

In addition, as shown in FIG. 1 , the first circuit 2 further includes a plurality of input-output driving circuits 21 , and two adjacent first connection nodes 11 connected to each other are electrically connected to the same input-output driving circuit 21 . That is, the control signal provided by the input/output driving circuit 21 is transmitted to the second circuit 3 through the plurality of first connection nodes 11A of the first connection node group 11 , the connection structure group 13 and the plurality of second connection nodes 12A of the second connection node group 12 .

As shown in FIG. 1 , in this embodiment, each input-output driving circuit 21 includes an output terminal. An impedance R is electrically connected to the output terminal of the input-output driving circuit 21 . As a voltage regulation impedance when outputting a control signal, it is generally called a pull-down impedance (pull low resistor). In other embodiments, the impedance R may not be set.

In this embodiment, the multiple input and output driving circuits 21 of the first circuit 2 may be connected to a control circuit 22 or a logic circuit (not shown in the figure), which is not limited in the present invention. The second circuit 3 may include a plurality of memory circuits 31 , a control circuit or an application circuit, which are not limited in the present invention. That is, the circuits connected to the plurality of second connection nodes 12A provided in the second circuit 3 are not limited in any way.

Please refer to FIG. 2 . In FIG. 2 , the three first connection nodes 11A in the same group are connected to each other. Furthermore, the three first connection nodes 11 of the first connection node group 11 in the same group transmit the control signal of the same input and output driving circuit 21 . Similarly, the three second connection nodes 12A in the same second connection node group 12 are also connected to each other to transmit the control signal transmitted by the I/O driving circuit 21 .

In this embodiment, the first circuit 2 and the second circuit 3 may be a wafer-level circuit (wafer), a chip-level circuit (chip), or a general-scale circuit. The input and output driving circuit 21 is a CMOS IO logic.

[Second embodiment]

Please refer to FIG. 3 . FIG. 3 is a schematic diagram of the input and output circuits of the second embodiment of the present invention.

The input and output circuit 1' is suitable for connecting a first circuit 2' and a second circuit 3'. The input and output circuit 1' is arranged between the first circuit 2' and the second circuit 3'. The input and output circuit 1' comprises a plurality of first connection node groups 11', a plurality of second connection node groups 12', a plurality of connection structure groups 13', a first auxiliary connection node 15', a second auxiliary connection node 16' and an auxiliary connection structure 17'.

A plurality of first connection nodes 11' are provided on one side of the first circuit 2'. A plurality of second connection nodes 12' are provided on one side of the second circuit 3'. Multiple sets of first connection node groups 11' and multiple sets of second connection node groups 12' are set correspondingly. Each first connection node group 11' is correspondingly provided with a second connection node group 12'. The first connection node group 11' includes one or more first connection nodes 11A'. The second connection node group 12' includes one or more second connection nodes 12A'. One or more first connection nodes 11A' of each first connection node group 11' and one or more second connection nodes 12A' of the corresponding second connection node group 12' are respectively correspondingly arranged. A connection structure 13A' is provided between each first connection node 11A' and the corresponding second connection node 12A'.

When the first connection node group 11' includes a plurality of first connection nodes 11A', the plurality of first connection nodes 11A' of the first connection node group 11' are connected to each other. When the second connection node group 12' includes a plurality of second connection nodes 12A', the plurality of second connection nodes 12A' of the second connection node group 12' are connected to each other. The connection structure group 13' also includes one or more connection structures 13A'. The number of first connection nodes 11A' of the first connection node group 11' is equal to the number of second connection nodes 12A' of the second connection node group 12'. Similarly, the number of first connection nodes 11A' in the first connection node group 11' and the number of second connection nodes 12A' in the second connection node group 12' are equal to the number of connection structures 13A' in the connection structure group 13'.

In this embodiment, the first connection node group 11' includes a plurality of first connection nodes 11A'. The second connection node group 12' includes a plurality of second connection nodes 12A'. The connection structure group 13' includes a plurality of connection structures 13A'. That is, the number of the first connection nodes 11A' of the first connection node group 11' may be two, three or more than three. The number of the second connection nodes 12A' of the second connection node group 12' can be two, three or more than three. Similarly, the number of connection structures 13A' in the connection structure group 13' can be two, three or more than three.

Multiple sets of connection structure groups 13' are arranged between multiple sets of first connection node groups 11' and multiple sets of second connection node groups 12'. A connection structure 13A' is provided between each first connection node 11A' and the corresponding second connection node 12A'. In this embodiment, the connecting structure 13A' can be, for example, a wafer bonding structure or a wire bonding structure.

The first auxiliary connection node 15' is arranged on one side of the first circuit 2'. In this embodiment, the first auxiliary connection node 15' and the first connection node 11' are arranged on the same side of the first circuit 2'. The second auxiliary connection node 16' is arranged at one side of the second circuit 3'. The second auxiliary connection node 16' and the second connection node 12' are arranged on the same side of the second circuit 3'.

In addition, the first auxiliary connection node 15' and the second auxiliary connection node 16' are set correspondingly. Moreover, the auxiliary connection structure 17' is arranged between the first auxiliary connection node 15' and the second auxiliary connection node 16', and connects the first auxiliary connection node 15' and the second auxiliary connection node 16'.

Similarly, in this embodiment, each first connection node 11' is connected to an input-output driving circuit 21'. Each second connection node 12' is connected to a circuit. The driving signal provided by the input and output driving circuit 21' of the first circuit 2' is transmitted to the second circuit 3' through the first connection nodes 11', the connection structure groups 13' and the second connection node groups 12' for circuit control.

In addition, in this embodiment, the multiple input and output driving circuits 21' of the first circuit 2' are electrically connected to a control circuit 22' or a logic circuit (not shown), which is not limited in the present invention. The second circuit 3' can be a memory circuit, a control circuit or an application circuit, which is not limited in the present invention. That is, the circuits connected to the plurality of second connection nodes 12' provided in the second circuit 3' are not limited in any way.

Similarly, as shown in FIG. 3 , in this embodiment, each input-output driving circuit 21' includes an output terminal. An impedance R is electrically connected to the output terminal of the input-output driving circuit 21'. As a voltage regulation impedance when outputting a control signal, it is generally called a pull-down impedance (pull low resistor). In other embodiments, the impedance R may not be set.

In this embodiment, the second circuit 3' may also include a memory matrix circuit (not shown). The memory matrix circuit (not shown) includes a plurality of memory circuits (not shown). The plurality of second connection nodes 12' are respectively connected to a plurality of memory circuits (not shown in the figure). In other embodiments, the second circuit 2 may include other application circuits, which is not limited in the present invention.

However, when the first circuit 2' and the second circuit 3' are aligned and connected in the stacking procedure, among the multiple first connection node groups 11', the multiple connection structure groups 13' and the multiple second connection node groups 12', there may be a group of the first connection node group 11', the connection structure group 13' and the second connection node group 12' in an abnormal transmission state (NG state). That is, the first connection node group 11', the connection structure group 13' and the second connection node group 12' cannot transmit the control signal or the transmitted control signal will produce a misjudgment result. At this time, the first auxiliary connection node 15', the second auxiliary connection node 16' and the auxiliary connection structure 17' can be used to assist in the transmission of the control signal.

That is, when one of the first connection node group 11', the corresponding second connection node group 12' and the corresponding connection structure group 13' of the plurality of first connection node groups 11' are in an abnormal transmission state, the first auxiliary connection node 15' and the second auxiliary connection node 16' can be connected to the first connection node group 11' in the abnormal transmission state and the corresponding second connection node group 12', so that the transmission must pass through the first connection node group 11' and the corresponding second connection node group 12 in the abnormal transmission state ’ a control signal.

In addition, the first auxiliary connection node 15' and the second auxiliary connection node 16' can also be connected to the first connection node 11' and the corresponding second connection node 12' in the abnormal transmission state through circuit setting, and can also be connected to the circuit (not shown) corresponding to the control circuit 22' in the first circuit 2' and the second circuit 3'.

In addition, the number of the first auxiliary connection node 15' and the second auxiliary connection node 16' can be adjusted according to actual needs, which is not limited in the present invention.

Similarly, in this embodiment, the multiple input and output drive circuits 21' of the first circuit 2' can be connected to a control circuit 22' or a logic circuit (not shown), which is not limited in the present invention. The second circuit 3' may include a plurality of memory circuits 31', a control circuit or an application circuit, which are not limited in the present invention. That is, the circuits connected to the plurality of second connection node groups 12' provided in the second circuit 3' are not limited in any way. In this embodiment, the first circuit 2' and the second circuit 3' may be a wafer-level circuit (wafer), a chip-level circuit (chip), or a general-scale circuit. The input and output driving circuit 21' is a CMOS IO logic.

[Third embodiment]

Please refer to FIG. 4 , which is a schematic diagram of a wafer device according to a third embodiment of the present invention.

The chip device C1 includes an input and output circuit C11, a first circuit C12 and a second circuit C13.

The input and output circuit C11 includes a plurality of first connection node groups C111 , a plurality of second connection node groups C112 and a plurality of connection structure groups C113 . The plurality of connection structure groups C113 are respectively connected to the plurality of first connection node groups C111 and the plurality of second connection node groups C112.

A connection structure group C113 is provided between each first connection node group C111 and the corresponding second connection node group C112. A plurality of first connection node groups C111 are disposed on one side of the first circuit C12. A plurality of second connection node groups C112 are provided on one side of the second circuit C13. A plurality of first connection node groups C111 are set corresponding to a plurality of second connection node groups C112.

In this embodiment, each first connection node group C111 includes one or more first connection nodes C111A. When the first connection node group C111 includes a plurality of first connection nodes C111A, the plurality of first connection nodes C111A of the first connection node group C111 are connected to each other. Each second connection node group C112 includes one or more second connection nodes C112A. When the second connection node group C112 includes a plurality of second connection nodes C112A, the plurality of second connection nodes C112A of the second connection node group C112 are connected to each other. The connection structure group C113 also includes one or more connection structures C113A. The number of first connection nodes C111A in the first connection node group C111 is equal to the number of second connection nodes C112A in the second connection node group C112 . Similarly, the number of first connection nodes C111A in the first connection node group C111 and the number of second connection nodes C112A in the second connection node group C112 are equal to the number of connection structures C113A in the connection structure group C113 . That is, the number of the first connection nodes C111A of the first connection node group C111 may be one, two, three or more than three. The number of the second connection nodes C112A of the second connection node group C112 can be one, two, three or more than three. Similarly, the number of connection structures C113A in the connection structure group C113 can be one, two, three or more than three.

In addition, the first circuit C12 further includes a plurality of input and output driving circuits C121 and a control circuit C122. The control circuit C122 is electrically connected to a plurality of input and output driving circuits C121. Each first connection node C111 is electrically connected to an input-output driving circuit C121. In this embodiment, the two adjacent first connection nodes C111 connected to each other are connected to the same input-output driving circuit C121.

In other embodiments, three adjacent first connection nodes C11 may be connected to each other. Furthermore, the three adjacent first connection nodes C111 transmit the control signal of the same input and output driving circuit C121. Similarly, three adjacent second connection nodes C112 corresponding to the three first connection nodes C111 connected to each other are also connected to each other, so as to transmit the control signal transmitted by the I/O driving circuit C121.

In addition, the input and output circuit C1 further includes a first auxiliary connection node C15 , a second auxiliary connection node C16 and an auxiliary connection structure C17 .

The first auxiliary connection node C15 is provided at one side of the first circuit C2. The second auxiliary connection node C16 is provided at one side of the second circuit C3. The first auxiliary connection node C15 and the second auxiliary connection node C16 are set correspondingly.

The auxiliary connection structure C17 is arranged between the first auxiliary connection node C15 and the second auxiliary connection node C16, and connects the first auxiliary connection node C15 and the second auxiliary connection node C16.

In addition, in this embodiment, the multiple input and output driving circuits C121 of the first circuit C12 are electrically connected to a control circuit C122 or a logic circuit (not shown), which is not limited in the present invention. The second circuit C13 can be a memory circuit, a control circuit or an application circuit, which is not limited in the present invention. That is, the circuits connected to the plurality of second connection nodes C112 provided in the second circuit C13 are not limited in any way.

Similarly, as shown in FIG. 4 , in this embodiment, each input-output driving circuit C121 includes an output terminal. An impedance R is electrically connected to the output terminal of the input-output driving circuit C121. As a voltage regulation impedance when outputting a control signal, it is generally called a pull-down impedance (pull low resistor). In other embodiments, the impedance R may not be set.

In this embodiment, the second circuit C13 may further include a memory matrix circuit (not shown). The memory matrix circuit (not shown) includes a plurality of memory circuits (not shown). The plurality of second connection nodes C112 are respectively connected to a plurality of memory circuits (not shown).

When the first circuit C12 and the second circuit C13 are aligned and bonded in the stacking process, among the multiple first connection node groups C111, the multiple connection structure groups C113, and the multiple second connection node groups C112, there may be one or more groups of two first connection nodes C111A, two connection structures C113A, and corresponding two second connection nodes C112A that are connected to each other and adjacent to each other in an abnormal transmission state (NG state). That is, the two first connection nodes C111 , the two connection structures C113 and the corresponding two second connection nodes C112 in the group cannot transmit the control signal or the transmitted control signal will produce a misjudgment result. At this time, the first auxiliary connection node C115, the second auxiliary connection node C116 and the auxiliary connection structure C117 can be used to assist in the transmission of the control signal. In this embodiment, the connecting structure C113A may be, for example, a pin row structure, a wafer bonding structure (wafer bonding) or a wire bonding structure (wire bonding).

That is, when two of the plurality of first connection nodes C111 are interconnected and adjacent to each other, the corresponding two interconnected second connection nodes C11 and the corresponding two connection structures C113 are in an abnormal transmission state, the first auxiliary connection node C115 and the second auxiliary connection node C116 can be connected to the two interconnected first connection nodes C111 and the corresponding two interconnected second connection nodes C112 in the abnormal transmission state, so that the transmission must pass through the abnormal transmission state. A control signal of the state of the two first connected nodes C111 connected to each other and the corresponding two connected second connected nodes C112.

In this embodiment, the first auxiliary connection node C115 and the second auxiliary connection node C116 may be connected to an additional auxiliary connection circuit (not shown), so as to be connected to one of the plurality of first connection node groups C111 and one of the corresponding plurality of second connection node groups C112. The auxiliary connection circuit (not shown in the figure) may be a circuit connection area arranged in a matrix.

In addition, the first auxiliary connection node C115 and the second auxiliary connection node C116 may also be connected to the first connection node C111 and the corresponding second connection node C112 in an abnormal transmission state by way of circuit setting, or the connection setting may be performed through the control circuit C122 in the first circuit C12 and the circuit (not shown) corresponding to the second circuit C13.

In addition, the number of the first auxiliary connection node C115 and the number of the second auxiliary connection node C116 can be adjusted according to actual needs, which is not limited in the present invention. In addition, the number of wafer circuits of the chip device C1 can also be adjusted according to actual needs, and the number of input and output circuits can be adjusted according to actual needs.

Similarly, in this embodiment, the multiple input and output driving circuits C121 of the first circuit C12 may be connected to a control circuit C122 or a logic circuit (not shown), which is not limited in the present invention. The second circuit C13 may include a plurality of memory circuits C131, a control circuit or an application circuit, which are not limited in the present invention. That is, the circuits connected to the plurality of second connection node groups C112 provided in the second circuit C13 are not limited in any way. In this embodiment, the first circuit C12 and the second circuit C13 may be a wafer-level circuit (wafer), a chip-level circuit (chip), or a general-scale circuit. The input and output driving circuit C121 is a CMOS IO logic.

[Advantageous Effects of Embodiment]

One of the beneficial effects of the present invention is that the input and output circuits and the chip device provided by the present invention can effectively improve the yield rate of the connection circuit between the wafer circuits by adding a plurality of connection nodes and auxiliary connection nodes, and thus improve the yield rate of the chip device.

The content disclosed above is only a preferred feasible embodiment of the present invention, and does not limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made by using the description and drawings of the present invention are included in the scope of the patent application of the present invention.

1, 1’, C11: input and output circuit 2, 2’, C12: First circuit 3, 3’, C13: Second circuit 11, 11’, C111: first connection node group 12, 12’, C112: Second connecting node group 13, 13’, C113: Connection structure group 21, 21’, C121: Input and output drive circuit 22, 22’, C122: Control circuit R: Impedance 31, 31’, C131: memory circuit 15’, C115: first auxiliary connection node 16’, C116: Second auxiliary connection node 17’, C117: Auxiliary connection structure C1: wafer device 11A, 11A': first connection node 12A, 12A': the second connection node 13A, 13A': connection structure

FIG. 1 is a schematic diagram of the input and output circuits of the first embodiment of the present invention.

FIG. 2 is another schematic diagram of the input and output circuits of the first embodiment of the present invention.

FIG. 3 is a schematic diagram of the input and output circuits of the second embodiment of the present invention.

FIG. 4 is a schematic diagram of a wafer device according to a third embodiment of the present invention.

1: Input and output circuit 2: The first circuit 3: The second circuit 11: The first connection node group 12: The second connection node group 13: Connection structure group 21: Input and output drive circuit 22: Control circuit R: Impedance 31:Memory circuit 11A: first connection node 12A: the second connection node 13A: Connection structure

Claims (10)

An input and output circuit, suitable for connecting a first circuit and a second circuit, the input and output circuit is arranged between the first circuit and the second circuit, the input and output circuit includes: multiple sets of first connection node groups, the multiple sets of first connection node groups are sequentially arranged on one side of the first circuit; multiple sets of second connection node groups, the multiple sets of second connection node groups are sequentially arranged on one side of the second circuit, the multiple sets of first connection node groups and the multiple sets of second connection node groups are set correspondingly, and each set of the first connection node groups is correspondingly provided with a group of the second connection nodes Node groups; and multiple sets of connection structure groups, arranged between the multiple groups of first connection node groups and the multiple groups of second connection node groups; wherein, a set of connection structure groups is provided between each group of the first connection node groups and a corresponding group of the second connection node groups, the first connection node group includes a plurality of first connection nodes, each of the first connection node groups is adjacent to and connected to each other, each of the second connection node groups includes a plurality of second connection nodes, and the second connection node groups The plurality of second connection nodes are adjacent to and connected to each other, and the connection structure group includes a plurality of connection structures. The input and output circuit according to claim 1, wherein the first circuit further includes a plurality of input and output drive circuits, each of the first connection node groups is electrically connected to one of the input and output drive circuits, the input and output drive circuits include an output terminal, and the output terminal of the input and output drive circuit is electrically connected to an impedance. The input and output circuit according to claim 1, wherein each connection structure of the connection structure group is a wafer bonding structure, a wire bonding structure or a pin row structure. An input and output circuit, suitable for connecting a first circuit and a second circuit, the input and output circuit is arranged between the first circuit and the second circuit, the input and output circuit includes: multiple sets of first connection node groups, the multiple first connection node groups are sequentially arranged on one side of the first circuit; multiple second connection node groups, the multiple second connection node groups are sequentially arranged on one side of the second circuit, the multiple first connection node groups and the multiple second connection node groups are set correspondingly, and each first connection node group is correspondingly provided with one second connection node group; A plurality of connection structure groups are arranged between the plurality of first connection node groups and the plurality of second connection node groups, one connection structure group is arranged between each first connection node group and the corresponding second connection node group; a first auxiliary connection node is arranged on one side of the first circuit; a second auxiliary connection node is arranged on one side of the second circuit, and the first auxiliary connection node and the second auxiliary connection node are set correspondingly; Auxiliary connection nodes; wherein, when one of the first connection node groups of the plurality of first connection node groups, one of the corresponding second connection node groups of the plurality of second connection node groups, and the corresponding connection structure group are in an abnormal transmission state, the first auxiliary connection node and the second auxiliary connection node are connected to the first connection node group in the abnormal transmission state and the corresponding second connection node group to transmit a control signal of the first connection node group in the abnormal transmission state and the corresponding second connection node group. When the first connection node group, the corresponding plurality of second connection node groups, and the correspondingly set connection structure groups are in a normal transmission state, the first An auxiliary connection node and the second auxiliary connection node will not be connected to any one of the first connection node group and any one of the second connection node groups. The input and output circuit according to claim 4, wherein the first connection node group includes one or more first connection nodes, the second connection node group includes one or more second connection nodes, and the connection structure group includes one or more connection structures. A chip device, comprising: a first circuit; a second circuit; and an input and output circuit, including a plurality of first connection node groups, a plurality of second connection node groups and a plurality of connection structure groups. A set of first connection node groups is set corresponding to the plurality of second connection node groups; wherein, each of the first connection node groups includes a plurality of first connection nodes, and the plurality of first connection nodes of the first connection node group are adjacent to and connected to each other, and each of the second connection node groups includes a plurality of second connection nodes, and the plurality of second connection nodes of the second connection node group are adjacent to and connected to each other. The chip device according to claim 6, further comprising: a first auxiliary connection node arranged on one side of the first circuit; a second auxiliary connection node arranged on one side of the second circuit, the first auxiliary connection node and the second auxiliary connection node are correspondingly arranged; and an auxiliary connection structure arranged on the first auxiliary connection node and the first auxiliary connection node Between two auxiliary connection nodes, and connected to the first auxiliary connection node and the second auxiliary connection node; wherein, when two of the plurality of first connection nodes are connected to each other and the adjacent first connection nodes, the corresponding two second connection nodes and the correspondingly set connection structure group are in an abnormal transmission state, the first auxiliary connection node and the second auxiliary connection node are connected to the first connection node group in the abnormal transmission state and the corresponding second connection node group, so that transmission must pass through the first connection node group in the abnormal transmission state and the corresponding second connection A control signal transmitted by a node group. A chip device, comprising: a first circuit; a second circuit; and an input and output circuit connected to the first circuit and the second circuit, the input and output circuit being disposed between the first circuit and the second circuit, the input and output circuit comprising: a plurality of first connection node groups, the plurality of first connection node groups being sequentially arranged on one side of the first circuit; a plurality of second connection node groups, the plurality of second connection node groups being sequentially arranged on one side of the second circuit, the plurality of first connection node groups and the plurality of second connection node groups being set correspondingly, each The first connection node group corresponds to one second connection node group; multiple connection structure groups are arranged between the multiple first connection node groups and the multiple second connection node groups, and one connection structure group is set between each first connection node group and the corresponding second connection node group; a first auxiliary connection node is arranged on one side of the first circuit; a second auxiliary connection node is arranged on one side of the second circuit, An auxiliary connection node and the second auxiliary connection node are set correspondingly; and an auxiliary connection structure is arranged between the first auxiliary connection node and the second auxiliary connection node, and connects the first auxiliary connection node and the second auxiliary connection node; wherein, when one of the first connection node groups of the plurality of first connection node groups, one of the second connection node groups of the corresponding plurality of second connection node groups, and the correspondingly set connection structure group are in an abnormal transmission state, the first auxiliary connection node and the second auxiliary connection node are connected to the abnormal transmission state The first connection node group and the corresponding second connection node group are used to transmit a control signal that must be transmitted through the first connection node group and the corresponding second connection node group in the abnormal transmission state. When the plurality of first connection node groups, the corresponding plurality of second connection node groups, and the corresponding set of connection structure groups are in a normal transmission state, the first auxiliary connection node and the second auxiliary connection node will not be connected to any one of the first connection node group and any one of the second connection node groups. The wafer device according to claim 8, wherein the first connection node group includes one first connection node, the second connection node group includes one second connection node, and the connection structure group includes one connection structure. The chip device according to claim 8, wherein the first connection node group includes a plurality of the first connection nodes, the first connection nodes of the first connection node group are connected to each other, the second connection node group includes a plurality of the second connection nodes, the second connection nodes of the second connection node group are connected to each other, and the connection structure group includes a plurality of the connection structures.

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