TWI805269B - Semiconductor structure and fabricating method thereof - Google Patents

Abstract

A ferroelectric field effect transistor (FeFET) having a double-gate structure includes a first gate electrode, a first ferroelectric material layer over the first gate electrode, a semiconductor channel layer over the first ferroelectric material layer, source and drain electrodes contacting the semiconductor channel layer, a second ferroelectric material layer over the semiconductor channel layer, and a second gate electrode over the second ferroelectric material layer.

Description

Semiconductor structure and manufacturing method thereof

The present disclosure relates to ferroelectric structures, and more particularly to memory cells, transistors, and memory structures including ferroelectric materials.

Ferroelectric (FE) memory is a candidate for the next generation of non-volatile memory due to its advantages of fast write/read speed, low power consumption and small size. However, it may be difficult to integrate FE materials with commonly used semiconductor device materials and structures while maintaining suitable ferroelectric properties and device performance.

Embodiments of the disclosure provide a semiconductor structure. The above semiconductor structure includes a first gate electrode, a first ferroelectric material layer located above the first gate electrode, a semiconductor channel layer located above the first ferroelectric material, a plurality of source electrodes and drain electrodes contacting the semiconductor channel layer, A second ferroelectric material layer located above the semiconductor channel layer, and a second gate electrode located above the second ferroelectric material layer.

Embodiments of the disclosure provide a semiconductor structure. The above-mentioned semiconductor structure includes a gate electrode, a semiconductor channel layer, a ferroelectric material layer between the gate electrode and the surface of the semiconductor channel layer, and a plurality of source electrodes and drain electrodes contacting the semiconductor channel layer. The semiconductor channel layer includes a first alternate stack of a plurality of first layers and a plurality of second layers, the first layer has a composition different from that of the second layer, and is located in the first Alternately stacking the third sub-layer above, the third sub-layer has a composition different from the first and second sub-layers, and the second layer of the plurality of first sub-layers and the plurality of second sub-layers above the third sub-layer Stack alternately. Wherein, each of the plurality of first layers of the first alternate stack and the second alternate stack includes a combination of the first metal oxide material MO _x and the second metal oxide material M'O _x , and the first alternate stack Each of the plurality of second sub-layers alternately stacked with the second includes zinc oxide, and the third sub-layer includes a combination of the first metal oxide material _MOx , the second metal oxide material _M'Ox , and zinc oxide. Wherein, M is a first metal selected from the group consisting of indium (In) and tin (Sn) and combinations thereof, and M' is a second metal selected from gallium (Ga), hafnium (Hf), zirconium ( Groups consisting of Zr), titanium (Ti), aluminum (Al), strontium (Sr), barium (Ba), scandium (Sc), magnesium (Mg), lanthanum (La), gadolinium (Gd) and combinations thereof .

Embodiments of the disclosure provide a method for manufacturing a semiconductor structure. The manufacturing method of the above-mentioned semiconductor structure includes forming a first gate electrode, forming a first ferroelectric material layer above the first gate electrode, forming a semiconductor channel layer above the first ferroelectric material layer, and forming a plurality of sources contacting the semiconductor channel layer. pole and drain electrodes, a second ferroelectric material layer is formed on the semiconductor channel layer, and a second gate electrode is formed on the second ferroelectric material layer.

The following disclosure provides many different embodiments or examples for implementing different features of the disclosure. Specific examples of each component and arrangement of the present disclosure are described below to simplify the description. Of course, these examples are not intended to limit the present disclosure. For example, if the description has a first feature formed on or over a second feature, it may include embodiments where the first feature and the second feature are formed in direct contact, and may include additional features formed on the first feature An embodiment in which the first feature and the second feature are not in direct contact with the second feature. Additionally, the present disclosure may repeat reference numbers and/or letters in various instances. This repetition is for simplicity and clarity and does not in itself dictate the relationship between the various embodiments and/or configurations discussed.

Further, this disclosure may use spatially relative terms such as "below," "beneath," "below," "above," "above," and similar terms in order to facilitate the description of an object in a schema. The relationship between an element or feature and another element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be turned in different orientations (rotated 90 degrees or otherwise) and the spatially relative terms used herein should be interpreted accordingly. Unless expressly stated otherwise, elements with the same reference sign should be considered to have the same material composition and have the same thickness in the same thickness range.

The present disclosure relates to ferroelectric (FE) structures, including metal-ferroelectric-semiconductor (MFS) structures, and more particularly to memory cells, transistors, and memory structures including ferroelectric materials .

Various embodiments relate to ferroelectric field effect transistor (FeFET) structures and fabrication methods thereof. FeFETs are emerging devices in which a ferroelectric (FE) layer is used as a gate insulating layer between the gate electrode and the channel region of the semiconductor material layer. Permanent electric field polarization in the ferroelectric (FE) layer allows this type of device to maintain the state of the transistor (on or off) without any electrical bias.

Ferroelectric materials are materials that can have spontaneous non-zero electrical polarization (ie, non-zero total electrical dipole moment) when the external electric field is zero. Spontaneous electrical polarization can be reversed by applying a strong external electric field in the opposite direction. Electric polarization depends not only on the external electric field at the time of measurement, but also on the history of the external electric field, so it has a hysteresis loop. The maximum value of electric polarization is called saturation polarization. The electrical polarization that remains after the external electric field that caused the saturation polarization is no longer applied (ie turned off) is called remnant polarization. The magnitude of the electric field that needs to be applied in the opposite direction to the residual polarization to achieve zero polarization is called the coercive electrical field.

In some embodiments, ferroelectric (FE) structures, such as FeFET structures, may form memory cells of a memory array. In FeFET-based memory cells, the FE material between the gate electrode and the channel region of the semiconductor material layer can have two stable remnant polarization states. In one remnant polarization state, the FeFET can be permanently "on" and in the other remnant polarization state, the FeFET can be permanently "off". Therefore, the polarization state of the FE layer can be used to encode information (ie, bits) in a non-volatile manner. The logic state of FeFET-based memory cells can be read non-destructively by sensing the resistance across the FeFET's terminals (eg, source and drain terminals). The difference between the threshold voltage of a FeFET in the "on" state and the "off" state can be referred to as the "memory window (MW)" of a FeFET-based memory cell.

To reprogram a FeFET-based memory cell, a sufficiently high voltage can be applied to the FeFET to cause the polarization state of the FE material to reverse, thereby changing the logic state of the FeFET memory cell.

For the purpose of forming ferroelectric based memory devices, it is generally desirable to have high remnant polarization as well as high coercive electric field. High remnant polarization increases the magnitude of electrical signals. The high coercive electric field makes the memory device more stable against perturbation caused by noise-level electric fields and disturbances. It is also desirable to have ferroelectric-based memory devices (eg, FeFET-based memory devices) with relatively large memory windows (MW) and high on-current (I _on ) to help ensure memory The logical state of the voxels is correctly interpreted during read operations.

FeFETs fabricated using thin film transistor (TFT) technology and structures, including the use of oxide semiconductors, are attractive for back-end-of-line (BEOL) integration option because TFTs can be processed at low temperatures and thus will not harm previously fabricated devices. However, to date, it has proven difficult to integrate ferroelectric gate oxides with oxide semiconductor channels while maintaining sufficient ferroelectric properties and device performance.

Accordingly, various embodiments provide ferroelectric structures including ferroelectric field effect transistors (FeFETs) and methods of forming ferroelectric structures with improved ferroelectric properties and device performance. Specifically, embodiments include a FeFET device having a dual gate structure including a first layer of ferroelectric material disposed between a first gate electrode and a first side of a channel layer, and a layer comprising a first ferroelectric material disposed between a first gate electrode and a first side of a channel layer. The second ferroelectric material layer between the gate electrode and the second side of the channel layer, wherein the second side of the channel layer is opposite to the first side of the channel layer. In various embodiments, the channel layer may be a metal oxide semiconductor channel layer.

In various embodiments, a FeFET device having a dual gate structure can be operated in a common gate control mode in which a common gate voltage can be simultaneously applied to the first gate electrode and the second gate electrode. This can provide FeFET-based memory devices with increased polarization, memory window, and on-current (I _on ).

Alternatively or additionally, a FeFET device having a dual gate structure can be operated in a separated gate control mode in which different voltages can be selectively applied to the first a gate electrode and a second gate electrode. In various embodiments, a first pair of source and drain electrodes can electrically contact a first side of the channel layer, and a second pair of source and drain electrodes can electrically contact a second side of the channel layer. The first gate electrode, the first ferroelectric material layer, the first pair of source and drain electrodes and the channel layer can provide the first FeFET memory cell, while the second gate electrode, the second ferroelectric material layer, the first Two pairs of source and drain electrodes and a channel layer provide a second FeFET memory cell. In some embodiments, the first FeFET memory unit may be a main memory unit, and the second FeFET memory unit may be a secondary memory unit or a backup (back-up) memory unit. In the event of failure or loss of function of the first FeFET memory cell (i.e. the main memory cell), the FeFET device operating in decentralized gate control mode can utilize the second memory cell (i.e. the backup memory cell) to store and/or retrieve logical state information. This can provide memory devices with improved reliability and performance.

Referring to FIG. 1A , there is shown a vertical cross-sectional view of a first exemplary structure according to an embodiment of the present disclosure prior to formation of an array of memory structures according to various embodiments of the present disclosure. The first exemplary structure includes a substrate 8 comprising a layer 10 of semiconductor material. Substrate 8 may be a bulk semiconductor substrate, such as a silicon substrate, in which a layer of semiconductor material extends continuously from the top surface of substrate 8 to the bottom surface of substrate 8, or substrate 8 may comprise a layer of semiconductor material 10 is a semiconductor-on-insulator layer, and the semiconductor material layer 10 serves as a top semiconductor layer and covers a buried insulator layer (eg, a silicon oxide layer). Exemplary structures may include various device regions, which may include a memory array region 50 in which at least one array of non-volatile memory cells may subsequently be formed.

The exemplary structure may also include a peripheral logic region 52 in which electrical interconnections between each non-volatile memory cell array and peripheral circuitry (including field effect transistors) may then be formed. The areas of the memory array area 50 and the peripheral logic area 52 can be used to form various components of peripheral circuits.

Semiconductor devices such as field effect transistors (FETs) may be formed on and/or in the semiconductor material layer 10 during front-end-of-line (FEOL) operations. For example, shallow trench isolation structures 12 may be formed in the upper portion of semiconductor material layer 10 by forming shallow trenches and then filling these shallow trenches with a dielectric material such as silicon oxide. . Other suitable dielectric materials are also within the scope of this disclosure. Various doped wells (not explicitly shown) may be formed in various regions of the upper portion of the semiconductor material layer 10 by performing a masked ion implantation process.

Gate structure 20 may be formed over the top surface of substrate 8 by depositing and patterning a gate dielectric layer, a gate electrode layer, and a gate capping dielectric layer. Each gate structure 20 may include a vertical stack of gate dielectric 22, gate electrode 24, and gate capping dielectric 28, referred to herein as a gate stack (gate dielectric 22, gate electrode 24, gate capping dielectric 28). It should be noted that, in order to make the description clear and easy to understand, the present disclosure hereinafter refers to the gate stack (gate dielectric 22, gate electrode 24, gate capping dielectric 28) simply as the gate stack (22, 24, 28). An ion implantation process may be performed to form an extension implant region, which may include a source extension region and a drain extension region. Dielectric gate spacers 26 may be formed around the gate stacks (22, 24, 28). The assembly of each gate stack ( 22 , 24 , 28 ) with dielectric gate spacers 26 constitutes gate structure 20 . An additional ion implantation process can be performed using the gate structure 20 as a self-aligned implant mask to form a deep active region. The deep active region may include deep source regions and deep drain regions. An upper portion of the deep active region may overlap some portion of the extended implant area. The combination of each extended implant region and the deep active region can constitute the active region 14, and the active region 14 can be a source region or a drain region according to the electrical bias. Semiconductor channels 15 may be formed under each gate stack ( 22 , 24 , 28 ) between adjacent pairs of active regions 14 . A metal-semiconductor alloy region 18 may be formed on the top surface of each active region 14 . Field effect transistors may be formed on the layer 10 of semiconductor material. Each field effect transistor may include a gate structure 20 , a semiconductor channel 15 , a pair of active regions 14 (one as a source region and the other as a drain region), and optionally a metal-semiconductor alloy region 18 . A complementary metal-oxide-semiconductor (CMOS) circuit 75 may be provided on the semiconductor material layer 10, and the complementary metal-oxide-semiconductor circuit 75 may include a peripheral circuit for a transistor array, such as will be subsequently Formed thin film transistor (thin film transistor, TFT) and memory device.

Various interconnection level structures can then be formed, these interconnection level structures are formed before forming the fin back gate field effect transistor array, and are collectively referred to herein as the lower interconnection level structure (L0 , L1, L2). In the case where a two-dimensional array of TFTs and memory devices will subsequently be formed over two levels of interconnect level metal lines, the lower interconnect level structure (L0, L1, L2) may include the contact level structure L0, the first An interconnection hierarchy L1, and a second interconnection hierarchy L2. The contact hierarchy L0 may include a planarization dielectric layer 31A comprising a planarization dielectric material such as silicon oxide and contact via structures 41V of various contact via structures 41V. The active region 14 is also the gate electrode 24 and is formed in the planarization dielectric layer 31A. The first interconnect level structure L1 includes a first interconnect level dielectric (interconnect level dielectric, ILD) layer 31B and a first metal line 41L formed in the first ILD layer 31B. The first ILD layer 31B is also called a first line-level dielectric layer. The first metal line 41L may contact a corresponding one of the contact via structures 41V. The second interconnection hierarchy L2 includes a second ILD layer 32, which may include a stack of a first via level dielectric material layer and a second line level dielectric material layer, or a line and via level layer of dielectric material. The second ILD layer 32 may be formed to have therein a second interconnect level metal interconnect structure (42V, 42L) including a first metal via structure 42V and a second interconnect level metal interconnect structure (42V, 42L). Two metal wires 42L. The top surface of the second metal line 42L may be coplanar with the top surface of the second ILD layer 32 .

FIG. 1B is a vertical cross-sectional view of a first exemplary structure during formation of an array of ferroelectric-based devices, such as TFT FeFET memory cells, according to an embodiment of the present disclosure. Referring to FIG. 1B, an array 95 of non-volatile memory cells, such as TFT FeFET devices, may be formed in the memory array region 50 above the second interconnect hierarchy L2. Details of the structure and process operations of the array 95 of non-volatile memory cells will be described in detail later. The third ILD layer 33 may be formed during the formation of the array 95 of non-volatile memory cells. The collection of all structures formed at the level of the array 95 of non-volatile memory cells is referred to herein as the third interconnect level structure L3.

FIG. 1C is a vertical cross-sectional view of a first exemplary structure after forming an upper-level metal interconnection structure according to an embodiment of the present disclosure. Referring to FIG. 1C , a third interconnection level metal interconnection structure ( 43V, 43L) may be formed in the third ILD layer 33 . The third interconnect level metal interconnect structure ( 43V, 43L) may include a second metal via structure 43V and a third metal line 43L. Additional interconnection hierarchies may subsequently be formed, referred to herein as upper interconnection hierarchies (L4, L5, L6, L7). For example, the upper interconnection hierarchy (L4, L5, L6, L7) may include a fourth interconnection level L4, a fifth interconnection level L5, a sixth interconnection level L6, and a seventh interconnection level Structure L7. The fourth interconnect level structure L4 may include a fourth ILD layer 34 having a fourth interconnect level metal interconnect structure (44V, 44L) formed therein, wherein the fourth interconnect level metal interconnect structure ( 44V, 44L ) may include a third metal via structure 44V and a fourth metal line 44L. The fifth interconnect level structure L5 may include a fifth ILD layer 35 having a fifth interconnect level metal interconnect structure (45V, 45L) formed therein, wherein the fifth interconnect level metal interconnect structure (45V, 45L) may include a fourth metal via structure 45V and a fifth metal line 45L. The sixth interconnect level structure L6 may include a sixth ILD layer 36 having a sixth interconnect level metal interconnect structure (46V, 46L) formed therein, wherein the sixth interconnect level metal interconnect structure ( 46V, 46L) may include a fifth metal via structure 46V and a sixth metal line 46L. The seventh interconnection level structure L7 may include a seventh ILD layer 37 having a sixth metal via structure 47V (which is a seventh interconnection level metal interconnection structure) and a metal pad ( bonding pad) 47B. Metal pad 47B may be configured for solder bonding (C4 ball bonding or wire bonding may be used), or may be configured for metal-to-metal bonding (eg, copper-to-copper bonding).

Each ILD layer may be referred to as ILD layer 30 . Each interconnect level metal interconnect structure may be referred to as a metal interconnect structure 40 . Each successive combination of metal via structures and overlying metal lines within the same interconnection hierarchy (second interconnection hierarchy L2-seventh interconnection hierarchy L7) can be achieved by using two single damascene ( The damascene process sequentially forms two different structures, or a dual damascene process can be used to simultaneously form a monolithic structure. Each metal interconnect structure 40 may include a respective metal liner (for example, a TiN, TaN, or WN layer having a thickness ranging from 2 nanometers (nm) to 20 nm), and a respective metal fill Materials (for example: W, Cu, Co, Mo, Ru, other elemental metals, or alloys thereof, or combinations thereof). Other suitable materials for the metal liner and metal fill material are also within the contemplation of the present disclosure. Various etch stop dielectric layers and dielectric capping layers may be sandwiched between vertically adjacent pairs of ILD layers 30 , or may be incorporated into one or more ILD layers 30 .

Although the present disclosure takes the example that an array 95 of non-volatile memory cells (eg, TFT FeFET devices) may be formed as a component of the third interconnection hierarchy L3, non-volatile memory cells are expressly contemplated herein. The array 95 of volatile memory cells may be formed as an embodiment of a component of any other interconnection hierarchy (eg, first interconnection hierarchy L1-seventh interconnection hierarchy L7). Further, although the present disclosure describes embodiments using combinations of eight interconnection hierarchies formed, embodiments using a different number of interconnection hierarchies are expressly contemplated herein. Furthermore, embodiments in which two or more arrays 95 of non-volatile memory cells are provided in a plurality of interconnected hierarchies of memory array region 50 are expressly contemplated herein. Although this disclosure describes embodiments in which the array 95 of non-volatile memory cells can be formed in a single interconnect hierarchy, it is expressly contemplated herein that the array 95 of non-volatile memory cells can be Embodiments formed over two vertically adjacent interconnect hierarchies. Further, embodiments are expressly contemplated herein in which the array 95 of non-volatile memory cells may be formed on or in the layer of semiconductor material 10 (eg, in a front-end-of-line (FEOL) operation).

2-9 and 11-21 are a series of vertical cross-sectional views of exemplary structures during the process of forming FeFET devices, such as TFT FeFET devices, according to various embodiments of the present disclosure. The FeFET devices can form a memory cell that can be part of an array 95 of memory cells as shown in FIG. 1C. Referring to FIG. 2 , a first dielectric material layer 110 may be deposited over the substrate 100 . Substrate 100 may be any suitable substrate, such as a semiconductor device substrate, and may include control elements formed during the FEOL process. In some embodiments, one or more additional dielectric layers (eg, ILD layers) may be deposited between the substrate 100 and the first dielectric material layer 110 . In such embodiments, the first dielectric material layer 110 may be omitted. For example, the third ILD layer 33 discussed above with reference to FIGS. 1B and 1C may be deposited over the substrate 100 or instead of the substrate 100 .

The first dielectric material layer 110 can be formed of any suitable dielectric material, such as silicon oxide (SiO ₂ ), or a high-k dielectric material, such as silicon nitride (SiN ₄ ), hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (Hf _0.5 Zr _0.5 O ₂ ), tantalum oxide (Ta ₂ O ₅ ), aluminum oxide (Al ₂ O ₃ ), hafnium dioxide-alumina (HfO ₂ -Al ₂ O ₃ ), zirconium oxide (ZrO ₂ ), etc. In some embodiments, the first dielectric material layer 110 may be a native oxide layer formed on the substrate 100 . Other suitable dielectric materials are also within the scope of this disclosure.

The first dielectric material layer 110 may be deposited using any suitable deposition process. In this context, suitable deposition processes may include chemical vapor deposition (chemical vapor deposition, CVD), physical vapor deposition (physical vapor deposition, PVD), atomic layer deposition (atomic layer deposition, ALD), high-density plasma chemical Vapor deposition (high density plasma CVD, HDPCVD), metal organic chemical vapor deposition (metalorganic CVD, MOCVD), plasma enhanced chemical vapor deposition (plasma enhanced CVD, PECVD), sputtering (sputtering), laser ablation Melting (laser ablation), etc.

FIG. 3 is a vertical cross-sectional view of an exemplary intermediate structure showing the bottom gate electrode 120 formed in the first dielectric material layer 110 . Referring to FIG. 3 , a bottom gate electrode 120 may be deposited on the first dielectric material layer 110 . In an embodiment, the bottom gate electrode 120 may be embedded in the first dielectric material layer 110 . For example, a photoresist layer (not shown) may be deposited on the first dielectric material layer 110 and patterned using photolithographic techniques. The pattern of the photoresist layer may be transferred to the first dielectric material layer 110, and thus, the first dielectric material layer 110 may be patterned to form trenches. A conductive material may be deposited in the trench and a planarization process is performed to planarize the bottom gate electrode 120 and the upper surface of the first dielectric material layer 110 .

Alternatively, the bottom gate electrode 120 may be deposited as a continuous electrode layer on the upper surface of the first dielectric material layer 110 such that the continuous electrode layer contacts the upper surface of the first dielectric material layer 110 . Selected portions of the continuous electrode may be removed (eg, by etching the continuous electrode layer using a patterned mask formed by a lithographic process) to form one or more discrete electrodes on the first dielectric material layer 110. The (discrete) patterned bottom gate electrode 120 . Next, additional dielectric material may be formed over the exposed surface of the first dielectric material layer 110, the side surfaces of the patterned electrode layer, and optionally over the upper surface of the bottom gate electrode 120 to separate the bottom The gate electrode 120 is embedded in a dielectric material. A planarization process may then be performed to planarize the upper surface of the bottom gate electrode 120 and the first dielectric material layer 110 to provide the bottom gate electrode 120 embedded in the first dielectric material layer 110, as shown in FIG. Show.

In other embodiments, the bottom gate electrode 120 may be embedded in a semiconductor material layer, such as the semiconductor material layer 10 shown in FIGS. 1A-1C .

The bottom gate electrode 120 may comprise any suitable conductive material, such as copper (Cu), aluminum (Al), zirconium (Zr), titanium (Ti), titanium nitride (TiN), tungsten (W), tantalum (Ta) , tantalum nitride (TaN), molybdenum (Mo), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), iridium (Ir), iron (Fe), beryllium ( Be), chromium (Cr), antimony (Sb), osmium (Os), thorium (Th), vanadium (V), alloys thereof, and combinations thereof. Other suitable conductive materials for the bottom gate electrode 120 are also within the contemplation of the present disclosure. In some embodiments, the material of the bottom gate electrode 120 can optionally have a lower coefficient of thermal expansion (CTE) than a ferroelectric (FE) material subsequently formed over the bottom gate electrode 120 . The CTE of the material layer. Using a bottom gate electrode 120 with a lower CTE than the CTE of the overlying FE material layer can impose tensile stress on the FE material layer and improve the ferroelectric properties of the FE material layer, as described in further detail below. discussed. In an embodiment, the CTE of the material of the bottom gate electrode 120 may be less than 14×10 ⁻⁶ /K.

Bottom gate electrode 120 may be deposited using any suitable deposition process. For example, suitable deposition processes may include physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), or combination. The thickness of the bottom gate electrode 120 can range from 10 nm to 100 nm, although smaller and larger thicknesses can also be used.

FIG. 4 is a vertical cross-sectional view of an exemplary intermediate structure showing an optional stress layer 130 deposited over the bottom gate electrode 120 and the upper surface of the first dielectric material layer 110 . Referring to FIG. 4 , the optional stress layer 130 may include a metal oxide material that may serve as a buffer layer for a ferroelectric material layer subsequently formed over the stress layer 130 . The material of the optional stress layer 130 may have a lattice mismatch with the ferroelectric material layer subsequently formed over the stress layer 130 such that tensile strain occurs in the ferroelectric material layer. It is well known that in many FE materials, such as in hafnium zirconium oxide (Hf _x Zr _1-x O _y , also known as "HZO"), small changes in the lattice parameter (lattice parameter) may cause most FE materials It has an ideal crystal phase (for example: orthorhombic crystal phase) relative to other crystal phases (for example: monoclinic crystal phase (monoclinic crystal phase)). The tensile strain induced by the lattice mismatch between the stressor layer 130 and the FE layer can provide the FE layer with improved ferroelectric properties, such as increased remnant polarization P _r .

The optional stress layer 130 may include metal oxide materials such as Ta ₂ O ₅ , K ₂ O, Rb ₂ O, SrO, BaO, aV ₂ O ₃ , a-Cr ₂ O ₃ , a-Ga ₂ O ₃ , a-Fe ₂ O ₃ , a-Ti ₂ O ₃ , a-In ₂ O ₃ , YAlO ₃ , Bi ₂ O ₃ , Yb ₂ O ₃ , Dy ₂ O ₃ , Gd ₂ O ₃ , SrTiO ₃ , DyScO ₃ , _TbScO3 , _GdScO3 , _NdScO3 , _NdGaO3 , _LaSrAlTaO3 (LSAT) and combinations thereof. In various embodiments, the stress layer 130 may include a multi-layer structure including at least one thin layer composed of LaSrMnO ₃ (LMSO). For example, the stress layer 130 may include a bilayer structure, such as LSMO/SrTiO ₃ , LSMO/DyScO ₃ , LSMO/TbScO ₃ , LSMO/GdScO ₃ , LSMO/NdScO ₃ , LSMO/NdGaO ₃ , and LSMO/LSAT. Other suitable materials for the stress layer 130 are also within the scope of the present disclosure. In various embodiments, the lattice constant a ₀ of the optional stress layer 130 may be greater than the in-plane lattice constant of the material of the ferroelectric (FE) material layer subsequently formed above the stress layer 130 , To induce tensile strain in the FE material layer.

The optional stressor layer 130 may be deposited using any suitable deposition process. In various embodiments, the optional stress layer 130 may be deposited using atomic layer deposition (ALD) or pulsed laser deposition (PLD). In some embodiments, the optional stress layer 130 may be thermally annealed at a temperature between 300 degrees Celsius (°C) and 700°C for 30 seconds to 10 minutes to increase the crystallinity of the stress layer 130 . Longer or shorter annealing times and higher or lower annealing temperatures may also be used. Alternatively or additionally, the stressor layer 130 may be deposited as a quasi-single crystal metal oxide material using a suitable deposition technique (eg, PLD). The optional stress layer 130 thickness can range from 0.5 nm to 5 nm, although smaller and larger thicknesses can also be used.

FIG. 5 is a vertical cross-sectional view of an exemplary intermediate structure showing an optional seed layer 135 deposited on the upper surface of an optional stressor layer 130 . In embodiments where optional stressor layer 130 is absent, optional seed layer 135 may be deposited on the upper surface of bottom gate electrode 120 and first dielectric material layer 110 . The optional seed layer 135 (also referred to as a ferroelectric promotional layer) includes materials that can be configured to promote the formation of a desired crystal structure in a layer of FE material subsequently formed thereon. For example, the seed layer 135 can promote cubic (cubic, c-phase), tetragonal (t-phase) and/or orthorhombic (c-phase), tetragonal (t-phase) and/or orthorhombic ( Orthorhombic, o-phase) crystal phase formation, and can also suppress the transition from the t-phase crystal structure to the m-phase crystal structure in the FE material layer. This enables the layer of FE material to have improved ferroelectric properties, such as increased remnant polarization P _r .

In various embodiments, the optional seed layer 135 can be a metal oxide material such as zirconia (ZrO ₂ ), zirconia-yttrium (ZrO ₂ -Y ₂ O ₃ ), hafnium oxide (HfO ₂ ), oxide Aluminum (Al ₂ O ₃ ), and hafnium zirconium oxide (Hf _x Zr _1-x O ₂ , where 0≤x≤1), and combinations thereof. Other suitable materials for the seed layer 135 are also within the scope of the present disclosure. The seed layer 135 may include a single layer of metal oxide material, or may include multiple layers of metal oxide material that may have different compositions. In various embodiments, the crystal structure of the seed layer material may include cubic crystal phase, tetragonal crystal phase and/or orthorhombic crystal phase.

The optional seed layer 135 may be deposited using any suitable deposition process. In various embodiments, the optional seed layer 135 may be deposited using atomic layer deposition (ALD) or pulsed laser deposition (PLD). In some embodiments, the optional seed layer 135 may be thermally annealed at a temperature between 300° C. and 700° C. for 30 seconds to 10 minutes to increase the crystallinity of the seed layer 135 . In embodiments where optional stressor layer 130 is present, stressor layer 130 and seed layer 135 may be annealed simultaneously, or may be annealed in separate annealing operations. Alternatively or additionally, the seed layer 135 may be deposited as a quasi-single crystal metal oxide material using a suitable deposition technique (eg, PLD). The optional seed layer 135 thickness can range from 0.1 nm to 5 nm, although smaller and larger thicknesses can also be used.

FIG. 6 is a vertical cross-sectional view of an exemplary intermediate structure showing a layer 140 of ferroelectric (FE) material deposited over the upper surface of an optional seed layer 135 . In embodiments where the optional seed layer 135 is absent, a layer of FE material 140 may be deposited over the upper surface of the optional stressor layer 130 . In embodiments where neither the optional seed layer 135 nor the optional stressor layer 130 are present, the FE material layer 140 may be deposited over the bottom gate electrode 120 and the upper surface of the first dielectric material layer 110 .

The layer of FE material 140 may be formed from any suitable ferroelectric material. In various embodiments, the FE material layer 140 can be a ferroelectric material based on hafnium oxide, such as Hf _x Zr _1-x O _y , where 0≤x≤1 (for example: Hf _0.5 Zr _0.5 O ₂ ), HfO ₂ , HfSiO, HfLaO, etc. In various embodiments, the FE material layer 140 can be hafnium zirconium oxide (HZO), doped with atoms with an ionic radius smaller than that of hafnium (for example: Al, Si, etc.), and/or doped with atoms with an ionic radius larger than that of hafnium (For example: La, Sc, Ca, Ba, Gd, Y, Sr, etc.). The concentration of the dopant may be configured to improve the ferroelectric properties of the layer of FE material 140 , for example to increase remnant polarization. In various embodiments, the dopant with an ionic radius smaller than hafnium and/or the dopant with an ionic radius larger than hafnium may have a doping concentration between about 1 mol.% and about 20 mol.%. In some embodiments, the FE material of the FE material layer 140 may include oxygen vacancy. Oxygen vacancies in the FE material may promote the formation of an orthorhombic (o-phase) crystal phase in the FE material layer 140 .

In some embodiments, the FE material of the FE material layer 140 may include AlN doped with Sc. Other suitable materials for the FE material layer 140 are also within the scope of the present disclosure, including but not limited to: ZrO ₂ , PbZrO ₃ , Pb[Zr _x Ti _1-x ]O ₃ (0≤x≤ 1) (PZT), Pb _1-x La _x Zr _1-y Ti _y O ₃ (PLZT), BaTiO ₃ , PbTiO ₃ , PbNb ₂ O ₆ , LiNbO ₃ , LiTaO ₃ , PbMg _1/3 Nb _2/3 O ₃ (PMN), PbSc _1/2 Ta _1/2 O ₃ (PST), SrBi ₂ Ta ₂ O ₉ (SBT), Bi _1/2 Na _1/2 TiO ₃ , and combinations thereof.

In some embodiments, the FE material layer 140 may include a single layer of FE material, or may include multiple layers of FE material that may have different compositions. In various embodiments, the crystal structure of the FE material layer 140 may include cubic, tetragonal and/or orthorhombic phases. In an embodiment, the FE material layer 140 may include a hafnium oxide-based ferroelectric material, such as Hf _x Zr _1-x O _y , and may have a structure such that the FE material has a cubic, tetragonal, and/or orthorhombic crystal structure. The volume is more than 50% larger than that of FE material with monoclinic crystal structure.

The layer of FE material 140 may be deposited using any suitable deposition process. In various embodiments, the layer of FE material 140 may be deposited using atomic layer deposition (ALD). The thickness of the layer of FE material 140 may range from 0.1 nm to 100 nm, although smaller and larger thicknesses may also be used.

In various embodiments, the layer of FE material 140 can optionally be under tensile strain (indicated by arrows 141 and 142 in FIG. sexually displayed). In some embodiments, the layer of FE material 140 may be subjected to a tensile strain of between 1.5% and 3.0% on at least a portion of the layer of FE material 140 . As described above, subjecting the layer of FE material 140 to tensile strain can promote the formation and stabilization of crystalline structures such as the orthorhombic phase, which can increase the ferroelectric properties of the material relative to other structures that may, for example, degrade the ferroelectric properties of the material. Characteristic monoclinic phase. In various embodiments where an optional stressor layer 130 is present, the tensile strain on the FE material layer 140 may be caused at least in part by a lattice mismatch between the stressor layer 130 and the FE material layer 140 . As mentioned above, the lattice constant a ₀ of the optional stressor layer 130 may be greater than the in-plane lattice constant of the material of the ferroelectric (FE) material layer 140 to induce tensile strain in the FE material layer.

Alternatively or additionally, the tensile strain on the layer of FE material 140 may be caused at least in part by a mismatch in the coefficient of thermal expansion (CTE) between the bottom gate electrode 120 and the layer of FE material 140 . As mentioned above, in various embodiments, the material of the bottom gate electrode 120 may have a lower CTE than the material of the FE material layer 140 . For example, in embodiments where the FE material layer 140 comprises hafnium zirconium oxide ⁽ HZO) having a CTE of 14×10 ⁻⁶ /K, the bottom gate electrode 120 may comprise /K material. Suitable conductive materials with a relatively low CTE include, but are not limited to: platinum (Pt), titanium (Ti), titanium nitride (TiN), tungsten (W), tantalum (Ta), tantalum nitride (TaN), Iron (Fe), Nickel (Ni), Beryllium (Be), Chromium (Cr), Cobalt (Co), Antimony (Sb), Iridium (Ir), Molybdenum (Mo), Osmium (Os), Thorium (Th), Vanadium (V), alloys thereof, and combinations thereof. In various embodiments, tensile strain can be induced in the FE material layer 140 by subjecting the intermediate structure shown in FIG. The intermediate structure is annealed at temperature for a time between 30 seconds and 5 minutes, followed by a cooling period. During cooling, the FE material layer 140 may shrink more than the bottom gate electrode 120 because of the difference in CTE. This may stretch the layer of FE material 140 in the direction of arrows 141 and 142 and thus subject the layer of FE material 140 to permanent tensile strain.

FIG. 7 is a vertical cross-sectional view of an exemplary intermediate structure showing an optional insulating layer 145 deposited on the upper surface above layer 140 of FE material. Referring to FIG. 7, an optional insulating layer 145 (also referred to as a "barrier" layer) may comprise a layer of dielectric material, such as a high-k dielectric material. Herein, high-k dielectric materials have a dielectric constant greater than 3.9 and may include, but are not limited to: hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), zirconium silicate (ZrSiO ₄ ), hafnium oxide Tantalum (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (Hf _x Zr _x-1 O _y ) (HZO), silicon nitride (SiN _x ), tantalum oxide (Ta ₂ O ₅ ), aluminum oxide (Al ₂ O ₃ ), Lanthanum Aluminate (LaAlO ₃ ), Hafnium Dioxide-Alumina (HfO ₂ - Al ₂ O ₃ ), Zirconia (ZrO ₂ ), Magnesium Oxide (MgO), Yttrium Oxide (Y ₂ O ₃ ) , lanthanum oxide (La ₂ O ₃ ), strontium oxide (SrO), gadolinium oxide (Gd ₂ O ₃ ), calcium oxide (CaO), scandium oxide (Sc ₂ O ₃ ), combinations thereof, and the like. In an embodiment, the optional insulating layer 145 may include Si, Mg, Al, Y ₂ O ₃ , La, Sr, Gd, N, Sc, Ca, etc., including Si, Mg, Al, Y ₂ O ₃ , La , Sr, Gd, N, Sc, Ca, etc. any combination compound. Other suitable dielectric materials are also within the scope of this disclosure.

Optional insulating layer 145 may be deposited using any suitable deposition process, as described above. In various embodiments, optional insulating layer 145 may be deposited using atomic layer deposition (ALD). The thickness of the optional insulating layer 145 can range from 0.1 nm to 10 nm, although smaller and larger thicknesses can also be used.

The optional insulating layer 145 can act as a barrier between the FE material layer 140 and the semiconducting channel layer, which can be subsequently formed over the insulating layer 145 . The optional insulating layer 145 can help reduce the surface state density (D _it ) and inhibit carrier (ie, electron and/or hole) injection from the semiconductor channel layer. In various embodiments, the optional material of the insulating layer 145 may have a higher band gap (E _g ), which is higher than that of the subsequently formed semiconductor channel layer. For example, in the case that the subsequently formed semiconductor channel layer is amorphous InGaZnO ₄ (a-IGZO), a-IGZO has an energy gap E _g of ~3.16eV (electron volts), and the optional insulating layer 145 The material may have a larger energy gap (for example: _Eg ≥ 3.5eV, such as Eg ≥ 5.0eV). Further, the conduction band offset (conduction band offset, E _CBO ) and valence band offset (valence band offset, E _VBO ) between the material of the insulating layer 145 and the semiconductor channel layer can be large enough (for example: E _CBO >1eV , E _VBO >1eV) to block the injection of charge carriers (including both electrons and holes) into the insulating layer 145 , thereby minimizing the leakage current from the semiconductor channel layer. In various embodiments, the optional insulating layer 145 may include silicon-doped hafnium oxide, such as Hf _{1-x Six} O _y , where x>0.1 and y>0.

In some embodiments, the FE material layer 140 may include hafnium zirconium oxide (HZO), and the optional insulating layer 145 may include a hafnium-containing dielectric material, such as silicon-doped hafnium oxide. The interface region 146 adjacent to the interface between the FE material layer 140 and the optional insulating layer 145 may include a first interface region portion 146a located in the FE material layer 140, and include a The second interface region portion 146b is adjacent to and located in the optional insulating layer 145 . Each of the first interface region portion 146a and the second interface region portion 146b may have a thickness of at least 1 nm. In various embodiments, within the interface region 146, the ratio of the atomic percentage of oxygen to the atomic percentage of zirconium may be greater than or equal to (≥) 1, and the ratio of the atomic percentage of oxygen to the atomic percentage of hafnium , can be greater than (>)1.

FIG. 8 is a vertical cross-sectional view of an exemplary intermediate structure showing a channel layer 150 a deposited on the upper surface of an optional insulating layer 145 during fabrication. In embodiments where the optional insulating layer 145 is not present, a channel layer 150 a may be deposited over the upper surface of the FE material layer 140 during fabrication. The channel layer 150 a may be made of an oxide semiconductor material during fabrication, such as M _x M' _{y Znz} O, where 0<(x, y, z)<1. M may be a metal selected from a group consisting of indium (In) and tin (Sn) or a combination thereof, and M' may be a metal selected from another group consisting of gallium ( Ga), hafnium (Hf), zirconium (Zr), titanium (Ti), aluminum (Al), strontium (Sr), barium (Ba), scandium (Sc), magnesium (Mg), lanthanum (La), gadolinium ( Gd) and its combination. In some embodiments, the channel layer 150 a may be amorphous indium gallium zinc oxide (a-IGZO) during fabrication. In other embodiments, indium may be partially or completely replaced by another metal, such as tin (Sn), which may be configured to provide a higher carrier density in the channel layer 150a during fabrication. mobility. Alternatively or additionally, gallium may be partially or completely substituted by another metal, such as hafnium (Hf), zirconium (Zr), titanium (Ti), aluminum (Al), strontium (Sr), barium (Ba ), scandium (Sc), magnesium (Mg), lanthanum (La), or gadolinium (Gd), the other metal can be configured to reduce oxygen vacancies and reduce the surface state density (D _it ).

In-fabrication channel layer 150a may be formed by depositing a series of sub-layers over the upper surface of optional insulating layer 145, or, in embodiments where optional insulating layer 145 is absent, The in-fabrication channel layer 150 a may be formed by depositing a series of sub-layers over the upper surface of the FE material layer 140 . Referring again to FIG. 8, the first layer 152A of the channel layer 150a during fabrication may comprise a combination of a first metal oxide material and a second metal oxide material. The first metal oxide material may consist of _MOx , where M is a metal selected from the group consisting of indium (In) and tin (Sn) or a combination thereof. The second metal oxide material may consist of _M'Ox , where M' is a metal selected from the group consisting of Gallium (Ga), Hafnium (Hf), Zirconium (Zr), Titanium (Ti), Aluminum (Al), strontium (Sr), barium (Ba), scandium (Sc), magnesium (Mg), lanthanum (La), gadolinium (Gd) and combinations thereof. In various embodiments, the first layer 152A may include a combination of _InOx and _GaOx . The first layer 152A may be deposited using any suitable deposition process. In various embodiments, the first layer 152A may be deposited using atomic layer deposition (ALD).

Referring again to FIG. 8, a second sublayer 154A of the channel layer 150a may be deposited over the upper surface of the first layer 152A during fabrication. The second sublayer 154A of the channel layer 150a may include zinc oxide (ZnO _x ) during fabrication. The second sublayer 154A may be deposited using any suitable deposition process. In various embodiments, the second sub-layer 154A may be deposited using atomic layer deposition (ALD).

In various embodiments, zinc oxide is deposited directly onto the gate dielectric material (i.e., optional insulating layer 145 in FIG. 8, or the layer of FE material in embodiments where optional insulating layer 145 is not present. 140), the surface roughness at the interface between the channel layer 150a and the gate dielectric may increase during fabrication due to the tendency of zinc oxide to form a polycrystalline grain structure. Thus, in various embodiments, the first layer 152A of the in-fabrication channel layer 150a formed over the gate dielectric (optional insulating layer 145/FE material layer 140) may comprise a first metal oxide material In combination with the second metal oxide material, a second sublayer 154A comprising zinc oxide may be formed over the first layer 152A. In various embodiments, the first layer 152A can be substantially free of zinc oxide. Further, in various embodiments, the first layer 152A may include a combination of a first metal oxide material and a second metal oxide material, wherein the first metal oxide material, such as indium oxide, can promote higher carrier (eg, electron) mobility, and the second metal oxide material, such as gallium oxide (GaO _x ), can reduce oxygen vacancies in the channel layer 150a during fabrication and reduce the surface state density ( D _it ).

FIG. 9 is a vertical cross-sectional view of an exemplary intermediate structure showing the completed semiconductor channel layer 150 deposited on the upper surface of the optional insulating layer 145 . Referring to FIG. 9, the completed semiconductor channel layer 150 can be formed by depositing a plurality of sub-layers, including a plurality of first-time layers 152A, 152N, 152M, 152T, and a plurality of second sub-layers 154A, 154N. , 154M, and at least one third sub-layer 156 .

In various embodiments, each of the first layers 152A, 152N, 152M, and 152T may include a combination of a first metal oxide material and a second metal oxide material. The first metal oxide material may consist of _MOx , where M is a metal selected from the group consisting of indium (In) and tin (Sn) or a combination thereof. The second metal oxide material may consist of _M'Ox , where M' is a metal selected from the group consisting of gallium (Ga), hafnium (Hf), zirconium (Zr), titanium (Ti), aluminum (Al), strontium (Sr), barium (Ba), scandium (Sc), magnesium (Mg), lanthanum (La), gadolinium (Gd) and combinations thereof. In various embodiments, each of the first layers 152A, 152N, 152M, and 152T may include a combination of _InOx and _GaOx . In some embodiments, each of the first layers 152A, 152N, 152M, and 152T may have the same composition. In other embodiments, the first layers 152A, 152N, 152M, and 152T may have different compositions. For example, in at least one of the first layers 152A, 152N, 152M, and 152T, the ratio of M:M' may be different from at least one of the remaining first layers 152A, 152N, 152M, and 152T. M:M' ratio. Alternatively or additionally, the metal material (M and/or M') of at least one of the first layers 152A, 152N, 152M, and 152T may be different from that of the remaining first layers 152A, 152N, 152M, and Metal material (M and/or M') of at least one of 152T.

In various embodiments, each of the second sub-layers 154A, 154N, 154M of the semiconductor channel layer 150 may include zinc oxide (ZnO _x ). As shown in FIG. 9, the semiconductor channel layer 150 may include a first alternate stack 151 of a first layer 152 and a second layer 154, and the first alternate stack 151 includes a group of first layers 152A, . . . , 152N and a A set of second sublayers 154A, . . . , 154N, wherein each of the first sublayers _152A , _. ), while the second sublayer 154A, . . . , 154N includes zinc oxide. It should be noted that, in order to make the description clear and easy to understand, the first layer (for example: the first layer 152A, 152N, 152M, 152T) is collectively referred to as the first layer 152 herein, and the second layer (for example: Second sub-layers 154A, 154N, 154M) are collectively referred to as second sub-layer 154 . In an embodiment, the first alternate stack 151 of multiple sub-layers may include at least two first sub-layers 152 and second sub-layers 154, for example at least four first sub-layers 152 and second sub-layers 154 (for example: eight one or more primary layers 152 and second secondary layers 154). The first layer 152 and the second layer 154 can alternate, so that each first layer 152 of the first alternate stack 151 can contact at least one second layer 154 of the first alternate stack 151, and the first alternate stack 151 Each of the second sub-layers 154 may contact at least one first sub-layer 152 of the first alternating stack 151 . In various embodiments, the uppermost sublayer of the first alternating stack of sublayers 151 may be a second sublayer 154N comprising zinc oxide. Alternatively, the uppermost sublayer of the first alternating stack 151 of sublayers may be a first first layer 152N comprising a combination of a first metal oxide material and a second metal oxide material (eg, InO _x and GaO _x ).

Still referring to FIG. 9 , the third sublayer 156 may be deposited over the uppermost layer of the first alternating stack 151 of the first layer 152 and the second sublayer 154 . In an embodiment, the third sub-layer 156 may include a combination of a first metal oxide material (MO _x ), a second metal oxide material (M′O _x ), and zinc oxide (ZnO _x ). The first metal oxide material may consist of _MOx , where M is a metal selected from the group consisting of indium (In) and tin (Sn) or a combination thereof. The second metal oxide material may consist of _M'Ox , where M' is a metal selected from the group consisting of gallium (Ga), hafnium (Hf), zirconium (Zr), titanium (Ti), aluminum (Al), strontium (Sr), barium (Ba), scandium (Sc), magnesium (Mg), lanthanum (La), gadolinium (Gd) and combinations thereof. In various embodiments, the third sublayer 156 may include a combination of _InOx , _GaOx , and _ZnOx . The third sublayer 156 may be deposited using any suitable deposition process. In various embodiments, the third sublayer 156 may be deposited using atomic layer deposition (ALD).

Still referring to FIG. 9 , the semiconductor channel layer 150 may further include a second alternating stack 153 of the first sub-layer 152 and the second sub-layer 154 disposed above the third sub-layer 156 . The second alternating stack 153 of the first sub-layers 152 and the second sub-layers 154 may include a set of first sub-layers 152M, ..., 152T and a set of second sub-layers 154M, wherein the set of first sub-layers 152M, ... Each of , 152T includes a combination of a first metal oxide material and a second metal oxide material (eg, InO _x and GaO _x ), while the set of second sublayers 154M includes zinc oxide. In an embodiment, the second alternate stack 153 of the first layer 152 and the second layer 154 may include at least two first layers 152 and second layers 154, for example at least four first layers 152 and The second sub-layer 154 (eg, eight or more of the first sub-layer 152 and the second sub-layer 154 ). The first layer 152 may alternate with the second layer 154, so that each first layer 152 of the second alternate stack 153 may contact at least one second layer 154 of the second alternate stack 153, and the second alternate stack 153 Each of the second sub-layers 154 may contact at least one first sub-layer 152 of the second alternating stack 153 . In various embodiments, the lowermost sublayer of the second alternating stack 153 contacting the third sublayer 156 may be the second sublayer 154M comprising zinc oxide. Alternatively, the lowermost sublayer of the second alternate stack 153 may be the first layer 152M, and the first layer 152M includes a combination of a first metal oxide material and a second metal oxide material (for example: InO _x and GaO x _x ).

In various embodiments, the uppermost sublayer of the second alternating stack 153 of sublayer compositions may be a first layer 152T, the first layer 152T includes a first metal oxide material and a second metal oxide material (eg: A combination of InO _x and GaO _x ). Alternatively, the uppermost sublayer of the second alternating stack 153 may be the second sublayer 154 comprising zinc oxide.

In various embodiments, the semiconductor channel layer 150 may have a symmetrical structure, and the symmetrical structure includes a first alternate stack 151 composed of a first layer 152 and a second sub-layer 154 , and a third alternate stack 151 above the first alternate stack 151 . layer 156 , and a second alternating stack 153 of the first sub-layer 152 and the second sub-layer 154 above the third sub-layer 156 . In some embodiments, the first alternating stack 151 and the second alternating stack 153 may include the same number of first sub-layers 152 and second sub-layers 154 . In some embodiments, the lowermost sublayer (for example: the first layer 152A) and the uppermost sublayer (for example: the first layer 152T) of the semiconductor channel layer 150 may be the first layer, and the first layer includes A combination of a first metal oxide material and a second metal oxide material (for example: InO _x and GaO _x ). The third sub-layer 156 may include a combination of the first metal oxide material, the second metal oxide material, and zinc oxide. The third sub-layer 156 may be in contact with the second sub-layer 154N, 154M comprising zinc oxide on its lower surface and upper surface.

In various embodiments, a first alternating stack 151 comprising a first sub-layer 152 and a second sub-layer 154, at least one third sub-layer 156, and a second stack of first sub-layers 152 and second sub-layers 154 The semiconductor channel layers 150 in the alternating stack 153 may have a total thickness between 1 nm and 100 nm (eg, between 2 nm and 70 nm), although larger or smaller thicknesses may also be used. The semiconductor channel layer 150 may be made of an oxide semiconductor material, such as M _x M' _{y Znz} O, where 0<(x, y, z)<1. M may be a first metal selected from a group consisting of indium (In) and tin (Sn) or a combination thereof, and M' may be a second metal selected from another group consisting of The group consists of gallium (Ga), hafnium (Hf), zirconium (Zr), titanium (Ti), aluminum (Al), strontium (Sr), barium (Ba), scandium (Sc), magnesium (Mg), lanthanum (La ), gadolinium (Gd) and their combinations. In some embodiments, the semiconductor channel layer 150 may be amorphous indium gallium zinc oxide (a-IGZO).

FIG. 10A is a diagram illustrating a pulse sequence 900 for an atomic layer deposition (ALD) system that may be used to form a plurality of layers (first layer 152) according to various embodiments of the present disclosure. , the second sub-layer 154 and the third sub-layer 156 ) the semiconductor channel layer 150 of amorphous oxide semiconductor (amorphous oxide semiconductor, AOS). Referring to FIG. 10A, a series of ALD precursor pulses (precursor pulses) introduced into the ALD reaction chamber over time t are schematically shown. The first pulse 901-a may be a mixture of precursors including a first metal (M) and a second metal (M′). The first metal (M) may be a metal selected from a group consisting of indium (In) and tin (Sn) or a combination thereof. The second metal (M') may be a metal selected from the group consisting of gallium (Ga), hafnium (Hf), zirconium (Zr), titanium (Ti), aluminum (Al), strontium (Sr) , barium (Ba), scandium (Sc), magnesium (Mg), lanthanum (La), gadolinium (Gd) and their combinations. In a non-limiting example, the first metal (M) may be indium, and the precursor of the first metal may be trimethyl-indium (TMIn). The second metal (M′) may be gallium, and the precursor of the second metal may be triethyl-gallium, Ga(C ₂ H ₅ ) ₃ (TEG/TEGa). Other suitable precursors are also within the scope of this disclosure. In various embodiments, the precursor mixture may be a solid precursor, including a mixture of solid precursors (also known as a "cocktail") containing the first metal (M) and the second metal (M'). A low pressure vessel (LPV) can be used to vaporize the solid precursor “cocktail” mixture and introduce (i.e. pulse) the resulting vaporized precursor mixture into an ALD chamber containing an intermediate structure as shown in Figure 7 in vivo. The precursor mixture is capable of reacting with the gate dielectric material (i.e., the optional insulating layer 145 shown in FIG. A first metal (M) and a second metal (M') are deposited on the gate dielectric material.

Still referring to FIG. 10A, after the introduction of the first pulse 901-a, the ALD reaction chamber can optionally be purged with an inert gas (eg, N2, Ar, etc.) and contains counter reactants. A second pulse 902 of -reactant) precursor can be introduced into the ALD reaction chamber. In various embodiments, the reverse reactant precursor may be an oxygen precursor, such as water vapor (H ₂ O), oxygen (O ₂ ), or ozone (O ₃ ). The reverse reactant precursor is capable of reacting with the first metal (M) and the second metal (M') to form the first layer 152A of the channel, the first layer 152A comprising the first metal oxide material and the second metal A combination of oxide materials such as InO _x and GaO _x .

After the second pulse 902 is introduced, the ALD reaction chamber can optionally be purged with an inert gas, and a third pulse 903-a can be introduced into the ALD reaction chamber. The third pulse 903-a may include a zinc precursor. In an embodiment, the zinc precursor may include diethylzinc, ie (C ₂ H ₅ ) ₂ Zn (DEZ), and/or dimethylzinc, ie, Zn(CH ₃ ) ₂ (DMZ). Other suitable precursors are also within the scope of this disclosure. The zinc precursor is capable of reacting with the metal oxide material of the first first layer 152A of the channel to deposit zinc on the first first layer 152A of the channel. The ALD chamber can again be optionally purged with an inert gas, and a second pulse 902 comprising a reverse reactant precursor (eg, an oxygen precursor, such as _H2O ) can be introduced into the ALD chamber middle. The reverse reactant precursor is capable of reacting with the zinc to form a second sublayer 154A of channels, the second sublayer 154A comprising zinc oxide.

This sequence can then be repeated by introducing additional pulses 901 (e.g., pulses 901-n) of the precursor mixture containing the first metal (M) and the second metal (M'), and then introducing the reverse reaction The pulse 902 of the material precursor, the pulse 903 of the zinc precursor (for example: pulse 903-n), and the second pulse 902 of the reverse reactant precursor, and repeat execution accordingly, to form the semiconductor channel layer 150 by the first A first alternate stack 151 composed of the primary layer 152A, the second sub-layer 154A, . . . , the first layer 152N, and the second sub-layer 154N.

After depositing the first alternating stack 151, the ALD chamber can optionally be purged with an inert gas, and additional pulses 904 can be introduced into the ALD chamber. The additional pulse 904 may be a precursor mixture comprising a plurality of precursors containing the first metal (M), the second metal (M'), and zinc. The first metal (M) may be a metal selected from a group consisting of indium (In) and tin (Sn) or a combination thereof. The second metal (M') may be a metal selected from the group consisting of gallium (Ga), hafnium (Hf), zirconium (Zr), titanium (Ti), aluminum (Al), strontium (Sr) , barium (Ba), scandium (Sc), magnesium (Mg), lanthanum (La), gadolinium (Gd) and their combinations. In one non-limiting example, the first metal (M) may be indium, and the precursor of the first metal may be trimethylindium (TMIn). The second metal (M′) may be gallium, and the precursor of the second metal may be triethylgallium, Ga(C ₂ H ₅ ) ₃ (TEG/TEGa). The zinc precursor may include diethylzinc ((C ₂ H ₅ ) ₂ Zn, DEZ) and/or dimethylzinc (Zn(CH ₃ ) ₂ , DMZ). Other suitable precursors are also within the scope of this disclosure. In various embodiments, the precursor mixture may be a solid precursor comprising a mixture (also known as a "cocktail") of a plurality of solid precursors, wherein the solid precursors contain a first metal (M), A second metal (M') and zinc. A low pressure vessel (LPV) can be used to vaporize the solid precursor "cocktail" mixture and introduce (ie, pulse) the resulting vaporized precursor mixture into the ALD reaction chamber. The precursor mixture can react with the uppermost second sub-layer 154N of the first alternate stack 151 to deposit the first metal (M), the second metal (M′) and zinc on the second sub-layer 154N.

The ALD chamber can again be optionally purged with an inert gas, and a second pulse 902 comprising a reverse reactant precursor (eg, an oxygen precursor, such as _H2O ) can be introduced into the ALD chamber middle. The reverse reactant precursor is capable of reacting with the first metal (M), the second metal (M'), and zinc to form a third sublayer 156, wherein the third sublayer 156 includes a first metal oxide material (eg: A combination of InO _x ), a second metal oxide material (eg GaO _x ), and zinc oxide (ZnO _x ).

The ALD reaction chamber can again be selectively purged with an inert gas, and an additional pulse 903-m of zinc precursor can be introduced, followed by a second pulse 902 of reverse reactant precursor, containing the first metal (M) and second metal (M') a pulse 901-m of the precursor mixture, and a second pulse 902 of the counter-reactant precursor. This sequence can then be repeated one or more times by introducing a pulse 903 of the zinc precursor followed by a pulse 902 of the counter-reactant precursor containing the first metal (M) and the second metal (M') before The pulse 901 of the precursor mixture (for example: pulse 901-t), and the second pulse 902 of the reverse reactant precursor to form the second sub-layer 154M, the first layer 152M, . . . of the semiconductor channel layer 150 The second alternate stack 153 composed of the second sub-layer 154T and the first-time layer 152T. It should be noted that, in order to make the description clear and easy to understand, pulses of the precursor mixture of the first metal (M) and the second metal (M') (for example: first pulse 901-a, pulse 901-n, Pulse 901 -m , pulse 901 -t ) are collectively referred to as pulse 901 , and pulses of the zinc precursor (eg, third pulse 903 -a , pulse 903 -n , additional pulse 903 -m ) are collectively referred to as pulse 903 .

FIG. 10B is a diagram illustrating an alternative pulse sequence 906 for an atomic layer deposition (ALD) system that may be used to form a layer consisting of a plurality of layers (first time) according to various embodiments of the present disclosure. Layer 152, the second sub-layer 154 and the third sub-layer 156) made of an amorphous oxide semiconductor (AOS) channel layer. Referring to FIG. 10B, in this embodiment, the pulse sequence 906 is similar to the pulse sequence 900 shown in FIG. 10A, except that the precursor mixture (including the first metal (M) and the second metal ( M') a single first pulse 901-a of a plurality of precursors), but the ALD system can operate in a co-pulse mode, in which the first precursor pulse 905-a and the second pulse Two precursor pulses 907-a can be simultaneously introduced into the ALD reaction chamber. The first precursor pulse 905-a may include a precursor including a first metal (M), while the second precursor pulse 907-a may include a precursor including a second metal (M'). Various precursors can be mixed in the ALD reaction chamber and react with the gate dielectric material to deposit the first metal (M) and the second metal (M′) on the gate dielectric material. Next, a second pulse 902 of the reverse reactant precursor (eg, an oxygen precursor such as H ₂ O) can be introduced into the ALD reaction chamber and mixed with the first metal (M) and the second metal (M') React to form the first layer 152A of the channel, the first layer 152A includes a combination of a first metal oxide material and a second metal oxide material (eg, _InOx and _GaOx ). The continuation of this process can be similar to the process described above with reference to FIG. Pulses 905 and 907 (e.g., pulses 905-n and 907-n) introducing the precursors of the first metal (M) and the second metal (M'), followed by another second pulse introducing the precursor of the opposite reactant Pulse 902, and executed in this order to form the first alternate stack 151 of the semiconductor channel layer 150 consisting of the first layer 152A, the second layer 154A, ..., the first layer 152N, and the second layer 154N .

Still referring to FIG. 10B, after forming the first alternating stack 151, the first precursor pulse 905-i, the second precursor pulse 907-i, and the third precursor pulse 903-i can be simultaneously introduced into the ALD reaction chamber . The first precursor pulse 905-i may comprise a precursor comprising a first metal (M), the second precursor pulse 907-i may comprise a precursor comprising a second metal (M'), and the third precursor pulse 903 -i may include a zinc-containing precursor. The first precursor pulse 905-i, the second precursor pulse 907-i, and the third precursor pulse 903-i can react with the uppermost second sub-layer 154N of the first alternate stack 151 to form a A first metal (M), a second metal (M') and zinc are deposited on 154N. Next, a second pulse 902 of the reverse reactant precursor (eg, an oxygen precursor, such as H ₂ O) can be introduced into the ALD reaction chamber and mixed with the first metal (M), the second metal (M') And the zinc reacts to form a third sub-layer 156, the third sub-layer 156 includes a first metal oxide material (eg: InO _x ), a second metal oxide material (eg: GaO _x ) and zinc oxide (ZnO _x ) combination. A process similar to that used to form the first alternating stack 151 may then be used, including introducing a pulse 903 of zinc precursor (eg, third pulse 903-m), a second pulse 902 of the reverse reactant precursor, and then Introduce pulses 905 and 907 of the precursors of the first metal (M) and the second metal (M') (for example: pulses 905-m, 905-t and pulses 907-m, 907-t), followed by the reverse Another second pulse 902 of the reactant precursor, and in this order, to form the second sub-layer 154M, the first layer 152M, . . . , the second sub-layer 154T, the first The second alternating stack 153 composed of the sub-layers 152T. It should be noted that for the sake of clarity of illustration, pulses of precursors of the first metal (M) will be included herein (for example: first precursor pulse 905-a, first precursor pulse 905-i, pulse 905- n, pulse 905-m, pulse 905-t) are collectively referred to as pulse 905, and the pulses containing the precursor of the second metal (M') (for example: second precursor pulse 907-a, second precursor pulse 907 -i, pulse 907-n, pulse 907-m, pulse 907-t) are collectively referred to as pulse 907.

FIG. 11 is a vertical cross-sectional view of an exemplary structure showing an optional second insulating layer 245 deposited over the upper surface of the semiconductor channel layer 150 . Referring to FIG. 11, the optional second insulating layer 245 (also referred to as a "barrier" layer) may comprise a layer of dielectric material such as any dielectric material of the optional insulating layer 145 previously described with reference to FIG. electrical material. Other suitable dielectric materials are also within the scope of this disclosure. In some embodiments, the optional second insulating layer 245 may be made of the same material as the optional insulating layer 145 . Alternatively, optional second insulating layer 245 may be composed of a different material than optional insulating layer 145 . The optional second insulating layer 245 may be deposited using any suitable deposition process, as described above. In various embodiments, the optional second insulating layer 245 may be deposited using atomic layer deposition (ALD). The thickness of the optional second insulating layer 245 can range from 0.1 nm to 10 nm, although smaller and larger thicknesses can also be used.

An optional second insulating layer 245 may act as a barrier between the semiconductor channel layer 150 and a layer of ferroelectric (FE) material that may subsequently be formed over the insulating layer 245 . The optional second insulating layer 245 can help reduce the density of surface states (D _it ) and inhibit the injection of carriers (ie, electrons and/or holes) from the semiconductor channel layer 150 . In various embodiments, the optional material of the second insulating layer 245 may have a higher energy gap (E _g ), which is higher than that of the semiconductor channel layer 150 . For example, in the case that the semiconductor channel layer 150 is amorphous InGaZnO ₄ (a-IGZO), a-IGZO has an energy gap _Eg of ~3.16Ev, and the material of the optional second insulating layer 245 can have a higher Large energy gap (for example: E _g ≥ 3.5eV, such as Eg ≥ 5.0eV). Further, the conduction band offset (E _CBO ) and valence band offset (E _VBO ) between the material of the optional second insulating layer 245 and the semiconductor channel layer 150 can be large enough (for example: E _CBO >1eV, E _VBO >1 eV) to block injection of charge carriers (including both electrons and holes) into the optional second insulating layer 245 and thereby minimize leakage current from the semiconductor channel layer 150 . In various embodiments, the optional second insulating layer 245 may include silicon-doped hafnium oxide, such as Hf _{1-x Six} O _y , where x>0.1 and y>0.

FIG. 12 is a vertical cross-sectional view of an exemplary structure showing an optional second seed layer 235 deposited over an upper surface of an optional second insulating layer 245 . In embodiments where the optional second insulating layer 245 is absent, an optional second seed layer 235 may be deposited over the upper surface of the semiconductor channel layer 150 . The optional second seed layer 235 (also referred to as a ferroelectric promoting layer) includes a material that can be configured to promote the formation of a desired crystal structure in a layer of FE material subsequently formed thereon. For example, the optional second seed layer 235 can promote cubic (c-phase), tetragonal (t-phase) and/or orthorhombic phases relative to monoclinic (m-phase) phases in subsequently formed layers of FE material. (o-phase) crystal phase formation, and can also suppress the transition from the t-phase crystal structure to the m-phase crystal structure in the FE material layer. This enables improved ferroelectric properties in the FE material layer, eg increased remnant polarization _Pr .

In various embodiments, the optional second seed layer 235 may comprise a metal oxide material, such as any material of the optional seed layer 135 described above with reference to FIG. 5 . Other suitable materials for the optional second seed layer 235 are also within the scope of the present disclosure. In some embodiments, the optional second seed layer 235 may be composed of the same material as the optional seed layer 135 . Alternatively, optional second seed layer 235 may be composed of a different material than optional seed layer 135 . The optional second seed layer 235 may comprise a single layer of metal oxide material, or may comprise multiple layers of metal oxide material which may have different compositions. In various embodiments, the crystal structure of the seed layer material may include cubic crystal phase, tetragonal crystal phase and/or orthorhombic crystal phase.

The optional second seed layer 235 may be deposited using any suitable deposition process. In various embodiments, the optional second seed layer 235 may be deposited using atomic layer deposition (ALD) or pulsed laser deposition (PLD). In some embodiments, the optional second seed layer 235 may be thermally annealed at a temperature between 300° C. and 700° C. for 30 seconds to 10 minutes to increase the crystallization of the optional second seed layer 235 Spend. Alternatively or additionally, the optional second seed layer 235 may be deposited as a quasi-single crystal metal oxide material using a suitable deposition technique (eg, PLD). The thickness of the optional second seed layer 235 can range from 0.1 nm to 5 nm, although smaller and larger thicknesses can also be used.

FIG. 13 is a vertical cross-sectional view of an exemplary structure showing a second ferroelectric (FE) material layer 240 formed over an optional second seed layer 235, and the upper surface deposited over the second FE material layer 240. The optional third seed layer 237 above. In embodiments where the optional second seed layer 235 is absent, a second FE material layer 240 may be deposited on the upper surface of the optional second insulating layer 245 . In embodiments where neither the optional second seed layer 235 nor the optional second insulating layer 245 is present, a second FE material layer 240 may be deposited over the upper surface of the semiconductor channel layer 150 .

Referring to FIG. 13, the second layer of FE material 240 may be formed of any suitable ferroelectric material, including any ferroelectric material of the layer of FE material 140 previously described with reference to FIG. Other suitable materials for the second FE material layer 240 are also within the contemplation of the present disclosure. In some embodiments, the second FE material layer 240 may be composed of the same material as the FE material layer 140 . Alternatively, the second FE material layer 240 may be composed of a material different from the FE material layer 140 .

In an embodiment, the second FE material layer 240 may include a single layer of FE material, or may include multiple layers of FE material that may have different compositions. In various embodiments, the crystal structure of the second FE material layer 240 may include cubic, tetragonal and/or orthorhombic phases. In an embodiment, the second FE material layer 240 may include a ferroelectric material based on hafnium oxide, such as Hf _x Zr _1-x O _y , and may have a structure such that it has a cubic, tetragonal, and/or orthorhombic crystal structure. The volume of the FE material is more than 50% larger than that of the FE material with a monoclinic crystal structure.

The second layer of FE material 240 may be deposited using any suitable deposition process. In various embodiments, the second FE material layer 240 may be deposited using atomic layer deposition (ALD). The thickness of the second FE material layer 240 can range from 0.1 nm to 100 nm, although smaller and larger thicknesses can also be used.

Still referring to FIG. 13 , an optional third seed layer 237 may be deposited over the upper surface of the second FE material layer 240 . The material included in the optional third seed layer 237 (also referred to as a ferroelectric facilitation layer) can be configured to promote the formation and maintenance of a desired crystal structure in the underlying second FE material layer 240 . For example, the optional third seed layer 237 may promote cubic (c-phase), tetragonal (t-phase) and/or orthorhombic phases relative to monoclinic (m-phase) phases in the second FE material layer 240. (o-phase) crystal phase formation, and can also suppress the transition from the t-phase crystal structure to the m-phase crystal structure in the second FE material layer 240 . This enables the layer of FE material to have improved ferroelectric properties, such as increased remnant polarization P _r .

In various embodiments, the optional third seed layer 237 may comprise a metal oxide material, such as any material of the optional seed layer 135 described above with reference to FIG. 5 . Other suitable materials for the optional third seed layer 237 are also within the scope of the present disclosure. In some embodiments, optional third seed layer 237 may be composed of the same material as optional seed layer 135 and/or optional second seed layer 235 . Alternatively, optional third seed layer 237 may be composed of a different material than optional seed layer 135 and/or optional second seed layer 235 . The optional third seed layer 237 may comprise a single layer of metal oxide material, or may comprise multiple layers of metal oxide material which may have different compositions. In various embodiments, the crystal structure of the seed layer material may include cubic crystal phase, tetragonal crystal phase and/or orthorhombic crystal phase.

The optional third seed layer 237 may be deposited using any suitable deposition process. In various embodiments, the optional third seed layer 237 may be deposited using atomic layer deposition (ALD) or pulsed laser deposition (PLD). In some embodiments, the optional third seed layer 237 may be thermally annealed at a temperature between 300° C. and 700° C. for 30 seconds to 10 minutes to increase the crystallization of the optional third seed layer 237 Spend. Alternatively or additionally, the optional third seed layer 237 may be deposited as a quasi-single crystal metal oxide material using a suitable deposition technique (eg, PLD). The thickness of the optional third seed layer 237 can range from 0.1 nm to 5 nm, although smaller and larger thicknesses can also be used.

FIG. 14 is a vertical cross-sectional view of an exemplary structure showing a layer of dielectric material 180 formed over an optional third seed layer 237 . In embodiments where the optional third seed layer 237 is absent, a dielectric material layer 180 may be deposited over the upper surface of the second FE material layer 240 . Referring to FIG. 14, the dielectric material layer 180 may be formed of a suitable dielectric material, such as aluminum oxide or silicon oxide. Other materials are also within the scope of this disclosure. In some embodiments, the dielectric material layer 180 may be a low-k dielectric material. Layer 180 of dielectric material may be deposited using a suitable deposition method as described above.

FIG. 15 is a vertical cross-sectional view of an exemplary structure showing a patterned mask 170 over a top surface of a dielectric material layer 180 during the process of forming a FeFET device. Patterning of the patterned mask 170 may use lithography to remove a portion of the mask material and expose regions 171 and 172 of the upper surface of the dielectric material layer 180 . The exposed regions 171 and 172 of the dielectric material layer 180 may respectively correspond to locations of source and drain regions, which may be formed later.

16 is a vertical cross-sectional view of an exemplary structure during the process of forming a FeFET device, showing openings 174 and 175 formed through dielectric material layer 180, optional third seed layer 237 , the second FE material layer 240 , the optional second seed layer 235 and the optional second insulating layer 245 to expose the upper surface of the semiconductor channel layer 150 . Referring to FIG. 16, an exemplary intermediate structure may be etched through a patterned mask 170 to remove the dielectric material layer 180, the optional third seed layer 237, the second FE material layer 240, the optional first The two seed layers 235 and some parts of the optional second insulating layer 245 expose the upper surface of the semiconductor channel layer 150 . The regions of the semiconductor channel layer 150 exposed through the openings 174 and 175 may correspond to the source and drain regions of the FeFET device, respectively. After the etching process, the patterned mask 170 may be removed using a suitable process, such as by ashing or dissolution using a solvent.

17 is a vertical cross-sectional view of an exemplary structure showing plasma treatment of source region 176 and drain region 177 of semiconductor channel layer 150 during the process of forming an FeFET device. Referring to FIG. 17, the source region 176 and the drain region 177 of the semiconductor channel layer 150 may be subjected to plasma treatment (schematically indicated by arrows 161 and 162). In an embodiment, the plasma treatment may be helium (He) plasma treatment. The plasma treatment of the source region 176 and the drain region 177 of the semiconductor channel layer 150 can be performed for a time between 5 seconds and 5 minutes, such as between 30 seconds and 120 seconds (for example: approximately equal to (~) 60 seconds). The power density used for the plasma treatment may be greater than 0.3 W/cm ² , such as between 0.8 and 1.2 W/cm ² (eg, ~0.98 W/cm ² ).

In an embodiment, the plasma treatment can reduce the contact resistance at the source region 176 and the drain region 177 . In various embodiments, the plasma treatment may result in regions relatively rich in the first metal (M) (eg, In) of the semiconductor channel layer 150 , which may facilitate a reduction in contact resistance. The plasma treatment can also create regions 178 , 179 of the semiconductor channel layer 150 below the source region 176 and the drain region 177 , wherein the regions 178 , 179 are relatively rich in oxygen vacancies. In an embodiment, the oxygen-vacancy-rich source region 176 and drain region 177 and regions 178, 179 may be located at a depth of at least about 0.5 nm below the upper surface 159 of the semiconductor channel layer 150 and may be within the semiconductor channel layer 150. Layer 150 extends below upper surface 159 to a depth of up to about 70 nm. In various embodiments, the concentration of oxygen vacancies in the regions 178 and 179 below the source region 176 and the drain region 177 may be greater than the concentration of oxygen vacancies in the central region 163 of the channel layer between the regions 178 and 179 . The source region 176 and the drain region 177 rich in oxygen vacancies of the semiconductor channel layer 150 can reduce the source-gate and drain-gate resistances of the semiconductor channel layer 150 .

18 is a vertical cross-sectional view of an exemplary structure including source electrode 190 and drain electrode 191 formed over source region 176 and drain region 177 of semiconductor channel layer 150 during the process of forming a FeFET device. Referring to FIG. 18, the source electrode 190 and the drain electrode 191 may include any suitable conductive material, such as titanium nitride (TiN), molybdenum (Mo), copper (Cu), aluminum (Al), zirconium (Zr), Titanium (Ti), tungsten (W), tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), iridium (Ir ), iron (Fe), beryllium (Be), chromium (Cr), antimony (Sb), osmium (Os), thorium (Th), vanadium (V), alloys thereof, and combinations thereof. Other suitable electrode materials are also within the scope of the present disclosure. The source electrode 190 and the drain electrode 191 can electrically contact the source region 176 and the drain region 177 of the semiconductor channel layer 150 respectively. The source electrode 190 and the drain electrode 191 can be deposited using any suitable deposition method, such as physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced Chemical Vapor Deposition (PECVD), or a combination thereof. In an embodiment, the source electrode 190 and the drain electrode 191 may be deposited by atomic layer deposition (ALD). In various embodiments, the source electrode 190 and the drain electrode 191 can be formed by an optional third seed layer on the upper surface of the dielectric material layer 180 and through the dielectric material layer 180 237 , depositing a conductive material layer in the openings 174 and 175 of the second FE material layer 240 , the optional second seed layer 235 , and the optional second insulating layer 245 . Next, a planarization process such as chemical mechanical planarization (CMP) may be performed to remove part of the conductive material from the upper surface of the dielectric material layer 180 and provide contact with the upper surface of the semiconductor channel layer 150. Discrete source electrodes 190 and drain electrodes 191 . In an embodiment, the upper surfaces of the source electrode 190 and the drain electrode 191 may be coplanar with the upper surface of the dielectric material layer 180 . In an embodiment, the source electrode 190 and the drain electrode 191 may have a thickness between the lower and upper surfaces of the source electrode 190 and the drain electrode 191, which is between about 50 nm and about 1000 nm.

19 is a vertical cross-sectional view of an exemplary structure showing a layer of dielectric material 180 and a patterned mask 185 over the upper surfaces of source electrodes 190 and drain electrodes 191 during the process of forming a FeFET device. Patterning of the patterned mask 185 may use lithography to remove a portion of the mask material and expose a portion of the upper surface of the dielectric material layer 180 . The exposed portion of the upper surface of the dielectric material layer 180 may correspond to the location of the upper gate electrode that may be subsequently formed.

20 is a vertical cross-sectional view of an exemplary structure during the process of forming a FeFET device, showing opening 193 formed through dielectric material layer 180 to expose the upper surface of optional third seed layer 237 . Referring to FIG. 20 , an exemplary intermediate structure may be etched through a patterned mask 185 to remove portions of the dielectric material layer 180 and expose the upper surface of the optional third seed layer 237 . In embodiments where the optional third seed layer 237 is not present, the etching process may expose the upper surface of the second FE material layer 240 . After the etching process, the patterned mask 185 may be removed using a suitable process, such as by ashing or dissolving with a solvent.

FIG. 21 is a vertical cross-sectional view of an exemplary structure forming a FeFET device 200 including an upper gate electrode 220 formed in an opening in a layer of dielectric material 180 . The upper gate electrode 220 may be formed from a suitable conductive material, including any conductive material of the bottom gate electrode 120 described above with reference to FIG. 3 . Other suitable materials for the upper gate electrode 220 are also within the contemplation of this disclosure. In some embodiments, the upper gate electrode 220 may be composed of the same material as the bottom gate electrode 120 . Alternatively, the upper gate electrode 220 may be composed of a different material than the bottom gate electrode 120 .

In some embodiments, the material of the upper gate electrode 220 can optionally have a lower coefficient of thermal expansion (CTE) than the CTE of the second FE material layer 240 . For example, in an embodiment where the second FE material layer 240 comprises hafnium zirconium oxide (HZO) having a CTE of 14×10 ⁻⁶ /K, the upper gate electrode 220 may comprise a CTE having a CTE of less than 14×10 ^-6 /K material. Suitable conductive materials with a relatively low CTE include, but are not limited to: platinum (Pt), titanium (Ti), titanium nitride (TiN), tungsten (W), tantalum (Ta), tantalum nitride (TaN), Iron (Fe), Nickel (Ni), Beryllium (Be), Chromium (Cr), Cobalt (Co), Antimony (Sb), Iridium (Ir), Molybdenum (Mo), Osmium (Os), Thorium (Th), Vanadium (V), alloys thereof, and combinations thereof. In various embodiments, tensile strain may be induced in the second FE material layer 240 by subjecting the structure shown in FIG. 21 to an annealing process, which may include temperatures between 400°C and 700°C. The structure was annealed at a temperature between 30 seconds and 5 minutes, followed by a cooling period. During cooling, the second FE material layer 240 may shrink more than the upper gate electrode 220 because of the difference in CTE. This can stretch the second layer of FE material 240 and thus subject the second layer of FE material 240 to permanent tensile strain.

The upper gate electrode 220 may be deposited using any suitable deposition method, such as physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), or a combination thereof. In various embodiments, the upper gate electrode 220 can be formed by above the upper surface of the dielectric material layer 180 and the source electrode 190 and the drain electrode 191 , and between the opening 193 in the dielectric material layer 180 This is done by depositing a layer of conductive material inside. Next, a planarization process such as chemical mechanical polishing (CMP) may be performed to remove a portion of the conductive material from the upper surfaces of the dielectric material layer 180, the source electrode 190, and the drain electrode 191 and provide a discrete upper surface. Gate electrode 220 . In an embodiment, the dielectric material layer 180 may contact the side surface of the upper gate electrode 220 and laterally separate the upper gate electrode 220 from the source electrode 190 and the drain electrode 191 , wherein the source electrode 190 and the drain electrode 191 are separated laterally. The pole electrodes 191 are located on both sides of the upper gate electrode 220 . In an embodiment, the upper surfaces of the source electrode 190 and the drain electrode 191 as well as the dielectric material layer 180 may be coplanar with the upper surface of the upper gate electrode 220 . In some embodiments, the upper gate electrode 220 may have a thickness between the lower and upper surfaces of the upper gate electrode, which is between about 50 nm and about 1000 nm.

The exemplary FeFET device 200 shown in FIG. 21 includes a double gate structure including a bottom gate electrode 120 disposed on a first side of a semiconductor channel layer 150, and a bottom gate electrode 120 disposed on a second side of the semiconductor channel layer 150. The upper gate electrode 220 . The first FE material layer 140 is located between the bottom gate electrode 120 and the semiconductor channel layer 150 , and the second FE material layer 240 is located between the upper gate electrode 220 and the semiconductor channel layer 150 . The source electrode 190 and the drain electrode 191 are in contact with the upper surface of the semiconductor channel layer 150 .

FIG. 22 is a vertical cross-sectional view of an alternative exemplary structure of a dual-gate FeFET device 300 including an optional fourth seed layer 137 disposed on a layer of FE material 140 and the optional insulating layer 145. The alternative example structure shown in FIG. 22 can be derived from the example intermediate structure in FIG. 6 by depositing an optional fourth seed layer 137 over the upper surface of the FE material layer 140 . The optional fourth seed layer 137 may have the same or similar composition and structure as the optional second seed layer 135, optional second seed layer 235, and/or optional third seed layer 237 described above. . The optional fourth seed layer 137 includes materials that can be configured to promote the formation and maintenance of a desired crystal structure in the underlying FE material layer 140 . The optional fourth seed layer 137 may be deposited using a suitable deposition process as described above. After the optional fourth seed layer 137 is deposited, the process operations described above with reference to FIGS. 7-21 may be performed to provide the FeFET device 300 as shown in FIG. 22 .

Fig. 23 is a circuit diagram schematically showing a FeFET device 200, 300 comprising a dual gate structure operating in a common gate control mode. Referring to FIG. 23 , the bottom gate electrode 120 and the upper gate electrode 220 may be connected to a common supply line so that the same voltage may be applied to both the bottom gate electrode 120 and the upper gate electrode 220 . The FE material layer 140 and the second FE material layer 240 can serve as gate insulating layers between the corresponding bottom gate electrode 120 and the upper gate electrode 220 and the semiconductor channel layer 150 . With respect to a FeFET device having a single gate electrode and a single layer of FE material on one side of the semiconductor channel layer 150 (i.e., a single-gate FeFET structure), by providing a bottom portion on opposite sides of the semiconductor channel layer 150 The gate electrode 120 and the upper gate electrode 220 also have the FE material layer 140 and the second FE material layer 240, so that the polarization, memory window and on-current (I _on ) of the double-gate FeFET devices 200 and 300 can be increased. In some embodiments, the polarization, memory window, and/or on-current can be effectively doubled compared to single-gate FeFET structures. It should be noted that the source electrode and the drain electrode can be interchanged herein, so the source electrode 190 and the drain electrode 191 can also be referred to as the source electrode 191 and the drain electrode 190 . Likewise, source region and drain region are also interchangeable herein.

24-37 are a series of vertical cross-sectional views of exemplary structures during the process of forming FeFET devices according to alternative embodiments of the present disclosure. FeFET devices according to alternative embodiments of FIGS. 24-37 may include a dual gate structure as shown in FeFET devices 200 , 300 of FIGS. 21 and 22 . In addition, the FeFET device according to the alternative embodiment of FIGS. 24 to 37 may also include a first pair of source and drain electrodes contacting a first side of the semiconductor channel, and a first pair of source and drain electrodes contacting a second side of the semiconductor channel. Two pairs of source and drain electrodes. This enables FeFETs with a dual gate structure to operate in a separated gate control mode, as described in further detail below.

FIG. 24 is a vertical cross-sectional view of an exemplary intermediate structure including a substrate 100, a first dielectric material layer 110 over the substrate 100, and a bottom gate electrode embedded in the first dielectric material layer 110 during the process of forming a FeFET device. 120, the optional stress layer 130 above the first dielectric material layer 110 and the bottom gate electrode 120, the optional seed layer 135 above the optional stress layer 130, the iron above the optional seed layer 135 A layer 140 of electrical (FE) material, and an optional insulating layer 145 over the layer 140 of FE material. The exemplary intermediate structure shown in Figure 24 can be derived from the exemplary intermediate structure shown in Figure 7, therefore, the substrate 100, the first dielectric material layer 110, the bottom gate electrode 120, and the optional The structure and details of the stressor layer 130, the optional seed layer 135, the FE material layer 140, and the optional insulating layer 145 are discussed repeatedly. In some embodiments, an additional seed layer (not shown in FIG. 24 ) may be located above the FE material layer 140, for example, as shown in FIG. 22, between the FE material layer 140 and the optional insulating layer 145. The optional fourth seed layer 137 between them.

FIG. 25 is a vertical cross-sectional view of an exemplary intermediate structure showing a patterned mask 301 over the upper surface of an optional insulating layer 145 during the process of forming a FeFET device. In embodiments where optional insulating layer 145 is absent, patterned mask 301 may be formed over the upper surface of FE material layer 140, or may be formed over an optional layer over FE material layer 140. layer, if the optional seed layer exists. Patterning of the patterned mask 301 may use lithography to remove portions of the mask material and expose portions of the optional insulating layer 145 . The openings through the patterned mask 301 can correspond to the locations of the bottom source and drain electrodes, which can be formed later.

FIG. 26 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, showing openings 302 and 303, wherein openings 302 and 303 are formed through optional insulating layer 145, FE material layer 140, optional The optional seed layer 135 and the optional stress layer 130 extend into the first dielectric material layer 110 . Referring to FIG. 26, an exemplary intermediate structure may be etched through a patterned mask 301 to remove the optional insulating layer 145, the FE material layer 140, the optional seed layer 135, the optional stress layer 130, and some parts of the first dielectric material layer 110 to form the openings 302 and 303 . Openings 302 and 303 may correspond to the locations of bottom source and drain electrodes, which may be formed later. After the etching process, the patterned mask 301 may be removed using a suitable process, such as by ashing or dissolving with a solvent.

FIG. 27 is a vertical cross-sectional view of an exemplary intermediate structure including bottom source electrode 304 and bottom drain electrode 305 formed in openings 302 and 303 during the process of forming a FeFET device. Referring to FIG. 27, the bottom source electrode 304 and the bottom drain electrode 305 may comprise any suitable conductive material, such as titanium nitride (TiN), molybdenum (Mo), copper (Cu), aluminum (Al), zirconium (Zr ), titanium (Ti), tungsten (W), tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), iridium (Ir), iron (Fe), beryllium (Be), chromium (Cr), antimony (Sb), osmium (Os), thorium (Th), vanadium (V), alloys thereof, and combinations thereof. Other suitable electrode materials are also within the scope of the present disclosure. The bottom source electrode 304 and the bottom drain electrode 305 can be deposited using any suitable deposition method, such as physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma Enhanced Chemical Vapor Deposition (PECVD), or a combination thereof. In various embodiments, bottom source electrode 304 and bottom drain electrode 305 may be formed by depositing a layer of conductive material on the upper surface of optional insulating layer 145 and through the optional insulating layer 145. Layer 145 , FE material layer 140 , optional seed layer 135 , and optional stressor layer 130 are carried into openings 302 , 303 in first dielectric material layer 110 . Next, a planarization process, such as chemical mechanical polishing (CMP), may be used to remove portions of the conductive material from above the upper surface of the optional insulating layer 145 and provide discrete bottom source electrodes 304 and bottom drain electrodes. 305. As shown in FIG. 27 , the bottom source electrode 304 and the bottom drain electrode 305 may extend into the first dielectric material layer 110 and communicate with the bottom gate electrode 120 embedded in the first dielectric material layer 110 spaced laterally. In various embodiments, the upper surfaces of the bottom source electrode 304 and the bottom drain electrode 305 can be coplanar with the upper surface of the optional insulating layer 145 . In embodiments where the optional insulating layer 145 is not present, the upper surfaces of the bottom source electrode 304 and the bottom drain electrode 305 may be coplanar with the upper surface of the FE material layer 140 .

28 is a vertical cross-sectional view of an exemplary intermediate structure, including optional insulating layer 145 and semiconductor channel layer 150 over the upper surfaces of bottom source electrode 304 and bottom drain electrode 305, during the process of forming a FeFET device. , the optional second insulating layer 245 above the semiconductor channel layer 150, the optional second seed layer 235 above the optional second insulating layer 245, the optional second FE above the second seed layer 235 material layer 240 , and an optional third seed layer 237 above the second FE material layer 240 . The exemplary intermediate structure shown in the 28th figure can be born out of the exemplary intermediate structure shown in the 13th figure, therefore, the semiconductor channel layer 150, the optional second insulating layer 245, and the optional second insulating layer 245 are omitted. The structure and details of the seed layer 235, the second FE material layer 240, and the optional third seed layer 237 are discussed repeatedly. Referring to FIG. 28 , the bottom source electrode 304 and the bottom drain electrode 305 may contact the bottom surface of the semiconductor channel layer 150 . In various embodiments, the semiconductor channel layer 150 may be an oxide semiconductor channel layer, as described above with reference to FIGS. 8 to 10B.

FIG. 29 is a vertical cross-sectional view of an exemplary intermediate structure showing a patterned mask 306 over the upper surface of an optional third seed layer 237 during the process of forming a FeFET device. In embodiments where the optional third seed layer 237 is absent, a patterned mask 306 may be formed over the upper surface of the second FE material layer 240 . Patterning of the patterned mask 306 may use lithography to remove portions of the mask material and expose portions of the optional third seed layer 237 . The patterned mask 306 may cover a region of the optional third seed layer 237 that covers the bottom gate electrode 120 and the bottom source electrode 304 and bottom drain electrode 305 .

30 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, showing the exemplary intermediate structure after an etch process that forms a multilayer structure 307 over the first dielectric material layer 110 . Referring to FIG. 30, the etching process can be performed through the patterned mask 306 to remove the optional third seed layer 237, the second FE material layer 240, the optional second seed layer 235, the optional second seed layer Two insulating layers 245 , semiconductor channel layer 150 , optional insulating layer 145 , FE material layer 140 , optional seed layer 135 , and some parts of optional stress layer 130 . After the etching process, the optional third seed layer 237, the second FE material layer 240, the optional second seed layer 235, the optional second insulating layer 245, the semiconductor channel layer 150, the optional insulating Layer 145 , FE material layer 140 , optional seed layer 135 , and optional remainder of stressor layer 130 may form multilayer structure 307 . In some embodiments, the etching process may generate a plurality of discrete multilayer structures 307 above the first dielectric material layer 110 . The upper surface of the first dielectric material layer 110 may be exposed between the respective multilayer structures 307 . Each multilayer structure 307 may include a bottom source electrode 304/305 and a bottom drain electrode 305/304. It should be noted that the bottom source electrode and the bottom drain electrode can be interchanged herein, so the bottom source electrode 304 and the bottom drain electrode 305 can also be referred to as the bottom source electrode 305 and the bottom drain electrode 304 . Bottom gate electrodes 120 may be located within first dielectric material layer 110 below each multilayer structure 307 and between corresponding bottom source electrodes 304 and bottom drain electrodes 305 . After the etching process, the patterned mask 306 may be removed using a suitable process, such as by ashing or dissolving with a solvent.

31 is a vertical cross-sectional view of an exemplary intermediate structure, including a second layer formed over the upper and side surfaces of the multilayer structure 307 and over the exposed upper surface of the first dielectric material layer 110, during the process of forming a FeFET device. Dielectric layer 310 of dielectric material. The second dielectric material layer 310 can be made of suitable dielectric materials, such as silicon oxide, aluminum oxide, and the like. Other materials are also within the scope of this disclosure. In some embodiments, the second dielectric material layer 310 may be a low-k dielectric material. The second layer of dielectric material 310 may be deposited using a suitable deposition method as described above.

FIG. 32 is a vertical cross-sectional view of an exemplary intermediate structure including a patterned mask 170 over the upper surface of the second dielectric material layer 310 during the process of forming a FeFET device. The patterning of the patterned mask 170 may use lithography to remove portions of the mask material and expose regions 171 and 172 of the upper surface of the second dielectric material layer 310 . The exposed regions 171 and 172 of the second dielectric material layer 310 may respectively correspond to locations of upper source and drain regions, which may be subsequently formed in the multilayer structure 307 .

FIG. 33 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, showing openings 312 and 313 formed through a second, optional third layer of dielectric material 310. The crystal layer 237 , the second FE material layer 240 , the optional second seed layer 235 , and the optional second insulating layer 245 are used to expose the upper surface of the semiconductor channel layer 150 . Referring to FIG. 33, an exemplary intermediate structure may be etched through the patterned mask 170 to remove the second dielectric material layer 310, the optional third seed layer 237, the second FE material layer 240, the optional Parts of the second seed layer 235 and the optional second insulating layer 245 are exposed, and the upper surface of the semiconductor channel layer 150 is exposed. The regions of the semiconductor channel layer 150 exposed by the openings 312 and 313 may correspond to the source and drain regions of the FeFET device, respectively. After the etching process, the patterned mask 170 may be removed using a suitable process, such as by ashing or dissolving with a solvent.

Still referring to FIG. 33 , the source region 176 and the drain region 177 of the semiconductor channel layer 150 may be subjected to plasma treatment (schematically indicated by arrows 161 and 162 ). In an embodiment, the plasma treatment may be the same as the plasma treatment described above with reference to FIG. 17 . Therefore, a repeated discussion of plasma treatment is omitted. In an embodiment, the plasma treatment can reduce the contact resistance at the source region 176 and the drain region 177 . In various embodiments, the plasma treatment can also generate regions 178 , 179 of the semiconductor channel layer 150 below the source region 176 and the drain region 177 , wherein the regions 178 , 179 can be relatively rich in oxygen vacancies. The source region 176 and the drain region 177 rich in oxygen vacancies of the semiconductor channel layer 150 can reduce the source-gate and drain-gate resistances of the semiconductor channel layer 150 .

34 is a vertical cross-sectional view of an exemplary intermediate structure including upper source electrode 314 and upper drain electrode 315 formed over source region 176 and drain region 177 of semiconductor channel layer 150 during the process of forming a FeFET device. . Referring to FIG. 34, upper source electrode 314 and upper drain electrode 315 may comprise any suitable conductive material, including any material of source electrode 190 and drain electrode 191 previously described with reference to FIG. 18 . In some embodiments, the upper source electrode 314 and the upper drain electrode 315 may be composed of the same material as the bottom source electrode 304 and the bottom drain electrode 305 . Alternatively, upper source electrode 314 and upper drain electrode 315 may be composed of a different material than bottom source electrode 304 and bottom drain electrode 305 .

The upper source electrode 314 and the upper drain electrode 315 can be deposited using any suitable deposition method, such as physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma Enhanced Chemical Vapor Deposition (PECVD), or a combination thereof. In various embodiments, the upper source electrode 314 and the upper drain electrode 315 may be formed by depositing a layer of conductive material over the upper surface of the second dielectric material layer 310 and within the openings 312 , 313 . Next, a planarization process such as a chemical mechanical polishing (CMP) process may be used to remove a portion of the conductive material from the upper surface of the second dielectric material layer 310 and provide a connection with the source region 176 and the semiconductor channel layer 150. Drain regions 177 contact discrete upper source electrodes 314 and upper drain electrodes 315 .

35 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, showing a patterned mask over the upper surface of the second dielectric material layer 310 and the upper source electrode 314 and upper drain electrode 315. Cover 185. Patterning of the patterned mask 185 may use lithography to remove portions of the mask material and expose a portion of the upper surface over the second dielectric material layer 310 . The exposed portion of the upper surface of the second dielectric material layer 310 may correspond to the location of the upper gate electrode which may be subsequently formed.

36 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, showing opening 193 formed through second dielectric material layer 310 to expose optional third seed layer 237 the upper surface of . Referring to FIG. 36 , an exemplary intermediate structure may be etched through the patterned mask 185 to remove portions of the second dielectric material layer 310 and expose the upper surface of the optional third seed layer 237 . In embodiments where the optional third seed layer 237 is not present, the etching process may expose the upper surface of the second FE material layer 240 . After the etching process, the patterned mask 185 may be removed using a suitable process, such as by ashing or dissolving with a solvent.

FIG. 37 is a vertical cross-sectional view of an exemplary intermediate structure of a FeFET device 400 including an upper gate electrode 220 formed in an opening in a second layer of dielectric material 310 . The upper gate electrode 220 may comprise the same composition and structure as the upper gate structure 220 described above with reference to FIG. form. Therefore, repeated discussion of the upper gate structure 220 is omitted.

The exemplary FeFET device 400 shown in FIG. 37 includes a double gate structure including a bottom gate electrode 120 disposed on a first side of a semiconductor channel layer 150, and a bottom gate electrode 120 disposed on a second side of a semiconductor channel layer 150. The upper gate electrode 220 . The first FE material layer 140 can be located between the bottom gate electrode 120 and the semiconductor channel layer 150 , and the second FE material layer 240 can be located between the upper gate electrode 220 and the semiconductor channel layer 150 . The upper source electrode 314 and the upper drain electrode 315 extend through the second FE material layer 240 and contact the upper surface of the semiconductor channel layer 150 . In addition, the bottom source electrode 304 and the bottom drain electrode 305 extend through the first FE material layer 140 and contact the bottom surface of the semiconductor channel layer 150 .

An exemplary FeFET device 400 having a dual gate structure as shown in FIG. 37 can be operated in a common gate control mode as previously described with reference to FIG. 23 . In addition, the exemplary FeFET device 400 having a dual gate structure and bottom source electrode 304, bottom drain electrode 305, upper source electrode 314, and upper drain electrode 315 can also be operated in a distributed gate control mode. Fig. 38 is a circuit diagram schematically showing a circuit having a double gate structure and a bottom source electrode 304, a bottom drain electrode 305, an upper source electrode 314 and an upper drain electrode 315 operating in a distributed gate control mode. FeFET device 400 . 37 and 38, the bottom gate electrode 120 and the upper gate electrode 220 can be connected to different power supply lines, so that different voltages can be selectively applied to the bottom gate electrode 120 and the upper gate electrode 220 . The FE material layer 140 and the second FE material layer 240 can serve as gate insulating layers between the corresponding bottom gate electrode 120 and the upper gate electrode 220 and the semiconductor channel layer 150 . The bottom source electrode 304 and the bottom drain electrode 305 are electrically connected to the first side (eg, the bottom) of the semiconductor channel layer 150 , and the upper source electrode 314 and the upper drain electrode 315 are electrically connected to the semiconductor channel layer 150 . Second side (eg: top). In an embodiment, the combination of the bottom gate electrode 120, the FE material layer 140, the bottom source electrode 304 and the bottom drain electrode 305, and the semiconductor channel layer 150 can provide the first FeFET structure 401 (for example: FeFET-based memory body unit), and the combination of the upper gate electrode 220, the second FE material layer 240, the upper source electrode 314, the upper drain electrode 315 and the semiconductor channel layer 150 can provide a second FeFET structure 402 (for example: based on FeFET memory unit). By applying a suitable voltage and/or current to the corresponding bottom gate electrode 120, upper gate electrode 220, bottom source electrode 304 and bottom drain electrode 305, upper source electrode 314 and upper drain electrode 315, the second A FeFET structure 401 and a second FeFET structure 402 can operate independently of each other. In some embodiments, one of the first FeFET structure 401 and the second FeFET structure 402 may serve as a master device (eg, a main memory cell), while the other of the first FeFET structure 401 and the second FeFET structure 402 Or it can be used as a secondary device or a spare device (for example: a spare memory unit). This can provide memory devices with improved reliability and performance. It should be noted that the upper source electrode and the upper drain electrode can be interchanged herein, so the upper source electrode 314 and the upper drain electrode 315 can also be referred to as the upper source electrode 315 and the upper drain electrode 314 .

39-43 are a series of vertical cross-sectional views of exemplary structures during the process of forming FeFET devices according to another alternative embodiment of the present disclosure. FIG. 39 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, showing openings 312 and 313 formed through a second, optional third layer of dielectric material 310. The crystal layer 237 , the second FE material layer 240 , the optional second seed layer 235 , and the optional second insulating layer 245 are used to expose the upper surface of the semiconductor channel layer 150 . The exemplary intermediate structure shown in FIG. 39 can be derived from the exemplary intermediate structure shown in FIG. 33 , therefore, repeated discussions on the structure and details of the exemplary intermediate structure in FIG. 39 are omitted. The exemplary intermediate structure shown in FIG. 39 differs from the intermediate structure shown in FIG. 33 in that the exemplary intermediate structure shown in FIG. 39 does not include a bottom source electrode 304 and a bottom drain electrode 305. However, it should be understood that the method operations shown in FIGS. 39-43 may be performed on an exemplary intermediate structure including a bottom source electrode 304 and a bottom drain electrode 305 .

FIG. 40 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, showing the dielectric material formed over the upper surface above the second dielectric material layer 310 and over the side and bottom surfaces of the openings 312 and 313. material spacer layer 325 . Referring to FIG. 40, a dielectric material spacer layer 325 may be conformally deposited over the upper surface of the second dielectric material layer 310, over the side and bottom surfaces of the opening 312, and over the side surfaces of the opening 313. and above the bottom surface. The dielectric material spacer layer 325 may be formed of a suitable dielectric material, such as silicon oxide, silicon nitride and/or aluminum oxide. In some embodiments, the dielectric material spacer layer 325 can be made of a low-k dielectric material, such as fluorinated silicon glass (fluorinated silicon glass, FSG), hydrogen silsesquioxane (hydrogen silsesquioxane, HSQ), benzene Cyclobutene (benzocyclobutene, BCB), organic polymers (such as SiLK™ material from Dow Chemical Company, FLARE™ material from Allied Signal Corp., etc.), carbon-doped silicon oxide, porous silicon dioxide (porous silica) , polymer foam (polymer foam), etc. Other suitable dielectric materials are also within the scope of this disclosure. Dielectric material spacer layer 325 may be deposited using a suitable deposition process as described above.

41 is a vertical cross-sectional view of an exemplary intermediate structure during formation of a FeFET device, showing the exemplary intermediate structure after an etch process from the upper surface of the second dielectric material layer 310 and the bottoms of openings 312 and 313. A spacer layer 325 of dielectric material is removed over the surface. Referring to FIG. 41, an anisotropic etch process, such as a dry etch process, may be used to remove the dielectric material spacers from above the upper surface of the second dielectric material layer 310 and from above the bottom surfaces of the openings 312 and 313. The horizontally extending portion of the object layer 325 exposes the source region 176 and the drain region 177 of the semiconductor channel layer 150 at the bottom of the openings 312 and 313 . After the etching process, the remaining portion of the dielectric material spacer layer 325 may be located above the vertically extending side surfaces of the corresponding openings 312 , 313 .

42 is a vertical cross-sectional view of an exemplary intermediate structure including upper source electrode 314 and upper drain electrode 315 formed over source region 176 and drain region 177 of semiconductor channel layer 150 during the process of forming a FeFET device. . Referring to FIG. 42, the upper source electrode 314 and the upper drain electrode 315 may include the same composition and structure as the upper source electrode 314 and the upper drain electrode 315 described above with reference to FIG. The upper source electrode 314 and the upper drain electrode 315 described in FIG. 34 are formed by the same process. Therefore, repeated discussions on the upper source electrode 314 and the upper drain electrode 315 are omitted. As shown in FIG. 42 , each of the upper source electrode 314 and the upper drain electrode 315 may be laterally surrounded by a spacer layer 325 of dielectric material. The dielectric material spacer layer 325 can separate the upper source electrode 314 and the upper drain electrode 315 with the optional second insulating layer 245, the optional second seed layer 235, the second FE material layer 240, and the optional second insulating layer 245. The selected third seed crystal layer 237 is separated.

FIG. 43 is a vertical cross-sectional view of an exemplary structure of a FeFET device 500 including an upper gate electrode 220 formed in a second layer of dielectric material 310 . Referring to FIG. 43, the upper gate electrode 220 may include the same composition and structure as the upper gate electrode 220 described above with reference to FIGS. The above upper gate electrode 220 is formed by the same process. Therefore, repeated discussion of the upper gate electrode 220 is omitted. As shown in FIG. 43 , a spacer layer 325 of dielectric material may be located between the upper gate electrode 220 and each of the upper source electrode 314 and the upper drain electrode 315 .

FIG. 44 is a vertical cross-sectional view of an alternative example structure of a dual-gate FeFET device 600, including a dielectric laterally surrounding the upper source electrode 314 and upper drain electrode 315 and the bottom source electrode 304 and bottom drain electrode 305. material spacer layer 325 . Referring to FIG. 44, an alternate example structure of a dual-gate FeFET device 600 can be derived from the example intermediate structure shown in FIG. A spacer layer 325 of dielectric material is conformally deposited over the side and bottom surfaces of openings 303, and an anisotropic etch process is then performed to remove the dielectric from optional insulating layer 145 and over the bottom surfaces of openings 303,303. The horizontally extending portion of the dielectric material spacer layer 325 is such that the remaining portion of the dielectric material spacer layer 325 is above the vertically extending side surfaces of the corresponding openings 302 , 303 . Next, the method operations shown in FIGS. 27-33 and 39-43 may be performed to provide the FeFET device 500 shown in FIG. 44 .

45 is a vertical cross-sectional view of an alternate example structure of a dual-gate FeFET device 700, including laterally surrounding upper gate electrode 220, upper source electrode 314 and upper drain electrode 315, bottom gate electrode 120, and bottom Dielectric material spacer layer 325 for source electrode 304 and bottom drain electrode 305 . The spacer layer 325 of dielectric material laterally surrounding the upper gate electrode 220 and the bottom gate electrode 120 may be formed using the processes previously described with reference to FIGS. 29-44 .

FIG. 46 is a flowchart illustrating operations of a method 800 of forming a FeFET device, such as FIGS. 21 , 22, 37, 43, 44, in accordance with various embodiments of the present disclosure. and FeFET devices 200, 300, 400, 500, 600, and 700 shown in Fig. 45. Referring to FIG. 3 and FIG. 46, in operation 801, the bottom gate electrode 120 may be formed. The bottom gate electrode 120 may be a buried electrode embedded in a dielectric layer. In an embodiment, the bottom gate electrode 120 may be made of a conductive material such as copper (Cu), aluminum (Al), zirconium (Zr), titanium (Ti), titanium nitride (TiN), tungsten (W ), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), iridium (Ir), iron (Fe), beryllium (Be), chromium (Cr), antimony (Sb), osmium (Os), thorium (Th), vanadium (V), alloys thereof, and combinations thereof.

Bottom gate electrode 120 may be formed using any suitable deposition process. For example, suitable deposition processes may include physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), or combination.

Referring to FIG. 6 and FIG. 46 , in operation 802 , a ferroelectric (FE) material layer 140 may be formed over the bottom gate electrode 120 . In an embodiment, the FE material layer 140 may be formed directly on the bottom gate electrode 120 . In other embodiments, one or more intermediate layers (eg, stress layer 130 , optional seed layer 135 ) may be disposed between FE material layer 140 and bottom gate electrode 120 . In various embodiments, the FE material layer 140 may be a ferroelectric material based on hafnium oxide, such as Hf _x Zr _1-x O _y , where 0≤x≤1 and y>0 (eg: Hf _0.5 Zr _0.5 O ₂ ) , HfO ₂ , HfSiO, HfLaO, etc. In various embodiments, the FE material layer 140 can be hafnium zirconium oxide (HZO), doped with atoms with an ionic radius smaller than that of hafnium (for example: Al, Si, etc.), and/or doped with atoms with an ionic radius larger than that of hafnium (For example: La, Sc, Ca, Ba, Gd, Y, Sr, etc.). The layer of FE material 140 may be deposited using any suitable deposition process, for example deposited using atomic layer deposition (ALD).

Referring to FIGS. 8 , 9 , 10A , 10B , 28 , and 46 , in operation 803 , a semiconductor channel layer 150 may be formed over the FE material layer 140 . In an embodiment, the semiconductor channel layer 150 may be formed directly on the FE material layer 140 . In other embodiments, one or more intermediate layers (eg, optional fourth seed layer 137 , optional insulating layer 145 ) may be disposed between the FE material layer 140 and the semiconductor channel layer 150 . In an embodiment, the semiconductor channel layer 150 may be composed of an oxide semiconductor material.

The operation 803 of forming the semiconductor channel layer 150 may include forming a first alternating stack 151 of first sub-layers 152 and second sub-layers 154, including a set of first sub-layers 152 and a set of second sub-layers 154, wherein the first Each of the layers 152 includes a combination of a first metal oxide material _MOx and a second metal oxide material _M'Ox , while the second sublayer 154 includes zinc oxide. In an embodiment, M may be at least one of indium (In) and tin (Sn), and M' may be gallium (Ga), hafnium (Hf), zirconium (Zr), titanium (Ti), aluminum ( At least one of Al), strontium (Sr), barium (Ba), scandium (Sc), magnesium (Mg), lanthanum (La), gadolinium (Gd), and combinations thereof.

In various embodiments, the operation 803 of forming the semiconductor channel layer 150 may further include forming the third sub-layer 156 on the first alternate stack 151 composed of the first sub-layer 152 and the second sub-layer 154 . The third sub-layer 156 may include a combination of a first metal oxide material (MO _x ), a second metal oxide material (M'O _x ) and zinc oxide, where M is the combination of indium (In) and tin (Sn). One, and M' is gallium (Ga), hafnium (Hf), zirconium (Zr), titanium (Ti), aluminum (Al), strontium (Sr), barium (Ba), scandium (Sc), magnesium (Mg ), lanthanum (La), gadolinium (Gd) and combinations thereof.

In various embodiments, the operation 803 of forming the semiconductor channel layer 150 may further include forming a second alternating stack 153 of the first sub-layer 152 and the second sub-layer 154 on the third sub-layer 156 . The second alternating stack 153 may include a set of first sublayers 152 and a set of second sublayers 154, wherein each of the first sublayers 152 includes a first metal oxide material MO _x and a second metal oxide material combination of M'O _x , while the second sublayer 154 includes zinc oxide. In an embodiment, M may be at least one of indium (In) and tin (Sn), and M' may be gallium (Ga), hafnium (Hf), zirconium (Zr), titanium (Ti), aluminum ( At least one of Al), strontium (Sr), barium (Ba), scandium (Sc), magnesium (Mg), lanthanum (La), gadolinium (Gd), and combinations thereof.

In various embodiments, the uppermost and lowermost sublayers of the semiconductor channel layer 150 may include a first layer comprising a first metal oxide material MO _x and a second metal oxide material M'O _x The combination. The third sub-layer 156 may contact the second sub-layer 154 including zinc oxide on surfaces above and below the third sub-layer 156 .

Referring to FIGS. 13 , 28 , and 46 , in operation 804 , a second ferroelectric (FE) material layer 240 is formed over the semiconductor channel layer 150 . In an embodiment, the second FE material layer 240 may be directly formed on the semiconductor channel layer 150 . In other embodiments, one or more intermediate layers (for example: an optional second insulating layer 245, an optional second seed layer 235) can be disposed between the second FE material layer 240 and the semiconductor channel layer 150 between. In various embodiments, the second FE material layer 240 may be a ferroelectric material based on hafnium oxide, such as Hf _x Zr _1-x O _y , where 0≤x≤1 and y>0 (for example: Hf _0.5 Zr _0.5 O ₂ ), HfO ₂ , HfSiO, HfLaO, etc. In various embodiments, the second FE material layer 240 can be hafnium zirconium oxide (HZO), doped with atoms with an ionic radius smaller than that of hafnium (for example: Al, Si, etc.), and/or doped with atoms with an ionic radius larger than that of hafnium Atoms (for example: La, Sc, Ca, Ba, Gd, Y, Sr, etc.). The second FE material layer 240 may be deposited using any suitable deposition process, for example deposited using atomic layer deposition (ALD).

15 to 18, 25 to 27, 32 to 34, 39 to 42, and 46, in operation 805, the source electrode 190 and the drain electrode 191 , the upper source electrode 314 and the upper drain electrode 315 , the bottom source electrode 304 and the bottom drain electrode 305 may be formed and contact the semiconductor channel layer 150 . In an embodiment, the source electrode 190 and the drain electrode 191, the upper source electrode 314 and the upper drain electrode 315, the bottom source electrode 304 and the bottom drain electrode 305 may be made of conductive materials such as nitride Titanium (TiN), molybdenum (Mo), copper (Cu), aluminum (Al), zirconium (Zr), titanium (Ti), tungsten (W), tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru ), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), iridium (Ir), iron (Fe), beryllium (Be), chromium (Cr), antimony (Sb), osmium (Os ), thorium (Th), vanadium (V), alloys thereof, and combinations thereof. The source electrode 190 and the drain electrode 191, the upper source electrode 314 and the upper drain electrode 315, the bottom source electrode 304 and the bottom drain electrode 305 may be deposited using any suitable deposition process, such as using atomic layer deposition (ALD). ) to deposit.

In some embodiments, the source and drain electrodes may include upper source and drain electrodes contacting the upper surface of the semiconductor channel layer 150, such as the source electrode 190 and the drain electrode 191, the upper source electrode 314 and the upper drain electrode. pole electrode 315 . The source electrode 190 and the drain electrode 191 , the upper source electrode 314 and the upper drain electrode 315 may extend through the second FE material layer 240 . Alternatively or additionally, the source and drain electrodes may include bottom source and drain electrodes contacting the bottom surface of the semiconductor channel layer 150 , such as bottom source electrode 304 and bottom drain electrode 305 .

In some embodiments, the source electrode 190 and the drain electrode 191 , the upper source electrode 314 and the upper drain electrode 315 , the bottom source electrode 304 and the bottom drain electrode 305 may be laterally separated by a dielectric material spacer layer 325 around.

In some embodiments, the source and drain electrodes may include upper source and drain electrodes contacting the source region 176 and the drain region 177 of the semiconductor channel layer 150, such as the source electrode 190 and the drain electrode 191, the upper The source electrode 314 and the upper drain electrode 315 . Before forming the source electrode 190 and the drain electrode 191 as the upper source and drain electrodes, the upper source electrode 314 and the upper drain electrode 315, the source region 176 and the drain region 177 of the semiconductor channel layer 150 can be Perform helium plasma treatment.

Referring to FIGS. 19-21 , 35-37 , 43 , and 46 , in operation 806 , an upper gate electrode 220 may be formed over the second FE material layer 240 . In an embodiment, the upper gate electrode 220 may be formed directly on the second FE material layer 240 . In other embodiments, one or more intermediate layers (eg, optional third seed layer 237 ) may be disposed between the upper gate electrode 220 and the second FE material layer 240 . In an embodiment, the upper gate electrode 220 may be made of conductive materials such as copper (Cu), aluminum (Al), zirconium (Zr), titanium (Ti), titanium nitride (TiN), tungsten (W ), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), iridium (Ir), iron (Fe), beryllium (Be), chromium (Cr), antimony (Sb), osmium (Os), thorium (Th), vanadium (V), alloys thereof, and combinations thereof.

The upper gate electrode 220 may be formed using any suitable deposition process. For example, suitable deposition processes may include physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), or combination.

Referring to all the drawings and according to various embodiments of the disclosure, the disclosure provides a semiconductor structure. The above semiconductor structure includes a first gate electrode, a first ferroelectric material layer located above the first gate electrode, a semiconductor channel layer located above the first ferroelectric material layer, a plurality of source electrodes and drain electrodes contacting the semiconductor channel layer , a second ferroelectric material layer located above the semiconductor channel layer, and a second gate electrode located above the second ferroelectric material layer. For example, the present disclosure provides FeFET devices 200 , 300 , 400 , 500 , 600 , 700 . The above-mentioned FeFET devices 200, 300, 400, 500, 600, 700 include a bottom gate electrode 120, an FE material layer 140 above the bottom gate electrode 120, a semiconductor channel layer 150 above the FE material layer 140, and a contact semiconductor channel layer. The multiple source and drain electrodes of 150 (for example: source electrode 190 and drain electrode 191, bottom source electrode 304 and bottom drain electrode 305, upper source electrode 314 and upper drain electrode 315), located in the semiconductor channel A second FE material layer 240 over layer 150 , and an upper gate electrode 220 over second FE material layer 240 .

In one embodiment, the plurality of source and drain electrodes includes an upper source electrode extending through the second ferroelectric material layer and contacts the upper surface of the semiconductor channel layer, and an upper drain electrode extending through the second ferroelectric material layer. The electrical material layer is in contact with the upper surface of the semiconductor channel layer. For example, the plurality of source and drain electrodes include an upper source electrode (eg, source electrode 190 , upper source electrode 314 ), extending through the second FE material layer 240 and contacting the upper surface of the semiconductor channel layer 150 , And includes an upper drain electrode (for example: drain electrode 191 , upper drain electrode 315 ), extending through the second FE material layer 240 and contacting the upper surface of the semiconductor channel layer 150 .

In another embodiment, each of the upper source electrode (eg: source electrode 190 , upper source electrode 314 ) and the upper drain electrode (eg: drain electrode 191 , upper drain electrode 315 ), It is laterally surrounded by a spacer layer 325 of dielectric material.

In another embodiment, the semiconductor structure above further includes a first dielectric material layer located below the first ferroelectric material layer and laterally surrounding the first gate electrode, and a second dielectric material layer located on the second ferroelectric material layer. The layer of electrical material overlies and laterally surrounds the second gate electrode, the upper source electrode, and the upper drain electrode, wherein the second gate electrode, the upper source electrode, and the upper drain electrode extend through the second dielectric material layer. For example, the FeFET device further includes a first dielectric material layer 110 positioned below the FE material layer 140 and laterally surrounding the bottom gate electrode 120, and a second dielectric material layer (eg, dielectric material layer 180, second dielectric material layer 180, Two dielectric material layers 310), located above the second FE material layer 240 and laterally surrounding the upper gate electrode 220, the upper source electrode (eg: source electrode 190, the upper source electrode 314) and the upper drain electrode ( For example: drain electrode 191 , upper drain electrode 315 ), wherein the upper gate electrode 220 , the upper source electrode and the upper drain electrode extend through the second dielectric material layer.

In another embodiment, the plurality of source and drain electrodes further include a bottom source electrode extending from the first dielectric material layer through the first ferroelectric material layer and contacting the bottom surface of the semiconductor channel layer, and including a bottom The drain electrode extends from the first dielectric material layer and passes through the first ferroelectric material layer and contacts the bottom surface of the semiconductor channel layer. For example, the plurality of source and drain electrodes further include a bottom source electrode 304 extending from the first dielectric material layer 110 through the FE material layer 140 and contacting the bottom surface of the semiconductor channel layer 150, and including a bottom drain electrode. The electrode 305 extends from the first dielectric material layer 110 through the FE material layer 140 and contacts the bottom surface of the semiconductor channel layer 150 .

In another embodiment, each of the bottom source electrode 304 and the bottom drain electrode 305 is laterally surrounded by a spacer layer 325 of dielectric material.

In another embodiment, the semiconductor channel layer (for example: the semiconductor channel layer 150) includes an oxide semiconductor material with a chemical formula M _x M' _{y Znz} O, wherein 0<(x, y, z)<1, M is The first metal is selected from the group consisting of indium (In) and tin (Sn) and their combinations, and M' is the second metal selected from gallium (Ga), hafnium (Hf), zirconium (Zr), titanium (Ti), aluminum (Al), strontium (Sr), barium (Ba), scandium (Sc), magnesium (Mg), lanthanum (La), gadolinium (Gd) and combinations thereof.

In another embodiment, the first ferroelectric material layer 140 and the second ferroelectric material layer 240 include hafnium oxide-based ferroelectric material. For example, the FE material layer 140 and the second FE material layer 240 include ferroelectric material based on hafnium oxide.

In another embodiment, at least one of the seed layer and the stressor layer is located between the first gate electrode and the bottom surface of the first ferroelectric material layer. For example, at least one of optional seed layer 135 and optional stressor layer 130 is located between bottom gate electrode 120 and the bottom surface of FE material layer 140 .

In another embodiment, at least one of the first seed layer and the first insulating layer is located between the upper surface of the first ferroelectric material layer and the bottom surface of the semiconductor channel layer, and the second insulating layer and the first At least one of the two seed layers is located between the upper surface of the semiconductor channel layer and the bottom surface of the second ferroelectric material layer. For example, at least one of the optional fourth seed layer 137 and the optional insulating layer 145 is located between the upper surface of the FE material layer 140 and the bottom surface of the semiconductor channel layer 150, and the optional first At least one of the two insulating layers 245 and the optional second seed layer 235 is located between the upper surface of the semiconductor channel layer 150 and the bottom surface of the second FE material layer 240 .

In another embodiment, the seed layer may be located between the upper surface of the second ferroelectric material layer and the bottom surface of the second gate electrode. For example, the optional third seed layer 237 may be located between the upper surface of the second FE material layer 240 and the bottom surface of the upper gate electrode 220 .

In another embodiment, the first gate electrode and the second gate electrode are coupled to a common voltage in a common gate control mode. For example, the bottom gate electrode 120 and the top gate electrode 220 are coupled to a common voltage in a common gate control mode.

In another embodiment, the first gate electrode and the second gate electrode are coupled to different voltages in the distributed gate control mode. For example, the bottom gate electrode 120 and the top gate electrode 220 are coupled to different voltages in the distributed gate control mode.

An additional embodiment relates to a semiconductor structure. The semiconductor structure above includes a gate electrode (for example: bottom gate electrode 120, upper gate electrode 220), a semiconductor channel layer 150, a ferroelectric material layer (for example: FE) between the gate electrode and the surface of the semiconductor channel layer 150. material layer 140, the second FE material layer 240), and a plurality of source and drain electrodes contacting the semiconductor channel layer 150 (for example: source electrode 190 and drain electrode 191, bottom source electrode 304 and bottom drain electrode 305 , the upper source electrode 314 and the upper drain electrode 315). The semiconductor channel layer 150 includes a first alternate stack 151 of a plurality of first-time layers 152 and a plurality of second-sub-layers 154, the first-time layers 152 have a composition different from that of the second sub-layers 154, and are located between the plurality of first-time layers 152 and the plurality of first-time layers 154. A third sublayer 156 above the first alternating stack 151 of the second sublayer 154, the third sublayer 156 having a composition different from that of the first layer 152 and the second sublayer 154, and a layer above the third sublayer 156 A second alternating stack 153 of a plurality of first sub-layers 152 and a plurality of second sub-layers 154 . Wherein, each of the plurality of first layers 152 of the first alternate stack 151 and the second alternate stack 153 includes a combination of the first metal oxide material MO _x and the second metal oxide material M'O _x , and the first Each of the plurality of second sublayers 154 of an alternating stack 151 and a second alternating stack 153 includes zinc oxide, and the third sublayer 156 includes a first metal oxide material MO _x , a second metal oxide material M'O _x in combination with zinc oxide. Wherein, M is a first metal selected from the group consisting of indium (In) and tin (Sn) and combinations thereof, and M' is a second metal selected from gallium (Ga), hafnium (Hf), zirconium ( Groups consisting of Zr), titanium (Ti), aluminum (Al), strontium (Sr), barium (Ba), scandium (Sc), magnesium (Mg), lanthanum (La), gadolinium (Gd) and combinations thereof .

In one embodiment, the lowermost sub-layer of the semiconductor channel layer 150 is a first-time layer 152 of a first alternate stack 151 of a plurality of first-time layers 152 and a plurality of second sub-layers 154, and the lowermost layer of the semiconductor channel layer 150 is The upper sub-layer is a first-time layer 152 of a second alternate stack 153 of a plurality of first-time layers 152 and a plurality of second sub-layers 154, and wherein the third sub-layer 156 and the plurality of layers on the upper surface of the third sub-layer 156 The first sublayer 152 is in contact with one second sublayer 154 of the second alternate stack 153 of the plurality of second sublayers 154, and the third sublayer 156 is in contact with the plurality of first sublayers 152 on the bottom surface of the third sublayer 156. In contact with one second sub-layer 154 of the first alternating stack 151 of the plurality of second sub-layers 154 .

In another embodiment, the above-mentioned gate electrode is a first gate electrode, and the above-mentioned ferroelectric material layer is a first ferroelectric material layer, located between the first gate electrode and the first surface of the semiconductor channel layer, and The semiconductor structure above further includes a second gate electrode and a second ferroelectric material layer, wherein the second ferroelectric material layer is located between the second gate electrode and the second surface of the semiconductor channel layer. For example, the above-mentioned gate electrode is the bottom gate electrode 120, and the above-mentioned ferroelectric material layer is the FE material layer 140, which is located between the bottom gate electrode 120 and the first surface of the semiconductor channel layer 150, and the above-mentioned semiconductor structure It further includes an upper gate electrode 220 and a second FE material layer 240 , wherein the second FE material layer 240 is located between the upper gate electrode 220 and the second surface of the semiconductor channel layer 150 .

An additional embodiment relates to a method of fabricating a semiconductor structure. The manufacturing method of the above-mentioned semiconductor structure includes forming a first gate electrode, forming a first ferroelectric material layer above the first gate electrode, forming a semiconductor channel layer above the first ferroelectric material layer, and forming a plurality of sources contacting the semiconductor channel layer. pole and drain electrodes, a second ferroelectric material layer is formed on the semiconductor channel layer, and a second gate electrode is formed on the second ferroelectric material layer. For example, the manufacturing method of the above-mentioned semiconductor structure includes forming the bottom gate electrode 120, forming the FE material layer 140 above the bottom gate electrode 120, forming the semiconductor channel layer 150 above the FE material layer 140, and forming the semiconductor channel layer 150. Multiple source and drain electrodes (for example: source electrode 190 and drain electrode 191, bottom source electrode 304 and bottom drain electrode 305, upper source electrode 314 and upper drain electrode 315), in the semiconductor channel layer 150 A second FE material layer 240 is formed above, and an upper gate electrode 220 is formed above the second FE material layer 240 .

In one embodiment, the formation of a plurality of source electrodes and drain electrodes contacting the semiconductor channel layer 150 includes forming a plurality of upper source electrodes and drain electrodes (for example: source electrodes 190 and drain electrodes 190 ) contacting the upper surface of the semiconductor channel layer 150. electrode 191, upper source electrode 314, and upper drain electrode 315), and the manufacturing method of the above-mentioned semiconductor structure further includes forming a plurality of bottom source electrodes and drain electrodes (for example: bottom source electrodes) that contact the bottom surface of the semiconductor channel layer 150 electrode 304 and bottom drain electrode 305).

In another embodiment, the method for manufacturing the above-mentioned semiconductor structure further includes forming a plurality of dielectric material spacer layers 325, and the plurality of dielectric material spacer layers 325 laterally surround the plurality of upper source and drain electrodes (for example: source electrodes) 190 and drain electrode 191 , upper source electrode 314 and upper drain electrode 315 ), and at least one of a plurality of bottom source and drain electrodes (eg, bottom source electrode 304 and bottom drain electrode 305 ).

In another embodiment, the formation of the semiconductor channel layer 150 includes forming a first alternate stack 151 of a plurality of first-time layers 152 and a plurality of second-time layers 154, and the first alternate stack 151 includes a first group of first-time layers 152 and a plurality of first-time layers 154. The second set of second sub-layers 154, each of the first set of first-time layers 152 comprises a combination of a first metal oxide material MO _x and a second metal oxide material M'O _x , and the second set of second sub-layers 152 The secondary layer 154 comprises zinc oxide; a third sublayer 156 is formed over the first alternating stack 151, wherein the third sublayer 156 comprises a first metal oxide material _MOx , a second metal oxide material _M'Ox and oxide combination of zinc; and forming a second alternating stack 153 of a plurality of first sub-layers 152 and a plurality of second sub-layers 154 above the third layer 156, the second alternating stack 153 comprising a third set of first sub-layers 152 and a fourth set of first sub-layers 152 set of second sub-layers 154, each of the third set of first-time layers 152 comprises a combination of a first metal oxide material MO _x and a second metal oxide material M'O _x , and a fourth set of second Layer 154 includes zinc oxide. Wherein, M is a first metal selected from the group consisting of indium (In) and tin (Sn) and combinations thereof, and M' is a second metal selected from gallium (Ga), hafnium (Hf), zirconium ( Groups consisting of Zr), titanium (Ti), aluminum (Al), strontium (Sr), barium (Ba), scandium (Sc), magnesium (Mg), lanthanum (La), gadolinium (Gd) and combinations thereof .

The foregoing text summarizes features of various embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily design or modify other processes and structures based on the present disclosure to achieve the same purpose and/or achieve the same advantages as the embodiments or examples introduced herein. Those with ordinary knowledge in the technical field also need to understand that these equivalent structures do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions and changes can be made to the present disclosure without departing from the spirit and scope of the present disclosure .

8: Substrate 10: Semiconductor material layer 12:Shallow trench isolation structure 14: Active area 15: Semiconductor channel 18: Metal-semiconductor alloy region 20:Gate structure 22: Gate dielectric 24: Gate electrode 26: Dielectric gate spacer 28: Gate capping dielectric 30: ILD layer 31A: Planarized dielectric layer 31B: The first ILD layer 32: Second ILD layer 33: The third ILD layer 34: The fourth ILD layer 35: Fifth ILD layer 36: The sixth ILD layer 37: Seventh ILD layer 40:Metal Interconnect Structure 41V: Contact through-hole structure 41L: first wire 42V: the first metal via structure 42L: Second metal wire 43V: second metal via structure 43L: third metal wire 44V: The third metal via structure 44L: fourth metal wire 45V: fourth metal via structure 45L: fifth metal wire 46V: fifth metal via structure 46L: sixth metal wire 47B: Metal pad 47V: sixth metal via structure 50: memory array area 52: Peripheral logic area 75: Complementary Metal Oxide Semiconductor Circuits 95: array L0: Contact hierarchy L1: First Interconnection Hierarchy L2: Second interconnection level structure L3: Third Interconnection Hierarchy L4: The fourth interconnection level structure L5: Fifth Interconnection Hierarchy L6: Sixth Interconnection Hierarchy L7: Seventh Interconnection Hierarchy 100: Substrate 110: the first dielectric material layer 120: Bottom gate electrode 130: stress layer 135: Seed crystal layer 140: FE material layer 141: Arrow 142: Arrow 145: insulating layer 146: interface area 146a: first interface area part 146b: second interface area part 150a: channel layer in manufacture 150: Semiconductor channel layer 151: first alternate stack 152: first layer 152A: The first layer 152N: first layer 152M: the first layer 152T: the first layer 153: second alternate stack 154: second layer 154A: Second layer 154N: the second layer 154M: the second layer 156: The third layer 900: pulse sequence 901-a: First Impulse 901-n: Pulse 901-m: Pulse 901-t: Pulse 902: second pulse 903-a: Third Pulse 903-n: Pulse 903-m: Additional Pulse 904: additional pulse t: time 903-i: third precursor pulse 905-a: First precursor pulse 905-n: Pulse 905-i: First precursor pulse 905-m: Pulse 905-t: Pulse 906: pulse sequence 907-a: Second precursor pulse 907-n: Pulse 907-i: Second precursor pulse 907-m: Pulse 907-t: Pulse 245: second insulating layer 235:Second seed layer 240: the second FE material layer 237: The third crystal layer 180: dielectric material layer 170: Patterned mask 171: area 172: area 174: opening 175: opening 159: upper surface 161: Arrow 162: Arrow 176: source area 177:Drain area 178: area 179: area 190: source electrode 191: Drain electrode 185: Patterned mask 193: opening 200: FeFET device 220: upper gate electrode 300: FeFET device 137: The fourth crystal layer 301: Patterned mask 302: opening 303: opening 304: Bottom source electrode 305: bottom drain electrode 306: Patterned mask 307: multi-layer structure 310: second dielectric material layer 312: opening 313: opening 314: upper source electrode 315: upper drain electrode 400: FeFET device 401: The first FeFET structure 402: Second FeFET structure 325: Dielectric material spacer layer 500: FeFET device 600: FeFET device 700: FeFET device 800: method 801~806: operation

Aspects of the present disclosure can be better understood from the following embodiments and accompanying drawings. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1A is a vertical cross-sectional view of a first exemplary structure before forming an array of memory devices according to an embodiment of the present disclosure. FIG. 1B is a vertical cross-sectional view of a first exemplary structure during formation of an array of memory devices according to an embodiment of the present disclosure. FIG. 1C is a vertical cross-sectional view of a first exemplary intermediate structure after forming an upper-level metal interconnection structure according to an embodiment of the present disclosure. FIG. 2 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, including a first dielectric layer deposited over a substrate. FIG. 3 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, showing a bottom electrode layer embedded in a first dielectric layer. 4 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, showing an optional stressor layer deposited on the upper surface above the bottom electrode layer and the first dielectric layer. FIG. 5 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, showing an optional seed layer deposited on the upper surface of an optional stressor layer. 6 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, showing a layer of ferroelectric (FE) material formed on the upper surface of an optional seed layer. FIG. 7 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, showing an optional insulating layer deposited on the upper surface above the layer of FE material. Figure 8 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, showing a portion of an in-fabrication channel layer deposited on the upper surface of an optional insulating layer. FIG. 9 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, showing a complete channel layer deposited on the upper surface of an optional insulating layer. FIG. 10A is a diagram illustrating a pulse sequence for an atomic layer deposition (ALD) system that may be used to form an amorphous oxide made of multiple sublayers, according to various embodiments of the present disclosure. semiconductor (AOS) channel layer. FIG. 10B is a schematic diagram showing an alternative pulse sequence for an atomic layer deposition (ALD) system that can be used to form non-aluminum composites made of multiple layers, according to various embodiments of the present disclosure. crystal oxide semiconductor (AOS) channel layer. FIG. 11 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, showing an optional second insulating layer deposited on the upper surface above the channel layer. FIG. 12 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, showing an optional second seed layer deposited on an upper surface of an optional second insulating layer. 13 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, showing a second layer of ferroelectric (FE) material formed over an optional second seed layer, and deposited on the second FE material. An optional third seed layer on the upper surface above the layer. FIG. 14 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, showing a layer of dielectric material formed over an optional third seed layer. FIG. 15 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, showing a patterned mask over the upper surface of the layer of dielectric material. Figure 16 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, shown formed through a layer of dielectric material, an optional third seed layer, a second layer of FE material, an optional third layer of The two seed layers and the optional second insulating layer are used to expose the opening on the upper surface of the channel layer. FIG. 17 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, showing plasma treatment of the source and drain regions as well as the channel layer. FIG. 18 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, including source and drain electrodes formed over source and drain regions of a channel layer. 19 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, showing a layer of dielectric material and a patterned mask on the upper surface above the source and drain electrodes. 20 is a vertical cross-sectional view of an exemplary structure during the process of forming a FeFET device, showing openings formed through the layer of dielectric material to expose the upper surface of an optional third seed layer. FIG. 21 is a vertical cross-sectional view of an exemplary structure of a FeFET device including a double gate structure according to an embodiment of the present disclosure. FIG. 22 is a vertical cross-sectional view of an exemplary structure of a FeFET device including a double gate structure according to another embodiment of the present disclosure. FIG. 23 is a circuit diagram schematically showing a FeFET device including a dual gate structure operating in a common gate control mode according to various embodiments of the present disclosure. Figure 24 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, including a substrate, a first dielectric layer above the substrate, a bottom gate electrode embedded in the first dielectric layer, a first dielectric layer and an optional stress layer over the bottom gate electrode, an optional seed layer over the optional stress layer, a ferroelectric (FE) material layer over the optional seed layer, and an optional seed layer over the FE material layer. Optional insulating layer. FIG. 25 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, showing a patterned mask on the upper surface of an optional insulating layer. Figure 26 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, shown formed through an optional insulating layer, a layer of FE material, an optional seed layer, and an optional stressor layer, and Extending to the opening in the first layer of dielectric material. FIG. 27 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, including bottom source and drain electrodes formed in openings. Figure 28 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, including an optional insulating layer and a channel layer on the upper surface of the bottom source and drain electrodes, an optional second channel layer above the channel layer. Two insulating layers, an optional second seed layer above the optional second insulating layer, a second FE material layer above the optional second seed layer, and an optional second seed layer above the second FE material layer Three crystal layers. FIG. 29 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, showing a patterned mask on the upper surface of an optional third seed layer. FIG. 30 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, after performing an etching process to form a multilayer structure over a first dielectric material layer. 31 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, including a second dielectric formed over the upper and side surfaces of the multilayer structure and over the exposed upper surface of the first layer of dielectric material. electrical material layer. FIG. 32 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, including a patterned mask on the upper surface above the second dielectric material layer. Figure 33 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, shown formed through a second dielectric material layer, an optional third seed layer, a second FE material layer, an optional The second seed layer, and the optional second insulating layer are used to expose the opening on the upper surface of the channel layer. 34 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, including upper source and drain electrodes formed over source and drain regions of a channel layer. 35 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, showing a second dielectric material layer and a patterned mask on the upper surface over the source and drain electrodes above. 36 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, showing openings formed through the second dielectric material layer to expose the upper surface of an optional third seed layer. Fig. 37 is a cross-sectional view of an exemplary structure of a FeFET device including a double gate structure and including upper and bottom source and drain electrodes. FIG. 38 is a circuit diagram schematically showing a FeFET device including a dual gate structure and including upper and bottom source and drain electrodes operating in a distributed gate control mode according to various embodiments of the present disclosure. Figure 39 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, shown formed through a second dielectric material layer, an optional third seed layer, a second FE material layer, an optional The second seed layer, and the optional second insulating layer are used to expose the opening on the upper surface of the channel layer. 40 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, showing a spacer layer of dielectric material formed on the upper surface above the second dielectric material layer and on the side and bottom surfaces of the opening. Figure 41 is an exemplary intermediate structure during the process of forming a FeFET device after an etch has been performed to remove a portion of the dielectric material spacer from the upper surface above the second dielectric material layer and from the side and bottom surfaces of the opening Vertical cross-sectional view after fabrication. 42 is a vertical cross-sectional view of an exemplary intermediate structure during the process of forming a FeFET device, including source and drain electrodes formed over source and drain regions of a channel layer. FIG. 43 is a vertical cross-sectional view of an exemplary structure of a FeFET device including a double gate structure and a dielectric spacer layer laterally surrounding the source and drain electrodes. FIG. 44 is a vertical cross-sectional view of an exemplary structure of another embodiment of a FeFET device including a double gate structure and a dielectric laterally surrounding the upper source and drain electrodes and the bottom source and drain electrodes. spacer layer. Figure 45 is a vertical cross-sectional view of an exemplary structure of another embodiment of a FeFET device comprising a dual gate structure and comprising laterally surrounding an upper gate and electrode, a bottom gate electrode, an upper source and a drain electrode, and a dielectric spacer layer for the bottom source and drain electrodes. FIG. 46 is a flowchart illustrating operations of a method of forming a FeFET device having a dual-gate structure, according to various embodiments of the present disclosure.

100: Substrate

110: the first dielectric material layer

120: Bottom gate electrode

130: stress layer

135: Seed crystal layer

140: FE material layer

145: insulating layer

150: Semiconductor channel layer

245: second insulating layer

235:Second seed layer

240: the second FE material layer

237: The third crystal layer

176: source area

177:Drain area

178: area

179: area

220: upper gate electrode

304: Bottom source electrode

305: bottom drain electrode

310: second dielectric material layer

314: upper source electrode

315: upper drain electrode

400: FeFET device

Claims (9)

A semiconductor structure, comprising: a first gate electrode; a first ferroelectric material layer located above the first gate electrode; a semiconductor channel layer located above the first ferroelectric material layer; multiple sources and drains A pole electrode, contacting the above-mentioned semiconductor channel layer, wherein the above-mentioned source and drain electrodes include an upper source electrode extending through the above-mentioned second ferroelectric material layer and contacting an upper surface of one of the above-mentioned semiconductor channel layers, and extending through the above-mentioned The second ferroelectric material layer is in contact with an upper drain electrode on the above-mentioned upper surface of the above-mentioned semiconductor channel layer; a second ferroelectric material layer is located above the above-mentioned semiconductor channel layer; and a second gate electrode is located on the above-mentioned second above the ferroelectric material layer. The semiconductor structure according to claim 1, further comprising: a first dielectric material layer located below the first ferroelectric material layer and laterally surrounding the first gate electrode; and a second dielectric material layer located Above the second ferroelectric material layer and laterally surrounding the second gate electrode extending through the second dielectric material layer, the upper source electrode, and the upper drain electrode. The semiconductor structure according to claim 2, wherein the source and drain electrodes further include: a bottom source electrode extending from the first dielectric material layer and passing through the first ferroelectric material layer, and contacting the semiconductor channel a bottom surface of the layer; and a bottom drain electrode extending from the first layer of dielectric material through the first layer of ferroelectric material and contacting the bottom surface of the semiconductor channel layer. The semiconductor structure as claimed in claim 1, wherein the above-mentioned semiconductor channel layer comprises an oxide semiconductor material having a chemical formula M _x M' _{y Znz} O, wherein 0<(x,y,z)<1, M is the first metal, selected from the group consisting of indium (In) and tin (Sn) and combinations thereof, and M' is a second metal selected from gallium (Ga), hafnium (Hf), zirconium (Zr), titanium (Ti), Aluminum (Al), strontium (Sr), barium (Ba), scandium (Sc), magnesium (Mg), lanthanum (La), gadolinium (Gd) and combinations thereof. The semiconductor structure according to claim 1, wherein at least one of a first seed layer and a first insulating layer is located between an upper surface of the first ferroelectric material layer and a bottom surface of the semiconductor channel layer , and at least one of a second insulating layer and a second seed layer is located between an upper surface of the semiconductor channel layer and a bottom surface of the second ferroelectric material layer. A semiconductor structure, comprising: a gate electrode; a semiconductor channel layer, wherein the semiconductor channel layer includes: a first alternate stack of a plurality of first layers and a plurality of second layers, and the first layer has a structure different from the above The composition of the second sub-layer; a third sub-layer, located above the first alternating stack of the first sub-layer and the second sub-layer, the third sub-layer has a different structure than the first layer and the second sub-layer composition of sub-layers; and a second alternating stack of said first and said second sub-layers above said third sub-layer, wherein said first layers of said first and said second alternating stacks Each of them includes a combination of a first metal oxide material MO _x and a second metal oxide material M'O _x , and the second sub-layer of the first alternate stack and the second alternate stack each comprising zinc oxide, and said third sublayer comprising a combination of said first metal oxide material MO _x , said second metal oxide material M'O _x and zinc oxide, and wherein M is the first metal, selected from the group consisting of indium (In) and tin (Sn) and combinations thereof, and M' is a second metal selected from gallium (Ga), hafnium (Hf), zirconium (Zr), titanium (Ti), Aluminum (Al), strontium (Sr), barium (Ba), scandium (Sc), magnesium (Mg), lanthanum (La), gadolinium (Gd) and their combinations; a ferroelectric material layer, located between the gate electrode and a surface of the semiconductor channel layer; and the complex and drain electrodes contacting the semiconductor channel layer. Such as the semiconductor structure of claim 6, wherein a lowermost sublayer of the above-mentioned semiconductor channel layer is a first-time layer of the first alternate stack of the above-mentioned first-time layer and the above-mentioned second sub-layer, and the above-mentioned semiconductor channel layer An uppermost sub-layer of the above-mentioned first-time layer and the above-mentioned second sub-layer is a first-time layer of the second alternate stack, and wherein the upper surface of one of the above-mentioned third sub-layer and the above-mentioned third sub-layer The above-mentioned first layer of the above-mentioned second sub-layer is in contact with one of the second alternate stacks of the above-mentioned second sub-layer, and the above-mentioned first layer on the bottom surface of one of the above-mentioned third sub-layers is in contact with the A second sublayer of said first alternating stack of said second sublayers contacts. A method for manufacturing a semiconductor structure, comprising: forming a first gate electrode; forming a first ferroelectric material layer above the first gate electrode; forming a semiconductor channel layer above the first ferroelectric material layer; A second ferroelectric material layer is formed above the semiconductor channel layer; a plurality of source and drain electrodes contacting the semiconductor channel layer are formed, wherein the source and drain electrodes include extending through the second ferroelectric material layer and contacting an upper source electrode on an upper surface of the above-mentioned semiconductor channel layer, and an upper drain electrode extending through the above-mentioned second ferroelectric material layer and contacting the above-mentioned upper surface of the above-mentioned semiconductor channel layer; A second gate electrode is formed on the material layer. The method for manufacturing a semiconductor structure according to claim 8, wherein the formation of the above-mentioned semiconductor channel layer includes: forming a first alternate stack of a plurality of first layers and a plurality of second layers, and the first alternate stack includes a first group of the above-mentioned The first layer, each of the first group of the first layers includes a combination of a first metal oxide material MO _x and a second metal oxide material M'O _x , and the first alternate stack comprising a second set of said second sublayers, said second set of said second sublayers comprising zinc oxide; forming a third sublayer over said first alternating stack, wherein said third sublayer comprises said first metal oxide a combination of material MO _x , the second metal oxide material M'O _x and zinc oxide; and forming a second alternate stack of the first layer and the second layer above the third layer, the above The second alternating stack includes a third set of said first layers, each of said third set of said first layers comprising said first metal oxide material _MOx and said second metal oxide material M'O The combination of _x , and the above-mentioned second alternate stacking includes a fourth group of the above-mentioned second sub-layers, the above-mentioned fourth group of the above-mentioned second sub-layers includes zinc oxide, wherein M is a first metal selected from indium (In) and tin ( Sn) and combinations thereof, and M' is a second metal selected from gallium (Ga), hafnium (Hf), zirconium (Zr), titanium (Ti), aluminum (Al), strontium (Sr) , barium (Ba), scandium (Sc), magnesium (Mg), lanthanum (La), gadolinium (Gd) and combinations thereof.

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