TWI805047B - Thyristor - Google Patents

Abstract

A thyristor includes a first transistor and a second transistor. A first end of the first transistor is configured to be an anode. The second transistor has a control end coupled to a second end of the first transistor. A first end of the second transistor is coupled to a control end of the first transistor. A second end of the second transistor is coupled to the first end of the second transistor to be a cathode.

Description

Thyristor

The present invention relates to a thyristor, and in particular to a rapidly conducting thyristor.

In the known technical field, it is a common practice to construct an ESD protection circuit through diodes. However, in high-speed applications, limited by the parasitic capacitance of the diode, the current discharge capability of the ESD protection circuit is also limited, which also affects the ESD protection capability.

The present invention provides various thyristors, which can increase the speed of being turned on.

The thyristor of the present invention includes a first transistor and a second transistor. The first transistor has a first end serving as an anode end. The second transistor has a control terminal to be coupled to the second terminal of the first transistor, the first terminal of the second transistor is coupled to the control terminal of the first transistor, and the second terminal of the second transistor is coupled to the The first end of the second transistor serves as the cathode end.

Another thyristor of the present invention includes a first well region, a first heavily doped region, a second heavily doped region, a third heavily doped region and a second well region. The first heavily doped region is disposed in the first well region and electrically coupled to the anode terminal. The second heavily doped region is disposed in the first well region and electrically coupled to the cathode end. The second well region is disposed in the base, and the third heavily doped region is disposed in the second well region and electrically coupled to the cathode terminal.

Based on the above, the thyristor of the present invention forms an embedded diode between the first heavily doped region (the second terminal of the first transistor) and the substrate (the control terminal of the first transistor). When a forward bias voltage is received between the anode terminal and the cathode terminal of the thyristor, the built-in diode can assist the thyristor to be turned on, and the first well region (the second terminal of the first transistor and the second electrode The control terminal of the crystal) can also be turned on at the same time as the auxiliary thyristor. Therefore, the turn-on speed of the thyristor can be effectively increased.

Please refer to FIG. 1 , which is a schematic circuit diagram of a thyristor according to an embodiment of the present invention. The thyristor 100 includes a transistor T1 and a transistor T2. The first terminal of the transistor T1 serves as the anode terminal AE of the thyristor 100 . The second terminal of the transistor T1 is coupled to the control terminal of the transistor T2, and the control terminal of the transistor T1 is coupled to the first terminal of the transistor T2. In addition, the second terminal of the transistor T2 is coupled to the first terminal of the transistor T2 and serves as the cathode terminal CE of the thyristor 100 .

In this embodiment, the first terminal of the transistor T1 can be the emitter of the transistor T1; the second terminal of the transistor T1 can be the collector of the transistor T1; the control terminal of the transistor T1 is the terminal of the transistor T1 base. In addition, the second terminal of the transistor T2 can be the emitter of the transistor T2; the second terminal of the transistor T2 can be the collector of the transistor T2; the control terminal of the transistor T2 is the base of the transistor T2. The conduction types of the transistor T1 and the transistor T2 are complementary. Specifically, the transistor T1 is a PNP type bipolar transistor, and the transistor T2 is an NPN type bipolar transistor.

In this embodiment, an embedded diode may be formed between the first terminal and the control terminal of the transistor T1. When a forward bias voltage is received between the anode terminal AE and the cathode terminal CE of the thyristor 100, a conduction path is formed between the first terminal of the transistor T1, the control terminal of the transistor T1 and the second terminal of the transistor T2 . At this time, the voltage on the second terminal of the floating transistor T1 will be pulled up due to the conduction of the above-mentioned built-in diode. In addition, the first terminal of transistor T1, the control terminal of transistor T1, the first terminal of transistor T2, the second terminal of transistor T1, the control terminal of transistor T2 and the second terminal of transistor T2 form another a conduction path. Under such conditions, the thyristor 100 can be turned on quickly.

In the application of electrostatic discharge protection, when the electrostatic discharge phenomenon occurs, the thyristor 100 can be quickly turned on in response to the electrostatic discharge voltage between the anode terminal AE and the cathode terminal CE, and then through the double conduction path, effectively complete the electrostatic discharge. The venting action of the discharge current effectively improves the level of electrostatic discharge protection.

Please refer to FIG. 2 , which is a schematic circuit diagram of a thyristor according to another embodiment of the present invention. The thyristor 200 includes a transistor T1, a transistor T2, a resistor R1 and a resistor R2. Different from the embodiment in FIG. 1 , the resistor R1 is coupled between the second terminal of the transistor T1 and the control terminal of the transistor T2 . The resistor R2 is coupled between the first terminal of the transistor T2 and the control terminal of the transistor T1. Wherein, the resistors R1 and R2 may be resistors formed by the semiconductor material between the transistor T1 and the transistor T2 in the integrated circuit.

Please refer to FIG. 3A below. FIG. 3A is a schematic structural diagram of a thyristor according to an embodiment of the present invention. The thyristor 301 includes a substrate 310 constructed of well regions, a first heavily doped region 321 , a second heavily doped region 322 , a third heavily doped region 323 and a well region 331 . Wherein, the substrate 310 may be an N-type deep well (NWD) region. The first heavily doped region 321 may be a P-type heavily doped region (P+), and is disposed in the substrate 310 . The second heavily doped region 322 may be an N-type heavily doped region (N+), and is disposed in the substrate 310 . The well region 331 may be a P-type well region (PWI) disposed in the substrate 310 , and the third heavily doped region 323 may be an N-type heavily doped region (N+) disposed in the well region 331 .

Wherein, the well area 331 is set in the substrate 310 which is an N-type deep well (NWD) area, and is surrounded by the N-type well area. Therefore, the well area 331 is a PWI (P-type Well Inside) type well area.

That is to say, in this embodiment, the conduction types of the substrate 310 , the second heavily doped region 322 and the third heavily doped region 323 are the same (N type). The conductivity types of the first heavily doped region 321 and the well region 331 are the same (P type).

In this embodiment, the first heavily doped region 321 , the substrate 310 and the well region 331 can form a transistor T1 as shown in FIG. 1 . The substrate 310 , the third heavily doped region 323 and the well region 331 can form the transistor T2 as shown in FIG. 1 . In addition, the first heavily doped region 321 is electrically coupled to the anode terminal AE of the thyristor 301 , and the substrate 310 , the second heavily doped region 322 and the third heavily doped region 323 are commonly coupled to the thyristor 301 The cathode terminal CE. 1, the first heavily doped region 321 corresponds to the first terminal (emitter) of the transistor T1; the substrate 310 corresponds to the control terminal (base) of the transistor T1; the well region 331 corresponds to the transistor T1 The second terminal (collector). In addition, the substrate 310 corresponds to the first terminal (collector) of the transistor T2; the well region 331 corresponds to the control terminal (base) of the transistor T2; the third heavily doped region 323 corresponds to the second terminal (emitter) of the transistor T2 pole).

In an embodiment, an embedded diode may be formed between the first heavily doped region 321 and the substrate 310 . When a forward bias voltage is received between the anode terminal AE and the cathode terminal CE of the thyristor 300, the embedded diode formed by the first heavily doped region 321 and the substrate 310 can be connected with the second heavily doped region 322 forms a conduction path. In addition, the voltage on the well region 331 which is floating at this time will be pulled up due to the conduction of the above-mentioned embedded diode. In this way, the well region 331 can form another conduction path with the third heavily doped region 323 . Under such conditions, the thyristor 300 can be turned on quickly. In the application of electrostatic discharge protection, it can accelerate the discharge efficiency of electrostatic discharge current and improve the level of protection.

It is worth mentioning that in this embodiment, the first heavily doped region 321 , the second heavily doped region 322 and the third heavily doped region 323 are sequentially disposed in the substrate 310 . In other embodiments of the present invention, please refer to FIG. 3B , which is a schematic structural diagram of a thyristor according to another embodiment of the present invention. In the thyristor 302, the third heavily doped region 323 disposed in the well region 331 It can also be disposed between the first heavily doped region 321 and the third heavily doped region 323 . That is to say, there is no limitation on the positions of the first heavily doped region 321 , the second heavily doped region 322 and the third heavily doped region 323 .

Please refer to FIG. 4 below. FIG. 4 is a schematic structural diagram of a thyristor according to another embodiment of the present invention. The thyristor 400 includes a substrate 410 constructed of a P-type well (PW), a first heavily doped region 421 , a second heavily doped region 422 , a third heavily doped region 423 , a well region 431 and a deep well region 432 . In this embodiment, the first heavily doped region 421 is a P-type heavily doped region (P+), and the second heavily doped region 422 and the third heavily doped region 423 are N-type heavily doped regions (N+ ). The well area 431 is a P-type well area (P-type Well Inside, PWI), and the deep well area 432 is an N-type deep well area (NWD).

In terms of configuration, the first heavily doped region 421 and the deep well region 432 are directly disposed in the substrate 410 . The well area 431 is configured in the deep well area 432 . The second heavily doped region 422 is disposed outside the well region 431 and disposed in the deep well region 432 . The third heavily doped region 423 is disposed in the well region 431 .

The first heavily doped region 421 is electrically connected to the anode terminal AE of the thyristor 400 , and the second heavily doped region 422 and the third heavily doped region 423 are both electrically connected to the cathode terminal CE of the thyristor 400 .

Corresponding to the embodiment of FIG. 1 , the substrate 410 , the deep well region 432 and the well region 431 in this embodiment can form a transistor T1 . The third heavily doped region 423 , the deep well region 432 and the well region 431 can form a transistor T2. An embedded diode can be formed between the first heavily doped region 421 , the substrate 410 and the deep well region 432 . In an initial state, the well region 431 is in a floating state.

When a forward bias is applied between the anode terminal AE and the cathode terminal CE of the thyristor 400 , the embedded diode between the substrate 410 and the deep well region 432 can be turned on and provide a conduction path. The voltage on the well region 431 in the floating state will be pulled up due to the conduction of the above-mentioned built-in diode. In this way, the well region 431 can provide another conduction path with the third heavily doped region 423 to effectively improve the conduction efficiency of the thyristor 400 .

In this embodiment, by enlarging the junction between the substrate 410 and the deep well region 432 , the capacitance provided by the depletion region of the embedded diode generated therebetween can be reduced, and the conduction efficiency of the embedded diode can be improved.

It is worth mentioning that in this embodiment, the second heavily doped region 422 can be disposed between the first heavily doped region 421 and the third heavily doped region 423 as shown in FIG. 4 . In other embodiments of the present invention, the third heavily doped region 423 disposed in the well region 431 can also be changed to be disposed between the first heavily doped region 421 and the second heavily doped region 422, without certain restrictions. .

Next, please refer to FIG. 5 , which is a schematic structural diagram of a thyristor according to another embodiment of the present invention. The thyristor 500 includes a substrate 510 constructed of well regions, a first heavily doped region 521 , a second heavily doped region 522 , a third heavily doped region 523 , a well region 531 and a well region 532 . In this embodiment, the substrate 510 is an N-type deep well region (NWD). The first heavily doped region 521 is a P-type heavily doped region (P+), and the second heavily doped region 522 and the third heavily doped region 523 are N-type heavily doped regions (N+). Both the well area 531 and the well area 532 are P-type deep well areas (P-type Well Inside, PWI).

In terms of configuration, the second heavily doped region 522 , the well region 531 and the well region 532 are directly disposed in the substrate 510 . The first heavily doped region 521 is disposed in the well region 532 . The second heavily doped region 522 is configured outside the well region 531 and also outside the well region 532 . The third heavily doped region 523 is disposed in the well region 531 . The well area 531 and the well area 532 are physically isolated from each other.

The first heavily doped region 521 is electrically connected to the anode terminal AE of the thyristor 500 , and the second heavily doped region 522 and the third heavily doped region 523 are both electrically connected to the cathode terminal CE of the thyristor 500 .

In this embodiment, an embedded diode can be formed among the first heavily doped region 521 , the well region 532 and the substrate 510 . In an initial state, the well region 531 is in a floating state.

When a forward bias voltage is received between the anode terminal AE and the cathode terminal CE of the thyristor 500, the embedded diode between the first heavily doped region 521, the well region 532 and the substrate 510 can be turned on and provide a conduction path. The voltage on the first well region 531 in the floating state will be pulled up due to the above-mentioned conduction of the built-in diode. In this way, the well region 531 can provide another conduction path with the third heavily doped region 523 to effectively improve the conduction efficiency of the thyristor 500 .

Please refer to FIG. 6 , which is a schematic diagram of an electrostatic discharge protection circuit according to an embodiment of the present invention. The electrostatic discharge protection circuit 600 includes thyristors SCR1 and SCR2. The cathode terminal of the thyristor SCR1 receives the power supply voltage VCCQ, and the anode terminal of the thyristor SCR1 is coupled to the pad DQ. The cathode terminal of the thyristor SCR2 is coupled to the pad DQ, and the anode terminal of the thyristor SCR2 receives the reference ground voltage VSSQ. In this embodiment, the thyristor SCR1 can be implemented using the thyristor 301 in FIG. 3A or the thyristor 500 in FIG. 5 , and the thyristor SCR2 can be implemented by using the thyristor 301 in FIG. 400 or the thyristor 500 of FIG. 5 . The electrostatic discharge protection circuit 600 effectively improves the protection level of electrostatic discharge under the condition of using the thyristors SCR1 and SCR2 which can be turned on quickly.

Please refer to FIGS. 7A to 7D . FIGS. 7A to 7D are schematic structural diagrams of thyristors according to various embodiments of the present invention. In FIG. 7A , a thyristor 701 includes well regions 711 , 721 and heavily doped regions 741 , 751 and 761 . Well region 721 may serve as a substrate. The well area 711 is set in the well area 721, wherein the well area 721 may be a P-type well area (PW), and the well area 711 may be an N-type deep well area (NWD). The heavily doped regions 741 and 751 are disposed in the well region 711 , and the heavily doped region 761 is disposed in the well region 721 . The heavily doped region 741 is electrically connected to the anode terminal AE of the thyristor 701 , and the heavily doped regions 751 and 761 are electrically connected to the cathode terminal CE of the thyristor 701 . The heavily doped region 741 is a P-type heavily doped region (P+), and the heavily doped regions 751 and 761 are both N-type heavily doped regions (N+).

In FIG. 7B , thyristor 702 includes well regions 712 , 722 and heavily doped regions 742 , 752 and 762 . Well region 722 may serve as a substrate. The well area 712 is arranged in the well area 722 , wherein the well area 722 may be a P-type well area (PW), and the well area 712 may be an N-type well area (NW). The heavily doped regions 742 and 752 are disposed in the well region 712 , and the heavily doped region 762 is disposed in the well region 722 . The heavily doped region 742 is electrically connected to the anode terminal AE of the thyristor 702 , and the heavily doped regions 752 and 762 are electrically connected to the cathode terminal CE of the thyristor 702 . The heavily doped region 742 is a P-type heavily doped region (P+), and the heavily doped regions 752 and 762 are both N-type heavily doped regions (N+).

In FIG. 7C , thyristor 703 includes well regions 713 , 723 , 773 and heavily doped regions 743 , 753 and 763 . Well region 723 may serve as a substrate. The well areas 713 and 773 are both arranged in the well area 723, and the well areas 713 and 773 are isolated from each other. The well area 723 may be a P-type well area (PW), and the well areas 713 and 773 may both be N-type well areas (NW). The heavily doped regions 743 and 753 are disposed in the well region 713 , and the heavily doped region 763 is disposed in the well region 773 . The heavily doped region 743 is electrically connected to the anode terminal AE of the thyristor 703 , and the heavily doped regions 753 and 763 are electrically connected to the cathode terminal CE of the thyristor 703 . The heavily doped region 743 is a P-type heavily doped region (P+), and the heavily doped regions 753 and 763 are both N-type heavily doped regions (N+).

In FIG. 7D , thyristor 704 includes well regions 714 , 724 , 774 and heavily doped regions 744 , 754 and 764 . Well region 724 may serve as a substrate. The well areas 714 and 774 are both disposed in the well area 723, and the well areas 714 and 774 are isolated from each other. The well area 724 can be a P-type well area (PW), and the well areas 714 and 774 can both be N-type deep well areas (NWD). The heavily doped regions 744 , 754 are disposed in the well region 714 , and the heavily doped region 764 is disposed in the well region 774 . The heavily doped region 744 is electrically connected to the anode terminal AE of the thyristor 704 , and the heavily doped regions 754 and 764 are electrically connected to the cathode terminal CE of the thyristor 704 . The heavily doped region 744 is a P-type heavily doped region (P+), and the heavily doped regions 754 and 764 are both N-type heavily doped regions (N+).

In summary, the thyristor of the present invention provides an embedded diode, and when a forward bias is applied between the anode and the cathode of the thyristor, the embedded diode can be turned on and provide a conduction path . Moreover, when the embedded diode is turned on, the voltage of the second terminal of the floating first transistor in the thyristor is pulled up, and the second transistor is turned on to provide another conduction path. That is to say, the thyristor of the present invention can provide double conduction paths, which can improve the conduction efficiency and the current discharge capability.

100, 200, 301, 302, 400, 500, SCR1, SCR2: thyratron 310, 410, 510: base 321, 421, 521: the first heavily doped region 322, 422, 522: the second heavily doped region 323, 423, 523: the third heavily doped region 331, 431, 432, 531, 532, 711~714, 721~724, 773, 774: well area 600: Electrostatic discharge protection circuit 741~744, 751~754, 761~764: heavily doped regions AE: anode end CE: cathode terminal R1, R2: resistance T1, T2: Transistor

FIG. 1 is a schematic circuit diagram of a thyristor according to an embodiment of the present invention. FIG. 2 is a schematic circuit diagram of a thyristor according to another embodiment of the present invention. FIG. 3A is a schematic structural diagram of a thyristor according to an embodiment of the present invention. FIG. 3B is a schematic structural diagram of a thyristor according to another embodiment of the present invention. FIG. 4 is a schematic structural diagram of a thyristor according to another embodiment of the present invention. FIG. 5 is a schematic structural diagram of a thyristor according to another embodiment of the present invention. FIG. 6 is a schematic diagram of an electrostatic discharge protection circuit according to an embodiment of the present invention. 7A to 7D are schematic structural diagrams of thyristors according to various embodiments of the present invention.

100: Brake AE: anode end CE: cathode terminal T1, T2: Transistor

Claims (10)

A thyristor, comprising: a first transistor with a first terminal serving as an anode terminal; and a second transistor with a control terminal coupled to the second terminal of the first transistor, the second transistor The first terminal of the crystal is coupled to the control terminal of the first transistor, and the second terminal of the second transistor is directly coupled to the first terminal of the second transistor and serves as a cathode terminal. The thyristor according to claim 1, wherein the first transistor is a PNP bipolar transistor, the second transistor is an NPN bipolar transistor, and the first terminal of the first transistor is an emitter , the second terminal of the first transistor is the collector, the second terminal of the second transistor is the emitter, and the first terminal of the second transistor is the collector. The thyristor according to claim 1, further comprising: a first resistor coupled between the second terminal of the first transistor and the control terminal of the second transistor; and a second resistor coupled Between the first terminal of the second transistor and the control terminal of the first transistor. The thyristor according to claim 1, wherein when a forward bias voltage is received between the anode terminal and the cathode terminal, the first terminal of the first transistor, the control terminal of the first transistor and the second A first conduction path is formed between the first terminals of the transistor, the first terminal of the first transistor, the control terminal of the first transistor, the first terminal of the second transistor, the first terminal of the first transistor A second conduction path is formed between the two terminals, the control terminal of the second transistor and the second terminal of the second transistor. A thyristor, comprising: a first well region; a first heavily doped region disposed in the first well region and electrically coupled to an anode terminal; a second heavily doped region disposed in the first well region In a well area, electrically coupled to a cathode end; a second well area; and a third heavily doped region, disposed in the second well area, electrically coupled to the cathode end, wherein the electrical The first heavily doped region coupled to the anode terminal has a P-type conductivity type, the second heavily doped region electrically coupled to the cathode terminal and the third heavily doped region electrically coupled to the cathode terminal The impurity region has an N-type conductivity. The thyristor as claimed in item 5, wherein the conduction types of the first well region, the second heavily doped region and the third heavily doped region are the same first conduction type, the first The conductivity type of the heavily doped region and the second well region is the same second conductivity type, the second well region is set in the first well region, the first conductivity type is N type, and the second well region is set in the first well region. The second conductivity type is P type, the first heavily doped region, the first well region and the second well region form a first transistor, the first well region, the third heavily doped region and the second well region A second transistor is formed in the second well area, the first transistor is a PNP type bipolar transistor, and the second transistor is an NPN type bipolar transistor. The thyristor as described in claim 5, further comprising: a deep well area, set in the first well area, Wherein, the second well region is disposed in the deep well region, and the second heavily doped region is disposed in the deep well region, and the conductivity type of the substrate, the first heavily doped region and the second well region is The same first conductivity type, the conductivity type of the second heavily doped region, the third heavily doped region and the deep well region is the same second conductivity type, the first conductivity type is P type, the second conductivity type is N type, the first well region, the deep well region and the second well region form a first transistor, the second well region, the deep well region and the third heavily doped The region forms a second transistor, the first transistor is a PNP type bipolar transistor, and the second transistor is an NPN type bipolar transistor. The thyristor as described in claim 5, further comprising: a third well region disposed in the first well region, wherein the second well region is disposed in the first well region, and the first heavily doped region is set in the second well region, the second well region and the third well region are isolated from each other, and the conductivity types of the first heavily doped region, the second well region and the third well region are the same A first conductivity type, the first well region, the second heavily doped region, and the third heavily doped region are the same second conductivity type, the first conductivity type is P type, and the first well region The second conductivity type is N type, the third well region, the first well region and the second well region form a first transistor, the second well region, the first well region and the third heavily doped The region forms a second transistor, the first transistor is a PNP type bipolar transistor, and the second transistor is an NPN type bipolar transistor. The thyristor according to claim 5, wherein the first well area is arranged in the second well area. The thyristor as described in claim item 5 further includes: a third well region, disposed in the second well region, wherein the third heavily doped region is disposed in the third well region, the third well region is isolated from the first well region, and the second well region area and the third well area are both N-type deep well areas.

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