TWI804342B - Dynamic voltage switching testing method - Google Patents
Dynamic voltage switching testing method Download PDFInfo
- Publication number
- TWI804342B TWI804342B TW111121663A TW111121663A TWI804342B TW I804342 B TWI804342 B TW I804342B TW 111121663 A TW111121663 A TW 111121663A TW 111121663 A TW111121663 A TW 111121663A TW I804342 B TWI804342 B TW I804342B
- Authority
- TW
- Taiwan
- Prior art keywords
- transistor
- voltage
- coupled
- test
- control circuit
- Prior art date
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 77
- 230000001133 acceleration Effects 0.000 claims abstract description 9
- 238000010998 test method Methods 0.000 claims description 21
- 238000010586 diagram Methods 0.000 description 5
- 230000002950 deficient Effects 0.000 description 4
- 230000003068 static effect Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000032683 aging Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
Landscapes
- Engineering & Computer Science (AREA)
- Environmental & Geological Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Testing Electric Properties And Detecting Electric Faults (AREA)
- Emergency Protection Circuit Devices (AREA)
Abstract
Description
本發明係與積體電路之可靠度測試有關,特別是關於一種應用於源極驅動器之動態電壓切換(Dynamic Voltage Switching,DVS)測試方法。 The present invention is related to reliability testing of integrated circuits, in particular to a dynamic voltage switching (Dynamic Voltage Switching, DVS) testing method applied to source drivers.
由於源極驅動器是由複數個運算放大器組成,因此確保此積體電路的生產品質相當重要。傳統的可靠度測試方法是對源極驅動器中的運算放大器本體測試功能時亦可同時兼顧品質測試。 Since the source driver is composed of a plurality of operational amplifiers, it is very important to ensure the production quality of this integrated circuit. The traditional reliability test method is to test the function of the operational amplifier body in the source driver and also take into account the quality test at the same time.
然而,由於傳統的作法僅能採用直流電壓加速因子而無法使直流偏壓點產生電壓變化,導致電流源偏壓電路的品質測試無法加速而難以提前在出貨前被檢測出來。一旦電流源偏壓電路在積體電路生產過程中產生缺陷,而又無法提前在出貨前被檢測出來,很可能會在產品保固期內導致源極驅動器發生故障,因而造成客戶的退貨率大增。此一問題亟待進一步加以解決。 However, because the traditional method can only use the DC voltage acceleration factor and cannot cause voltage changes at the DC bias point, the quality test of the current source bias circuit cannot be accelerated and it is difficult to be detected in advance before shipment. Once the current source bias circuit has a defect in the production process of the integrated circuit, but it cannot be detected in advance before shipment, it is likely to cause the source driver to fail during the product warranty period, thus causing the customer's return rate greatly increased. This problem needs to be further resolved.
因此,本發明提出一種動態電壓切換測試方法,藉以有效解決先前技術所遭遇到之上述問題。 Therefore, the present invention proposes a dynamic voltage switching test method to effectively solve the above-mentioned problems encountered in the prior art.
根據本發明之一較佳具體實施例為一種動態電壓切換測試方法。於此實施例中,動態電壓切換測試方法包括下列步驟:(a) 加入電壓控制電路至測試電路;以及(b)當該電壓控制電路運作於測試模式時,該電壓控制電路利用電壓加速因子使該測試電路進行動態電壓切換,以加速可靠度測試。 A preferred embodiment of the present invention is a dynamic voltage switching test method. In this embodiment, the dynamic voltage switching test method includes the following steps: (a) Adding a voltage control circuit to the test circuit; and (b) when the voltage control circuit operates in the test mode, the voltage control circuit uses a voltage acceleration factor to make the test circuit perform dynamic voltage switching to speed up reliability testing.
於一實施例中,測試電路為電流源偏壓電路,測試電路包括複數個直流偏壓點分別耦接複數個開關,電壓控制電路控制該複數個開關開啟或關閉,以使該複數個直流偏壓點產生電位差。 In one embodiment, the test circuit is a current source bias circuit, the test circuit includes a plurality of DC bias points respectively coupled to a plurality of switches, the voltage control circuit controls the plurality of switches to turn on or off, so that the plurality of DC The bias point creates a potential difference.
於一實施例中,測試電路包括第一電晶體至第七電晶體,第一電晶體與第二電晶體的控制端彼此耦接於第一直流偏壓點,第七電晶體與第三電晶體耦接於工作電壓與接地電壓之間,第六電晶體與第四電晶體耦接於工作電壓與接地電壓之間,第五電晶體與第一電晶體耦接於工作電壓與接地電壓之間,第三電晶體與第四電晶體的控制端彼此耦接於第二直流偏壓點,第五電晶體至第七電晶體的控制端彼此耦接於第三直流偏壓點,第一開關之一端耦接第一直流偏壓點且其另一端耦接至第五電晶體與第一電晶體之間,第二開關之一端耦接第二直流偏壓點且其另一端耦接至第七電晶體與第三電晶體之間,第三開關之一端耦接第三直流偏壓點且其另一端耦接至第六電晶體與第七電晶體之間。 In one embodiment, the test circuit includes a first transistor to a seventh transistor, the control ends of the first transistor and the second transistor are coupled to the first DC bias point, and the seventh transistor and the third transistor are connected to each other. The transistor is coupled between the working voltage and the ground voltage, the sixth transistor and the fourth transistor are coupled between the working voltage and the ground voltage, the fifth transistor and the first transistor are coupled between the working voltage and the ground voltage Between them, the control terminals of the third transistor and the fourth transistor are coupled to each other at the second DC bias point, the control terminals of the fifth transistor to the seventh transistor are coupled to each other at the third DC bias point, and the first One end of a switch is coupled to the first DC bias point and the other end is coupled between the fifth transistor and the first transistor; one end of the second switch is coupled to the second DC bias point and the other end is coupled to Connected between the seventh transistor and the third transistor, one end of the third switch is coupled to the third DC bias point and the other end is coupled between the sixth transistor and the seventh transistor.
於一實施例中,電壓控制電路係根據第一控制信號及第二控制信號的數值選擇性地操作於正常操作模式或不同的測試模式下。 In one embodiment, the voltage control circuit selectively operates in a normal operation mode or a different test mode according to the values of the first control signal and the second control signal.
於一實施例中,當第一控制信號為0且第二控制信號為1時,電壓控制電路操作於第一測試模式下,電壓控制電路提供給第一直流偏壓點至第三直流偏壓點的電壓值分別為0、0、工作電壓。 In one embodiment, when the first control signal is 0 and the second control signal is 1, the voltage control circuit operates in the first test mode, and the voltage control circuit provides the first DC bias point to the third DC bias point The voltage values of the pressure points are 0, 0, and the working voltage respectively.
於一實施例中,當第一控制信號為1且第二控制信號為0時,電壓控制電路操作於第二測試模式下,電壓控制電路提供給第一直流偏壓點至第三直流偏壓點的電壓值均為0。 In one embodiment, when the first control signal is 1 and the second control signal is 0, the voltage control circuit operates in the second test mode, and the voltage control circuit provides the first DC bias point to the third DC bias point The voltage value of the pressure point is 0.
於一實施例中,當第一控制信號與第二控制信號均為0時,電壓控制電路操作於第三測試模式下,電壓控制電路提供給第一直流偏壓點至第三直流偏壓點的電壓值均為工作電壓。 In one embodiment, when both the first control signal and the second control signal are 0, the voltage control circuit operates in the third test mode, and the voltage control circuit provides the first DC bias point to the third DC bias point The voltage value of the point is the working voltage.
於一實施例中,測試電路為位準偏移器偏壓電路且包括第一輸出端及第二輸出端,分別輸出第一電壓及第二電壓,電壓控制電路包括第一電晶體至第十電晶體,第一電晶體與第二電晶體串接於工作電壓與第一輸出端之間,第十一電晶體耦接於工作電壓與第一輸出端之間,第三電晶體串接於第一輸出端與接地電壓之間,第四電晶體耦接於工作電壓與第一輸出端之間,第五電晶體耦接於第一輸出端與接地電壓之間,第六電晶體耦接於工作電壓與第二輸出端之間,第十二電晶體耦接於第二輸出端與接地電壓之間,第七電晶體耦接於第二輸出端與第十二電晶體的控制端之間,第八電晶體耦接於第十二電晶體的控制端與接地電壓之間,第九電晶體耦接於第二輸出端與接地電壓之間,第十電晶體耦接於工作電壓與第二輸出端之間。 In one embodiment, the test circuit is a level shifter bias circuit and includes a first output terminal and a second output terminal, respectively outputting a first voltage and a second voltage, and the voltage control circuit includes a first transistor to a second output terminal. Ten transistors, the first transistor and the second transistor are connected in series between the working voltage and the first output terminal, the eleventh transistor is coupled between the working voltage and the first output terminal, and the third transistor is connected in series Between the first output terminal and the ground voltage, the fourth transistor is coupled between the operating voltage and the first output terminal, the fifth transistor is coupled between the first output terminal and the ground voltage, and the sixth transistor is coupled connected between the working voltage and the second output terminal, the twelfth transistor is coupled between the second output terminal and the ground voltage, and the seventh transistor is coupled between the second output terminal and the control terminal of the twelfth transistor The eighth transistor is coupled between the control terminal of the twelfth transistor and the ground voltage, the ninth transistor is coupled between the second output terminal and the ground voltage, and the tenth transistor is coupled to the operating voltage and the second output terminal.
於一實施例中,電壓控制電路分別運作於第一測試模式及第二測試模式下,致使測試電路進行動態電壓切換,以加速可靠度測試。 In one embodiment, the voltage control circuit operates in the first test mode and the second test mode respectively, so that the test circuit performs dynamic voltage switching to speed up the reliability test.
於一實施例中,於第一測試模式下,電壓控制電路控制第二電晶體、第三電晶體、第五電晶體、第六電晶體、第七電晶體及第九電晶體關閉,致使第一輸出端及第二輸出端所輸出的第一電壓及第二電壓均為工作電壓。 In one embodiment, in the first test mode, the voltage control circuit controls the second transistor, the third transistor, the fifth transistor, the sixth transistor, the seventh transistor and the ninth transistor to turn off, so that the The first voltage and the second voltage output by the first output terminal and the second output terminal are both working voltages.
於一實施例中,於第二測試模式下,電壓控制電路控制第二電晶體、第三電晶體、第四電晶體、第六電晶體、第七電晶體及第十電晶體關閉,致使第一輸出端及第二輸出端所輸出的第一電壓及第二電壓均為接地電壓。 In one embodiment, in the second test mode, the voltage control circuit controls the second transistor, the third transistor, the fourth transistor, the sixth transistor, the seventh transistor and the tenth transistor to turn off, so that the The first voltage and the second voltage output by the first output terminal and the second output terminal are both ground voltages.
於一實施例中,動態電壓切換測試方法係透過電路內部訊號之切換來進行動態電壓切換測試,而非僅是拉高電壓進行測試。 In one embodiment, the dynamic voltage switching test method is to perform the dynamic voltage switching test by switching the internal signal of the circuit, rather than just pulling up the voltage for testing.
相較於先前技術,本發明之動態電壓切換測試方法並非僅是拉高電壓進行靜態測試,而是透過電路內部訊號之切換來進行動態電壓切換(DVS)測試,藉以加速產品的可靠度測試,以提前在出貨時將有缺陷的產品攔檢出來,故可有效確保積體電路產品之品質在保固期內不會發生故障,大幅減少客戶的退貨率。 Compared with the previous technology, the dynamic voltage switching test method of the present invention is not just to pull up the voltage for static testing, but to perform dynamic voltage switching (DVS) testing through the switching of internal signals in the circuit, so as to speed up the reliability testing of products. Defective products can be checked out in advance when they are shipped, so it can effectively ensure that the quality of integrated circuit products will not break down during the warranty period, and greatly reduce the return rate of customers.
S10~S12:步驟 S10~S12: Steps
2:電流源偏壓電路 2: Current source bias circuit
M1~M7:第一電晶體~第七電晶體 M1~M7: first transistor~seventh transistor
A:第一直流偏壓點 A: The first DC bias point
B:第二直流偏壓點 B: The second DC bias point
C:第三直流偏壓點 C: The third DC bias point
D1~D3:開關 D1~D3: switch
CON:電壓控制電路 CON: voltage control circuit
AVDD:工作電壓 AVDD: working voltage
AGND:接地電壓 AGND: ground voltage
C0:第一控制信號 C0: the first control signal
C1:第二控制信號 C1: Second control signal
I1:電流 I1: current
R:電阻 R: resistance
3:位準偏移器偏壓電路 3: Level shifter bias circuit
OUT1:第一輸出端 OUT1: the first output terminal
OUT2:第二輸出端 OUT2: the second output terminal
VP:第一電壓 VP: first voltage
VN:第二電壓 VN: the second voltage
MT1~MT10:第一電晶體~第十電晶體 MT1~MT10: first transistor~tenth transistor
MP:第十一電晶體 MP: eleventh transistor
MN:第十二電晶體 MN: Twelfth Transistor
IA:電流源 IA: current source
IB:電流源 IB: current source
DE:二極體 DE: Diode
LV_IN:低壓輸入信號 LV_IN: Low voltage input signal
MP1~MP4:電晶體 MP1~MP4: Transistor
MN1~MN2:電晶體 MN1~MN2: Transistor
LVN1~LVN2:低壓電晶體 LVN1~LVN2: low voltage transistor
OUT:輸出端 OUT: output terminal
OUTN:輸出端 OUTN: output terminal
圖1繪示本發明之一較佳具體實施例之動態電壓切換測試方法的流程圖。 FIG. 1 is a flowchart of a dynamic voltage switching test method according to a preferred embodiment of the present invention.
圖2繪示本發明之動態電壓切換測試方法應用於電流源偏壓電路之一實施例的示意圖。 FIG. 2 is a schematic diagram of an embodiment of applying the dynamic voltage switching test method of the present invention to a current source bias circuit.
圖3繪示本發明之動態電壓切換測試方法應用於位準偏移器偏壓電路之一實施例的示意圖。 FIG. 3 is a schematic diagram of an embodiment of applying the dynamic voltage switching test method of the present invention to a level shifter bias circuit.
圖4及圖5分別繪示圖3運作於第一測試模式及第二測試模式下的示意圖。 FIG. 4 and FIG. 5 are schematic diagrams of FIG. 3 operating in the first test mode and the second test mode, respectively.
根據本發明之一較佳具體實施例為一種動態電壓切換測試方法。於此實施例中,動態電壓切換測試方法可透過電路內部訊號之切換對於源極驅動器進行動態電壓切換來加速產品的可靠度測試,以提前在出貨時攔檢出有缺陷的產品,明顯不同於僅拉高電壓進行靜態測試的傳統作法,但不以此為限。 A preferred embodiment of the present invention is a dynamic voltage switching test method. In this embodiment, the dynamic voltage switching test method can perform dynamic voltage switching on the source driver through the switching of the internal signal of the circuit to speed up the reliability test of the product, so as to detect defective products in advance when shipping, which is obviously different The traditional method of only pulling up the voltage for static testing, but not limited thereto.
請參照圖1,圖1繪示此實施例中之動態電壓切換測試方法的流程圖。如圖1所示,動態電壓切換測試方法包括下列步驟:步驟S10:加入電壓控制電路至測試電路;以及步驟S12:當電壓控制電路運作於測試模式時,電壓控制電路利用電壓加速因子使測試電路進行動態電壓切換,以加速可靠度測試。 Please refer to FIG. 1 . FIG. 1 shows a flow chart of the dynamic voltage switching test method in this embodiment. As shown in Figure 1, the dynamic voltage switching test method includes the following steps: Step S10: adding a voltage control circuit to the test circuit; and Step S12: when the voltage control circuit operates in the test mode, the voltage control circuit uses the voltage acceleration factor to make the test circuit Perform dynamic voltage switching to speed up reliability testing.
請參照圖2,圖2繪示動態電壓切換測試方法應用於電流源偏壓電路之一實施例的示意圖。如圖2所示,電流源偏壓電路2包括複數個直流偏壓點A~C分別耦接複數個開關D1~D3,電壓控制電路CON控制該複數個開關D1~D3開啟或關閉,以使該複數個直流偏壓點A~C產
生電位差,進而加速具缺陷的電晶體老化,縮短產品可靠度測試所需時間。
Please refer to FIG. 2 . FIG. 2 is a schematic diagram of an embodiment of a dynamic voltage switching test method applied to a current source bias circuit. As shown in FIG. 2 , the current
需說明的是,此實施例係於電流源偏壓電路2加入電壓控制電路CON與開關D1~D3,利用電壓加速因子(AFV)來加速產品可靠度測試,以確保積體電路產品之品質。舉例而言,電壓加速因子(AFV)可以如下式所示:AFV=exp(β*(Vstress-Vuse))=exp(1*(21-1))=1.41E+10
It should be noted that in this embodiment, the voltage control circuit CON and switches D1~D3 are added to the current
如圖2所示,電流源偏壓電路2包括第一電晶體M1至第七電晶體M7。第一電晶體M1至第四電晶體M4為N型電晶體且第五電晶體M5至第七電晶體M7為P型電晶體。第一電晶體M1與第二電晶體M2的控制端彼此耦接於第一直流偏壓點A。電流I1流經第二電晶體M2。第七電晶體M7與第三電晶體M3耦接於工作電壓AVDD與接地電壓AGND之間。第六電晶體M6與第四電晶體M4耦接於工作電壓AVDD與接地電壓AGND之間。電阻R耦接於第四電晶體M4與接地電壓AGND之間。第五電晶體M5與第一電晶體M1耦接於工作電壓AVDD與接地電壓AGND之間。第三電晶體M3與第四電晶體M4的控制端彼此耦接於第二直流偏壓點B。第五電晶體M5至第七電晶體M7的控制端彼此耦接於第三直流偏壓點C。第一開關D1之一端耦接第一直流偏壓點A且其另一端耦接至第五電晶體M5與第一電晶體M1之間。第二開關D2之一端耦接第二直流偏壓點B且其另一端耦接至第七電晶體M7與第三電晶體M3之間。第三開關D3之一端耦接第三直流偏壓點C且其另一端耦接至第六電晶體M6與第四電晶體M4之間。
As shown in FIG. 2 , the current
於實際應用中,電壓控制電路CON可根據第一控制信號C0及第二控制信號C1的數值選擇性地操作於正常操作模式或不同的測試模式下,其一實施例的真值表如表1,但不以此為限。 In practical applications, the voltage control circuit CON can selectively operate in the normal operation mode or different test modes according to the values of the first control signal C0 and the second control signal C1. The truth table of one embodiment is shown in Table 1 , but not limited to this.
如表1所示,當第一控制信號C0為0且第二控制信號C1為1時,電壓控制電路CON操作於第一測試模式下,電壓控制電路CON提供給第一直流偏壓點A至第三直流偏壓點C的電壓值均為0。當第一控制信號C0為1且第二控制信號C1為0時,電壓控制電路CON操作於第二測試模式下,電壓控制電路CON提供給第一直流偏壓點A至第三直流偏壓點C的電壓值分別為0、0、工作電壓AVDD。當第一控制信號與第二控制信號C1均為1時,電壓控制電路CON操作於第三測試模式下,電壓控制電路CON提供給第一直流偏壓點A至第三直流偏壓點C的電壓值均為工作電壓AVDD。由上述可知:此實施例係透過電路內部訊號之切換來進行動態電壓切換測試,明顯不同於僅拉高電壓進行靜態測試的傳統作法。 As shown in Table 1, when the first control signal C0 is 0 and the second control signal C1 is 1, the voltage control circuit CON operates in the first test mode, and the voltage control circuit CON provides the first DC bias point A The voltage values up to the third DC bias point C are all zero. When the first control signal C0 is 1 and the second control signal C1 is 0, the voltage control circuit CON operates in the second test mode, and the voltage control circuit CON provides the first DC bias point A to the third DC bias The voltage values of point C are respectively 0, 0, and the working voltage AVDD. When the first control signal and the second control signal C1 are both 1, the voltage control circuit CON operates in the third test mode, and the voltage control circuit CON provides the first DC bias point A to the third DC bias point C The voltage values are the working voltage AVDD. From the above, it can be seen that this embodiment performs the dynamic voltage switching test through the switching of the internal signal of the circuit, which is obviously different from the traditional method of only pulling up the voltage for static testing.
請參照圖3,圖3繪示動態電壓切換測試方法應用於位準偏移器偏壓電路之一實施例的示意圖。 Please refer to FIG. 3 . FIG. 3 is a schematic diagram of an embodiment of a dynamic voltage switching test method applied to a level shifter bias circuit.
如圖3所示,位準偏移器偏壓電路3包括第一輸出端OUT1及第二輸出端OUT2,用以分別輸出第一電壓VP及第二電壓VN。電壓控制電路CON包括第一電晶體MT1至第十電晶體MT10。第一電晶體MT1與第二電晶體MT2串接於工作電壓AVDD與第一輸出端OUT1之間。第十一電晶體MP耦接於工作電壓AVDD與第一輸出端OUT1之間。第三電晶體MT3及電流源IA串接於第一輸出端OUT1與接地電壓AGND之間。第四電晶體MT4耦接於工作電壓AVDD與第一輸出端OUT1之間。第五電晶體MT5耦接於第一輸出端OUT1與接地電壓AGND之間。電流源IB與第六電晶體MT6串接於工作電壓AVDD與第二輸出端OUT2之間。第十二電晶體MN耦接於第二輸出端OUT2與接地電壓AGND之間。第七電晶體MT7耦接於第二輸出端OUT2與第十二電晶體MN的控制端之間。第八電晶體MT8耦接於第十二電晶體MN的控制端與接地電壓AGND之間。第九電晶體MT9耦接於第二輸出端OUT2與接地電壓AGND之間。第十電晶體MT10耦接於工作電壓AVDD與第二輸出端OUT2之間。
As shown in FIG. 3 , the level
電晶體MP1、MP3、MN1及LVN1串接於工作電壓AVDD與接地電壓AGND之間。電晶體MP2、MP4、MN2及LVN2串接於工作電壓AVDD與接地電壓AGND之間。電晶體MP1及MP2的控制端均耦接至第一輸出端OUT1。電晶體MN1及MN2的控制端均耦接至第二輸出端OUT2。電晶體MP3及MP4的控制端分別耦接輸出端OUT及OUTN。二極 體DE耦接於電晶體LVN1及LVN2的控制端之間。電晶體LVN1及LVN2為低壓電晶體元件。電晶體LVN1的控制端接收低壓輸入信號LV_IN。 The transistors MP1, MP3, MN1 and LVN1 are connected in series between the working voltage AVDD and the ground voltage AGND. The transistors MP2, MP4, MN2 and LVN2 are connected in series between the working voltage AVDD and the ground voltage AGND. The control terminals of the transistors MP1 and MP2 are both coupled to the first output terminal OUT1. The control terminals of the transistors MN1 and MN2 are both coupled to the second output terminal OUT2. The control terminals of the transistors MP3 and MP4 are respectively coupled to the output terminals OUT and OUTN. Diode The body DE is coupled between the control terminals of the transistors LVN1 and LVN2. Transistors LVN1 and LVN2 are low-voltage transistor elements. The control terminal of the transistor LVN1 receives the low voltage input signal LV_IN.
需說明的是,此實施例係於位準偏移器偏壓電路3加入包括第一電晶體MT1至第十電晶體MT10的電壓控制電路CON,利用電壓加速因子(AFV)來加速產品可靠度測試,以確保積體電路產品之品質。舉例而言,電壓加速因子(AFV)可以如下式所示:AFV=exp(β*(Vstress-Vuse))=exp(1*(21-1))=1.41E+10
It should be noted that in this embodiment, a voltage control circuit CON including the first transistor MT1 to the tenth transistor MT10 is added to the level
於實際應用中,電壓控制電路CON可分別運作於第一測試模式及第二測試模式下,致使位準偏移器偏壓電路3進行動態電壓切換,以加速可靠度測試,但不以此為限。
In practical applications, the voltage control circuit CON can operate in the first test mode and the second test mode respectively, so that the level
如圖4所示,於第一測試模式下,電壓控制電路CON控制第二電晶體MT2、第三電晶體MT3、第五電晶體MT5、第六電晶體MT6、第七電晶體MT7及第九電晶體MT9關閉,致使第一輸出端OUT1與第二輸出端OUT2均輸出工作電壓AVDD,但不以此為限。 As shown in Figure 4, in the first test mode, the voltage control circuit CON controls the second transistor MT2, the third transistor MT3, the fifth transistor MT5, the sixth transistor MT6, the seventh transistor MT7 and the ninth transistor The transistor MT9 is turned off, so that both the first output terminal OUT1 and the second output terminal OUT2 output the operating voltage AVDD, but not limited thereto.
如圖5所示,於第二測試模式下,電壓控制電路CON控制第二電晶體MT2、第三電晶體MT3、第四電晶體MT4、第六電晶體MT6、第七電晶體MT7及第十電晶體MT10關閉,致使第一輸出端OUT1與第二輸出端OUT2均輸出接地電壓AGND,但不以此為限。 As shown in Figure 5, in the second test mode, the voltage control circuit CON controls the second transistor MT2, the third transistor MT3, the fourth transistor MT4, the sixth transistor MT6, the seventh transistor MT7 and the tenth transistor The transistor MT10 is turned off, so that both the first output terminal OUT1 and the second output terminal OUT2 output the ground voltage AGND, but not limited thereto.
需說明的是,第一輸出端OUT1與第二輸出端OUT2於第一測試模式下均輸出工作電壓AVDD且於第二測試模式下均輸出接地電壓AGND,可有助於確保動態電壓切換(DVS)測試的正常運作且同時可保護低壓電晶體LVN1及LVN2。 It should be noted that both the first output terminal OUT1 and the second output terminal OUT2 output the operating voltage AVDD in the first test mode and both output the ground voltage AGND in the second test mode, which can help ensure dynamic voltage switching (DVS ) to test the normal operation and protect the low-voltage transistors LVN1 and LVN2 at the same time.
相較於先前技術,本發明之動態電壓切換測試方法並非僅是拉高電壓進行靜態測試,而是透過電路內部訊號之切換來進行動態電壓切換(DVS)測試,藉以加速產品的可靠度測試,以提前在出貨時將有缺陷的產品攔檢出來,故可有效確保積體電路產品之品質在保固期內不會發生故障,大幅減少客戶的退貨率。 Compared with the previous technology, the dynamic voltage switching test method of the present invention is not just to pull up the voltage for static testing, but to perform dynamic voltage switching (DVS) testing through the switching of internal signals in the circuit, so as to speed up the reliability testing of products. Defective products can be checked out in advance when they are shipped, so it can effectively ensure that the quality of integrated circuit products will not break down during the warranty period, and greatly reduce the return rate of customers.
S10~S12:步驟 S10~S12: Steps
Claims (5)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW111121663A TWI804342B (en) | 2022-06-10 | 2022-06-10 | Dynamic voltage switching testing method |
| CN202211017992.XA CN117250471A (en) | 2022-06-10 | 2022-08-24 | Dynamic Voltage Switching Test Method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW111121663A TWI804342B (en) | 2022-06-10 | 2022-06-10 | Dynamic voltage switching testing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TWI804342B true TWI804342B (en) | 2023-06-01 |
| TW202349017A TW202349017A (en) | 2023-12-16 |
Family
ID=87803386
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW111121663A TWI804342B (en) | 2022-06-10 | 2022-06-10 | Dynamic voltage switching testing method |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN117250471A (en) |
| TW (1) | TWI804342B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4950921A (en) * | 1987-08-26 | 1990-08-21 | Nec Corporation | Semiconductor integrated circuit having a built-in voltage generator for testing at different power supply voltages |
| US20060076971A1 (en) * | 2004-09-07 | 2006-04-13 | Krishnan Anand T | System and method for accurate negative bias temperature instability characterization |
| TWI705260B (en) * | 2019-05-24 | 2020-09-21 | 台灣積體電路製造股份有限公司 | Circuit screening system and circuit screening method |
| TWI707149B (en) * | 2018-02-23 | 2020-10-11 | 百慕達商邁威國際有限公司 | On-chip reliability monitor and method |
| TWI764509B (en) * | 2021-01-12 | 2022-05-11 | 宏汭精測科技股份有限公司 | Universal switching platform and method for device dynamics characterization |
-
2022
- 2022-06-10 TW TW111121663A patent/TWI804342B/en active
- 2022-08-24 CN CN202211017992.XA patent/CN117250471A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4950921A (en) * | 1987-08-26 | 1990-08-21 | Nec Corporation | Semiconductor integrated circuit having a built-in voltage generator for testing at different power supply voltages |
| US20060076971A1 (en) * | 2004-09-07 | 2006-04-13 | Krishnan Anand T | System and method for accurate negative bias temperature instability characterization |
| TWI707149B (en) * | 2018-02-23 | 2020-10-11 | 百慕達商邁威國際有限公司 | On-chip reliability monitor and method |
| TWI705260B (en) * | 2019-05-24 | 2020-09-21 | 台灣積體電路製造股份有限公司 | Circuit screening system and circuit screening method |
| TWI764509B (en) * | 2021-01-12 | 2022-05-11 | 宏汭精測科技股份有限公司 | Universal switching platform and method for device dynamics characterization |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117250471A (en) | 2023-12-19 |
| TW202349017A (en) | 2023-12-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2006260030A (en) | Constant voltage power supply circuit and inspection method for constant voltage power supply circuit | |
| US9525937B2 (en) | Circuit for suppressing audio output noise and audio output circuit | |
| CN103532538B (en) | A level shifting circuit for high voltage applications | |
| JP2005151438A (en) | Comparator circuit | |
| US20210156894A1 (en) | High-speed afe for current monitoring applications | |
| US6198312B1 (en) | Low level input voltage comparator | |
| US7518377B2 (en) | Measurement apparatus, test apparatus, and measurement method | |
| TWI804342B (en) | Dynamic voltage switching testing method | |
| JPH0993055A (en) | Operational amplifier | |
| TWI824947B (en) | Dynamic voltage switching testing method | |
| CN101655517B (en) | Voltage detection circuit and voltage detection method | |
| JP2017174116A (en) | Voltage regulator | |
| CN103916115B (en) | Transmission gate circuit | |
| JP3068146B2 (en) | Semiconductor integrated circuit | |
| CN111416579A (en) | Receiver front-end circuit and method of operation | |
| CN120546613A (en) | Slew rate enhancement circuit for operational amplifier | |
| JP4819407B2 (en) | Semiconductor device having trimming circuit, trimming method and manufacturing method thereof | |
| KR100930500B1 (en) | Bandgap Reference Circuit Using Comparator | |
| JP4016854B2 (en) | Semiconductor device having operational amplifier circuit | |
| JP2009074850A (en) | Inspection method of semiconductor integrated circuit and semiconductor integrated circuit | |
| CN115173840A (en) | High-voltage side current comparison circuit | |
| CN112350676B (en) | Semiconductor amplifier circuit and semiconductor circuit | |
| JP5974998B2 (en) | Operational amplifier | |
| CN101931373B (en) | Output circuit using analog amplifier | |
| US12470187B2 (en) | Play mute circuit and method |