TWI803218B - Semiconductor device and semiconductor module - Google Patents

Abstract

The present invention provides a semiconductor device that is hard to damage caused by thermal runaway. On the substrate, a plurality of units of three or more are arranged side by side in the first direction. Conductor protrusions are arranged on the substrate. Each of the plurality of units includes a bipolar transistor, and a ballast resistance element connected to the bipolar transistor. The conductor protrusions are connected to the emitter layers of the bipolar transistors of the plurality of units. The bipolar transistors of a plurality of units are connected in parallel. Among the plurality of units, the resistance value of the ballast resistance element included in the first unit at the end is greater than the resistance value of the ballast resistance element included in at least one second unit other than the end.

Description

Semiconductor device and semiconductor module

The invention relates to a semiconductor device and a semiconductor module including a bipolar transistor.

High-frequency power amplifiers for mobile communication devices use power amplifiers in which a plurality of bipolar transistors such as heterojunction bipolar transistors are connected in parallel. If the temperature is not uniform among the plurality of bipolar transistors during operation, the characteristics will be lowered or the components will be destroyed. Patent Document 1 discloses a semiconductor device capable of improving the temperature uniformity of a bipolar transistor having a multi-finger structure.

In the semiconductor device disclosed in Patent Document 1, the emitter fingers are formed in a more slender shape under the condition of a constant area from the peripheral portion of the wafer to the central portion. Also, when an emitter ballast resistor is provided, it is relatively high at the periphery of the chip and relatively low at the center. The plurality of emitter fingers are respectively connected to a common emitter pad through an emitter ballast resistor. The collector electrode and the base electrode are respectively connected to the collector pad and the base pad.

The heat generated in the emitter finger is diffused in the thickness direction and in-plane direction of the substrate. Since the perimeter length of the emitter fingers at the central portion is longer than that of the emitter fingers at the peripheral portion of the chip, the heat dissipation characteristics of the emitter at the central portion pointing in the in-plane direction are improved. The heat diffused in the thickness direction and in-plane direction of the substrate is finally conducted to the package housing the semiconductor device and the like. [Prior art literature] [Patent Document]

[Patent Document 1] Japanese Patent Application Laid-Open No. 7-176538

[Problem to be solved by the invention]

When a semiconductor device is flip-chip mounted on a module substrate or the like, it is difficult to dissipate heat from the substrate constituting the semiconductor device to the outside. If the heat generated in the bipolar transistor stays in the semiconductor device, there is a case where the bipolar transistor is thermally runaway to cause destruction. An object of the present invention is to provide a semiconductor device that is difficult to be damaged by thermal runaway. [means to solve the problem]

According to an aspect of the present invention, a semiconductor device is provided, including: Substrate; A plurality of units of 3 or more are arranged side by side in the first direction on the above-mentioned substrate; and conductor protrusions, arranged on the above-mentioned substrate and protruding in a direction away from the above-mentioned substrate; Each of the plurality of units above includes: a bipolar transistor comprising a collector layer, a base layer and an emitter layer; and a ballast resistance element connected to the bipolar transistor; The above-mentioned conductor protrusion is connected to the emitter layer of the above-mentioned bipolar transistor of the above-mentioned plurality of units; The above-mentioned bipolar transistors of the above-mentioned plurality of units are connected in parallel with each other; and Among the plurality of units, the resistance value of the ballast resistance element included in the first unit at the end is greater than the resistance value of the ballast resistance element included in at least one second unit other than the end.

According to other aspects of the present invention, a semiconductor module is provided, including: A semiconductor device comprising: a substrate, a plurality of units arranged side by side in a first direction on the substrate, and a conductor protrusion arranged on the substrate and protruding in a direction away from the substrate; and A module substrate, on which the above-mentioned semiconductor device is flip-chip mounted via the above-mentioned conductor protrusion; Each of the plurality of units includes a bipolar transistor including a collector layer, a base layer, and an emitter layer; The above-mentioned bipolar transistors of the above-mentioned plurality of units are connected in parallel; The above-mentioned conductor protrusion overlaps the above-mentioned plurality of units when viewed from above, and is electrically connected to the emitter layer of the above-mentioned bipolar transistor of the above-mentioned plurality of units; and The above module substrates include: a through hole, which overlaps the above-mentioned conductor protrusion in plan view, is long in the above-mentioned first direction, and is electrically connected to the above-mentioned conductor protrusion; and The through-hole includes a portion wider than the width of the central portion at a portion offset from the central portion of the range where the plurality of cells are arranged in the above-mentioned first direction toward the end portion.

According to still other viewpoints of the present invention, a semiconductor module is provided, including: A semiconductor device comprising: a substrate, a plurality of units arranged side by side in a first direction on the substrate, and a conductor protrusion arranged on the substrate and protruding in a direction away from the substrate; and A module substrate, on which the above-mentioned semiconductor device is flip-chip mounted via the above-mentioned conductor protrusion; Each of the plurality of units includes a bipolar transistor including a collector layer, a base layer, and an emitter layer; The above-mentioned bipolar transistors of the above-mentioned plurality of units are connected in parallel; The above-mentioned conductor protrusion overlaps the above-mentioned plurality of units when viewed from above, and is electrically connected to the emitter layer of the above-mentioned bipolar transistor of the above-mentioned plurality of units; and The above module substrates include: at least 2 through holes, which overlap with the above-mentioned conductor protrusion in plan view, are electrically connected to the above-mentioned conductor protrusion, and are arranged side by side in the above-mentioned first direction; and In the central part of the range where the plurality of cells are arranged in the first direction, the through hole is not arranged. [Invention effect]

According to experience, it is known that the second unit other than both ends is more likely to be damaged than the first unit at both ends. By setting the resistance value of the ballast resistance element included in the first unit to be greater than the resistance value of the ballast resistance element included in the second unit, a relatively large current flows through the second unit, and heat is generated increase. Therefore, it is possible to suppress a decrease in the damage resistance of the second unit during low-temperature operation. In addition, with the above-mentioned configuration as the through-hole of the module substrate, the heat dissipation characteristic of the unit in the central part is relatively lowered, and the temperature is easy to rise. Therefore, it is possible to suppress a decrease in the damage resistance of the second unit during low-temperature operation.

[first embodiment] The semiconductor device of the first embodiment will be described with reference to the diagrams of FIGS. 1 to 4 . FIG. 1 is an equivalent circuit diagram of a semiconductor device of the first embodiment. The semiconductor device of the first embodiment includes a plurality of cells 20 . A plurality of units 20 are arranged side by side in one direction on the substrate to form a unit row. Here, the so-called "arranged in one direction" does not necessarily need to be arranged in a straight line, for example, they can also be arranged in a zigzag shape. In FIG. 1 , two cells 20A positioned at both ends of the cell row, two cells 20 positioned inside one from both ends, and two cells 20B positioned at the center of the cell row are shown.

Each of the plurality of units 20 includes: a bipolar transistor 21 , a base ballast resistor 22 , and an input capacitor 23 . The bipolar transistors 21 of the plurality of units 20 are connected in parallel. The emitter of the bipolar transistor 21 is connected to the emitter common wiring 50 , and the collector is connected to the collector common wiring 51 .

The bipolar transistors 21 of the plurality of units 20 are respectively connected to the base bias wiring 52 common to the plurality of units 20 through the base ballast resistance element 22 , and are connected to the common base bias wiring 52 of the plurality of units 20 through the input capacitor 23 The high-frequency signal input wiring 53 is connected. The base bias current is supplied to the bipolar transistor 21 through the common base bias wiring 52 and the base ballast resistance element 22 of each cell 20 . Among the plurality of cells 20, the resistance value of the base ballast resistance element 22 included in the end cell 20A is greater than the resistance value of the base ballast resistor element 22 included in at least one cell 20B other than the end portion.

A high-frequency signal is input to the bipolar transistor 21 through the high-frequency signal input wiring 53 and the input capacitor 23 of each cell 20 . The high-frequency signal amplified by the bipolar transistor 21 is output from the collector common wiring 51 . Further, a collector voltage is applied to the bipolar transistor 21 through the choke coil and the common collector wiring 51 .

Fig. 2 is a schematic plan view of the semiconductor device of the first embodiment. A plurality of units 20 are arranged side by side in one direction. The xyz Cartesian coordinate system in which the direction in which a plurality of cells 20 are arranged is defined as the y direction, and the normal direction of the surface of the substrate is defined as the z direction is defined. A sub-collector layer 25 of n-type conductivity is disposed on the surface portion of the substrate. In plan view, bipolar transistor 21 and a pair of collector electrodes 30C are arranged in sub-collector layer 25 . A pair of collector electrodes 30C sandwiches bipolar transistor 21 in the y direction.

As described later with reference to FIG. 3 , the bipolar transistor 21 includes a base mesa 21BM, which includes a collector layer 21C, a base layer 21B, and an emitter layer 21E sequentially stacked on the sub-collector layer 25 . In a plan view, a pair of emitter electrodes 30E are arranged at intervals in the y direction so as to be included in the base mesa 21BM, and furthermore, a base electrode 30B is arranged. Each of the emitter electrodes 30E has a shape that is long in the x direction in plan view. The base electrode 30B includes a base finger 30BF long in the x direction and a base contact 30BC. The base finger 30BF is arranged between a pair of emitter electrodes 30E. The base contact portion 30BC is continuous with one end portion of the base finger portion 30BF.

The shape, size, and relative positional relationship of the emitter electrode 30E and the base electrode 30B are the same among the plurality of cells 20 . Therefore, the ratio of the length (dimension in the x direction) to the width (dimension in the y direction) of the emitter electrode 30E is the same among all the cells 20 . In addition, the plurality of cells 20 are equally arranged at equal intervals in the y direction.

In FIG. 2 , the collector electrode 30C, the emitter electrode 30E, and the base electrode 30B are hatched rising to the right. Mark the conductor pattern in the wiring layer of the first layer with a relatively light hatching line descending to the right. In addition, the base ballast resistance element 22 is marked with a relatively light hatching rising to the right. On the wiring layer of the first layer, emitter wiring 31E, collector wiring 31C, base wiring 31B, collector common wiring 51 , and base bias wiring 52 are arranged.

The emitter wiring 31E crosses the base finger 30BF from one of the emitter electrodes 30E, and reaches the other emitter electrode 30E. The pair of emitter electrodes 30E are connected to each other by emitter wiring 31E.

The plurality of collector wirings 31C each overlap the collector electrode 30C in plan view, and are connected to the collector electrode 30C. The plurality of collector lines 31C extend to the outside of the sub-collector layer 25 in one of the x directions, and are continuous with the collector common line 51 .

The plurality of base wirings 31B each overlap the base contact portion 30BC in plan view, and are connected to the base contact portion 30BC. The plurality of base wirings 31B extend to the outside of the sub-collector layer 25 in one of the x directions. The plurality of base lines 31B are respectively connected to a common base bias line 52 via a base ballast resistance element 22 .

The emitter common wiring 50 and the high-frequency signal input wiring 53 are arranged on the wiring layer of the second layer. The emitter common line 50 extends from the cell 20A at one end to the cell 20A at the other end in the y direction in a plan view, and is connected to the emitter line 31E disposed on each of the plurality of cells 20 . The high-frequency signal input wiring 53 extends in the y direction so as to cross the base wiring 31B arranged on each of the plurality of cells 20 . The portion of the base wiring 31B that overlaps the high-frequency signal input wiring 53 has a larger dimension in the y direction than other portions. The input capacitor 23 is formed in a region where the base wiring 31B overlaps with the high-frequency signal input wiring 53 .

Conductor protrusions 54 are arranged so as to overlap with emitter common wiring 50 in plan view. The conductor bump 54 is connected to the emitter common wiring 50 and is used as an external connection terminal when the flip chip is mounted on a module substrate.

Fig. 3 is the sectional view at the dot chain line 3-3 of Fig. 2. A sub-collector layer 25 is disposed on the substrate 15 . A base mesa 21BM is disposed on a part of the sub-collector layer 25 . The base mesa 21BM includes a collector layer 21C, a base layer 21B, and an emitter layer 21E stacked in order from the sub-collector layer 25 . The bipolar transistor 21 is constituted by the collector layer 21C, the base layer 21B, and the emitter layer 21E. On the emitter layer 21E, a pair of cap layers 26A are arranged at intervals in the y direction. Contact layers 26B are disposed on the pair of cap layers 26A, respectively.

Next, an example of the material of these semiconductor layers is demonstrated. Semi-insulating GaAs is used for the substrate 15 . The sub-collector layer 25 and the collector layer 21C are formed of n-type GaAs. The base layer 21B is formed of p-type GaAs. The emitter layer 21E is formed of n-type InGaP. The cap layer 26A and the contact layer 26B are formed of n-type GaAs and n-type InGaAs, respectively.

Emitter electrodes 30E are disposed on the pair of contact layers 26B, respectively. The emitter electrode 30E is electrically connected to the emitter layer 21E through the contact layer 26B and the top cover layer 26A. In the emitter layer 21E, a region overlapping with the cap layer 26A in a planar view functions substantially as an emitter region of the bipolar transistor 21 .

By using the emitter electrode 30E as an etching mask to etch away unnecessary portions of the contact layer 26B and the cap layer 26A, the contact layer 26B and the cap layer 26A are formed in a self-aligned manner. Therefore, the top-view shapes of the contact layer 26B and the cap layer 26A are basically the same as the top-view shapes of the emitter electrode 30E. In addition, the emitter electrode 30E may be formed by using a lift-off method after removing unnecessary portions of the cap layer 26A and the contact layer 26B by etching using a resist mask.

A base electrode 30B is disposed on the emitter layer 21E between the pair of cap layers 26A. The base electrode 30B passes through the emitter layer 21E in the thickness direction to reach the alloyed region 27 of the base layer 21B, thereby being electrically connected to the base layer 21B.

Collector electrodes 30C are disposed on the sub-collector layers 25 on both sides of the base mesa 21BM, respectively. The collector electrode 30C is electrically connected to the collector layer 21C via the sub-collector layer 25 .

An interlayer insulating film 35 is disposed over the entire area of the substrate 15 so as to cover the collector electrode 30C, the emitter electrode 30E, the base electrode 30B, and the like. An emitter contact hole 40E and a collector contact hole 40C are provided on the interlayer insulating film 35 . An emitter wiring 31E and a collector wiring 31C are arranged on the interlayer insulating film 35 . The emitter wiring 31E is connected to the emitter electrode 30E through the emitter contact hole 40E. The pair of emitter electrodes 30E are electrically connected to each other by emitter wiring 31E. The collector wiring 31C is connected to the collector electrode 30C through the collector contact hole 40C.

A second-layer interlayer insulating film 36 is disposed on the interlayer insulating film 35 so as to cover the emitter wiring 31E and the collector wiring 31C. An emitter contact hole 41E included in the emitter wiring 31E in plan view is provided on the second-layer interlayer insulating film 36 . An emitter common wiring 50 is arranged on the interlayer insulating film 36 . The emitter common wiring 50 is connected to the emitter wiring 31E through the emitter contact hole 41E.

A protective film 37 is disposed on the emitter common wiring 50 , and an opening 42E is provided on the protective film 37 . Conductor protrusions are arranged in the opening 42E of the protective film 37 . The conductor protrusion extends over the protective film 37 at the periphery of the opening 42E. The conductor protrusion 54 protrudes from the upper surface of the protective film 37 in a direction away from the substrate 15 .

The conductor protrusion 54 includes a bottom bump metal layer 54A, a Cu pillar 54B, and a solder layer 54C that are sequentially stacked from the emitter common wiring 50 . The conductor protrusion of this kind of structure is called Cu pillar bump. As the conductor bump 54 , in addition to the Cu post bump, an Au bump, a solder ball bump, a conductor post (pillar), or the like may be used.

The top cover layer 26A, the contact layer 26B, the emitter electrode 30E, the emitter wiring 31E, the emitter common wiring 50, and the conductor protrusion 54 not only function as a current path through which the emitter current flows, but also serve as a bipolar electrode. The heat generated in the crystal 21 is conducted to the function of the thermal conduction path of the module substrate.

Next, the excellent effect of the first embodiment will be described with reference to FIG. 4 . FIG. 4 is a graph showing the measurement results of the destruction margin of a semiconductor device in which the resistance value of the base ballast resistance element 22 is set to be the same in all the cells 20 . The horizontal axis represents the collector voltage in relative value, and the vertical axis represents the collector current in relative value. The solid line and the dotted line in the graph of FIG. 4 represent the results measured under the conditions that the substrate temperature is room temperature and -30° C., respectively. When the substrate temperature is lowered from room temperature to -30° C., as indicated by a hollow arrow, it can be seen that the damage resistance is lowered.

As a result of investigating the samples where damage occurred, it was found that damage was concentrated in the cells 20 other than the ends among the plurality of cells 20 , especially the cells 20 near the center in the y direction. Hereinafter, the reason why the destruction occurs intensively in the cells 20 in the vicinity of the center will be considered.

The reason why the destruction occurs concentratedly in the cells 20 near the center is that the damage resistance of the cells 20 near the center is lower than that of the cells 20 at the ends. Referring to the damage resistance graph shown in FIG. 4 , it is considered that the reason why the damage resistance of the central cell 20 is relatively low is that the temperature of the cells 20 near the center during operation is lower than that of the end cells. For example, as shown in FIG. 2 , the cells 20 near the center are connected to the center of the conductor protrusion 54 functioning as a heat conduction path, and the cells 20A at the end are connected to the end of the conductor protrusion 54 . Therefore, the heat dissipation characteristics from the cells 20 near the center are relatively increased, and as a result, the temperature is considered to be relatively lower.

In the first embodiment, the resistance value of the base ballast resistance element 22 of at least one cell 20B other than the end cell 20A is relatively reduced. Therefore, the collector current of the cell 20B is relatively increased compared with the collector current of the end cell 20A. As a result, the temperature of the cell 20B rises, and the reduction of the damage resistance is suppressed. In order to improve the damage resistance of the semiconductor device, it is preferable to relatively reduce the resistance value of the base ballast resistance element 22 of the cell 20 in the part where damage is particularly likely to occur.

[Second embodiment] Next, a semiconductor device according to a second embodiment will be described with reference to FIGS. 5 and 6 . Hereinafter, descriptions of the common configurations of the semiconductor device of the first embodiment described with reference to FIGS. 1 to 4 are omitted.

FIG. 5 is a schematic plan view of the semiconductor device of the second embodiment, and FIG. 6 is a cross-sectional view at the dotted line 6-6 in FIG. 5 . In the first embodiment, the width (dimension in the x direction) of the conductor protrusion 54 (FIG. 2) is constant. On the other hand, in the second embodiment, the width of a part including the center in the longitudinal direction (y direction) of the conductor protrusion 54 is narrower than the width of the other part on the end side. In FIG. 5 , the conductor protrusion 54 is hatched. For example, the width of at least a part overlapping with the cell 20B having a relatively lower resistance value of the base ballast resistance element 22 is narrower than that of at least a part overlapping with the cells 20A at both ends in plan view. As the width of the conductor protrusion 54 is narrowed, as shown in FIG. 6 , a region where the conductor protrusion 54 is not arranged is generated above the cell 20B at a certain position in the x direction.

Next, the excellent effect of the second embodiment will be described. In the second embodiment, the width of the conductor protrusion 54 is narrowed in the area where the cells 20B are arranged in the x direction. Therefore, compared with the configuration in which the width of the conductor protrusion 54 is constant, the heat dissipation characteristic of the cell 20B is lowered, and the temperature rise is increased. As a result, the temperature difference between the cell 20B and the cell 20A decreases. This makes it difficult to cause damage due to temperature unevenness, and improves the damage resistance of the semiconductor device.

Next, a semiconductor device according to a modified example of the second embodiment will be described. In the second embodiment, the temperature is increased by adopting both the structure in which the resistance value of the base ballast resistance element 22 is different among the cells 20 and the structure in which the width of the conductor protrusion 54 is different according to the position in the y direction. the uniformity. As a modified example, only a configuration in which the resistance value of the base ballast resistance element 22 is made the same among the plurality of cells 20 and the width of the conductor protrusion 54 varies depending on the position in the y direction may be employed.

In FIG. 5 , the number of cells 20B that relatively lowers the resistance value of the base ballast resistance element 22 is set to two. The unit 20B that relatively reduces the resistance value of the base ballast resistance element 22 may be one, or three or more. It is preferable to relatively reduce the resistance value of the base ballast resistance element 22 of the unit 20 which is particularly prone to damage.

[third embodiment] Next, a semiconductor device according to a third embodiment will be described with reference to FIG. 7 . Hereinafter, the description of the configuration common to the semiconductor device of the second embodiment described with reference to FIGS. 5 and 6 is omitted.

Fig. 7 is a schematic plan view of the semiconductor device of the third embodiment. In the second embodiment (FIG. 5), the width of the portion other than the end portion of the conductor protrusion 54 is narrower than that of the portion at the end portion. On the other hand, in the third embodiment, at the position where the cell 20B having a relatively low resistance value of the base ballast resistance element 22 is disposed, the conductor protrusion 54 is separated in the y direction. In FIG. 7 , the conductor protrusion 54 is hatched. That is, the two cells 20B do not overlap the conductor protrusion 54 in plan view. In addition, the number of cells 20 that do not overlap with the conductor protrusion 54 in plan view is not limited to two. The conductor protrusions 54 may be arranged so that one cell 20 does not overlap the conductor protrusions 54 , or the conductor protrusions 54 may be arranged so that three or more cells 20 do not overlap the conductor protrusions 54 .

The bipolar transistor 21 of the unit 20B does not overlap with the conductor protrusion 54 in plan view. Moreover, only a part of the bipolar transistor 21 of the unit 20B may be set as the structure which does not overlap with the conductor protrusion 54 in planar view. The emitter common wiring 50 continues from the position of the cell 20A where one of the ends is arranged to the position of the cell 20A where the other end is arranged.

Next, the excellent effect of the third embodiment will be described. In the third embodiment, since at least a part of the bipolar transistor 21 of the unit 20B does not overlap with the conductor protrusion 54, the heat dissipation characteristic of the unit 20B is lower than that of the units 20A at both ends. The amount of heat dissipation from the unit 20B, which is relatively prone to low temperature, is relatively reduced, so that the uniformity of temperature among the units 20 is improved. As a result, damage due to temperature variation is less likely to occur, and the damage resistance of the semiconductor device can be improved.

Next, a semiconductor device according to a modified example of the third embodiment will be described. In the third embodiment, the temperature uniformity is improved by adopting both the structure in which the resistance value of the base ballast resistance element 22 is different among the cells 20 and the structure in which the conductor protrusion 54 is divided into two parts. As a modified example, only a structure in which the resistance value of the base ballast resistance element 22 is made the same among the plurality of cells 20 and the conductor protrusion 54 is separated into two parts may be employed.

[Fourth embodiment] Next, a semiconductor device according to a fourth embodiment will be described with reference to FIG. 8 . Hereinafter, the description of the configuration common to the semiconductor device of the second embodiment described with reference to FIGS. 5 and 6 is omitted.

Fig. 8 is a schematic plan view of a semiconductor device according to a fourth embodiment. In the second embodiment ( FIG. 5 ), one conductor protrusion 54 long in the y direction is arranged. On the other hand, in the fourth embodiment, the plurality of conductor protrusions 54 are arranged side by side in the y direction in the range from the unit 20A at one end of the plurality of units 20 to the unit 20A at the other end. In FIG. 8 , the conductor protrusion 54 is hatched. Each of the conductor protrusions 54 has a circular shape in plan view. In addition, the shape of each of the conductor protrusions 54 in plan view may be a shape such as a rounded square, rounded rectangle, or the like.

The distribution density of the conductor protrusions 54 decreases from both ends of the range where the plurality of cells 20 are arranged toward the center. For example, when the distance between the geometric centers of the adjacent conductor protrusions 54 is marked as D1, the distance D1 between the vicinity of the center is wider than the distance D1 between the vicinity of the ends in the y direction.

Next, the excellent effect of the fourth embodiment will be described. In the fourth embodiment, in the range where a plurality of units 20 are arranged, since the distribution density of the conductor protrusions 54 near the center in the y direction is relatively low, the heat dissipation characteristics of the bipolar transistors 21 of the units 20 near the center are relatively relatively low. lower. In addition, near the center, a cell 20B having a relatively low resistance value of the base ballast resistance element 22 is disposed. Therefore, similarly to the second embodiment, the uniformity of temperature among the cells 20 is improved. As a result, damage due to temperature variation is less likely to occur, and the damage resistance of the semiconductor device can be improved.

Next, a semiconductor device according to a modified example of the fourth embodiment will be described. In the fourth embodiment, by adopting both the structure in which the resistance value of the base ballast resistance element 22 is different among the cells 20, and the structure in which the distribution density of the conductor protrusions 54 is different according to the position in the y direction, the improvement can be improved. Uniformity of temperature. As a modified example, only a structure in which the resistance value of the base ballast resistance element 22 is made the same among the plurality of cells 20 and the distribution density of the conductor protrusions 54 varies depending on the position in the y direction may be employed. [Fifth Embodiment] Next, a semiconductor device according to a fifth embodiment will be described with reference to FIG. 9 . Hereinafter, descriptions of the common configurations of the semiconductor device of the first embodiment described with reference to FIGS. 1 to 4 are omitted.

Fig. 9 is a schematic plan view of a semiconductor device according to a fifth embodiment. In the first embodiment ( FIG. 2 ), a plurality of units 20 are equally arranged in the y direction. On the other hand, in the fifth embodiment, the distance D between the centers of two adjacent cells 20 in the y direction differs depending on the position in the y direction. As the center of the cell 20, the geometric center of the respective bipolar transistor 21 of the cell 20 is used. The distance D between the center of the unit 20A at both ends and the center of the adjacent unit 20 is compared with the distance D between the centers of the two adjacent units 20 of the unit 20B that includes the base ballast resistance element 22 with a relatively low resistance value. wider.

The conductor protrusion 54 extends from the position of the cell 20A where one end portion is disposed to the position of the cell 20A where the other end portion is disposed. In FIG. 9 , the conductor protrusion 54 is hatched. The conductor protrusion 54 has a constant width.

Next, the excellent effect of the fifth embodiment will be described. Focusing on the distance D between the centers of the cells 20, the temperature of the cells 20 close to the center that are closely arranged tends to rise. Focusing only on the positional relationship between the long conductor protrusion 54 in the y direction and the cells 20, the heat dissipation characteristics of the cells 20 near the center are higher than those of the cells 20 near the ends. As described above, the heat dissipation characteristics of the cells 20 near the center where the temperature tends to rise tend to rise relatively. Thus, the uniformity of temperature among the units 20 is improved. As a result, damage due to temperature variation is less likely to occur, and the damage resistance of the semiconductor device can be improved.

[Sixth embodiment] Next, the semiconductor module of the sixth embodiment will be described with reference to the diagrams of FIGS. 10A to 10D. The semiconductor module of the sixth embodiment includes the semiconductor device of the first embodiment described with reference to the diagrams of FIG. 1 to FIG. 4 , and a module substrate on which the semiconductor device is mounted.

FIG. 10A is a diagram showing a planar arrangement of main components of a semiconductor device 60 included in the semiconductor module of the sixth embodiment. A plurality of units 20 and conductor protrusions 54 overlapping the plurality of units 20 in plan view are provided on the substrate 15 . As shown in FIG. 3 , the conductive protrusion 54 is electrically connected to the emitter layer 21E of the unit 20 . In addition to the conductor protrusion 54, a conductor protrusion 55 for grounding and a conductor protrusion 56 for signal input and output are also provided.

FIG. 10B is a diagram showing a planar arrangement of main components of a module substrate 70 included in the semiconductor module of the sixth embodiment. Solder pads 74 , 75 , 76 are disposed on the upper surface of the module substrate 70 . Through-holes 84 and 85 are provided so as to overlap with the pads 74 and 75 respectively in plan view. External connection terminals 94 and 95 are disposed on the lower surface of the module substrate.

10C and 10D are schematic cross-sectional views of the semiconductor module of the sixth embodiment. The semiconductor device 60 is flip-chip mounted on the module substrate 70 . FIG. 10C is equivalent to the section at the dotted line 10C-10C in FIG. 10A and FIG. 10B , and FIG. 10D is equivalent to the section at the dotted line 10D-10D in FIG. 10A and FIG. 10B .

The conductor protrusions 54 , 55 , 56 of the semiconductor device 60 are respectively connected to the pads 74 , 75 , 76 of the module substrate 70 by solder. The through hole 84 connects the pad 74 on the upper surface with the external connection terminal 94 on the lower surface. Other through-holes 85 connect the pads 75 on the upper surface with the external connection terminals 95 on the lower surface. The external connection terminals 94 and 95 are connected to pads of the motherboard, for example.

The shapes of the pads 74 , the through holes 84 , and the external connection terminals 94 in plan view are long in the direction in which the plurality of cells 20 are arranged. The pads 74, the through-holes 84, and the external connection terminals 94 are shifted from the central portion to the end of the range where the plurality of cells 20 are arranged in the array direction of the cells 20, including a portion 74A wider than the central portion. , 84A, 94A.

Next, the excellent effect of the eighth embodiment will be described. The through hole 84 of the module substrate 70 not only has the function of electrically connecting the semiconductor device 60 and the motherboard, but also has the function of conducting the heat generated in the unit 20 of the semiconductor device 60 to the heat conduction path of the motherboard. In the sixth embodiment, the pads 74, the through-holes 84, and the external connection terminals 94 are located at positions offset from the central portion, and include wide portions 74A, 84A, and 94A. Therefore, the thermal resistance of the thermal conduction path from the unit 20 overlapping the wide portions 74A, 84A, 94A to the motherboard in plan view is lower than the thermal resistance of the thermal conduction path from the central portion of the unit 20 to the motherboard. In other words, the heat dissipation characteristics of the units 20 near the center are relatively low.

The temperature of the cells 20 near the center where the temperature is relatively difficult to rise due to the positional relationship with the conductor protrusion 54 is easily raised by the structure of the penetrating through hole 84 . Therefore, the temperature uniformity of the plurality of units 20 is improved. As a result, damage due to temperature variation is less likely to occur, and the damage resistance of the semiconductor device can be improved.

Next, the semiconductor module of the modified example of the sixth embodiment will be described. In the semiconductor module of the sixth embodiment, as the semiconductor device 60, the semiconductor device of the first embodiment described with reference to FIGS. device. In addition, it is also possible to use a semiconductor device having the same resistance value of the base ballast resistance element 22 in all the cells 20 as the semiconductor device 60 of the semiconductor module of the sixth embodiment.

[Seventh embodiment] Next, the semiconductor module of the seventh embodiment will be described with reference to the diagrams of FIGS. 11A to 11D. Hereinafter, descriptions of common configurations with the semiconductor module of the sixth embodiment described with reference to FIGS. 10A to 10D are omitted.

FIG. 11A is a diagram showing a planar arrangement of main components of a semiconductor device 60 included in the semiconductor module of the seventh embodiment, which is the same as that shown in FIG. 10A .

FIG. 11B is a diagram showing a planar arrangement of main components of a module substrate 70 included in the semiconductor module of the seventh embodiment. 11C and 11D are schematic cross-sectional views of the semiconductor module of the seventh embodiment. Fig. 11C is equivalent to the section at the dotted line 11C-11C in Figs. 11A and 11B, and Fig. 11D is equivalent to the section at the dotted line 11D-11D in Figs. 11A and 11B.

In the sixth embodiment ( FIG. 10B ), the widths of the through-holes 84 and the external connection terminals 94 vary depending on the positions in the arrangement direction of the cells 20 . In contrast, the seventh embodiment includes two through-holes 84 arranged side by side in the direction in which the plurality of cells 20 are arranged. Near the center of the range where a plurality of cells 20 are arranged, no through hole 84 is arranged. Two external connection terminals 94 are arranged similarly to the through holes 84 . In addition, the pad 74 continues from the location of the cell 20 at one end to the location of the cell 20 at the other end.

Next, the excellent effect of the seventh embodiment will be described. In the seventh embodiment, as in the sixth embodiment, the temperature of the cells 20 near the center where the temperature is relatively difficult to increase due to the positional relationship with the conductor protrusion 54 is easily increased by the structure of the through hole 84 . Therefore, the temperature uniformity of the plurality of units 20 is improved. As a result, damage due to temperature variation is less likely to occur, and the damage resistance of the semiconductor device can be improved.

[Eighth embodiment] Next, the semiconductor device of the eighth embodiment will be described. Hereinafter, the description of the configuration common to the semiconductor device of any one of the first to sixth embodiments will be omitted.

In the semiconductor devices of the first to sixth embodiments, one amplifier circuit is constituted by a plurality of cells 20 (for example, FIG. 1 ) connected in parallel. In the semiconductor device of the eighth embodiment, a plurality of, for example, two amplifier circuits composed of a plurality of cells 20 connected in parallel are arranged on a common substrate 15 ( FIG. 3 ). Conductor protrusions 54 ( FIG. 3 , FIG. 11A ) are provided in each amplifying circuit. The two amplifier circuits are preferably arranged adjacent to each other in the direction (x direction) perpendicular to the arrangement direction of the cells 20 .

Next, the excellent effect of the eighth embodiment will be described. In the eighth embodiment, two amplifying circuits can be operated as, for example, differential amplifiers. By adopting the same configuration as that of the semiconductor device of any one of the first to sixth embodiments in each of the plurality of amplifier circuits, the damage resistance of the differential amplifier can be improved.

The above-mentioned embodiments are examples, and it is of course possible to partially replace or combine the configurations shown in different embodiments. Regarding the same function and effect brought about by the same configuration of a plurality of embodiments, it is not mentioned successively in each embodiment. Furthermore, this invention is not limited to the said Example. For example, those skilled in the art to which the present invention pertains understand that various changes, improvements, combinations, and the like are possible.

15: Substrate 20: unit 20A: End unit 20B: 1 unit other than end 21: bipolar transistor 21B: base layer 21BM: base mesa 21C: collector layer 21E: emitter layer 22: Base ballast resistor element 23: Input capacitor 25: Sub-collector layer 26A: top cover layer 26B: Contact layer 27:Alloyed area 30B: base electrode 30BC: base contact 30BF: base finger 30C: collector electrode 30E: Emitter electrode 31B: Base wiring 31C: collector wiring 31E: Emitter wiring 35, 36: interlayer insulating film 37: Protective film 40C: collector contact hole 40E: Emitter contact hole 41E: Emitter contact hole 42E: opening 50: Emitter common wiring 51: Collector common wiring 52: Base bias wiring 53: High-frequency signal input wiring 54: Conductor protrusion 54A: Bottom bump metal layer 54B: Cu pillar bump 54C: Solder layer 55: Conductor protrusion for grounding 56: Conductor protrusion for signal input and output 60:Semiconductor device 70:Module substrate 74:Pad 74A: The part with the widest pad width 75, 76: Pad 84: through hole 84A: The wide part of the through hole 85: through hole 94: External connection terminal 94A: The wide part of the external connection terminal 95: External connection terminal

[ Fig. 1 ] is an equivalent circuit diagram of the semiconductor device of the first embodiment. [ Fig. 2 ] is a schematic plan view of the semiconductor device of the first embodiment. [Fig. 3] is a sectional view at the point-chain line 3-3 in Fig. 2. [FIG. 4] It is a graph which shows the measurement result of the destruction boundary of the semiconductor device which made the resistance value of the base ballast resistance element the same in all cells. [ Fig. 5 ] is a schematic plan view of a semiconductor device according to a second embodiment. [Fig. 6] is a sectional view at the dot chain line 6-6 of Fig. 5. [ Fig. 7 ] is a schematic plan view of a semiconductor device according to a third embodiment. [ Fig. 8 ] is a schematic plan view of a semiconductor device according to a fourth embodiment. [ Fig. 9 ] is a schematic plan view of a semiconductor device according to a fifth embodiment. [FIG. 10A] is a diagram showing the layout of the main components of the semiconductor device included in the semiconductor module of the sixth embodiment in a plan view, and FIG. 10B is a diagram showing the layout of the main components of the module substrate in a top view. , FIGS. 10C and 10D are schematic cross-sectional views of the semiconductor module of the sixth embodiment. [FIG. 11A] is a diagram showing the arrangement of the main components of the semiconductor device included in the semiconductor module of the seventh embodiment in a plan view, and FIG. 11B is a diagram showing the arrangement of the main components of the module substrate in a plan view. , FIGS. 11C and 11D are schematic cross-sectional views of the semiconductor module of the seventh embodiment.

20: unit 20A: End unit 20B: 1 unit other than end 21: bipolar transistor 21BM: base mesa 22: Base ballast resistor element 23: Input capacitor 25: Sub-collector layer 30B: base electrode 30BC: base contact 30BF: base finger 30C: collector electrode 30E: Emitter electrode 31B: Base wiring 31C: collector wiring 31E: Emitter wiring 50: Emitter common wiring 51: Collector common wiring 52: Base bias wiring 53: High-frequency signal input wiring 54: Conductor protrusion

Claims (9)

A semiconductor device comprising: Substrate; A plurality of units of 3 or more are arranged side by side in the first direction on the above-mentioned substrate; and Conductor protrusions are arranged on the above-mentioned substrate and protrude in a direction away from the above-mentioned substrate; Each of the plurality of units above includes: a bipolar transistor comprising a collector layer, a base layer and an emitter layer; and a ballast resistance element connected to the bipolar transistor; The above-mentioned conductor protrusion is connected to the emitter layer of the above-mentioned bipolar transistor of the above-mentioned plurality of units; The above-mentioned bipolar transistors of the above-mentioned plurality of units are connected in parallel with each other; and Among the plurality of units, the resistance value of the ballast resistance element included in the first unit at the end is greater than the resistance value of the ballast resistance element included in at least one second unit other than the end. The semiconductor device according to claim 1, wherein, Each of the plurality of cells further includes an emitter electrode connected to the emitter layer of the bipolar transistor; and The emitter electrode has a shape that is long in a second direction perpendicular to the first direction in plan view, and the ratio of the length in the second direction of the emitter electrode to the width in the first direction of the emitter electrode is between all cells same. The semiconductor device according to claim 1 or 2, wherein, The conductor protrusion overlaps the bipolar transistors of the plurality of cells in a plan view, and has a shape long in the first direction, and at least a part of the protrusion overlapping the second cell has a width wider than that of the first cell in a plan view. At least a portion of the cell overlap has a narrow width. The semiconductor device according to claim 1 or 2, wherein, The conductor protrusions are separated in the first direction at a position where at least one of the second units is arranged. The semiconductor device according to claim 1 or 2, wherein, The plurality of conductor protrusions are arranged side by side in the first direction within the range from the unit at one end of the plurality of units to the unit at the other end, and the distribution density of the conductor protrusions is adjusted from the plurality of units described above. The two ends of the range of a unit decrease toward the center. The semiconductor device according to claim 1 or 2, wherein, The distance between the geometric center of the above-mentioned bipolar transistor of the above-mentioned first unit and the geometric center of the above-mentioned bipolar transistor of the unit adjacent to the above-mentioned first unit in the first direction is less than the above-mentioned first unit and includes the above-mentioned The distance between the geometric centers of the bipolar transistors of the two adjacent cells in the second cell in the first direction is wide. A semiconductor module, comprising: A semiconductor device according to any one of Claims 1 to 6; and The module substrate is flip-chip-mounted with the above-mentioned semiconductor device via the above-mentioned conductor protrusions. A semiconductor module, comprising: A semiconductor device comprising: a substrate, a plurality of units arranged side by side in a first direction on the substrate, and a conductor protrusion arranged on the substrate and protruding in a direction away from the substrate; and a module substrate, on which the above-mentioned semiconductor device is flip-chip mounted via the above-mentioned conductor protrusion; and Each of the plurality of units includes a bipolar transistor including a collector layer, a base layer, and an emitter layer; The above-mentioned bipolar transistors of the above-mentioned plurality of units are connected in parallel; The above-mentioned conductor protrusion overlaps the above-mentioned plurality of units when viewed from above, and is electrically connected to the emitter layer of the above-mentioned bipolar transistor of the above-mentioned plurality of units; and The above module substrates include: a through hole, which overlaps the above-mentioned conductor protrusion in plan view, is long in the above-mentioned first direction, and is electrically connected to the above-mentioned conductor protrusion; and The through-hole includes a portion wider than the width of the central portion at a portion offset from the central portion of the range where the plurality of cells are arranged in the above-mentioned first direction toward the end portion. A semiconductor module, comprising: A semiconductor device comprising: a substrate, a plurality of units arranged side by side in a first direction on the substrate, and a conductor protrusion arranged on the substrate and protruding in a direction away from the substrate; and A module substrate, on which the above-mentioned semiconductor device is flip-chip mounted via the above-mentioned conductor protrusion; Each of the plurality of units includes a bipolar transistor including a collector layer, a base layer, and an emitter layer; The above-mentioned bipolar transistors of the above-mentioned plurality of units are connected in parallel; The above-mentioned conductor protrusion overlaps the above-mentioned plurality of units when viewed from above, and is electrically connected to the emitter layer of the above-mentioned bipolar transistor of the above-mentioned plurality of units; and The above module substrates include: at least two through holes, which overlap with the above-mentioned conductor protrusion in plan view, are electrically connected to the above-mentioned conductor protrusion, and are arranged side by side in the above-mentioned first direction; and The above-mentioned through hole is not arranged in the central part of the range where the above-mentioned plurality of cells are arranged in the above-mentioned first direction.

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