TWI803204B - Memory device having merged active area and method for manufacturing the same - Google Patents

Abstract

The present application provides a memory device and method for manufacturing the same. The memory device includes a semiconductor substrate including an isolation structure and an active area surrounded by the isolation structure; a fuse gate structure disposed over the active area; a device gate structure disposed over the active area and adjacent to the fuse gate structure; and a contact plug coupled to the active area and extending away from the semiconductor substrate, wherein at least a portion of the active area is disposed under the device gate structure.

Description

Memory element with merged active area and its preparation method

This application claims priority from U.S. Patent Application Nos. 17/541,829 and 17/543,966 (i.e., with priority dates of "December 3, 2021" and "December 7, 2021"), the content of which is It is incorporated herein by reference in its entirety.

The present disclosure relates to a memory device and a manufacturing method thereof, in particular to a semiconductor device including a merged active area (AA) and a manufacturing method thereof.

Nonvolatile memory devices retain data even when their power is cut off. One type of non-volatile memory device is a one-time-programmable (OTP) memory device. Using the OTP memory device, the user can only program the OTP memory device once, and the data stored in the OTP memory device cannot be modified. The OTP memory device includes a fuse that is initially in a short state and is in an open state after being programmed. Signals are transmitted to the fuse through metal interconnection lines disposed on the semiconductor substrate.

However, the wiring of such metal interconnection constitutes an obstacle to increasing the wiring density of the memory device, so the reduction of the minimum feature size is limited. Accordingly, it is desirable to develop improvements that address related manufacturing challenges.

The above "prior art" description is only to provide background technology, and does not acknowledge that the above "prior art" description discloses the subject of this disclosure, and does not constitute the prior art of this disclosure, and any description of the above "prior art" shall not form part of this case.

An embodiment of the disclosure provides a memory device. The memory element includes a semiconductor substrate, the substrate includes an isolation structure and an active area surrounded by the isolation structure; a fuse gate structure is arranged on the active area; an element gate structure is arranged on the active area above and adjacent to the fuse gate structure; and a contact plug coupled to the active region and extending away from the semiconductor substrate, wherein the active region is disposed below the fuse gate structure and the device gate structure and cross with it.

In some embodiments, the active region extends between the contact plug and the fuse gate structure in a top view.

In some embodiments, the fuse gate structure is parallel to the device gate structure.

In some embodiments, the fuse gate structure and the device gate structure extend vertically on the active region.

In some embodiments, the active region is substantially perpendicular to the fuse gate structure and the device gate structure when viewed from a top view.

In some embodiments, the device gate structure is disposed between the fuse gate structure and the contact plug.

In some embodiments, a current can flow from the contact plug through the active region to the fuse gate structure.

In some embodiments, the fuse gate structure includes a fuse gate dielectric disposed on the semiconductor substrate and a fuse gate electrode disposed on the fuse gate dielectric.

In some embodiments, the fuse gate dielectric is at least partially disposed on the active region.

In some embodiments, the fuse gate electrode includes polysilicon.

In some embodiments, the device gate structure includes a device gate dielectric disposed on the semiconductor substrate and a device gate electrode disposed on the device gate dielectric.

In some embodiments, the device gate dielectric is at least partially disposed on the active region.

In some embodiments, the device gate electrode includes polysilicon.

In some embodiments, the memory device further includes a metal component disposed on and coupled to the contact plug.

In some embodiments, the space above the fuse gate structure is free of the metal feature.

In some embodiments, the metal member is electrically connected to the fuse gate structure through the active region and the contact plug.

Another embodiment of the disclosure provides a memory device. The memory element includes a substrate, the substrate includes an isolation structure and a plurality of active areas surrounded by the isolation structure; a fuse gate structure is arranged on and crosses the plurality of active areas; an element gate a structure disposed on and intersecting the plurality of active regions and adjacent to the fuse gate structure; and a plurality of contact plugs correspondingly coupled to the plurality of active regions and extending away from the substrate, wherein the plurality of active regions Each of the plurality of active regions is disposed at least partially under the fuse gate structure and the device gate structure.

In some embodiments, the plurality of active regions are separated from each other by the isolation structure.

In some embodiments, the plurality of contact plugs are aligned with each other.

In some embodiments, the plurality of contact plugs are separated from each other by a gate dielectric layer disposed on the substrate.

In some embodiments, the memory device further includes a metal member disposed on the gate dielectric layer and coupled to one of the plurality of contact plugs.

In some embodiments, the fuse gate structure and the device gate structure are parallel to each other and cross over the plurality of active regions.

In some embodiments, a signal can be transmitted from one of the plurality of contact plugs to the fuse gate structure through one of the plurality of active regions.

In some embodiments, the substrate is semiconductive.

Another embodiment of the disclosure provides a method for manufacturing a memory device. The preparation method includes the following steps: providing a substrate, including an isolation structure and an active area surrounded by the isolation structure; forming a fuse gate structure on the active area; forming an element gate structure adjacent to the pole structure; and forming a contact plug coupled with the active region and extending away from the substrate, wherein the fuse gate structure is parallel to the element gate structure and on the active region form.

In some embodiments, the formation of the fuse gate structure and the formation of the device gate electrode structure are performed separately and sequentially.

In some embodiments, the formation of the fuse gate structure is performed before the formation of the device gate structure.

In some embodiments, the device gate structure is formed before the fuse gate structure is formed.

In some embodiments, the contact plug is formed by electroplating.

In some embodiments, the manufacturing method further includes disposing a gate dielectric layer on the substrate.

In some embodiments, the fuse gate structure and the device gate structure are surrounded by the gate dielectric layer.

In some embodiments, the contact plug is formed after disposing the gate dielectric layer.

In some embodiments, the contact plug is formed by removing a portion of the gate dielectric layer to form a groove, and filling the groove with a conductive material.

In some embodiments, the portion of the gate dielectric layer is removed by etching.

In some embodiments, the manufacturing method further includes forming a metal member on the contact plug.

In a word, since the signal can be transmitted through the active area on the substrate instead of the metal interconnection on the substrate, the area occupied by the metal interconnection can be significantly reduced or even eliminated. In addition, since the element gate structure can be formed adjacent to the fuse gate structure, the area occupied by the element gate structure can also be greatly reduced. Therefore, the overall size of the memory device can be further reduced.

The technical features and advantages of the present disclosure have been broadly summarized above, so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art of the present disclosure should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the disclosure defined by the appended claims.

The following disclosure provides a number of different embodiments or examples for implementing different features of the disclosure. Specific embodiments or examples of components and arrangements are set forth below to simplify the disclosure. Of course, these are examples only and are not intended to be limiting. For example, the description below that a first feature is formed "over" or "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which Embodiments in which additional features may be formed within the range of the first feature and the second feature, so that the first feature may not be in direct contact with the second feature.

Furthermore, parameter words and/or letters are repeated in some embodiments for the sake of brevity and clarity, which in themselves do not determine the relationship between some embodiments and/or configurations discussed.

In addition, for ease of description, spatial relative terms such as "under", "under", "below", "upper", "above", "above" and other spatial relative terms may be used herein to describe an element shown in the figure. Or the relationship of a feature to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation depicted in the figures. The elements may be at other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein translated accordingly.

FIG. 1 is a cross-sectional view illustrating the top surface of a memory device 100 according to some embodiments of the present disclosure. FIG. 2 is a cross-sectional view illustrating a side surface of the memory device 100 taken along line AA' in FIG. 1 . FIG. 3 is a cross-sectional view illustrating the side of the memory device 100 taken along line BB' in FIG. 1 . In some embodiments, the memory device 100 includes unit cells arranged along rows and columns. In some embodiments, the memory device 100 is a fuse type memory device.

In some embodiments, the memory device 100 includes a semiconductor substrate 101 . In some embodiments, the semiconductor substrate 101 is semiconductive in nature. In some embodiments, the semiconductor substrate 101 is a semiconductor wafer (eg, a silicon wafer) or a semiconductor-on-insulator (SOI) wafer (eg, a silicon-on-insulator wafer). In some embodiments, the semiconductor substrate 101 is a silicon substrate.

In some embodiments, the semiconductor substrate 101 includes an isolation structure 101a and an active area (AA) 101b surrounded by the isolation structure 101a. In some embodiments, the fabrication technology of the isolation structure 101 a is an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, etc. or a combination thereof.

In some embodiments, the isolation structure 101 a is a trench isolation structure extending from the top surface of the semiconductor substrate 101 into the semiconductor substrate 101 . In some embodiments, the depth of the isolation structure 101a is substantially greater than, equal to, or smaller than the depth of the active region 101b. In some embodiments, the isolation structure 101a is a shallow trench isolation (STI). In some embodiments, the isolation structure 101a defines the boundary of the active region 101b.

In some embodiments, the active region 101b is completely surrounded by the isolation structure 101a. In some embodiments, the semiconductor substrate 101 includes some active regions 101b disposed on the semiconductor substrate 101 . In some embodiments, each active region 101b is surrounded by the isolation structure 101a, so the active regions 101b are separated by the isolation structure 101a and electrically isolated from each other. In some embodiments, the active regions 101b are arranged along a row.

In some embodiments, the active region 101 b is a doped region in the semiconductor substrate 101 . In some embodiments, the active region 101 b extends horizontally on or below the top surface of the semiconductor substrate 101 . In some embodiments, each active region 101b includes the same type of dopant. In some embodiments, each active region 101b includes a different type of dopant than the other active regions 101b. In some embodiments, each active region 101b has the same conductivity type. In some embodiments, the active region 101b includes N-type dopants.

In some embodiments, the memory device 100 includes a fuse gate structure 102 disposed on a semiconductor substrate 101 . In some embodiments, the fuse gate structure 102 is disposed on the active region 101 b of the semiconductor substrate 101 . In some embodiments, the fuse gate structure 102 is electrically connected to a fuse bit line. In some embodiments, the fuse gate structure 102 may be blown when a breakdown voltage is applied. In some embodiments, the fuse gate structure 102 is disposed on and crosses the active region 101b. In some embodiments, the fuse gate structure 102 is substantially perpendicular to the active region 101b from a top view.

In some embodiments, the fuse gate structure 102 includes a fuse gate dielectric 102a and a fuse gate electrode 102b disposed on the fuse gate dielectric 102a. In some embodiments, the fuse gate dielectric 102 a is disposed on the semiconductor substrate 101 . In some embodiments, the fuse gate dielectric 102a is in contact with the active region 101b. The fuse gate dielectric 102a is at least partially disposed on the active region 101b. In some embodiments, the fuse gate dielectric 102a includes an oxide or a metal-containing oxide. In some embodiments, the fuse gate dielectric 102a includes silicon oxide. In some embodiments, the fuse gate dielectric 102a may be broken or damaged during dielectric breakdown.

In some embodiments, the fuse gate electrode 102b is disposed on the fuse gate dielectric 102a. In some embodiments, the fuse gate electrode 102b includes polysilicon, silicide, or the like. In some embodiments, a mask layer is disposed between the fuse gate dielectric 102a and the fuse gate electrode 102b. In some embodiments, the mask layer includes silicon nitride, silicon oxynitride, etc. or a combination thereof.

In some embodiments, the memory device 100 includes a device gate structure 103 adjacent to the fuse gate structure 102 . The device gate structure 103 is disposed on the semiconductor substrate 101 . In some embodiments, the device gate structure 103 is disposed on the active region 101 b of the semiconductor substrate 101 . In some embodiments, the device gate structure 103 is parallel to the fuse gate structure 102 . In some embodiments, the device gate structure 103 is disposed on and crosses the active region 101b. In some embodiments, viewed from a top view, the device gate structure 103 is substantially perpendicular to the active region 101b.

In some embodiments, the device gate structure 103 includes a device gate dielectric 103a and a device gate electrode 103b disposed on the device gate dielectric 103a. In some embodiments, the device gate dielectric 103 a is disposed on the semiconductor substrate 101 . In some embodiments, the device gate dielectric 103a is in contact with the active region 101b. The device gate dielectric 103a is at least partially disposed on the active region 101b. In some embodiments, the device gate dielectric 103a includes an oxide or a metal-containing oxide. In some embodiments, the device gate dielectric 103a includes silicon oxide.

In some embodiments, the device gate electrode 103b is disposed on the device gate dielectric 103a. In some embodiments, the device gate electrode 310b includes polysilicon, silicide, or the like. In some embodiments, a mask layer is disposed between the device gate dielectric 310a and the device gate electrode 310b. In some embodiments, the mask layer includes silicon nitride, silicon oxynitride, etc. or a combination thereof.

In some embodiments, the active region 101b is disposed under and intersects the fuse gate structure 102 and the device gate structure 103 . In some embodiments, the active region 101b is disposed under the fuse gate structure 102 and the device gate structure 103 and extends between the fuse gate structure 102 and the device gate structure 103 in a top view. A portion of the active region 101b under the fuse gate structure 102 and a portion of the active region 101b under the device gate structure 103 merge.

In some embodiments, the fuse gate structure 102 and the device gate structure 103 extend vertically on the active region 101b. From a top view, the active region 101b is substantially perpendicular to the fuse gate structure 102 and the device gate structure 103 . In some embodiments, the fuse gate structure 102 is parallel to the device gate structure 103 and crosses the active region 101b. Each active region 101b is at least partially disposed under the fuse gate structure 102 and the device gate structure 103 .

In some embodiments, the memory device 100 includes contact plugs 104 disposed on the semiconductor substrate 101 . In some embodiments, the contact plug 104 is coupled to and contacts the active region 101 b of the semiconductor substrate 101 . In some embodiments, the memory device 100 includes some contact plugs 104 disposed on the active region 101b and correspondingly coupled thereto.

In some embodiments, the contact plug 104 extends from the active region 101 b away from the semiconductor substrate 101 . In some embodiments, the active region 101 b extends between the contact plug 104 and the fuse gate structure 102 or between the contact plug 104 and the device gate structure 103 as viewed from a top view. In some embodiments, the device gate structure 103 is disposed between the fuse gate structure 102 and the contact plug 104 . In some embodiments, the contact plugs 104 are aligned with each other. In some embodiments, the contact plugs 104 are arranged vertically.

In some embodiments, the contact plug 104 includes a conductive material such as copper, silver, gold, or the like. In some embodiments, the contact plug 104 has a tapered shape. In some embodiments, as shown in FIG. 3 , there is no device gate structure 103 in the region between two horizontally arranged contact plugs.

In some embodiments, a conductive path is formed along the active region 101 b and between the contact plug 104 and the fuse gate structure 102 . Current can flow from the contact plug 104 to the fuse gate structure 102 through the active region 101b. In some embodiments, a signal can be transmitted from the contact plug 104 to the fuse gate structure 102 through the active region 101b. In some embodiments, when a voltage is applied from the contact plug 104 through the active region 101b to the fuse gate structure 102, the conductive path is formed on the fuse gate dielectric 102a.

In some embodiments, as shown in FIG. 4 and FIG. 5 , a gate dielectric layer 105 is disposed on the semiconductor substrate 101, and the gate dielectric layer 105 surrounds the fuse gate structure 102, the element gate structure 103 and contact plug 104 . In some embodiments, the gate dielectric layer 105 covers the fuse gate structure 102 and the device gate structure 103 . In some embodiments, the top surface of the contact plug 104 is exposed through the gate dielectric layer 105 .

In some embodiments, the fuse gate structure 102 , the device gate structure 103 and the contact plug 104 are isolated from each other by the gate dielectric layer 105 . In some embodiments, the contact plugs 104 are separated from each other by a gate dielectric layer 105 . In some embodiments, the gate dielectric layer 105 includes a gate dielectric material such as oxide, polymer or the like.

In some embodiments, as shown in FIGS. 4 and 5 , the metal member 106 is disposed on and coupled to the contact plug 104 . In some embodiments, the metal member 106 is disposed on the gate dielectric layer 105 . In some embodiments, a portion of the metal member 106 is in contact with the gate dielectric layer 105 . In some embodiments, the metal member 106 is electrically connected to the fuse gate structure 102 through the active region 101 b and the contact plug 104 . In some embodiments, the space above the fuse gate structure 102 is free of metal features 106 . In some embodiments, metal member 106 includes a conductive material, such as copper, silver, gold, or the like.

FIG. 6 is a flowchart illustrating a method S200 of manufacturing the memory device 100 according to some embodiments of the present disclosure. 7 to 20 are cross-sectional views illustrating intermediate stages of fabrication of the memory device 100 according to some embodiments of the present disclosure.

For the stages shown in FIG. 7 to FIG. 20 , reference may also be made to the description of the flow chart in FIG. 6 . In the following discussion, the fabrication stages of FIGS. 7-20 are discussed with reference to the process steps shown in FIG. 6 . The preparation method S200 includes some operations, and the description and illustration should not be considered as limiting the sequence of operations. The preparation method S200 includes some steps (S201, S202, S203 and S204).

Referring to FIG. 7 , a semiconductor substrate 101 is provided according to step S201 in FIG. 6 . In some embodiments, the semiconductor substrate 101 is semiconductive. In some embodiments, the semiconductor substrate 101 is a silicon substrate.

Referring to FIG. 8, a semiconductor substrate 101 includes an isolation structure 101a. In some embodiments, the isolation structure 101 a is formed by forming grooves on the top surface of the semiconductor substrate 101 through a lithography process and an etching process (eg, an anisotropic etching process). Then, an insulating material is filled into the groove by a deposition process, such as a chemical vapor deposition (CVD) process.

In addition, a part of the insulating material on the top surface of the semiconductor substrate 101 is removed through a planarization process, and the remaining part of the insulating material forms the isolation structure 101a. For example, the planarization process may include a grinding process, an etching process, or a combination thereof.

Referring to FIG. 9, a semiconductor substrate 101 includes an active region 101b. In some embodiments, the active region 101b is formed after the isolation structure 101a is formed. In some embodiments, isolation structures 101a define the boundaries of subsequently formed active regions 101b. In some embodiments, the active region 101b is formed and surrounded by the isolation structure 101a.

In some embodiments, the active region 101b is formed through an ion implantation process or an ion doping process. In the ion implantation process, the isolation structure 101a is used as a mask pattern. In another embodiment, the ion implantation process is performed before the formation of the isolation structure 101a. In such an alternative embodiment, the well region is formed by an ion implantation process, and then the isolation structure 101a is formed in the well region. The part of the well region laterally surrounded by the isolation structures 101a forms the active region 101b. In some embodiments, the semiconductor substrate 101 shown in FIG. 9 is similar to the semiconductor substrate 101 described above or the arrangement shown in any one of FIGS. 1-5 .

Referring to FIG. 10 , according to step S202 in FIG. 6 , a fuse gate structure 102 is formed on the active region 101 b of the semiconductor substrate 101 . In some embodiments, the fuse gate structure 102 is formed by forming a fuse gate dielectric 102a on the active region 101b, and then forming a fuse gate electrode 102b on the fuse gate dielectric 102a.

In some embodiments, the fuse gate dielectric 102a is formed by an oxidation process or a deposition process (such as a CVD process). In some embodiments, the fuse gate electrode 102b is formed by a deposition process, such as a CVD process. In some embodiments, the fuse gate structure 102 shown in FIG. 10 has an arrangement similar to the fuse gate structure 102 described above or shown in any one of FIGS. 1-5 .

Referring to FIG. 11 , according to step S203 in FIG. 6 , an element gate structure 103 is formed on the active region 101 b of the semiconductor substrate 101 . In some embodiments, the device gate structure 103 is formed by forming a device gate dielectric 103a on the active region 101b, and then forming a device gate electrode 103b on the device gate dielectric 103a.

In some embodiments, the device gate dielectric 103a is formed through an oxidation process or a deposition process, such as a CVD process. In some embodiments, the device gate electrode 103b is formed through a deposition process, such as a CVD process. In some embodiments, the device gate electrode structure 103 shown in FIG. 11 has an arrangement similar to the device gate electrode structure 103 described above or shown in any one of FIGS. 1-5 .

In some embodiments, the formation of the fuse gate structure 102 (step S202 ) and the formation of the device gate structure 103 (step S203 ) are performed separately and sequentially. In some embodiments as shown in FIGS. 10 and 12 , the fuse gate structure 102 is formed before the device gate structure 103 is formed. In some embodiments as shown in FIGS. 11 and 12 , the device gate structure 103 is formed before the fuse gate structure 102 is formed.

In some embodiments, as shown in FIG. 12 , the fuse gate structure 102 and the device gate structure 103 are formed simultaneously. In some embodiments, the fuse gate structure 102 is adjacent to the device gate structure 103 . In some embodiments, the fuse gate structure 102 is parallel to the device gate structure 103 and formed on the active region 101b.

Referring to FIGS. 13 to 17 , contact plugs 104 are formed according to step S204 in FIG. 6 . In some embodiments, the contact plug 104 is coupled with the active region 101 b and extends away from the semiconductor substrate 101 . In some embodiments, as shown in FIG. 13 , the gate dielectric layer 105 is disposed on the semiconductor substrate 101 through a deposition process, such as a CVD process.

In some embodiments, the fuse gate structure 102 and the device gate structure 103 are surrounded by a gate dielectric layer 105 . In some embodiments, the gate dielectric layer 105 covers the top surface of the semiconductor substrate 101 . The active region 101b is also covered by the gate dielectric layer 105 .

After the gate dielectric layer 105 is disposed on the semiconductor substrate 101 , as shown in FIG. 14 , a first patterned photoresist 107 is disposed on the gate dielectric layer 105 . In some embodiments, the first patterned photoresist 107 includes a first opening 107 a to expose a portion of the gate dielectric layer 105 .

In some embodiments, the first patterned photoresist 107 is formed by disposing a photoresist material on the gate dielectric layer 105, covering some parts of the photoresist material, and then removing the exposed part of the photoresist material, so that The photoresist material forms the first patterned photoresist 107 . In some embodiments as shown in FIG. 15 , the portion of the gate dielectric layer 105 exposed through the first patterned photoresist 107 is removed by etching or any other suitable process.

After removing the exposed portion of the gate dielectric layer 105, as shown in FIG. 15, a groove 105a is formed. In some embodiments, the groove 105a has a rectangular or tapered shape. In some embodiments, the groove 105a extends through the gate dielectric layer 105 to expose a portion of the active region 101b. After the groove 105a is formed, as shown in FIG. 16 , the first patterned photoresist 107 is removed by etching, stripping or any other suitable process.

In some embodiments, the contact plug 104 is formed after disposing the gate dielectric layer 105 . After forming the groove 105a, a conductive material fills the groove 105a to form the contact plug 104, as shown in FIG. 17 . In some embodiments, the contact plugs 104 are formed by electroplating or any other suitable process. In some embodiments, the contact plug 104 shown in FIG. 17 has an arrangement similar to that of the contact plug 104 described above or shown in any one of FIGS. 1-5 .

After the contact plug 104 is formed, as shown in FIG. 18 , a second patterned photoresist 108 is disposed on the gate dielectric layer 105 . In some embodiments, the second patterned photoresist 108 includes a second opening 108 a to expose a part of the contact plug 104 and the gate dielectric layer 105 .

In some embodiments, the second patterned photoresist 108 is formed by disposing a photoresist material on the gate dielectric layer 105, covering some parts of the photoresist material, and then removing the exposed part of the photoresist material, so that The photoresist material forms the second patterned photoresist 108 .

In some embodiments, as shown in FIG. 19 , a metal member 106 is formed on the contact plug 104 and the gate dielectric layer 105 and within the second opening 108 a. In some embodiments, the metal member 106 is formed by electroplating or any other suitable process. After the metal member 106 is formed, as shown in FIG. 20 , the second patterned photoresist 108 is removed by etching, stripping or any other suitable process. In some embodiments, the metal member 106 shown in FIG. 20 has an arrangement similar to the metal member 106 described above or the members shown in any one of FIGS. 4-5 .

An embodiment of the present disclosure provides a memory device. The memory element includes a semiconductor substrate, the substrate includes an isolation structure and an active area surrounded by the isolation structure; a fuse gate structure is arranged on the active area; an element gate structure is arranged on the active area and adjacent to the fuse gate structure; and a contact plug coupled with the active region and extending away from the semiconductor substrate, wherein the active region is disposed between the fuse gate structure and the device gate structure down and cross it.

In another embodiment of the present disclosure, a memory device is provided. The memory element includes a substrate, the substrate includes an isolation structure and a plurality of active regions surrounded by the isolation structure; a fuse gate structure is arranged on and intersects with the plurality of active regions; an element gate structure , disposed on and intersecting the plurality of active regions and adjacent to the fuse gate structure; and a plurality of contact plugs, correspondingly coupled with the plurality of active regions and extending away from the substrate, wherein the plurality of Each of the active regions is disposed at least partially under the fuse gate structure and the device gate structure.

In another embodiment of the present disclosure, a method for manufacturing a memory device is provided. The preparation method includes the following steps: providing a substrate, including an isolation structure and an active area surrounded by the isolation structure; forming a fuse gate structure on the active area; forming an element gate structure adjacent to the pole structure; and forming a contact plug coupled with the active region and away from the substrate, wherein the fuse gate structure is parallel to the element gate structure and formed on the active region .

In a word, since the signal can be transmitted through the active area on the substrate instead of the metal interconnection on the substrate, the area occupied by the metal interconnection can be significantly reduced or even eliminated. In addition, since the element gate structure can be formed adjacent to the fuse gate structure, the area occupied by the element gate structure can also be greatly reduced. Therefore, the overall size of the memory device can be further reduced.

Although the present disclosure and its advantages have been described in detail, it should be understood that other changes, substitutions and substitutions can be made hereto without departing from the spirit and scope of the present disclosure as defined by the patent claims disclosed. For example, many of the processes described above can be performed in different ways and replaced by other processes or combinations thereof.

Furthermore, the scope of the disclosure is not limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure of this disclosure that they can use existing or future developed processes, machinery, manufacturing, A composition of matter, means, method, or step. Accordingly, such processes, machinery, manufacture, material composition, means, methods, or steps are included in the scope of the patent disclosure of this disclosure.

100: memory components 101:Semiconductor substrate 101a: Isolation structure 101b: Active Area (AA) 102: Fuse gate structure 102a: Fuse gate dielectric 102b: Fuse gate electrode 103: Component gate structure 103a: Component gate dielectric 103b: element gate electrode 104: contact plug 105: gate dielectric layer 105a: Groove 106: metal components 107: The first patterned photoresist 107a: first opening 108: Second patterned photoresist 108a: second opening S200: Preparation method S201: step S202: step S203: step S204: step

The disclosure content of the present application can be understood more fully when the drawings are combined with the embodiments and the patent scope of the application. The same reference numerals in the drawings refer to the same components. FIG. 1 is a cross-sectional view illustrating the top surface of a memory device according to some embodiments of the present disclosure. FIG. 2 is a cross-sectional view illustrating the side of a memory device taken along line AA' in FIG. 1 of an embodiment. FIG. 3 is a cross-sectional view illustrating the side of a memory device taken along line BB' in FIG. 1 of an embodiment. FIG. 4 is a cross-sectional view illustrating another embodiment of the side of the memory device taken along line AA' in FIG. 1 . FIG. 5 is a cross-sectional view illustrating another embodiment of the side of the memory device taken along line BB' in FIG. 1 . FIG. 6 is a flowchart illustrating a method for fabricating a memory device according to some embodiments of the present disclosure. 7 to 20 are cross-sectional views illustrating intermediate stages of fabrication of memory devices according to some embodiments of the present disclosure.

101:Semiconductor substrate

101a: Isolation structure

101b: Active Area (AA)

102: Fuse gate structure

102a: Fuse gate dielectric

102b: Fuse gate electrode

103: Component gate structure

103a: Component gate dielectric

103b: element gate electrode

104: contact plug

105: gate dielectric layer

106: metal components

Claims (31)

A memory element, comprising: a semiconductor substrate, including an isolation structure and an active area surrounded by the isolation structure; a fuse gate structure, arranged on each of the active areas and intersecting with it; an element gate a structure disposed on and crossing each of the active regions and adjacent to the fuse gate structure; and a contact plug coupled with the active regions and extending away from the semiconductor substrate. The memory device as claimed in claim 1, wherein the active region extends between the contact plug and the fuse gate structure in a top view. The memory device as claimed in claim 1, wherein the fuse gate structure is parallel to the device gate structure. The memory device of claim 1, wherein the fuse gate structure and the device gate structure extend vertically on the active region. The memory device as claimed in claim 1, wherein the active region is substantially perpendicular to the fuse gate structure and the device gate structure when viewed from a top view. The memory device as claimed in claim 1, wherein the device gate structure is disposed between the fuse gate structure and the contact plug. The memory device as claimed in claim 1, wherein a current can flow from the contact plug through the active region to the fuse gate structure. The memory element as claimed in claim 1, wherein the fuse gate structure comprises a fuse gate dielectric disposed on the semiconductor substrate, and a fuse disposed on the fuse gate dielectric Wire gate electrode. The memory device as claimed in claim 8, wherein the fuse gate dielectric is at least partially disposed on the active area. The memory element as claimed in claim 1, wherein the element gate structure includes an element gate dielectric disposed on the semiconductor substrate, and an element gate electrode disposed on the element gate dielectric . The memory device of claim 10, wherein the device gate dielectric is at least partially disposed on the active region. The memory device according to claim 1, further comprising a metal member disposed on and coupled to the contact plug. The memory device of claim 12, wherein the region on the fuse gate structure does not contain metal components. The memory device as claimed in claim 12, wherein the metal member is electrically connected to the fuse gate structure through the active area and the contact plug. A memory element, comprising: a substrate including an isolation structure and a plurality of active regions surrounded by the isolation structure; a fuse gate structure arranged on and crossing the plurality of active regions; an element gate a structure configured on and crossing the plurality of active regions, wherein the element gate structure is adjacent to the fuse gate structure; and a plurality of contact plugs are correspondingly connected to the plurality of active regions, and extending away from the substrate; wherein each of the plurality of active regions is at least partially disposed under the fuse gate structure and the device gate structure. The memory device according to claim 15, wherein the plurality of active areas are separated from each other by the isolation structure. The memory device as claimed in claim 15, wherein the plurality of contact plugs are aligned with each other. The memory device as claimed in claim 15, wherein the plurality of contact plugs are separated from each other by a gate dielectric layer disposed on the substrate. The memory element as claimed in claim 15, wherein the fuse gate structure and the element gate The structures are parallel to each other and cross on each of the active regions. The memory device according to claim 15, wherein a signal can be transmitted from one of the plurality of contact plugs to the fuse gate structure through one of the plurality of active regions. A method for preparing a memory element, comprising: providing a substrate, including an isolation structure and an active area surrounded by the isolation structure; forming a fuse gate structure on the active area; a fuse gate structure adjacent to an element gate structure; and a contact plug coupled to the active region and extending away from the substrate; wherein the fuse gate structure is parallel to the element gate structure and at the formed on the active zone. The manufacturing method as claimed in claim 21, wherein the formation of the fuse gate structure and the formation of the element gate structure are performed separately and sequentially. The manufacturing method as claimed in claim 21, wherein the formation of the fuse gate structure is performed before the formation of the device gate structure. The manufacturing method as claimed in claim 21, wherein the element gate structure is formed before the fuse gate structure is formed. The manufacturing method as claimed in claim 21, wherein the contact plug is formed by electroplating. The preparation method according to claim 21, further comprising disposing a gate dielectric layer on the substrate. The manufacturing method as claimed in claim 26, wherein the fuse gate structure and the element gate structure are surrounded by the gate dielectric layer. The manufacturing method as claimed in claim 26, wherein the contact plug is formed after disposing the gate dielectric layer. The manufacturing method as claimed in claim 26, wherein the contact plug is formed by removing a part of the gate dielectric layer to form a groove, and filling the groove with a conductive material. The method of claim 29, wherein the portion of the gate dielectric layer is removed by etching. The manufacturing method as claimed in claim 21, further comprising forming a metal member on the contact plug.

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