TWI802431B - Memory structure - Google Patents

Abstract

A memory structure including a substrate and at least one memory cell is provided. The memory cell is located on the substrate. The memory cell includes the following components. A first conductive line, a first conductive layer, a second conductive layer, and the second conductive line are sequentially stacked. The first conductive line and the first conductive layer are electrically insulated from each other. The first conductive layer and the second conductive layer are electrically insulated from each other. The second conductive layer and the second conductive line are electrically insulated from each other. The first conductive line, the first conductive layer, the second conductive layer, and the second conductive line are located on a first side of a channel layer. The first conductive line and the second conductive line are connected to the channel layer. The first conductive layer and the second conductive layer are electrically insulated from the channel layer. A first charge storage layer is located between the first conductive layer and the channel layer. A second charge storage layer is located between the second conductive layer and the channel layer.

Description

memory structure

The present invention relates to a semiconductor structure, and more particularly to a memory structure.

Since non-volatile memory (such as flash memory) can perform operations such as storing, reading, and erasing data multiple times, and has the function that when the power supply is interrupted, the stored data will not be lost. Due to the advantages of non-volatile memory, short data access time, and low power consumption, non-volatile memory has become a memory widely used in personal computers and electronic devices. However, how to increase the density of memory cells is the goal of continuous efforts.

The invention provides a memory structure, which is beneficial to increase the density of memory cells.

The invention proposes a memory structure, including a substrate and at least one memory cell. Memory cells are located on the substrate. The memory cell includes a first wire, a first conductive layer, a second conductive layer, a second wire, a channel layer, a first charge storage layer and a second charge storage layer. The first wire, the first conductive layer, the second conductive layer and the second wire are stacked in sequence. The first wire and the first conductive layer are electrically insulated from each other. The first conductive layer and the second conductive layer are electrically insulated from each other. The second conductive layer and the second wire are electrically insulated from each other. The first wire, the first conductive layer, the second conductive layer and the second wire are located on the first side of the channel layer. The first wire and the second wire are connected to the channel layer. The first conductive layer and the second conductive layer are electrically insulated from the channel layer. The first charge storage layer is located between the first conductive layer and the channel layer. The second charge storage layer is located between the second conductive layer and the channel layer.

According to an embodiment of the present invention, in the above memory structure, the memory structure may be a 3D AND flash memory (3D AND flash memory) structure.

According to an embodiment of the present invention, in the above memory structure, a plurality of memory cells can be stacked away from the base.

According to an embodiment of the present invention, in the above memory structure, two adjacent memory cells stacked in a direction away from the substrate may share the second wire.

According to an embodiment of the present invention, in the above memory structure, components in two adjacent memory cells that share the second wire may have a symmetrical configuration relationship.

According to an embodiment of the present invention, the above memory structure may further include a first selection transistor and a second selection transistor. The first selection transistor is electrically connected to one end of the first wire. The second selection transistor is electrically connected to the other end of the first wire.

According to an embodiment of the present invention, in the above memory structure, the first wire can be located between the first selection transistor and the second selection transistor.

According to an embodiment of the present invention, the above memory structure may further include a third selection transistor and a fourth selection transistor. The third selection transistor is electrically connected to one end of the second wire. The fourth selection transistor is electrically connected to the other end of the second wire.

According to an embodiment of the present invention, in the above memory structure, the second wire can be located between the third selection transistor and the fourth selection transistor.

According to an embodiment of the present invention, the above memory structure may further include a plurality of bit lines. The first selection transistor and the third selection transistor are electrically connected to different bit lines.

According to an embodiment of the present invention, the above memory structure may further include a source line. The second selection transistor and the fourth selection transistor are electrically connected to the same source line.

According to an embodiment of the present invention, the above memory structure may further include at least one word line. The first conductive layer and the second conductive layer in the same memory cell can be electrically connected to the same word line.

According to an embodiment of the present invention, in the above memory structure, two adjacent memory cells stacked in a direction away from the substrate can be electrically connected to different word lines.

According to an embodiment of the present invention, in the above memory structure, the memory cells may further include a dielectric layer. The dielectric layer is located between the first wire and the first conductive layer.

According to an embodiment of the present invention, in the above memory structure, the memory cells may further include a dielectric layer. The dielectric layer is located between the first conductive layer and the second conductive layer.

According to an embodiment of the present invention, in the above memory structure, the memory cells may further include a dielectric layer. The dielectric layer is located between the second conductive layer and the second wire.

According to an embodiment of the present invention, in the above memory structure, the memory cell may further include a first dielectric layer and a second dielectric layer. The first dielectric layer is located between the first charge storage layer and the channel layer. The second dielectric layer is located between the first charge storage layer and the first conductive layer.

According to an embodiment of the present invention, in the above memory structure, the memory cell may further include a first dielectric layer and a second dielectric layer. The first dielectric layer is located between the second charge storage layer and the channel layer. The second dielectric layer is located between the second charge storage layer and the second conductive layer.

According to an embodiment of the present invention, the above memory structure may further include dielectric pillars. The dielectric post is located on the second side of the channel layer. The first side and the second side may be opposite sides.

According to an embodiment of the present invention, in the above memory structure, the channel layer may surround the dielectric pillar.

Based on the above, in the memory structure proposed by the present invention, the memory cell includes a first wire, a first conductive layer, a second conductive layer, a second wire, a channel layer, a first charge storage layer and a second charge storage layer, Therefore, the memory cell can be a twin bit cell, and random access can be performed on the memory cell. In some embodiments, when operating on a bit in the memory cell, the first wire can be used as a local bit line, and the second wire can be used as a local source line. ). In some embodiments, the first wire can be used as a local source line and the second wire can be used as a local bit line when operating on another bit in the memory cell. In addition, since the two bits in the memory cell share the local bit line and the local source line, it is beneficial to increase the memory cell density when stacking multiple memory cells.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

Embodiments are listed below and described in detail with accompanying drawings, but the provided embodiments are not intended to limit the scope of the present invention. In order to facilitate understanding, the same components will be described with the same symbols in the following description. In addition, the drawings are for illustration purposes only and are not drawn to original scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a schematic circuit diagram of a memory structure according to some embodiments of the present invention. FIG. 2 is a cross-sectional view of the memory cell in FIG. 1 .

Please refer to FIG. 1 and FIG. 2 , the memory structure 10 includes a substrate 100 and at least one memory cell MC. In some embodiments, the memory structure 10 can be a non-volatile memory, such as a flash memory. In some embodiments, the memory structure 10 may be a three-dimensional NAND flash memory structure. The substrate 100 can be a semiconductor substrate, such as a silicon substrate. In this embodiment, the number of memory cells MC is multiple as an example, but the number of memory cells MC is not limited to the number in the figure. In addition, each memory cell MC can operate independently.

The memory cells MC are located on the substrate 100 . The memory cell MC includes a wire 102 , a conductive layer 104 , a conductive layer 106 , a wire 108 , a channel layer 110 , a charge storage layer 112 and a charge storage layer 114 . The wire 102 , the conductive layer 104 , the conductive layer 106 and the wire 108 are stacked in sequence. The wire 102 and the conductive layer 104 are electrically insulated from each other. The conductive layer 104 and the conductive layer 106 are electrically insulated from each other. The conductive layer 106 and the wire 108 are electrically insulated from each other.

In some embodiments, the wire 102 can be used as a local bit line or a local source line. The material of the wire 102 is, for example, doped polysilicon. In some embodiments, the conductive layer 104 can be used as a word line. The material of the conductive layer 104 is, for example, tungsten. In some embodiments, the conductive layer 106 can be used as a word line. The material of the conductive layer 106 is, for example, tungsten. In some embodiments, the wire 108 can be used as a local bit line or a local source line. The material of the wire 108 is, for example, doped polysilicon.

In addition, the wire 102 , the conductive layer 104 , the conductive layer 106 and the wire 108 are located on the first side S1 of the channel layer 110 . In some embodiments, the wire 102 can surround the channel layer 110 , the conductive layer 104 can surround the channel layer 110 , the conductive layer 106 can surround the channel layer 110 , and the wire 108 can surround the channel layer 110 . The wire 102 and the wire 108 are connected to the channel layer 110 . The conductive layer 104 and the conductive layer 106 are electrically insulated from the channel layer 110 . The material of the channel layer 110 is, for example, semiconductor material, such as polysilicon.

The charge storage layer 112 is located between the conductive layer 104 and the channel layer 110 . In some embodiments, the charge storage layer 112 can be further located between the conductive layer 104 and the wire 102 and between the conductive layer 104 and the conductive layer 106 . The material of the charge storage layer 112 is, for example, a charge trapping material, such as silicon nitride.

The charge storage layer 114 is located between the conductive layer 106 and the channel layer 110 . In some embodiments, the charge storage layer 114 can be further located between the conductive layer 106 and the conductive layer 104 and between the conductive layer 106 and the wire 108 . The material of the charge storage layer 114 is, for example, a charge trapping material, such as silicon nitride.

In addition, the memory cell MC may further include at least one of the dielectric layer 116, the dielectric layer 118, the dielectric layer 120, the dielectric layer 122, the dielectric layer 124, the dielectric layer 126, the dielectric layer 128 and the dielectric column 130. By. The dielectric layer 116 is located between the wire 102 and the conductive layer 104 . In some embodiments, the dielectric layer 116 is further positioned between the wire 102 and the charge storage layer 112 . The material of the dielectric layer 116 is, for example, silicon oxide.

The dielectric layer 118 is located between the conductive layer 104 and the conductive layer 106 . In some embodiments, the dielectric layer 118 is further positioned between the charge storage layer 112 and the charge storage layer 114 . The material of the dielectric layer 118 is, for example, silicon oxide.

The dielectric layer 120 is located between the conductive layer 106 and the wire 108 . In some embodiments, the dielectric layer 120 is further positioned between the charge storage layer 114 and the wire 108 . The material of the dielectric layer 120 is, for example, silicon oxide.

The dielectric layer 122 is located between the charge storage layer 112 and the channel layer 110 . In some embodiments, the dielectric layer 122 can be further located between the charge storage layer 112 and the dielectric layer 116 and between the charge storage layer 112 and the dielectric layer 118 . The material of the dielectric layer 122 is, for example, silicon oxide.

The dielectric layer 124 is located between the charge storage layer 112 and the conductive layer 104 . The material of the dielectric layer 124 is, for example, silicon oxide.

The dielectric layer 126 is located between the charge storage layer 114 and the channel layer 110 . In some embodiments, the dielectric layer 126 can be further located between the charge storage layer 114 and the dielectric layer 118 and between the charge storage layer 114 and the dielectric layer 120 . The material of the dielectric layer 126 is, for example, silicon oxide.

The dielectric layer 128 is located between the charge storage layer 114 and the conductive layer 106 . The material of the dielectric layer 128 is, for example, silicon oxide.

In some embodiments, the wire 102 and the conductive layer 104 can be electrically insulated from each other by at least one of the dielectric layer 116 , the dielectric layer 122 , the charge storage layer 112 and the dielectric layer 124 . In some embodiments, the conductive layer 104 and the conductive layer 106 can be formed by the dielectric layer 124, the charge storage layer 112, the dielectric layer 122, the dielectric layer 118, the dielectric layer 126, the charge storage layer 114, and the dielectric layer 128. At least one of them is electrically insulated from each other. In some embodiments, the conductive layer 106 and the wire 108 can be electrically insulated from each other by at least one of the dielectric layer 128 , the charge storage layer 114 , the dielectric layer 126 and the dielectric layer 120 . In some embodiments, the conductive layer 104 can be electrically insulated from the channel layer 110 by at least one of the dielectric layer 124 , the charge storage layer 112 and the dielectric layer 122 . In some embodiments, the conductive layer 106 can be electrically insulated from the channel layer 110 by at least one of the dielectric layer 128 , the charge storage layer 114 and the dielectric layer 126 .

The dielectric pillar 130 is located on the second side S2 of the channel layer 110 . In some embodiments, the first side S1 and the second side S2 may be opposite sides. In some embodiments, the channel layer 110 may surround the dielectric pillar 130 . The material of the dielectric pillar 130 is, for example, silicon oxide.

In some embodiments, a plurality of memory cells MC (eg, memory cells MC1 and MC2 ) can be stacked in a direction D1 away from the substrate 100 . In addition, two adjacent memory cells MC (eg, memory cell MC1 and memory cell MC2 ) stacked in the direction D1 ( FIG. 2 ) away from the substrate 100 may share the wire 108 . In addition, components in two adjacent memory cells MC (eg, memory cell MC1 and memory cell MC2 ) that share the wire 108 may have a symmetrical configuration relationship.

Please refer to FIG. 1 , the memory structure 10 may further include a selection transistor T1 , a selection transistor T2 , a selection transistor T3 , a selection transistor T4 , a bit line BLe, a bit line BLo and a source line SL. In some embodiments, the bit lines BLe and BLo can be global bit lines. In some embodiments, the source line SL may be a global source line.

The selection transistor T1 is electrically connected to one end of the wire 102 , and the selection transistor T2 is electrically connected to the other end of the wire 102 . The wire 102 can be located between the selection transistor T1 and the selection transistor T2. The selection transistor T3 is electrically connected to one end of the wire 108 , and the selection transistor T4 is electrically connected to the other end of the wire 108 . The wire 108 can be located between the selection transistor T3 and the selection transistor T4.

In addition, the selection transistor T1 and the selection transistor T3 can be electrically connected to different bit lines. For example, the select transistor T1 can be electrically connected to the bit line BLe, and the select transistor T3 can be electrically connected to the bit line BLo. In addition, the selection transistor T2 and the selection transistor T4 can be electrically connected to the same source line SL.

In some embodiments, when the memory cell MC is operated, the selection transistor T1 and the selection transistor T2 can be used to control the electrical connection of the wire 102 to the bit line BLe or the source line SL. In addition, when the wire 102 is electrically connected to the bit line BLe, the wire 102 can be used as a local bit line. In addition, when the wire 102 is electrically connected to the source line SL, the wire 102 can be used as a local source line.

In some embodiments, when the memory cell MC is operated, the selection transistor T3 and the selection transistor T4 can be used to control the electrical connection of the wire 108 to the bit line BLo or the source line SL. In addition, when the wire 108 is electrically connected to the bit line BLo, the wire 108 can be used as a local bit line. In addition, when the wire 108 is electrically connected to the source line SL, the wire 108 can be used as a local source line.

Based on the above-mentioned embodiment, it can be seen that in the memory structure 10, the memory cell MC includes the wire 102, the conductive layer 104, the conductive layer 106, the wire 108, the channel layer 110, the charge storage layer 112 and the charge storage layer 114, so the memory cell MC can be It is a double-bit memory cell, and can perform random access to the memory cell MC. In some embodiments, when operating on a bit in the memory cell MC, the wire 102 can be used as a local bit line, and the wire 108 can be used as a local source line. In some embodiments, when operating another bit in the memory cell MC, the wire 102 can be used as a local source line, and the wire 108 can be used as a local bit line. In addition, because the two bits in the memory cell MC share the local bit line and the local source line, it is beneficial to increase the density of the memory cells MC when stacking a plurality of memory cells MC.

FIG. 3 is a schematic circuit diagram of a memory structure according to other embodiments of the present invention. In addition, the cross-sectional view of the memory cell in FIG. 3 can refer to the description of FIG. 2 .

Referring to FIGS. 1 to 3 , the differences between the memory structure 20 in FIG. 3 and the memory structure 10 in FIG. 1 are as follows. The memory structure 20 of FIG. 3 may further include at least one word line WL. In some embodiments, the word line WL may be a global word line. In FIG. 3 , the conductive layer 104 and the conductive layer 106 in the same memory cell MC can be electrically connected to the same word line WL. That is, in FIG. 3 , the conductive layer 104 and the conductive layer 106 can be used as local word lines. In some embodiments, as shown in FIG. 3 , two adjacent memory cells MC (eg, memory cell MC1 and memory cell MC2 ) stacked in the direction D1 away from the substrate 100 ( FIG. 2 ) can be electrically connected to different word line WL. For example, as shown in FIG. 3 , the memory cell MC1 can be electrically connected to the word line WL1 , and the memory cell MC2 can be electrically connected to the word line WL2 . That is, as shown in FIG. 3 , the conductive layer 104 and the conductive layer 106 in the memory cell MC1 can be electrically connected to the same word line WL1, and the conductive layer 104 and the conductive layer 106 in the memory cell MC2 can be electrically connected. to the same word line WL2.

In addition, the same or similar components in the memory structure 20 and the memory structure 10 are represented by the same symbols, and the same or similar contents in the memory structure 20 and the memory structure 10 can be referred to the above-mentioned embodiments for the memory structure 10 , which will not be explained here.

To sum up, in the memory structure of the above embodiments, the memory cells can be double-bit memory cells, and random access can be performed on the memory cells. In addition, since the two bits in the memory cell share the local bit line and the local source line, it is beneficial to increase the memory cell density when stacking a plurality of memory cells.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

10,20: Memory structure 100: base 102,108: Wire 104,106: conductive layer 110: Channel layer 112,114: charge storage layer 116,118,120,122,124,126,128: dielectric layer 130: Dielectric column BLe, BLo: bit line D1: Direction MC, MC1, MC2: memory cells S1: first side S2: second side SL: source line T1~T4: select transistor WL,WL1,WL2: word line

FIG. 1 is a schematic circuit diagram of a memory structure according to some embodiments of the present invention. FIG. 2 is a cross-sectional view of the memory cell in FIG. 1 . FIG. 3 is a schematic circuit diagram of a memory structure according to other embodiments of the present invention.

100: base

102,108: Wire

104,106: conductive layer

110: Channel layer

112,114: charge storage layer

116,118,120,122,124,126,128: dielectric layer

130: Dielectric column

D1: Direction

MC, MC1, MC2: memory cells

S1: first side

S2: second side

Claims (20)

A memory structure comprising: base; and at least one memory cell on the substrate, wherein the memory cell comprises: A first wire, a first conductive layer, a second conductive layer and a second wire stacked in sequence, the first wire and the first conductive layer are electrically insulated from each other, the first conductive layer and the second The conductive layers are electrically insulated from each other, and the second conductive layer and the second wire are electrically insulated from each other; A channel layer, wherein the first wire, the first conductive layer, the second conductive layer and the second wire are located on the first side of the channel layer, wherein the first wire and the second Two wires are connected to the channel layer, and the first conductive layer and the second conductive layer are electrically insulated from the channel layer; a first charge storage layer located between the first conductive layer and the channel layer; and The second charge storage layer is located between the second conductive layer and the channel layer. The memory structure according to claim 1, wherein the memory structure comprises a three-dimensional gate flash memory structure. The memory structure according to claim 1, wherein a plurality of memory cells are stacked in a direction away from the substrate. The memory structure according to claim 1, wherein two adjacent memory cells stacked in a direction away from the substrate share the second wire. The memory structure according to claim 4, wherein components in two adjacent memory cells sharing the second wire have a symmetrical configuration relationship. The memory structure as described in claim item 1 further includes: a first selection transistor electrically connected to one end of the first wire; and The second selection transistor is electrically connected to the other end of the first wire. The memory structure according to claim 6, wherein the first wire is located between the first selection transistor and the second selection transistor. The memory structure as described in claim item 6 further includes: a third selection transistor electrically connected to one end of the second wire; and The fourth selection transistor is electrically connected to the other end of the second wire. The memory structure according to claim 8, wherein the second wire is located between the third selection transistor and the fourth selection transistor. The memory structure according to claim 8, further comprising a plurality of bit lines, wherein the first select transistor and the third select transistor are electrically connected to different bit lines. The memory structure according to claim 8, further comprising a source line, wherein the second selection transistor and the fourth selection transistor are electrically connected to the same source line. The memory structure according to claim 1, further comprising at least one word line, wherein the first conductive layer and the second conductive layer in the same memory cell are electrically connected to the same word line Yuan line. The memory structure according to claim 12, wherein two adjacent memory cells stacked in a direction away from the substrate are electrically connected to different word lines. The memory structure as claimed in item 1, wherein the memory cells further include: The dielectric layer is located between the first wire and the first conductive layer. The memory structure as claimed in item 1, wherein the memory cells further include: The dielectric layer is located between the first conductive layer and the second conductive layer. The memory structure as claimed in item 1, wherein the memory cells further include: The dielectric layer is located between the second conductive layer and the second wire. The memory structure as claimed in item 1, wherein the memory cells further include: a first dielectric layer between the first charge storage layer and the channel layer; and The second dielectric layer is located between the first charge storage layer and the first conductive layer. The memory structure as described in claim item 1 further includes: a first dielectric layer between the second charge storage layer and the channel layer; and The second dielectric layer is located between the second charge storage layer and the second conductive layer. The memory structure as claimed in item 1, wherein the memory cells further include: The dielectric column is located on the second side of the channel layer, wherein the first side and the second side are opposite sides. The memory structure of claim 1, wherein the channel layer surrounds the dielectric pillar.

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